Plugs for interconnect lines for advanced integrated circuit structure fabrication

Abstract

Embodiments of this invention belong to the field of advanced integrated circuit fabrication, and more particularly, relate to the fabrication and resulting structures of integrated circuit structures with 10-nanometer nodes and smaller. In one example, an integrated circuit structure includes an interlayer dielectric (ILD) layer on a substrate. Conductive interconnects are located in trenches within the ILD layer, the conductive interconnects having a first portion and a second portion, the first portion being laterally adjacent to the second portion. Dielectric plugs are located between and laterally adjacent to the first and second portions of the conductive interconnects, the dielectric plugs comprising a metal oxide material.

Description

Technical Field

[0001] The embodiments of the present invention belong to the field of advanced integrated circuit structure manufacturing, and in particular, relate to the manufacturing of integrated circuit structures with 10-nanometer nodes and smaller, and the resulting structures. [] Prior Technology

[0002] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to increasingly smaller features enables increased density of functional cells on the limited surface area of ​​a semiconductor wafer. For example, shrinking transistor size allows for the integration of an increased number of memory or logic devices on a single chip, resulting in the manufacture of products with increased capacity. However, this desire for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] The variability in traditional and currently known manufacturing processes may limit their potential for further extension into the 10-nanometer or sub-10-nanometer range. Therefore, the manufacturing of functional components required for future technology nodes may require the introduction of new methodologies or the integration of new technologies into or replacement of current manufacturing processes. Summary of the Invention

[0004] and Simple Explanation of the Diagram

[0005] Figure 1A illustrates a cross-sectional view of the initial structure after the deposition (but before patterning) of the hard masking material layer formed on the interlayer dielectric (ILD) layer.

[0006] Figure 1B illustrates a cross-sectional view of the structure of Figure 1A following a hard mask layer patterned by halving the pitch.

[0007] Figure 2A is a schematic diagram of a method for manufacturing semiconductor fins with a pitch reduced to one-quarter, according to an embodiment of the present invention.

[0008] Figure 2B illustrates a cross-sectional view of a semiconductor fin manufactured using a pitch reduction of one-quarter, according to an embodiment of the present invention.

[0009] Figure 3A is a schematic diagram of a method for manufacturing semiconductor fins with a combined fin pitch reduced to one-quarter, according to an embodiment of the present invention.

[0010] Figure 3B illustrates a cross-sectional view of a semiconductor fin manufactured using a method of reducing the fin pitch to one-quarter, according to an embodiment of the present invention.

[0011] Figures 4A-4C are cross-sectional views illustrating various operations in a method for manufacturing a plurality of semiconductor fins, according to embodiments of the present invention.

[0012] Figure 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure, according to an embodiment of the present invention.

[0013] Figure 5B illustrates a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure, according to another embodiment of the present invention.

[0014] Figures 6A-6D are cross-sectional views illustrating various operations in the manufacture of the three-layer trench isolation structure, according to embodiments of the present invention.

[0015] Figures 7A-7E are oblique three-dimensional cross-sectional views illustrating various operations in a method of manufacturing an integrated circuit structure, according to an embodiment of the present invention.

[0016] Figures 8A-8F illustrate slightly convex cross-sectional views taken along the a-a' axis of Figure 7E, according to an embodiment of the present invention, of various operations in a method for manufacturing an integrated circuit structure.

[0017] Figure 9A illustrates a slightly convex cross-sectional view along the a-a' axis of Figure 7E, which shows an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region, according to an embodiment of the present invention.

[0018] Figure 9B illustrates a cross-sectional view along the b-b' axis of Figure 7E, representing an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures, according to an embodiment of the present invention.

[0019] Figure 10 illustrates a cross-sectional view of an integrated circuit structure taken at the source or drain position, according to an embodiment of the present invention.

[0020] Figure 11 illustrates a cross-sectional view of another integrated circuit structure taken at the source or drain position, according to an embodiment of the present invention.

[0021] Figures 12A-12D illustrate cross-sectional views taken at the source or drain positions and represent various operations in the manufacture of an integrated circuit structure according to embodiments of the present invention.

[0022] Figures 13A and 13B illustrate plan views showing various operations in a method for patterning fins with multiple gate spacings to form a local isolation structure, according to embodiments of the present invention.

[0023] Figures 14A-14D illustrate plan views showing various operations in a method for patterning fins with a single gate spacing to form a local isolation structure, according to another embodiment of the invention.

[0024] Figure 15 illustrates a cross-sectional view of an integrated circuit structure with fins having multiple gate spacings for local isolation, according to an embodiment of the present invention.

[0025] Figure 16A illustrates a cross-sectional view of an integrated circuit structure with fins having a single gate spacing for local isolation, according to another embodiment of the present invention.

[0026] Figure 16B illustrates a cross-sectional view showing the location where a finned isolation structure can be formed to replace the gate electrode, according to an embodiment of the present invention.

[0027] Figures 17A-17C illustrate the various depth possibilities of fin cutting manufactured using fin trimming isolation methods, according to embodiments of the present invention.

[0028] Figure 18 illustrates a plan view and a corresponding cross-sectional view taken along the a-a' axis, showing possible choices of depth for a portion of a fin cut within a fin relative to a wider location, according to an embodiment of the invention.

[0029] Figures 19A and 19B illustrate cross-sectional views of various operations in a method for selecting the location of a stressor at the end of a fin with a wide cut, according to an embodiment of the present invention.

[0030] Figures 20A and 20B illustrate cross-sectional views of various operations in a method for selecting the location of the stress source at the end of a fin with partial cuts, according to an embodiment of the present invention.

[0031] Figures 21A-21M illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure with differential fin end dielectric plugs, according to an embodiment of the present invention.

[0032] Figures 22A-22D are cross-sectional views illustrating an exemplary structure of a PMOS fin end stress source dielectric plug, according to an embodiment of the present invention.

[0033] Figure 23A illustrates a cross-sectional view of another semiconductor structure with fin end stress-sensing characteristics, according to another embodiment of the present invention.

[0034] Figure 23B illustrates a cross-sectional view of another semiconductor structure with fin end stress-sensing characteristics, according to another embodiment of the present invention.

[0035] Figure 24A illustrates an oblique view of a fin with tensile uniaxial stress, according to an embodiment of the present invention.

[0036] Figure 24B illustrates an oblique view of a fin with compressive uniaxial stress, according to an embodiment of the present invention.

[0037] Figures 25A and 25B illustrate plan views showing various operations in a method for patterning fins with a single gate spacing at a selected gate line cut position to form a local isolation structure, according to embodiments of the present invention.

[0038] Figures 26A-26C illustrate cross-sectional views of various possibilities for polysilicon cutting and fin trimming isolation (FTI) partial fin cutting locations and dielectric plugs at polysilicon cutting locations only for the structure of Figure 25B, according to embodiments of the present invention.

[0039] Figure 27A illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate wire cut, the gate wire cut having a dielectric plug extending into a dielectric spacer of the gate wire, according to an embodiment of the present invention.

[0040] Figure 27B illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate wire cut having a dielectric plug extending beyond the gate wire, according to another embodiment of the invention.

[0041] Figures 28A-28F illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure with a gate wire cut having a dielectric plug having an upper portion of dielectric spacers extending beyond the gate wire and a lower portion of the dielectric spacers extending into the gate wire, according to another embodiment of the invention.

[0042] Figures 29A-29C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure having residual virtual gate material on a portion of the bottom of a permanent gate stack, according to an embodiment of the present invention.

[0043] Figures 30A-30D illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having residual virtual gate material on a portion at the bottom of a permanent gate stack, according to another embodiment of the invention.

[0044] Figure 31A illustrates a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure, according to an embodiment of the present invention.

[0045] Figure 31B illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure, according to another embodiment of the present invention.

[0046] Figure 32A illustrates a plan view of a plurality of gate lines above a pair of semiconductor fins, according to an embodiment of the present invention.

[0047] Figure 32B illustrates a cross-sectional view taken along axis a-a' of Figure 32A, according to an embodiment of the present invention.

[0048] Figure 33A illustrates a cross-sectional view of a pair of NMOS devices having differential voltage thresholds based on modulation doping, and a pair of PMOS devices having differential voltage thresholds based on modulation doping, according to an embodiment of the present invention.

[0049] Figure 33B illustrates a cross-sectional view of a pair of NMOS devices having differential voltage thresholds according to a differential gate electrode structure, and a pair of PMOS devices having differential voltage thresholds according to a differential gate electrode structure, according to another embodiment of the present invention.

[0050] Figure 34A illustrates a cross-sectional view of a group of three NMOS devices having a differential gate electrode structure and a differential voltage threshold value based on modulation doping, and a group of three PMOS devices having a differential gate electrode structure and a differential voltage threshold value based on modulation doping, according to an embodiment of the present invention.

[0051] Figure 34B illustrates a cross-sectional view of a group of three NMOS devices having a differential voltage threshold based on a differential gate electrode structure and a differential voltage threshold based on modulation doping, according to another embodiment of the present invention.

[0052] Figures 35A-35D illustrate cross-sectional views of various operations in a method of manufacturing an NMOS device having a differential voltage threshold value according to a differential gate electrode structure, according to another embodiment of the present invention.

[0053] Figures 36A-36D illustrate cross-sectional views of various operations in a method of manufacturing a PMOS device having a differential voltage threshold value according to a differential gate electrode structure, according to another embodiment of the present invention.

[0054] Figure 37 illustrates a cross-sectional view of an integrated circuit structure with a P / N junction, according to an embodiment of the present invention.

[0055] Figures 38A-38H illustrate cross-sectional views of various operations in a method for manufacturing integrated circuit structures using bimetallic gates instead of gate process flows, according to embodiments of the present invention.

[0056] Figures 39A-39H illustrate cross-sectional views showing various operations in a method of manufacturing a bissilicide-based integrated circuit, according to an embodiment of the present invention.

[0057] Figure 40A illustrates a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device, according to an embodiment of the present invention.

[0058] Figure 40B illustrates a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device, according to another embodiment of the present invention.

[0059] Figure 41A illustrates a cross-sectional view of a semiconductor device having conductive contacts on the source or drain regions, according to an embodiment of the present invention.

[0060] Figure 41B illustrates a cross-sectional view of another semiconductor device having conductive contacts on the raised source or drain region, according to an embodiment of the present invention.

[0061] Figure 42 illustrates a plan view of a plurality of gate lines above a pair of semiconductor fins, according to an embodiment of the present invention.

[0062] Figures 43A-43C illustrate cross-sectional views taken along axis a-a' of Figure 42 for various operations in a method of manufacturing an integrated circuit structure, according to an embodiment of the present invention.

[0063] Figure 44 illustrates a cross-sectional view of an integrated circuit structure taken along the b-b' axis of Figure 42, according to an embodiment of the present invention.

[0064] Figures 45A and 45B respectively illustrate a plan view and a corresponding cross-sectional view of an integrated circuit structure including a grooved contact plug having a hard shielding material thereon, according to an embodiment of the present invention.

[0065] Figures 46A-46D illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure including a trench contact plug having a hard masking material thereon, according to an embodiment of the present invention.

[0066] Figure 47A illustrates a plan view of a semiconductor device having a gate contact disposed above the inactive portion of a gate electrode. Figure 47B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed above the inactive portion of a gate electrode.

[0067] Figure 48A illustrates a plan view of a semiconductor device having a gate contact via disposed above the active portion of the gate electrode, according to an embodiment of the present invention. Figure 48B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above the active portion of the gate electrode, according to an embodiment of the present invention.

[0068] Figures 49A-49D illustrate cross-sectional views illustrating various operations in a method of manufacturing a semiconductor structure having a gate contact structure disposed above the active portion of the gate, according to embodiments of the present invention.

[0069] Figure 50 illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure having trench contacts including an overlying insulating cover, according to an embodiment of the present invention.

[0070] Figures 51A-51F illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating layer and a gate stack including an overlying insulating layer, according to embodiments of the present invention.

[0071] Figure 52A illustrates a plan view of a semiconductor device having a gate contact via disposed above the active portion of the gate, according to another embodiment of the present invention.

[0072] Figure 52B illustrates a plan view of another semiconductor device having a trench contact via coupled with a pair of trench contacts, according to another embodiment of the present invention.

[0073] Figures 53A-53E illustrate cross-sectional views showing various operations in a method of manufacturing an integrated circuit structure having a gate stack covered with an insulating cap, according to an embodiment of the present invention.

[0074] Figure 54 is a schematic diagram of a method for reducing the pitch of trenches used to manufacture interconnect structures to one-quarter, according to an embodiment of the present invention.

[0075] Figure 55A illustrates a cross-sectional view of a metallization layer manufactured using a pitch reduction of one-quarter, according to an embodiment of the present invention.

[0076] Figure 55B illustrates a cross-sectional view of a metallization layer manufactured using a pitch reduction scheme on top of a metallization layer manufactured using a pitch reduction scheme of one-quarter, according to an embodiment of the present invention.

[0077] Figure 56A illustrates a cross-sectional view of an integrated circuit structure having a metallization layer composed of metal lines on top of a metallization layer composed of different metal lines, according to an embodiment of the present invention.

[0078] Figure 56B illustrates a cross-sectional view of an integrated circuit structure having a metallization layer composed of metal lines coupled to a metallization layer composed of different metal lines, according to an embodiment of the present invention.

[0079] Figures 57A-57C illustrate cross-sectional views of individual interconnects with various lining and conductive capping configurations, according to embodiments of the present invention.

[0080] Figure 58 illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with metal wire composition and pitch on top of two metallization layers with different metal wire compositions and smaller pitches, according to an embodiment of the present invention.

[0081] Figures 59A-59D illustrate cross-sectional views of various interconnect and via configurations having a bottom conductive layer, according to embodiments of the present invention.

[0082] Figures 60A-60D are cross-sectional views illustrating the structural configuration of the recessed line morphology for the BEOL metallization layer, according to an embodiment of the present invention.

[0083] Figures 61A-61D are cross-sectional views illustrating the structural configuration of the stepped line morphology used for the BEOL metallization layer, according to an embodiment of the present invention.

[0084] Figure 62A illustrates the plan view and corresponding cross-sectional view taken along the a-a' axis of the plan view of the metallization layer, according to an embodiment of the present invention.

[0085] Figure 62B illustrates a cross-sectional view of the wire end or plug, according to an embodiment of the present invention.

[0086] Figure 62C illustrates another cross-sectional view of the wire end or plug, according to an embodiment of the present invention.

[0087] Figures 63A-63F illustrate plan views and corresponding cross-sectional views, illustrating various operations in a plug final processing scheme according to embodiments of the present invention.

[0088] Figure 64A illustrates a cross-sectional view of a conductive wire plug with a seam therein, according to an embodiment of the present invention.

[0089] Figure 64B illustrates a cross-sectional view of a stack of metallization layers including conductive wire plugs at lower metal wire locations, according to an embodiment of the present invention.

[0090] Figure 65 illustrates the first view of the cell layout of a memory cell.

[0091] Figure 66 illustrates a first view of the cell layout of a memory cell with internal node jumpers, according to an embodiment of the present invention.

[0092] Figure 67 is a second view illustrating the cell layout of memory cells.

[0093] Figure 68 is a second view illustrating the cell layout of a memory cell with internal node jumpers, according to an embodiment of the present invention.

[0094] Figure 69 is a third view illustrating the cell layout of memory cells.

[0095] Figure 70 is a third view illustrating the cell layout of a memory cell with internal node jumpers, according to an embodiment of the present invention.

[0096] Figures 71A and 71B respectively illustrate the bit cell layout and schematic diagram, for a six-electro-electric (6T) static random access memory (SRAM) according to an embodiment of the present invention.

[0097] Figure 72 illustrates cross-sectional views of two different layouts of the same standard unit, according to an embodiment of the present invention.

[0098] Figure 73 illustrates a plan view of four different unit configurations indicating even (E) or odd (O) numbers, according to an embodiment of the present invention.

[0099] Figure 74 illustrates a plan view of a block-level polycrystalline silicon lattice according to an embodiment of the present invention.

[0100] Figure 75 illustrates an acceptable (through) layout based on an example of a standard unit with different versions, according to an embodiment of the present invention.

[0101] Figure 76 illustrates an unacceptable (failed) layout based on an embodiment of the present invention, according to different versions of the standard unit.

[0102] Figure 77 illustrates another acceptable (through) layout based on a standard unit with different versions, according to an embodiment of the present invention.

[0103] Figure 78 illustrates a partially cut plan view and a corresponding cross-sectional view of a fin-based thin-film resistor structure, wherein the cross-sectional view is obtained along the a-a' axis of the partially cut plan view, according to an embodiment of the present invention.

[0104] Figures 79-83 illustrate plan views and corresponding cross-sectional views, illustrating various operations in a method for manufacturing a fin-based thin-film resistor structure according to embodiments of the present invention.

[0105] Figure 84 illustrates a plan view of a fin-based thin-film resistor structure having various exemplary positions for anode or cathode electrode contacts, according to an embodiment of the present invention.

[0106] Figures 85A-85D illustrate plan views of various fin geometries used to manufacture fin-based precision resistors, according to embodiments of the present invention.

[0107] Figure 86 illustrates a cross-sectional view of the lithography mask structure according to an embodiment of the present invention.

[0108] Figure 87 illustrates a computing device according to one embodiment of the present invention.

[0109] Figure 88 illustrates an inserter that includes one or more embodiments of the present invention.

[0110] Figure 89 is an isometric view of a mobile computing platform that utilizes an IC manufactured according to one or more of the processes described herein or includes one or more of the features described herein, according to an embodiment of the present invention.

[0111] Figure 90 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present invention. Implementation

[0112] This description describes the fabrication of advanced integrated circuit structures. In the following description, several specific details, such as specific integration and material states, are set forth to provide a thorough understanding of embodiments of the invention. Those skilled in the art will understand that embodiments of the invention can be practiced without these specific details. In other instances, well-known features (such as integrated circuit design layouts) are not described in detail to avoid unnecessarily obscuring embodiments of the invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily depicted to scale.

[0113] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the claimed subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "scope, example, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as a superior or advantageous alternative to other implementations. Furthermore, there is no intention to be bound by any express or implied theory set forth in the prior art, background, brief summary, or the following detailed description.

[0114] This specification includes references to "an embodiment" or "an embodiment". The appearance of the terms "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with the invention.

[0115] Terminology. The following paragraphs provide definitions or background for terms found in this invention (including the appended claims):

[0116] "Contains". This term is open-ended. As used in the claims appended hereto, this term does not exclude additional structures or operations.

[0117] "Configured". Individual units or components may be described or requested to be "configured" to perform one or more functions. In this context, "configured" is used to imply a structure by indicating that its units or components include the structure that performs those functions during operation. Thus, a unit or component can be said to be configured to perform that function, even when the specified unit or component is not currently operational (e.g., not turned on or in use). Describing a unit or circuit or component as being "configured" to perform one or more functions explicitly indicates that 35 USC §112 (paragraph 6) should not be referenced to that unit or component.

[0118] "First," "Second," etc. As used in the text, these terms are used as identifiers for the nouns that follow them and do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0119] "Coupled" – The following description refers to elements, nodes, or features that are "coupled" together. As used herein, unless otherwise expressly stated, "coupled" means that one element, node, or feature is directly or indirectly connected to (or directly or indirectly communicates with) another element, node, or feature, and not necessarily mechanically.

[0120] In addition, certain terms may be used in the following description for illustrative purposes only and are not intended to be restrictive. For example, terms such as “higher,” “lower,” “above,” and “below” refer to orientation in the graphics to which the reference applies. Terms such as “front,” “back,” “rear,” “side,” “outer,” and “inner” describe the orientation or position, or both, of a portion of a component within a constant (but arbitrary) frame of the reference, as will be made clear from the text and related graphics of the component discussed in the reference description. This terminology may include words explicitly mentioned above, their derivatives, and words with similar meanings.

[0121] "Prohibition"—As used in this text, prohibition is used to describe a reduction or mitigation of an effect. When a component or feature is described as prohibiting an action, movement, or state, it completely prevents the result or consequence or future state. Furthermore, "prohibition" can also refer to a reduction or mitigation of the possible additional consequences, performance, or effect. Therefore, when a component, element, or feature is designated as prohibiting a result or state, it is not necessary to completely prevent or eliminate that result or state.

[0122] The embodiments described herein pertain to front-end process (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all steps up to (but not including) the deposition of metal interconnect layers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., no wiring).

[0123] The embodiments described herein pertain to back-end process (BEOL) semiconductor processing and structure. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected by wiring on the wafer (e.g., metallization layers or multiple layers). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for wafer-to-package connections. During the manufacturing phase of BEOL, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be incorporated into the BEOL.

[0124] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although the exemplary processing scheme can be described using a FEOL processing scenario, these methods can also be applied to BEOL processing. Similarly, although the exemplary processing scheme can be described using a BEOL processing scenario, these methods can also be applied to FEOL processing.

[0125] Pitch segmentation and patterning schemes may be implemented such that the embodiments described herein or may be included as part of the embodiments described herein. Pitch segmentation patterning generally refers to halving the pitch, reducing the pitch to one-quarter, etc. Pitch segmentation schemes may be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, lithography is first performed to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. Pitch segmentation processing is then implemented as a technique to increase line density.

[0126] In one embodiment, the term "grating structure," used for fins, gate lines, metal lines, ILD lines, or hard mask lines, is used herein to refer to a close-pitch grating structure. In this embodiment, the close pitch cannot be directly obtained through a selected lithography. For example, a pattern based on a selected lithography may be formed first, but the pitch may be halved by patterning with spacer masking, as known in the art. Furthermore, the original pitch may be reduced to one-quarter by a second round of spacer masking patterning. Therefore, the grating-like pattern described herein may have metal lines, ILD lines, or hard mask lines separated by a substantially constant pitch and having a substantially constant width. For example, in some embodiments, the pitch variation may be within 10 percent and the width variation may be within 10 percent, and in some embodiments, the pitch variation may be within 5 percent and the width variation may be within 5 percent. The pattern may be manufactured by halving the pitch or reducing the pitch to one-quarter (or other pitch segmentation). In one embodiment, the grating is not necessarily a single pitch.

[0127] In the first example, pitch halving can be implemented to double the line density of the resulting grating structure. Figure 1A illustrates a cross-sectional view of the initial structure after the deposition of the hard masking material layer formed on the interlayer dielectric (ILD) layer (but before its patterning). Figure 1B illustrates a cross-sectional view of the structure of Figure 1A after the hard masking layer is patterned by pitch halving.

[0128] Referring to Figure 1A, the initial structure 100 has a hard masking material layer 104, which is formed on the interlayer dielectric (ILD) layer 102. A patterned mask 106 is disposed on the hard masking material layer 104. The patterned mask 106 has spacers 108 formed along the sidewalls of its features (lines) on the hard masking material layer 104.

[0129] Referring to FIG. 1B, the hard mask material layer 104 is patterned with a pitch halved. Specifically, the patterned mask 106 is removed first. The resulting pattern of the spacers 108 has twice the density of the mask 106, or half its pitch or features. The pattern of the spacers 108 is transferred to the hard mask material layer 104, for example, by an etching process to form a patterned hard mask 110, as shown in FIG. 1B. In one such embodiment, the patterned hard mask 110 is formed as a grating pattern with unidirectional lines. The grating pattern of the patterned hard mask 110 can be a close-pitch grating structure. For example, a close pitch may not be achievable directly by a selected lithography technique. Even, although not shown, the original pitch can be reduced to one-quarter by a second round of spacer mask patterning. Thus, the grating pattern of the patterned hard mask 110 of FIG. 1B can have hard mask lines separated by a constant pitch and having a constant width between them. The resulting size may be much smaller than the critical size of the lithography technology already in use.

[0130] Therefore, for front-end process online (FEOL) or back-end process online (BEOL) (or both) integration schemes, the cover film can be patterned using lithography and etching processes (which may involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartet). It should be understood that other pitch division methods can also be implemented. In any case, in one embodiment, a gridded layout can be fabricated by using a selected lithography method, such as 193nm immersion lithography (193i). Pitch division can be implemented as a factor of n to increase the line density in the gridded layout. The formation of a gridded layout using 193i lithography plus pitch division as a factor of "n" can be specified as 193i + P / n pitch division. In one such embodiment, 193nm immersion scaling can be extended over many generations using cost-effective pitch division.

[0131] In the manufacture of integrated circuit devices, multi-gate transistors, such as three-gate transistors, have become more common as device sizes continue to shrink. Three-gate transistors are typically manufactured on bulk silicon substrates or silicon insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-volume bulk silicon substrate facilities.

[0132] However, the miniaturization of multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits decreases and the total number of basic building blocks manufactured in a given area increases, the limitations of the semiconductor processes used to manufacture these building blocks become increasingly problematic.

[0133] According to one or more embodiments of the present invention, a pitch reduction of one-quarter is implemented to pattern a semiconductor layer to form semiconductor fins. In one or more embodiments, a fin pitch reduction of one-quarter is combined.

[0134] Figure 2A is a schematic diagram of a pitch reduction method 200 for manufacturing semiconductor fins according to an embodiment of the present invention. Figure 2B illustrates a cross-sectional view of a semiconductor fin manufactured using the pitch reduction method according to an embodiment of the present invention.

[0135] Referring to Figure 2A, in operation (a), a photoresist layer (PR) is patterned to form photoresist feature 202. Photoresist feature 202 can be patterned using standard lithography techniques such as 193 immersion lithography. In operation (b), photoresist feature 202 is used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form a first backbone (BB1) feature 204. A first spacer (SP1) feature 206 is then formed adjacent to the sidewall of the first backbone feature 204. In operation (c), the first backbone feature 204 is removed, leaving only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206', as depicted in Figure 2A. This thinning can be performed before (as shown) or after the removal of BB1 (feature 204), depending on the necessary spacing and size required for feature BB2 (208, described below). In operation (d), the first spacer feature 206, or the thinned first spacer feature 206', is used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form the second backbone (BB2) feature 208. The second spacer (SP2) feature 210 is then formed as a sidewall adjacent to the second backbone feature 208. In operation (e), the second backbone feature 208 is removed so that only the second spacer feature 210 remains. The remaining second spacer feature 210 can then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins, having a size with a pitch reduced to one-quarter relative to the initially patterned photoresist feature 202. As an example, referring to FIG2B, a plurality of semiconductor fins 250 (such as silicon fins formed from a bulk silicon layer) are formed by using a second spacer feature 210 as a mask for patterning (e.g., dry or plasma etching patterning). In the example of FIG2B, the plurality of semiconductor fins 250 have substantially the same pitch and spacing.

[0136] It should be understood that the spacing between the initial patterned photoresist features can be modified to alter the structural results of a quarter-pitch process. In one example, Figure 3A is a schematic diagram of a quarter-pitch merging fin configuration 300 for manufacturing semiconductor fins, according to an embodiment of the present invention. Figure 3B illustrates a cross-sectional view of a semiconductor fin manufactured using a quarter-pitch merging fin configuration, according to an embodiment of the present invention.

[0137] Referring to Figure 3A, in operation (a), a photoresist layer (PR) is patterned to form photoresist feature 302. Photoresist feature 302 can be patterned using standard lithography techniques (such as 193 immersion lithography), but its spacing (e.g., spacing referred to as sub-design rule spaces) may ultimately interfere with the spacing of the design rules required to produce a uniform pitch multiplication pattern. In operation (b), photoresist feature 302 is used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form a first backbone (BB1) feature 304. First spacer (SP1) features 306 are then formed adjacent to the sidewalls of the first backbone feature 304. However, compared to the scheme shown in Figure 2A, some adjacent first spacer features 306 are merged spacer features due to the denser photoresist features 302. In operation (c), the first backbone feature 304 is removed so that only the first spacer features 306 remain. Before or after the removal of the first backbone feature 304, some of the first spacer features 306 may be thinned to form thinned first spacer features 306', as depicted in FIG3A. In operation (d), the first spacer features 306 and the thinned first spacer features 306' are used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form a second backbone (BB2) feature 308. The second spacer (SP2) feature 310 is then formed adjacent to the sidewall of the second backbone feature 308. However, at locations where the BB2 feature 308 is a merged feature (such as the central BB2 feature 308 in FIG3A), the second spacer is not formed. In operation (e), the second backbone feature 308 is removed so that only the second spacer features 310 remain. The remaining second spacer features 310 may then be used to pattern a semiconductor layer to provide a plurality of semiconductor fins, having a pitch reduced to one-quarter of the size relative to the initially patterned photoresist feature 302.

[0138] As an example, referring to FIG3B, a plurality of semiconductor fins 350 (such as silicon fins formed from a bulk silicon layer) are formed using a second spacer feature 310 as a mask for patterning (e.g., dry or plasma etching patterning). However, in the example of FIG3B, the plurality of semiconductor fins 350 have varying pitches and spacings. This method of merging fin spacer patterning can be implemented to substantially eliminate fins appearing in certain locations of the pattern of the plurality of fins. Thus, merging the first spacer feature 306 in certain locations allows for the fabrication of six or four fins based on two first backbone features 304 (which typically produce eight fins), as described in association with FIG2A and 2B. In one example, the inner fins have a tighter pitch than would normally be allowed by producing the fins at a uniform pitch and then removing unwanted fins, although the latter method can still be implemented according to the embodiments described herein.

[0139] In an exemplary embodiment, referring to FIG3B, in the integrated circuit structure, the first complex semiconductor fins 352 have the longest dimension along a first direction (y, entering the page). Adjacent individual semiconductor fins 353 of the first complex semiconductor fins 352 are isolated from each other by a first amount (S11) in a second direction (x) orthogonal to the first direction y. The second complex semiconductor fins 354 have the longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second complex semiconductor fins 354 are isolated from each other by a first amount (S1) in the second direction. The closest semiconductor fins 356 and 357 of each of the first and second complex semiconductor fins 352 and 354 are isolated from each other by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 is greater than twice the first amount S1.

[0140] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous and have an underlying single-crystal silicon substrate. In one embodiment, each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 has an outwardly tapering sidewall along a second direction x, from the top to the bottom of each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0141] In another exemplary embodiment, referring to Figures 3A and 3B, a method of manufacturing an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). A primary spacer structure 306 is formed as a sidewall adjacent to the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The primary spacer structure 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) is merged. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and first, second, third, and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (e.g., the central pair of secondary backbone structures 308) are merged. A secondary spacer structure 310 is formed as a sidewall adjacent to the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. The semiconductor material is then patterned with secondary spacer structures 310 to form semiconductor fins 350 in the semiconductor material.

[0142] In one embodiment, a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1) are patterned with a sub-design regularity spacing between the first and second primary backbone structures. In one embodiment, the semiconductor material comprises silicon. In one embodiment, individual semiconductor fins 350 have outwardly tapering sidewalls along a second direction x from the top to the bottom of the individual semiconductor fins 350. In one embodiment, the semiconductor fins 350 are continuous and have an underlying single-crystal silicon substrate. In one embodiment, patterning the semiconductor material with a secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein adjacent individual semiconductor fins of the first plurality of semiconductor fins 352 are separated from each other by a first amount S1 in a second direction x orthogonal to the first direction y. The second complex semiconductor fins 354 are formed to have the longest dimension along the first direction y, wherein adjacent individual semiconductor fins of the second complex semiconductor fins 354 are isolated from each other by a first amount S1 in the second direction x. The closest semiconductor fins 356 and 357 of the first complex semiconductor fins 352 and the second complex semiconductor fins 354 (individually) are isolated from each other by a second amount S2 in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1. In one such embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice the first amount S1 but less than three times the first amount S1. In one embodiment, the first complex semiconductor fins 352 have exactly five semiconductor fins, and the second complex semiconductor fins 254 have exactly five semiconductor fins, as shown in FIG3B.

[0143] In another embodiment, it should be understood that a fin trimming process is performed, wherein fin removal is performed as an alternative to the fin-merging method, and the fins may be trimmed (removed) during hard mask patterning or by physically removing the fins. As an example of the latter method, Figures 4A-4C are cross-sectional views illustrating various operations in a method of manufacturing a plurality of semiconductor fins, according to embodiments of the present invention.

[0144] Referring to Figure 4A, a patterned hard mask layer 402 is formed on a semiconductor layer 404 (such as a bulk single-crystal silicon layer). Referring to Figure 4B, fins 406 are then formed in the semiconductor layer 404, for example, by a dry or plasma etching process. Referring to Figure 4C, selected fins 406 are removed, for example, using a masking and etching process. In the example shown, one of the fins 406 is removed, leaving a residual fin stub 408, as shown in Figure 4C. In this "final fin trimming" method, the hard mask 402 is patterned integrally to provide a grating structure without the removal or modification of individual features. The total number of fins is not modified until after the fins are manufactured.

[0145] In another embodiment, multilayer trench isolation regions (which may be referred to as shallow trench isolation (STI) structures) may be implemented between semiconductor fins. In one embodiment, the multilayer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0146] Ideally, a bulk silicon-based fin or three-gate transistor would be used. However, a concern is that the region (sub-fin) beneath the active silicon fin portion of the device (e.g., the gate control region, or HSi) may be under reduced or no gate control. Consequently, if the source or drain region is at or below the HSi point, leakage paths may exist through this sub-fin region. Therefore, leakage paths in the sub-fin region should be controlled for better device operation.

[0147] One approach to addressing the aforementioned problems involves the use of well implantation operations, in which the daughter fin region is heavily doped (e.g., much greater than 2E18 / cm3), which shuts off daughter fin leakage but also results in substantial doping within the fin. The addition of halo implantation further increases fin doping to the point that the ends of its line fins are doped at high levels (e.g., greater than about 1E18 / cm3).

[0148] Another approach involves doping via sub-fin doping, rather than necessarily transferring the same level of doping to the HSi portion of those fins. These processes can involve selectively doping the sub-fin regions of tri-gate or FinFET transistors fabricated on a bulk silicon wafer, for example, via diffusion from tri-gate-doped glass sub-fins. For example, selectively doping the sub-fin regions of tri-gate or FinFET transistors can reduce sub-fin leakage while maintaining low fin doping. The incorporation of solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow, after being recessed from the fin sidewalls, transfers doping into the sub-fin regions while keeping the fin body relatively undoped.

[0149] Therefore, the process may include using a solid source doped layer (e.g., boron-doped oxide) deposited on the fins after fin etching. Subsequently, after trench filling and polishing, this doped layer, along with the trench filler material, is recessed to define the fin height (HSi) of the device. This operation removes the doped layer from the fin sidewalls above the HSi. Thus, the doped layer appears only along the fin sidewalls in the sub-fin region, ensuring precise control of the doping layout. After drive-in annealing, the high doping is confined to the sub-fin region, rapidly transitioning to the low doping in the adjacent region of the fin above the HSi (which forms the transistor channel region). Typically, borosilicate glass (BSG) is applied to NMOS fins for doping, while phosphosilicate (PSG) or arsenicislicate glass (AsSG) layers are applied to PMOS fins for doping. In one example, the P-type solid-state dopant source layer is a BSG layer having a boron concentration in the range of about 0.1-10 wt%. In another example, the N-type solid-state dopant source layer is a PSG layer or an AsSG layer, each having a phosphorus or arsenic concentration in the range of about 0.1-10 wt%. A silicon nitride capping layer may be included on the doped layer, and a silicon dioxide or silicon oxide filler material may then be included on the silicon nitride capping layer.

[0150] According to another embodiment of the invention, sub-fin leakage is sufficiently low for relatively thin fins (e.g., fins with a width of less than about 20 nanometers), wherein an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is included on the silicon nitride capping layer. It should be understood that doping of the sub-fin region (such as halo doping) can also be implemented using this structure.

[0151] Figure 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure, according to an embodiment of the present invention.

[0152] Referring to Figure 5A, an integrated circuit structure includes a fin 502, such as a silicon fin. The fin 502 has a lower fin portion (sub-fin) 502A and an upper fin portion 502B (HSi). A first insulating layer 504 is directly on the sidewall of the lower fin portion 502A of the fin 502. A second insulating layer 506 is directly on the first insulating layer 504, which is directly on the sidewall of the lower fin portion 502A of the fin 502. A dielectric filler material 508 is directly adjacent to the second insulating layer 506, which is directly on the first insulating layer 504, which is directly on the sidewall of the lower fin portion 502A of the fin 502.

[0153] In one embodiment, the first insulating layer 504 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 504 comprises silicon and oxygen and contains no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. In one embodiment, the first insulating layer 504 has a thickness in the range of 0.5-2 nanometers.

[0154] In one embodiment, the second insulating layer 506 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the second insulating layer 506 has a thickness in the range of 2-5 nanometers.

[0155] In one embodiment, the dielectric filling material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, a gate electrode is ultimately formed on the top of the fin portion 502B above the fin 502 and laterally adjacent to the sidewall of the fin portion 502B above the fin 502.

[0156] It should be understood that during processing, the fin portions of the semiconductor fins may be eroded or worn away. Simultaneously, the trench isolation structure between the fins may also be eroded to have a non-planar morphology, or may be formed into a non-planar morphology during manufacturing. As an example, Figure 5B illustrates a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure, according to another embodiment of the present invention.

[0157] Referring to FIG. 5B, an integrated circuit structure includes a first fin 552, such as a silicon fin. The first fin 552 has a lower fin portion 552A, an upper fin portion 552B, and a shoulder feature 554 (on the region between the lower fin portion 552A and the upper fin portion 552B). A second fin 562 (such as a second silicon fin) has a lower fin portion 562A, an upper fin portion 562B, and a shoulder feature 564 (on the region between the lower fin portion 562A and the upper fin portion 562B). A first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end portion 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 further has a second end portion 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. The second insulating layer 576 is directly on the first insulating layer 574, which is directly on the sidewall of the fin portion 552A below the first fin 552 and directly on the sidewall of the fin portion 562A below the second fin 562.

[0158] The dielectric filling material 578 is directly adjacent to the second insulating layer 576, which is directly on the first insulating layer 574. The first insulating layer 574 is directly on the sidewall of the lower fin portion 552A of the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562. In one embodiment, the dielectric filling material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric filling material 578 is lower than at least one of the shoulder features 554 of the first fin 552 and lower than at least one of the shoulder features 564 of the second fin 562, as shown in FIG5B.

[0159] In one embodiment, the first insulating layer 574 is an undoped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 574 comprises silicon and oxygen and contains no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. In one embodiment, the first insulating layer 574 has a thickness in the range of 0.5-2 nanometers.

[0160] In one embodiment, the second insulating layer 576 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the second insulating layer 576 has a thickness in the range of 2-5 nanometers.

[0161] In one embodiment, the dielectric filler material 578 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, a gate electrode is ultimately formed above the top of the fin portion 552B of the first fin 552 and laterally adjacent to the sidewall of the fin portion 552B of the first fin 552, and above the top of the fin portion 562B of the second fin 562 and laterally adjacent to the sidewall of the fin portion 562B of the second fin 562. The gate electrode is further located above the dielectric filler material 578 between the first fin 552 and the second fin 562.

[0162] Figures 6A-6D are cross-sectional views illustrating various operations in the manufacture of the three-layer trench isolation structure, according to embodiments of the present invention.

[0163] Referring to FIG. 6A, a method of manufacturing an integrated circuit structure includes forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on and conformally to the fin 602, as shown in FIG. 6B. In one embodiment, the first insulating layer 604 comprises silicon and oxygen and contains no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0164] Referring to FIG. 6C, the second insulating layer 606 is formed directly on and conformally to the first insulating layer 604. In one embodiment, the second insulating layer 606 comprises silicon and nitrogen. A dielectric filling material 608 is formed directly on the second insulating layer 606, as shown in FIG. 6D.

[0165] In one embodiment, the method further involves a recessed dielectric filler material 608, a first insulating layer 604, and a second insulating layer 606 to provide a fin 602 having an exposed upper fin portion 602A (e.g., upper fin portions 502B, 552B, or 562B in Figures 5A and 5B). The resulting structure may be as described in association with Figures 5A or 5B. In one embodiment, the recessed dielectric filler material 608, the first insulating layer 604, and the second insulating layer 606 involve a wet etching process. In another embodiment, the recessed dielectric filler material 608, the first insulating layer 604, and the second insulating layer 606 involve a plasma etching or dry etching process.

[0166] In one embodiment, the first insulating layer 604 is formed using a chemical vapor deposition process. In one embodiment, the second insulating layer 606 is formed using a chemical vapor deposition process. In one embodiment, the dielectric filler material 608 is formed using a spin-coating process. In such an embodiment, the dielectric filler material 608 is a spin-coated material and is exposed to vapor treatment (e.g., before or after a recess etching process) to provide a hardened material comprising silicon and oxygen. In one embodiment, a gate electrode is ultimately formed on the top of the fin portion above the fin 602 and laterally adjacent to the sidewall of the fin portion above the fin 602.

[0167] In another embodiment, gate sidewall spacer material may be retained above certain trench isolation areas as a protection against erosion of those trench isolation areas during subsequent processing operations. For example, Figures 7A-7E illustrate oblique three-dimensional cross-sectional views of various operations in a method of manufacturing an integrated circuit structure, according to an embodiment of the present invention.

[0168] Referring to FIG. 7A, a method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A gate structure 706 is formed above the upper fin portion 702B and above the insulating structure 704. In one embodiment, the gate structure is a placeholder or virtual gate structure, which includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard shield 706C. A dielectric material 708 is formed conformally to the upper fin portion 702B of the fin 702, conformally to the gate structure 706, and conformally to the insulating structure 704.

[0169] Referring to Figure 7B, a hard mask material 710 is formed over the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-coating process.

[0170] Referring to Figure 7C, the hard masking material 710 is recessed to form a recessed hard masking material 712, exposing a portion of the dielectric material 708, which is conformal to the fin portion 702B above the fin 702 and conformal to the gate structure 706. The recessed hard masking material 712 covers a portion of the dielectric material 708 and is conformal to the insulating structure 704. In one embodiment, the hard masking material 710 is recessed using a wet etching process. In another embodiment, the hard masking material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0171] Referring to Figure 7D, the dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 along the sidewall of the gate structure 706 (becoming the dielectric spacer 714A), along the sidewall of the fin portion 702B above the fin 702, and above the insulating structure 704.

[0172] Referring to Figure 7E, the recessed hard masking material 712 is removed from the structure of Figure 7D. In one embodiment, the gate structure 706 is a virtual gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a stack of gate electrodes. In one embodiment, further processing includes forming an embedded source or drain structure on the opposite side of the gate structure 706, as described in more detail below.

[0173] Referring again to FIG7E, in one embodiment, the integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure further includes a second fin (right 702), such as a second silicon fin, having a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is directly adjacent to the sidewall of the lower fin portion 702A of the first fin and directly adjacent to the sidewall of the lower fin portion 702A of the second fin. A gate electrode 706 is located above the upper fin portion 702B of the first fin (left 702), above the upper fin portion 702B of the second fin (right 702), and above the first portion 704A of the insulating structure 704. The first dielectric spacer 714A is along the sidewall of the fin portion 702B above the first fin (left 702), while the second dielectric spacer 702C is along the sidewall of the fin portion 702B above the second fin (right 702). The second dielectric spacer 714C is connected to the first dielectric spacer 714B above the second portion 704B of the insulating structure 704 located between the first fin (left 702) and the second fin (right 702).

[0174] In one embodiment, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as stoichiometric Si3N4 silicon nitride material, silicon-rich silicon nitride material, or silicon-poor silicon nitride material.

[0175] In one embodiment, the integrated circuit structure 700 further includes embedded source or drain structures on the opposite side of the gate electrode 706, the embedded source or drain structures having a bottom surface below the top surfaces of the first and second dielectric spacers 714B and 714C, along the sidewalls of the fin portions 702B above the first and second fins 702; and the source or drain structures having a top surface above the top surfaces of the first and second dielectric spacers 714B and 714C, along the sidewalls of the fin portions 702B above the first and second fins 702, as described below in association with FIG. 9B. In one embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filling material directly and laterally on the second insulating layer, also as described below in association with FIG. 9B.

[0176] Figures 8A-8F illustrate slightly convex cross-sectional views taken along the a-a' axis of Figure 7E, according to an embodiment of the present invention, of various operations in a method for manufacturing an integrated circuit structure.

[0177] Referring to FIG8A, a method of manufacturing an integrated circuit structure includes forming a fin 702, such as a silicon fin. The fin 702 has a lower fin portion (not shown in FIG8A) and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewall of the lower fin portion 702A of the fin 702. A pair of gate structures 706 are formed above the upper fin portion 702B and above the insulating structure 704. It should be understood that the perspective views shown in FIG8A-8F are slightly highlighted to show portions of the gate structures 706 and the insulating structure, ahead of (outside the page) the upper fin portion 702B, with the upper fin portion slightly inside the page. In one embodiment, the gate structure 706 is a placeholder or virtual gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0178] Referring to Figure 8B, which corresponds to the process operation described in association with Figure 7A, the dielectric material 708 is formed conformally to the fin portion 702B above the fin 702, conformally to the gate structure 706, and conformally to the exposed portion of the insulating structure 704.

[0179] Referring to Figure 8C, which corresponds to the process operation described in association with Figure 7B, a hard mask material 710 is formed over a dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-coating process.

[0180] Referring to Figure 8D, which corresponds to the process operation described in association with Figure 7C, the hard mask material 710 is recessed to form a recessed hard mask material 712, exposing a portion of the dielectric material 708, which is conformal to the fin portion 702B above the fin 702 and conformal to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708, which is conformal to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0181] Referring to Figure 8E, which corresponds to the process operation described in association with Figure 7D, dielectric material 708 is anisotropically etched to form patterned dielectric material 714 along the sidewall of gate structure 706 (becoming part 714A), along the sidewall of fin portion 702B above fin 702, and above insulating structure 704.

[0182] Referring to Figure 8F, which corresponds to the process operation described in association with Figure 7E, the recessed hard mask material 712 is removed from the structure of Figure 8E. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and a stack of gate electrodes. In one embodiment, further processing includes forming an embedded source or drain structure on the opposite side of the gate structure 706, as described in more detail below.

[0183] Referring again to FIG8F, in one embodiment, the integrated circuit structure 700 includes a fin 702, such as a silicon fin, having a lower fin portion (not visible in FIG8F) and an upper fin portion 702B. An insulating structure 704 is directly adjacent to the sidewall of the lower fin portion of the fin 702. A first gate electrode (left 706) is located above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. A second gate electrode (right 706) is located above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. The first dielectric spacer (714A to the right of the left 706) is along the sidewall of the first gate electrode (706), and the second dielectric spacer (714A to the left of the right 706) is along the sidewall of the second gate electrode (706). The second dielectric spacer is connected to the first dielectric spacer above the third part 704A” of the insulating structure 704 between the first gate electrode (706) and the second gate electrode (706).

[0184] Figure 9A illustrates a slightly projecting cross-sectional view along the a-a' axis of Figure 7E, representing an integrated circuit structure including a permanent gate stack and epitaxial source or drain regions, according to an embodiment of the present invention. Figure 9B illustrates a cross-sectional view along the b-b' axis of Figure 7E, representing an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures, according to an embodiment of the present invention.

[0185] Referring to Figures 9A and 9B, in one embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on the opposite side of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surfaces 990 of the first and second dielectric spacers 714B and 714C, along the sidewalls of the fin portions 702B above the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surfaces of the first and second dielectric spacers 714B and 714C, along the sidewalls of the fin portions 702B above the first and second fins 702.

[0186] In one embodiment, the gate stack 706 is a permanent gate stack 920. In such an embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 (such as a working function gate layer), and a gate filler material 926, as shown in FIG9A. In one embodiment, wherein the permanent gate structure 920 is located above the insulating structure 704, the permanent gate structure 920 is formed on a residual polysilicon portion 930, which may be a residual portion of a replacement gate process involving a sacrificial polysilicon gate electrode.

[0187] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 directly on the first insulating layer 902, and a dielectric filling material 906 directly and laterally on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer comprising silicon and oxygen. In one embodiment, the second insulating layer 904 comprises silicon and nitrogen. In one embodiment, the dielectric filling material 906 comprises silicon and oxygen.

[0188] In another embodiment, the epitaxial embedded source or drain region is implemented as the source or drain structure of a semiconductor fin. As an example, FIG10 illustrates a cross-sectional view of an integrated circuit structure taken at the source or drain location, according to an embodiment of the present invention.

[0189] Referring to Figure 10, the integrated circuit structure 1000 includes P-type devices, such as P-type metal-oxide-semiconductor (PMOS) devices. The integrated circuit structure 1000 also includes N-type devices, such as N-type metal-oxide-semiconductor (PMOS) devices.

[0190] The PMOS device of Figure 10 includes a first plurality of semiconductor fins 1002, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, portions above the fins 1002 are removed, and the same or different semiconductor materials are grown to form source or drain structures 1004. It should be understood that the source or drain structure 1004 will appear identical in a cross-sectional view taken from either side of the gate electrode; for example, it will appear substantially identical on the source side as on the drain side. In one embodiment, as shown, the source or drain structure 1004 has a portion below and above the upper surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structure 1004 is strongly faceted. In one embodiment, a conductive contact 1008 is formed above the source or drain structure 1004. However, in one such embodiment, the strong facets and relatively wide growth of the source or drain structure 1004 at least to some extent inhibited the good coverage by the conductive contact 1008.

[0191] The NMOS device of Figure 10 includes a second plurality of semiconductor fins 1052, such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain location, portions above the fins 1052 are removed, and the same or different semiconductor materials are grown to form source or drain structures 1054. It should be understood that the source or drain structure 1054 will appear identical in a cross-sectional view taken from either side of the gate electrode; for example, it will appear substantially identical on the source side as on the drain side. In one embodiment, as shown, the source or drain structure 1054 has a portion below and above the upper surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structure 1054 is weakly faceted relative to the source or drain structure 1004. In one embodiment, a conductive contact 1058 is formed above the source or drain structure 1054. In one such embodiment, the relatively weak facets of the source or drain structure 1054 and the resulting relatively narrow growth (as compared to the source or drain structure 1004) enhance the good coverage of the conductive contact 1058.

[0192] The shape of the source or drain structure of a PMOS device can be modified to increase the contact area with the overlying contacts. For example, Figure 11 illustrates a cross-sectional view of an integrated circuit structure taken at the source or drain location, according to an embodiment of the present invention.

[0193] Referring to FIG11, the integrated circuit structure 1100 includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which may be formed above an upper fin portion such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 on a second side of this first gate electrode opposite to the first side. In one embodiment, the first 1104 and the second epitaxial source or drain structure include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick profile, as shown in FIG11. A first conductive electrode 1108 is located above the first epitaxial source or drain structure 1104.

[0194] Referring again to FIG11, in one embodiment, the integrated circuit structure 1100 also includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is on a first side of the second gate electrode (which may be formed above the upper fin portion of the channel portion of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of this second gate electrode opposite to the first side. In one embodiment, the third 1154 and the fourth epitaxial source or drain structure include silicon and have substantially the same outline as the outline 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is located above the third epitaxial source or drain structure 1154.

[0195] In one embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In one embodiment, the first epitaxial source or drain structure 1104 has a height of about 50 nanometers and a width in the range of 30-35 nanometers. In such an embodiment, the third epitaxial source or drain structure 1154 has a height of about 50 nanometers and a width in the range of 30-35 nanometers.

[0196] In one embodiment, the gradient of the first epitaxial source or drain structure 1104 is from approximately 20% germanium concentration at the bottom 1104A of the first epitaxial source or drain structure 1104 to approximately 45% germanium concentration at the top 1104B of the first epitaxial source or drain structure 1104. In one embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In such an embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0197] Figures 12A-12D illustrate cross-sectional views taken at the source or drain positions and represent various operations in the manufacture of an integrated circuit structure according to embodiments of the present invention.

[0198] Referring to FIG12A, a method of manufacturing an integrated circuit structure includes forming fins, such as silicon fins formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In one embodiment, although not shown, a gate electrode is formed above a portion of the fin portion 1202B on the upper fin 1202, at the position entering the page. This gate electrode has a first side opposite to a second side and defines source or drain positions on those first and second sides. For example, for illustrative purposes, the cross-sectional position of the views in FIG12A-12D is taken at one of the source or drain positions on one of the sides of the gate electrode.

[0199] Referring to Figure 12B, the source or drain position of fin 1202 is recessed to form a recessed fin portion 1206. The recessed source or drain position of fin 1202 may be on one side of the gate electrode and on a second side of the gate electrode. Referring to both Figures 12A and 12B, in one embodiment, a dielectric spacer 1204 is formed along the sidewall of a portion of fin 1202, for example, on one side of the gate structure. In such an embodiment, the recessed fin 1202 relates to the fin 1202 below the top surface 1204A of the recessed dielectric spacer 1204.

[0200] Referring to FIG12C, an epitaxial source or drain structure 1208 is formed on a recessed fin 1206, for example, and thus may be formed on one side of a gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206, on the second side of this gate electrode. In one embodiment, the epitaxial source or drain structure 1208 comprises silicon and germanium and has a matchstick profile, as shown in FIG12C. In one embodiment, a dielectric spacer 1204 is included and is located along the lower portion 1208A of the sidewall of the epitaxial source or drain structure 1208, as shown.

[0201] Referring to FIG12D, a conductive electrode 1210 is formed on an epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filler material 1201B. In one embodiment, the conductive electrode 1210 follows the contour of the epitaxial source or drain structure 1208, as shown. In other embodiments, a portion of the epitaxial source or drain structure 1208 is etched during the fabrication of the conductive electrode 1210.

[0202] In another embodiment, fin trimming isolation (FTI) and a single gate spacing for isolated fins are described. A non-planar transistor system using fins of semiconductor material protruding from a substrate surface utilizes a gate electrode that surrounds two, three, or even all sides of the fin (i.e., dual-gate, triple-gate, nanowire transistors). Source and drain regions are typically formed subsequently in the fin, or as regrowth portions of the fin, on either side of the gate electrode. To isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or space may be formed between two adjacent fins. This isolation gap typically requires some form of masking etching. Once isolated, a gate stack is then patterned over the individual fins, again typically with some form of masking etching (e.g., wire etching or aperture etching according to a particular embodiment).

[0203] One potential problem with the aforementioned fin isolation technology is that the gates are not self-aligned with the ends of the fins, and the alignment of the gate stack pattern and the semiconductor fin pattern relies on the overlap of these two patterns. As a result, lithography overlap tolerance is added to the dimensional adjustments of the semiconductor fins and isolation gaps, requiring the fins to be longer and the isolation gaps to be larger than originally intended, otherwise the intended positioning of the transistor function will be compromised. Device architectures and manufacturing techniques that reduce this excessive dimensional adjustment thus provide a highly advantageous improvement in transistor density.

[0204] Another potential problem with the aforementioned fin isolation technology is that the stress in the semiconductor fins desired to improve carrier mobility may be lost from the channel region of the transistor, where too much fin surface is left empty during manufacturing, allowing for fin strain reduction. The device architecture and manufacturing techniques that maintain a higher level of desired fin stress thus provide a favorable improvement for the performance of nonplanar transistors.

[0205] According to embodiments of the present invention, gate fin isolation architectures and techniques are described herein. In the exemplary embodiments shown, non-planar transistors in a microelectronic device (such as an integrated circuit (IC)) are isolated from each other in a manner self-aligned to the gate electrodes of the transistors. While embodiments of the present invention can be applied to virtually any IC utilizing non-planar transistors, exemplary ICs include (but are not limited to): microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0206] In one embodiment, the ends of adjacent semiconductor fins are electrically isolated from each other by an isolation region, which is disposed relative to the gate electrode using only a patterned mask step. In one embodiment, a single mask is used to form a plurality of sacrificial placeholders with a fixed pitch, a first subset of which defines the location or size of the isolation region and a second subset of which defines the location or size of the gate electrode. In some embodiments, the first subset of the placeholders is removed, and an isolation cut is formed within the semiconductor fin in the opening obtained from the removal of the first subset, while the second subset of the placeholders is ultimately replaced by a non-sacrificial gate electrode stack. Because the subset of placeholders used for gate electrode replacement is used to form the isolation region, the method and the resulting architecture are referred to herein as "through-gate" isolation. One or more of the through-gate isolation embodiments described herein can, for example, enable higher transistor density and higher levels of favorable transistor channel stress.

[0207] By utilizing the isolation defined after the layout or definition of the gate electrode, a higher transistor density can be achieved because the fin isolation size adjustment and layout can be perfectly achieved with the gate electrode at the pitch such that both the gate electrode and the isolation region are integer multiples of the minimum characteristic pitch of a single shielding order. In a further embodiment where the semiconductor fin has a lattice mismatch with the substrate (on which the fin is disposed), a greater level of strain is maintained by the isolation defined after the layout or definition of the gate electrode. For such embodiments, other features of the transistor (such as the gate electrode and additional source or drain material) formed before the ends of the fin are defined to help mechanically maintain fin strain after the isolation cut is formed into the fin.

[0208] To provide further background, transistor scaling can benefit from tighter packaging of cells within a chip. Currently, most cells are isolated from their neighbors by two or more dummy gates (which have embedded fins). These cells are isolated by etching the fins beneath these two or more dummy gates (which connect one cell to another). Scaling can significantly benefit if the number of dummy gates separating adjacent cells can be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins beneath the two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the chip that can be used for the cells. In one embodiment, the method described herein enables the use of only a single dummy gate to separate adjacent cells.

[0209] In one embodiment, the fin trimming isolation method is implemented as a self-aligned patterning scheme. Here, the fins beneath a single gate are etched away. Therefore, adjacent cells can be separated by a single virtual gate. Advantages of this approach include saving on-chip space and allowing for greater computational power for a given area. This approach also allows fin trimming to be performed at sub-fin pitch distances.

[0210] Figures 13A and 13B illustrate plan views showing various operations in a method for patterning fins with multiple gate spacings to form a local isolation structure, according to embodiments of the present invention.

[0211] Referring to Figure 13A, a plurality of fins 1302 are shown having a length along a first direction 1304. It can be seen that the grids 1306 (which have spacings 1307 therebetween) that define the positions for ultimately forming the plurality of gate lines are along a second direction 1308 orthogonal to the first direction 1304.

[0212] Referring to Figure 13B, a portion of the plurality of fins 1302 is cut (e.g., removed by an etching process) to leave fins 1310 with cuts 1312 therein. The isolation structure ultimately formed in the cuts 1312 therefore has a size greater than that of a single gate line, for example, the size of three gate lines 1306. Thus, the gate structure ultimately formed along the location of the gate lines 1306 will be at least partially formed above the isolation structure formed in the cuts 1312. Therefore, the cuts 1312 are relatively wide fin cuts.

[0213] Figures 14A-14D illustrate plan views showing various operations in a method for patterning fins with a single gate spacing to form a local isolation structure, according to another embodiment of the invention.

[0214] Referring to Figure 14A, a method of manufacturing an integrated circuit structure includes forming a plurality of fins 1402, each of which has a longest dimension along a first direction 1404. A plurality of gate structures 1406 are located above the plurality of fins 1402, each of which has a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In one embodiment, the gate structure 1406 is a sacrificial or dummy gate line, for example, manufactured from polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are connected to a portion of an underlying silicon substrate.

[0215] Referring to Figure 14B, dielectric material structure 1410 is formed between adjacent complex gate structures 1406.

[0216] Referring to Figure 14C, a portion 1412 of one of the complex gate structures 1406 is removed to expose a portion 1414 of each of the complex fins 1402. In one embodiment, removing this portion 1412 of one of the complex gate structures 1406 involves using a photomask 1416 that is wider than the width 1418 of this portion 1412 of one of the complex gate structures 1406.

[0217] Referring to Figure 14D, the exposed portions 1414 of each of the plurality of fins 1402 are removed to form a cut area 1420. In one embodiment, the exposed portions 1414 of each of the plurality of fins 1402 are removed using a dry or plasma etching process. In one embodiment, removing the exposed portions 1414 of each of the plurality of fins 1402 involves etching to a depth less than the height of the plurality of fins 1402. In such an embodiment, this depth is greater than the depth of the source or drain regions in the plurality of fins 1402. In one embodiment, this depth is deeper than the depth of the active portions of the plurality of fins 1402 to provide isolation tolerance. In one embodiment, the exposed portions 1414 of each of the plurality of fins 1402 are removed without etching or substantially etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402. In one embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without side-etching or substantially side-etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402.

[0218] In one embodiment, the cut region 1420 is ultimately filled with an insulating layer, for example, at the location of the removed portion 1414 of each of the plurality of fins 1402. Exemplary insulating layers or "polysilicon cuts" or "plugs" structures are described below. However, in other embodiments, the cut region 1420 is only partially filled with an insulating layer, wherein conductive structures are then formed. The conductive structures may be used as local interconnects. In one embodiment, before filling the cut region 1420 with an insulating layer or with an insulating layer for incorporating local interconnect structures, dopants may be implanted or delivered through the cut region 1420 via a solid-source dopant layer into the fin or the local cut portion of the fins.

[0219] Figure 15 illustrates a cross-sectional view of an integrated circuit structure with fins having multiple gate spacings for local isolation, according to an embodiment of the present invention.

[0220] Referring to Figure 15, the silicon fin 1502 has a first fin portion 1504 that is laterally adjacent to a second fin portion 1506. The first fin portion 1504 is separated from the second fin portion 1506 by a relatively wide cut 1508 (as described in association with Figures 13A and 13B), the relatively wide cut 1508 having a width X. A dielectric filler material 1510 is formed in the relatively wide cut 1508 and electrically isolates the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are located above the silicon fin 1502, each of which may include a gate dielectric and gate electrode stack 1514, a dielectric capping layer 1516, and sidewall spacers 1518. The two gate lines (the two gate lines on the left, 1512) occupy a relatively wide cut 1508, and (in this way) the first fin portion 1504 is separated from the second fin portion 1506 by effectively two virtual or inactive gates.

[0221] Conversely, the fin portions can be separated by a single gate spacing. As an example, Figure 16A illustrates a cross-sectional view of an integrated circuit structure with fins having a single gate spacing for local isolation, according to another embodiment of the invention.

[0222] Referring to Figure 16A, the silicon fin 1602 has a first fin portion 1604 that is laterally adjacent to a second fin portion 1606. The first fin portion 1604 is separated from the second fin portion 1606 by a relatively narrow cut 1608, as described in association with Figures 14A-14D, the relatively narrow cut 1608 having a width Y, where Y is smaller than X in Figure 15. A dielectric filler material 1610 is formed in the relatively narrow cut 1608 and electrically isolates the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are located above the silicon fin 1602, each of which may include a gate dielectric and gate electrode stack 1614, a dielectric capping layer 1616, and sidewall spacers 1618. The dielectric filler material 1610 occupies the position where a single gate line previously stood, and the first fin portion 1604 is separated from the second fin portion 1606 by a single "inserted" gate line. In one embodiment, residual spacer material 1620 remains on the sidewall of the location where the gate line portion was removed, as shown. It should be understood that other areas of fin 1602 can be isolated from each other by two or more inactive gate lines (areas 1622 with three inactive gate lines) manufactured by an earlier, wider fin cutting process, as described below.

[0223] Referring again to FIG16A, an integrated circuit structure 1600 includes a fin 1602, such as a silicon fin. The fin 1602 has a longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0224] The first gate structure 1612A is located above the first upper portion 1604 of the fin 1602. The first gate structure 1612A has a longest dimension along a second direction 1652 orthogonal to the first direction 1650 (e.g., entering the page). The center 1613A of the first gate structure 1612A is separated from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. The second gate structure 1612B is located above the first upper portion 1604 of the fin. The second gate structure 1612B has a longest dimension along the second direction 1652. The center 1613B of the second gate structure 1612B is separated from the center 1613A of the first gate structure 1612A by the same pitch along the first direction 1650. The third gate structure 1612C is located above the second upper portion 1606 of the fin 1602, and has the longest dimension along the second direction 1652. The center 1613C of the third gate structure 1612C is separated from the center 1611 of the isolation structure 1610 by the pitch along the first direction 1650. In one embodiment, the isolation structure 1610 has a top that is substantially coplanar with the top of the first gate structure 1612A, the top of the second gate structure 1612B, and the top of the third gate structure 1612C, as shown in the figure.

[0225] In one embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between the sidewall of the high-k gate dielectric layer 1662, as shown for example, the third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewall of the high-k gate dielectric layer 1662.

[0226] In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of a fin 1602 located between a first gate structure 1612A and an isolation structure 1610. A second epitaxial semiconductor region 1664B is located on the first upper portion 1604 of the fin 1602 located between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is located on a second upper portion 1606 of the fin 1602 located between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon and germanium. In another embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon.

[0227] In one embodiment, the isolation structure 1610 induces stress on a first upper portion 1604 and a second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer, wherein conductive structures are subsequently formed. The conductive structures may be used as local interconnects. In one embodiment, before the isolation structure 1610 is formed with an insulating layer or with an insulating layer incorporating local interconnect structures, dopants are implanted or delivered into the fin or local cut portions of the fins via a solid-source dopant layer.

[0228] In another embodiment, it should be understood that isolation structures such as the aforementioned isolation structure 1610 can be formed to replace the active gate electrode at a localized location or a wider location of the fin cut. Furthermore, the depth of these localized or wider locations of the fin cut can be formed to vary relative to the depth within each fin. In the first example, FIG16B illustrates a cross-sectional view showing the location where the fin isolation structure can be formed to replace the gate electrode, according to an embodiment of the invention.

[0229] Referring to Figure 16B, a fin 1680 (such as a silicon fin) is formed on and connected to a substrate 1682. The fin 1680 has a fin tip or a wide fin cut 1684, which may be formed, for example, during fin patterning, such as in the final fin trimming method described above. The fin 1680 also has a partial cut 1686 in which a portion of the fin 1680 is removed, for example, using a fin trimming isolation method in which a dummy gate is replaced with a dielectric plug, as described above. An active gate electrode 1688 is formed above the fin and (for illustrative purposes) is shown slightly in front of the fin 1680 against the background, where the dashed line represents the area covered from the front view. A dielectric plug 1690 may be formed on the fin tip or the wide fin cut 1684 to replace the use of an active gate in these locations. Alternatively, or in an alternative, a dielectric plug 1692 may be formed on the partial cut 1686 instead of using an active gate at this location. It should be understood that an epitaxial source or drain region 1694 is also shown at the location of the fin 1680 between the active gate electrode 1688 and the plug 1690 or 1692. Furthermore, in one embodiment, the surface roughness of the fin tip on the partial cut 1686 is rougher than that of the fin tip at the location of the wider cut, as shown in FIG16B.

[0230] Figures 17A-17C illustrate the various depth possibilities of fin cutting manufactured using fin trimming isolation methods, according to embodiments of the present invention.

[0231] Referring to Figure 17A, a semiconductor fin 1700 (such as a silicon fin) is formed on and connected to a lower substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B, as defined by the height relative to the insulating structure 1704 of the fin 1700. A partial fin isolation cut 1706A separates the fin 1700 from the second fin portion 1712 into the first fin portion 1710. In the example of Figure 17A, as shown along the a-a' axis, the depth of the partial fin isolation cut 1706A is the full depth from the fin 1700 to the substrate 1702.

[0232] Referring to Figure 17B, in the second example, as shown along the a-a' axis, the depth of the partial fin isolation cut 1706B is deeper than the full depth from fin 1700 to base 1702. That is, cut 1706B extends into the underlying base 1702.

[0233] Referring to Figure 17C, in the third example, as shown along the a-a' axis, the depth of the partial fin isolation cut 1706C is less than the full depth of the fin 1700, but deeper than the upper surface of the isolation structure 1704. Referring again to Figure 17C, in the fourth example, as shown along the a-a' axis, the depth of the partial fin isolation cut 1706D is less than the full depth of the fin 1700, and is at a level substantially coplanar with the upper surface of the isolation structure 1704.

[0234] Figure 18 illustrates a plan view and a corresponding cross-sectional view taken along the a-a' axis, showing possible choices of depth for a portion of a fin cut within a fin relative to a wider location, according to an embodiment of the invention.

[0235] Referring to FIG. 18, the first and second semiconductor fins 1800 and 1802 (such as silicon fins) have upper fin portions 1800B and 1802B extending over the insulating structure 1804. Both fins 1800 and 1802 have fin tips or wide fin cuts 1806, which may be formed, for example, at the time of fin patterning, such as in the aforementioned final fin trimming method. Both fins 1800 and 1802 also have partial cuts 1808 in which a portion of one of fins 1800 or 1802 is removed, for example, using a fin trimming isolation method in which a dummy gate is replaced with a dielectric plug, as described above. In one embodiment, the surface roughness of the tips of fins 1800 and 1802 at the partial cut 1808 is rougher than that of the tips of the fins at location 1806, as shown in FIG. 18.

[0236] Referring to the cross-sectional view of Figure 18, the lower fin portions 1800A and 1802A can be viewed below the height of the insulating structure 1804. Also seen in this cross-sectional view are the residual portions 1810 of the fins removed during the final fin trimming process, prior to the formation of the insulating structure 1804, as described above. Although shown protruding above the substrate, the residual portions 1810 may also be at or within the substrate level, as illustrated by the additional wide cut depth 1820 in the example. It should be understood that the wide cuts 1806 of fins 1800 and 1802 may also be at the level described with respect to the cut depth 1820, as illustrated in the example. The partial cut 1808 may have an exemplary depth corresponding to the depths described with respect to Figures 17A-17C, as shown.

[0237] Referring collectively to Figures 16A, 16B, 17A-17C, and 18, according to an embodiment of the present invention, an integrated circuit structure includes a silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along a first direction. A first isolation structure separates the first end of a second portion of the fin from the first end of the first portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. A gate structure includes a gate electrode located above the top of a sidewall of a region of the first portion of the fin and laterally adjacent to the sidewall of the region of the first portion of the fin. The gate structure has a width along the first direction, and the center of the gate structure is isolated from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is located above a second end of the first portion of the fin, the second end being opposite to the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness smaller than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is separated from the center of the gate structure by the pitch along the first direction.

[0238] In one embodiment, the first end of the first portion of the fin has a fan-shaped morphology, as shown in FIG16B. In one embodiment, a first epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction being wider than the width of the first portion of the fin under the gate structure along the second direction, for example, as described in the epitaxial features associated with FIG11 and 12D, having a width wider than the fin portions (on which they are grown in the perspective views shown in FIG11 and 12D). In one embodiment, the gate structure further includes a high-k dielectric layer, between the gate electrode and the first portion of the fin and along the sidewall of the gate electrode.

[0239] Referring collectively to Figures 16A, 16B, 17A-17C, and 18, according to another embodiment of the invention, an integrated circuit structure includes a silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure separates the first end of a second portion of the fin from the first end of the first portion of the fin along the direction. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode located above the top of a sidewall of a region of the first portion of the fin and laterally adjacent to the sidewall of that region of the first portion of the fin. A second isolation structure is located above a second end of the first portion of the fin, the second end being opposite to the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0240] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has the width along the direction. The second isolation structure has the width along the direction. In one embodiment, the center of the gate structure is isolated from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is isolated from the center of the gate structure by a pitch along the direction.

[0241] Referring collectively to Figures 16A, 16B, 17A-17C, and 18, according to another embodiment of the invention, an integrated circuit structure includes a first silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along a direction, and an interruption along that direction separates the first end of the first portion of the first fin from a first end of a second portion of the fin. The first portion of the first fin has a second end opposite to the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second silicon-containing fin having a top and sidewalls, wherein the top has a longest dimension along the direction. The integrated circuit structure also includes a residual or fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, wherein the top has a longest dimension along the direction, and the depth of the top and the first end of the first portion of the fin are not coplanar.

[0242] In one embodiment, the depth of the first end of the first portion of the fin is lower than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is higher than the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth lower than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth higher than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth coplanar with the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth lower than the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth higher than the top of the residual fin portion.

[0243] In another embodiment, the dielectric plug formed at the location of a localized or broad fin cut can be adjusted to provide specific stress for that fin or fin portion. The dielectric plug may be referred to as a fin end stress source in this type of implementation.

[0244] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements for such devices can be achieved through channel stress induced from a polysilicon plug-in filling process. Embodiments may include utilizing the material properties of the polysilicon plug-in filling process to induce mechanical stress in the channels of a metal-oxide-semiconductor (MOSFET). As a result, the induced stress can enhance the transistor's mobility and drive current. Furthermore, a plug-in filling method described herein allows for the removal of any seams or voids formed during deposition.

[0245] To provide background, the unique material properties of the plug filler material used to modulate the intercalation stress within the channel can induce stress. According to one or more embodiments, by tuning the composition, deposition, and post-processing conditions of the plug filler material, the stress within the channel is modulated to benefit both NMOS and PMOS transistors. Furthermore, these plugs can reside deeper within the fin substrate compared to other common stress-generating techniques, such as epitaxial sources or drains. The nature of the plug filler used to achieve this effect also removes seams or voids during deposition and mitigates certain defect modes during the process.

[0246] To provide further background, there is currently no intentional stress engineering for gate (polysilicon) plugs. Stress enhancement from conventional stress sources (such as epitaxial source or drain), virtual polysilicon gate removal, stress lining (etc.) unfortunately tend to decrease as device pitch shrinks. According to one or more embodiments of the present invention to address one or more of the above-mentioned problems, an additional source of stress is incorporated into the transistor structure. Another possible advantage of this process is the removal of seams or voids within the plug (which can be common in other chemical vapor deposition methods).

[0247] Figures 19A and 19B illustrate cross-sectional views of various operations in a method for selecting the location of a stressor at the end of a fin with a wide cut (e.g., as part of the final fin trimming process as described above), according to an embodiment of the present invention.

[0248] Referring to Figure 19A, a fin 1900 (such as a silicon fin) is formed on and connected to a substrate 1902. The fin 1900 has a fin tip or a wide fin cut 1904, which may be formed, for example, during fin patterning, such as in the final fin trimming described above. An active gate electrode position 1906 and a virtual gate electrode position 1908 are formed above the fin 1900 and (for illustrative purposes) are shown slightly in front of the fin 1900 against the background, where the dashed lines represent the area covered from the front view. It should be understood that an epitaxial source or drain region 1910 is also shown at the location of the fin 1900 between gate positions 1906 and 1908. Furthermore, an interlayer dielectric material 1912 is included at the location of the fin 1900 between gate positions 1906 and 1908.

[0249] Referring to Figure 19B, the gate occupant structure or virtual gate location 1908 is removed, exposing the fin tip or wide fin cut 1904. This removal creates an opening 1920 in which a dielectric plug (e.g., a fin tip stress source dielectric plug) can ultimately be formed.

[0250] Figures 20A and 20B illustrate cross-sectional views of various operations in a method for selecting the location of a stressor at the end of a fin with partial cuts (e.g., as part of the fin trimming isolation process described above), according to an embodiment of the present invention.

[0251] Referring to Figure 20A, a fin 2000 (such as a silicon fin) is formed on and connected to a substrate 2002. The fin 2000 has a partial cut 2004 in which a portion of the fin 2000 is removed, for example, using a fin trimming isolation method in which a dummy gate is removed and the fin is etched in the partial location, as described above. Active gate electrode locations 2006 and dummy gate electrode locations 2008 are formed above the fin 2000 and (for illustrative purposes) are shown slightly in front of the fin 2000 against the background, where the dashed lines represent the area covered from the front view. It should be understood that an epitaxial source or drain region 2010 is also shown at the location of the fin 2000 between gate locations 2006 and 2008. In addition, interlayer dielectric material 2012 is included at the position of fin 2000 between gate positions 2006 and 2008.

[0252] Referring to Figure 20B, the gate occupant structure or virtual gate location 2008 is removed, exposing the fin tip with a local cut 2004. This removal creates an opening 2020, in which a dielectric plug (e.g., a fin tip stress source dielectric plug) can ultimately be formed.

[0253] Figures 21A-21M illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure with differential fin end dielectric plugs, according to an embodiment of the present invention.

[0254] Referring to Figure 21A, the initial structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the initial structure 2100 includes a first fin 2102 (such as a first silicon fin) formed on and connected to the substrate 2104. The first fin 2102 has a fin tip 2106, which can be formed from a partial or wide fin cut. A first active gate electrode position 2108 and a first dummy gate electrode position 2110 are formed above the first fin 2102 and (for illustrative purposes) are shown slightly in front of the first fin 2102 against the background, where the dashed lines represent the area covered from the front view. An epitaxial N-type source or drain region 2112 (such as an epitaxial silicon source or drain structure) is also shown at the position of the first fin 2102 between gate positions 2108 and 2110. In addition, interlayer dielectric material 2114 is included at the position of the first fin 2102 between gate positions 2108 and 2110.

[0255] The PMOS region of the initial structure 2100 includes a second fin 2122 (such as a second silicon fin) formed on and connected to the substrate 2104. The second fin 2122 has fin ends 2126, which can be formed from partial or broad fin cuts. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed above the second fin 2122 and (for illustrative purposes) shown slightly in front of the second fin 2122 against the background, where dashed lines represent the area covered from the front view. An epitaxial P-type source or drain region 2132 (such as an epitaxial silicon-germanium source or drain structure) is also shown at the location of the second fin 2122 between gate locations 2128 and 2130. In addition, interlayer dielectric material 2134 is included at the position of the second fin 2122 between gate positions 2128 and 2130.

[0256] Referring to Figure 21B, the first and second dummy gate electrodes at locations 2110 and 2130 are individually removed. During removal, the fin tip 2106 of the first fin 2102 and the fin tip 2126 of the second fin 2122 are exposed. This removal also individually creates openings 2116 and 2136, in which dielectric plugs (e.g., fin tip stress source dielectric plugs) can ultimately be formed.

[0257] Referring to Figure 21C, the material liner 2140 is formed conformally to the structure of Figure 21B. In one embodiment, the material liner includes silicon and nitrogen, such as a silicon nitride material liner.

[0258] Referring to Figure 21D, a protective coronal layer 2142 (such as a metal nitride layer) is formed on the structure of Figure 21C.

[0259] Referring to Figure 21E, a hard mask material 2144 (such as a carbon-based hard mask material) is formed on top of the structure in Figure 21D. A lithography mask or mask stack 2146 is formed on top of the hard mask material 2144.

[0260] Referring to Figure 21F, portions of the hard masking material 2144 and the protective coronal layer 2142 in the PMOS region are removed from the structure in Figure 21E. The lithography mask or mask stack 2146 is also removed.

[0261] Referring to Figure 21G, the second material liner 2148 is formed conformally to the structure of Figure 21F. In one embodiment, the second material liner includes silicon and nitrogen, such as a second silicon nitride material liner. In one embodiment, the second material liner 2148 has different stress states to adjust the stress in the exposed plug.

[0262] Referring to Figure 21H, a second hard masking material 2150 (such as a second carbon-based hard masking material) is formed on top of the structure of Figure 21G and then recessed into the opening 2136 of the PMOS region of the structure.

[0263] Referring to Figure 21I, the second material liner 2148 is etched from the structure of Figure 2H to remove the second material liner 2148 from the NMOS region and recess the second material liner 2148 in the PMOS region of the structure.

[0264] Referring to Figure 2J, the hard mask material 2144, the protective coronal layer 2142, and the second hard mask material 2150 are removed from the structure of Figure 2I. This removal leaves two different filling structures for the opening 2116, as opposed to the opening 2136, individually.

[0265] Referring to Figure 2K, insulating filler material 2152 is formed in openings 2116 and 2136 of the structure in Figure 2J and is planarized. In one embodiment, insulating filler material 2152 is a flowable oxide material, such as flowable silicon oxide or silicon dioxide material.

[0266] Referring to Figure 2L, insulating filler material 2152 is recessed within openings 2116 and 2136 of the structure in Figure 2K to form recessed insulating filler material 2154. In one embodiment, a vapor oxidation process is performed as part of or following the recessing process to harden the recessed insulating filler material 2154. In such an embodiment, the recessed insulating filler material 2154 is reduced in size, inducing tensile stress on fins 2102 and 2122. However, relatively less tensile stress-inducing material exists in the PMOS region compared to the NMOS region.

[0267] Referring to Figure 21M, the third material liner 2156 is located above the structure of Figure 21L. In one embodiment, the third material liner 2156 comprises silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 is used to prevent the recessed insulating filler 2154 from being etched away during subsequent source or drain contact etching.

[0268] Figures 22A-22D are cross-sectional views illustrating an exemplary structure of a PMOS fin end stress source dielectric plug, according to an embodiment of the present invention.

[0269] Referring to Figure 22A, the opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformally fitted to the lower portion of the material liner 2140 and recessed relative to the upper portion of the material liner 2140. A recessed insulating filler material 2154 is located within the second material liner 2148 and has an upper surface coplanar with the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material liner 2148. The third material liner 2156 has a seam 2157, for example, an artificial product of the deposition process for forming the third material liner 2156.

[0270] Referring to Figure 22B, the opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformally fitted to the lower portion of the material liner 2140 and recessed relative to the upper portion of the material liner 2140. A recessed insulating filler material 2154 is located within the second material liner 2148 and has an upper surface coplanar with the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is situated on the upper surface of the insulating filler material 2154 and on the upper surface of the second material liner 2148. The third material liner 2156 has no seams.

[0271] Referring to Figure 22C, the opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformally fitted to the lower portion of the material liner 2140 and recessed relative to the upper portion of the material liner 2140. The recessed insulating filler material 2154 is located within and above the second material liner 2148 and has an upper surface located above the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler material 2154. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0272] Referring to Figure 22D, the opening 2136 on the PMOS region of structure 2100 includes a material liner 2140 along the sidewall of the opening 2136. A second material liner 2148 is conformally fitted to the lower portion of the material liner 2140 and recessed relative to the upper portion of the material liner 2140. A recessed insulating filler 2154 is located within the second material liner 2148 and has an upper surface recessed below the upper surface of the second material liner 2148. A third material liner 2156 is located within the upper portion of the material liner 2140 and is located on the upper surface of the insulating filler 2154 and on the upper surface of the second material liner 2148. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0273] Referring collectively to Figures 19A, 19B, 20A, 20B, 21A-21M, and 22A-22D, according to an embodiment of the present invention, an integrated circuit structure includes a fin (such as silicon) having a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is located above a first end of the fin. A gate structure includes a gate electrode located above the top of the sidewall of a region of the fin and laterally adjacent to the sidewall of that region of the fin. The gate structure is isolated from the first isolation structure along the direction. A second isolation structure is located above a second end of the fin, opposite to the first end. The second isolation structure is isolated from the gate structure along the direction. Both the first and second isolation structures include a first dielectric material (e.g., material liner 2140) laterally surrounding a recessed second dielectric material (e.g., a second material liner 2148) that is different from the first dielectric material. The recessed second dielectric material is laterally surrounding at least a portion of a third dielectric material (e.g., the recessed insulating filler material 2154) that is different from the first and second dielectric materials.

[0274] In one embodiment, both the first and second isolation structures further include a fourth dielectric material (e.g., a third material liner 2156) laterally surrounded by the upper portion of the first dielectric material, the fourth dielectric material being located on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further located on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a substantially vertical central seam. In yet another such embodiment, the fourth dielectric material has no seam.

[0275] In one such embodiment, the third dielectric material has an upper surface coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface lower than the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface higher than the upper surface of the second dielectric material, and the third dielectric material is further located above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0276] In one embodiment, the first isolation structure has a width along the direction, the gate structure has the width along the direction, and the second isolation structure has the width along the direction. In such an embodiment, the center of the gate structure is isolated from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is isolated from the center of the gate structure by a pitch along the direction. In one embodiment, both the first and second isolation structures are located in corresponding trenches in the interlayer dielectric layer.

[0277] In one such embodiment, a first source or drain region is located between the gate structure and the first isolation structure. A second source or drain region is located between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer located between the gate electrode and the fin and along the sidewall of the gate electrode.

[0278] In another embodiment, the depth of individual dielectric plugs may vary within the semiconductor structure or within an architecture formed on a common substrate. As an example, FIG23A illustrates a cross-sectional view of another semiconductor structure with fin-end stress-sensing characteristics, according to another embodiment of the invention. Referring to FIG23A, a shallow dielectric plug 2308A is included, together with a pair of deep dielectric plugs 2308B and 2308C. In such an embodiment, as shown, the depth of the shallow dielectric plug 2308C is substantially equal to the depth of the semiconductor fin 2302 within the substrate 2304, while the depths of the pair of deep dielectric plugs 2308B and 2308C are less than the depth of the semiconductor fin 2302 within the substrate 2304.

[0279] Referring again to Figure 23A, this configuration enables stress amplification on a fin trimming isolation (FTI) device in a trench, which is etched deeper into the substrate 2304 to provide isolation between adjacent fins 2302. This can be implemented to increase the density of transistors on the wafer. In one embodiment, the stress effect induced on the plug-filled transistors is amplified in the FTI transistors because stress transfer occurs in the fins and in the substrate or well beneath the transistors.

[0280] In another embodiment, the width or amount of the tensile stress-sensing oxide layer included in the dielectric plug can be varied within the semiconductor structure or within an architecture formed on a common substrate, for example, depending on whether the device is a PMOS or NMOS device. As an example, FIG23B illustrates a cross-sectional view of another semiconductor structure having fin-end stress-sensing characteristics, according to another embodiment of the invention. Referring to FIG23B, in a particular embodiment, the NMOS device includes a relatively larger tensile stress-sensing oxide layer 2350 compared to the corresponding PMOS device.

[0281] Referring again to Figure 23B, in one embodiment, differential plug filling is implemented to sense appropriate stress in the NMOS and PMOS. For example, NMOS plugs 2308D and 2308E have a larger volume and wider tensile stress-sensing oxide layer 2350 compared to PMOS plugs 2308F and 2308G. Plug filling can be patterned to sense different stresses in the NMOS and PMOS devices. For example, photolithography can be used to open up the PMOS device (e.g., widen the dielectric plug trench of the PMOS device), at which point different filling options can be implemented to differentiate the plug filling in the NMOS relative to the PMOS device. In an exemplary embodiment, reducing the volume of flowable oxide in the plug on the PMOS device can reduce the induced tensile stress. In one such embodiment, compressive stress can be dominant, for example, from the compressive stress source and drain regions. In other embodiments, the use of different plug liners or different plug materials provides tunable stress control.

[0282] As described above, it should be understood that polysilicon plug stress effects can contribute to both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to embodiments of the invention, the semiconductor fins are uniaxially stressed semiconductor fins. Uniaxially stressed semiconductor fins can be uniaxially stressed under tensile or compressive stress. For example, FIG24A illustrates an oblique view of a fin with tensile uniaxial stress, and FIG24B illustrates an oblique view of a fin with compressive uniaxial stress, according to one or more embodiments of the invention.

[0283] Referring to Figure 24A, the semiconductor fin 2400 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2400 on either side of the channel region (C). The discrete channel region of the semiconductor fin 2400 has a current direction (pointing away from each other and towards the ends 2402 and 2404) along the direction of uniaxial tensile stress, from the source region (S) to the drain region (D).

[0284] Referring to Figure 24B, the semiconductor fin 2450 has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2450 on either side of the channel region (C). The discrete channel region of the semiconductor fin 2450 has a current direction (pointing towards each other and away from the arrows at ends 2452 and 2454) along the direction of uniaxial compressive stress, from the source region (S) to the drain region (D). Therefore, the embodiments described herein can be implemented to improve transistor mobility and drive current, allowing for faster circuit and chip execution.

[0285] In another embodiment, a relationship may exist between the locations where gate wire cutting (polysilicon cutting) is performed and fin trimming isolation (FTI) partial fin cutting is performed. In one embodiment, FTI partial fin cutting is performed only at the locations where polysilicon cutting is performed. However, in such an embodiment, FTI cutting may not necessarily be performed at every location where polysilicon cutting is performed.

[0286] Figures 25A and 25B illustrate plan views showing various operations in a method for patterning fins with a single gate spacing at a selected gate line cut position to form a local isolation structure, according to embodiments of the present invention.

[0287] Referring to Figure 25A, a method of manufacturing an integrated circuit structure includes forming a plurality of fins 2502, each of which has a longest dimension along a first direction 2504. A plurality of gate structures 2506 are located above the plurality of fins 2502, each of which has a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In one embodiment, the gate structure 2506 is a sacrificial or dummy gate line, for example, manufactured from polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are connected to a portion of an underlying silicon substrate.

[0288] Referring again to FIG. 25A, a dielectric material structure 2510 is formed between adjacent members of the plurality of gate structures 2506. Portions 2512 and 2513 of two of the plurality of gate structures 2506 are removed to expose portions of each of the plurality of fins 2502. In one embodiment, removing these portions 2512 and 2513 of the plurality of gate structures 2506 involves using a photolithography window wider than the width of each of these portions 2512 and 2513 of the gate structures 2506. The exposed portions of each of the plurality of fins 2502 at location 2512 are removed to form a cut area 2520. In one embodiment, the exposed portions of each of the plurality of fins 2502 are removed using a dry or plasma etching process. However, the exposed portions of each of the plurality of fins 2502 at location 2513 are masked to prevent removal. In one embodiment, regions 2512 / 2520 represent both polysilicon dicing and FTI partial fin dicing. However, position 2513 represents polysilicon dicing only.

[0289] Referring to Figure 25B, the polysilicon cut and FTI partial fin cut locations 2512 / 2520 and the polysilicon cut location 2513 are filled with an insulating structure 2530, such as a dielectric plug. Exemplary insulating structures or "polysilicon cuts" or "plugs" structures are described below.

[0290] Figures 26A-26C illustrate cross-sectional views of various possibilities for polysilicon dicing and FTI partial fin dicing locations in different regions of the structure of Figure 25B, as well as dielectric plugs at polysilicon dicing locations only, according to embodiments of the present invention.

[0291] Referring to Figure 26A, a cross-sectional view of portion 2600A of the dielectric plug 2530 at position 2513 is shown along axis a-a' of the structure in Figure 25B. Portion 2600A of the dielectric plug 2530 is shown on the uncut fins 2502 and between the dielectric material structures 2510.

[0292] Referring to Figure 26B, a cross-sectional view of portion 2600B of the dielectric plug 2530 at position 2512 is shown along the b-b' axis of the structure in Figure 25B. Portion 2600B of the dielectric plug 2530 is shown at the cut fin position 2520 and between the dielectric material structures 2510.

[0293] Referring to Figure 26C, a cross-sectional view of a portion 2600C of the dielectric plug 2530 at position 2512 is shown along the c-c' axis of the structure in Figure 25B. The portion 2600C of the dielectric plug 2530 is shown on a trench isolation structure 2602 between fins 2502 and between dielectric material structures 2510. In one embodiment, an example of which is described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating filler material 2602C on the second insulating layer 2602B.

[0294] Referring collectively to Figures 25A, 25B, and 26A-26C, according to an embodiment of the present invention, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, each of which is along a first direction. A plurality of gate structures are formed above the plurality of fins, each of which is along a second direction orthogonal to the first direction. Dielectric material structures are formed between adjacent gate structures. A portion of a first gate structure is removed to expose a first portion of each of the plurality of fins. A portion of a second gate structure is removed to expose a second portion of each of the plurality of fins. The exposed first portions of each of the plurality of fins are removed, but the exposed second portions of each of the plurality of fins are not removed. A first insulating structure is formed in the locations where the first portions of the plurality of fins have been removed. A second insulating structure is formed in the locations where the second portions of the plurality of gate structures have been removed.

[0295] In one embodiment, removing portions of the first and second of the plurality of gate structures involves using a photomask wider than the width of each portion of the first and second of the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth at least equal to the height of the plurality of fins. In such an embodiment, this depth is greater than the depth of the source or drain regions in the plurality of fins. In one embodiment, the plurality of fins comprises silicon and is connected to a portion of a silicon substrate.

[0296] Referring collectively to Figures 16A, 25A, 25B, and 26A-26C, according to another embodiment of the invention, the integrated circuit structure includes a silicon-containing fin having a longest dimension along a first direction. An isolation structure is located above the upper portion of the fin, having a center along the first direction. A first gate structure is located above the upper portion of the fin, having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is separated from its center by a pitch along the first direction. A second gate structure is located above the upper portion of the fin, having a longest dimension along the second direction. The center of the second gate structure is separated from its center by the pitch along the first direction. A third gate structure is located above the upper portion of the fin, opposite to the isolation structure from the first and second gate structures, having a longest dimension along the second direction. The center of the third gate structure is separated from the center of the gate structure by the pitch along the first direction.

[0297] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between the sidewalls of the high-k gate dielectric layer. In another such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating capping on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0298] In one embodiment, a first epitaxial semiconductor region is located on the upper portion of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is located on the upper portion of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is located on the upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0299] Referring collectively to Figures 16A, 25A, 25B, and 26A-26C, according to another embodiment of the invention, the integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure having a longest dimension along a first direction. An isolation structure is located on the STI structure, the isolation structure having a center along the first direction. A first gate structure is located on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is separated from the center of the gate structure by a pitch along the first direction. A second gate structure is located on the STI structure, the second gate structure having a longest dimension along the second direction. The center of the second gate structure is separated from the center of the first gate structure by the pitch along the first direction. A third gate structure is located on the STI structure, opposite to the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is separated from the center of the isolation structure by the pitch along the first direction.

[0300] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between the sidewalls of the high-k gate dielectric layer. In another embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating capping on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0301] In another configuration, whether polysilicon cutting is combined with FTI partial fin cutting or polysilicon cutting is performed alone, the insulating structure or dielectric plug used to fill the cutting position can extend laterally into or even beyond the dielectric spacer of the corresponding cut gate line.

[0302] In a first example in which the trench contact shape is not affected by the polysilicon-cut dielectric plug, FIG27A illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate wire cut having a dielectric plug extending into a dielectric spacer of the gate wire, according to an embodiment of the present invention.

[0303] Referring to Figure 27A, the integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulating material 2706 is located between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is located above the first silicon fin 2702 and above the second silicon fin 2704, along a second direction 2709, which is orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. Gate line 2708 has an interruption 2710 above insulating material 2706, between a first end 2708C and a second end 2708D of gate line 2708. Interruption 2710 is filled with a dielectric plug 2712.

[0304] The trench contact 2714 is located above the first silicon fin 2702 and above the second silicon fin 2704, along the second direction 2709, on the first side 2708A of the gate line 2708. The trench contact 2714 is connected above the insulating material 2706, and is laterally adjacent to the dielectric plug 2712 at position 2715. The dielectric spacer 2716 is laterally located between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is connected along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712, which is narrower than the width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0305] In one embodiment, the second trench contact 2718 is located above the first silicon fin 2702 and above the second silicon fin 2704, along the second direction 2709, on the second side 2708B of the gate line 2708. The second trench contact 2718 is connected above the insulating material 2706, at a position 2719 laterally adjacent to the dielectric plug 2712. In such an embodiment, the second dielectric spacer 2720 is laterally located between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is connected along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712, which is narrower than the width laterally adjacent to the second side 2708B of the gate line 2708.

[0306] In one embodiment, the gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric capping layer 2726. In one embodiment, the dielectric plug 2712 includes the same material as the dielectric spacer 2714 but is separated from the dielectric spacer 2714. In one embodiment, the dielectric plug 2712 includes a different material from the dielectric spacer 2714.

[0307] In a second example in which the trench contact shape is not affected by the polysilicon-cut dielectric plug, Figure 27B illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure with a gate wire cut having a dielectric plug extending beyond the dielectric spacer of the gate wire, according to another embodiment of the invention.

[0308] Referring to Figure 27B, the integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulating material 2756 is located between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is located above the first silicon fin 2752 and above the second silicon fin 2754, along a second direction 2759, which is orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. Gate line 2758 has an interruption 2760 above insulating material 2756, between a first end 2758C and a second end 2758D of gate line 2758. Interruption 2760 is filled with a dielectric plug 2762.

[0309] The trench contact 2764 is located above the first silicon fin 2752 and above the second silicon fin 2754, along the second direction 2759, on the first side 2758A of the gate line 2758. The trench contact 2764 is connected above the insulating material 2756, laterally adjacent to the dielectric plug 2762 at position 2765. The dielectric spacer 2766 is laterally located between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is a dielectric spacer 2766 that is interrupted along the first side 2758A of the gate line 2758 but not along the dielectric plug 2762. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762, which is narrower than the width (W2) laterally adjacent to the dielectric spacer 2766.

[0310] In one embodiment, the second trench contact 2768 is located above the first silicon fin 2752 and above the second silicon fin 2754, along the second direction 2759, on the second side 2758B of the gate line 2758. The second trench contact 2768 is connected above the insulating material 2756, laterally adjacent to the position 2769 of the dielectric plug 2762. In such an embodiment, the second dielectric spacer 2770 is laterally located between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is a dielectric spacer 2770 that is interrupted along the second side 2758B of the gate line 2758 but not along the dielectric plug 2762. The second groove contact 2768 has a width that is laterally adjacent to the dielectric plug 2762, which is narrower than the width that is laterally adjacent to the second dielectric spacer 2770.

[0311] In one embodiment, the gate line 2758 includes a high-k gate dielectric layer 2772, a gate electrode 2774, and a dielectric capping layer 2776. In one embodiment, the dielectric plug 2762 includes the same material as the dielectric spacer 2764 but is separated from the dielectric spacer 2764. In one embodiment, the dielectric plug 2762 includes a different material from the dielectric spacer 2764.

[0312] In a third example where the dielectric plug at the polysilicon cut position gradually tapers from the top to the bottom of the plug, Figures 28A-28F illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure with a gate wire cut having a dielectric plug having an upper portion of dielectric spacers extending beyond the gate wire and a lower portion of the dielectric spacers extending into the gate wire, according to another embodiment of the invention.

[0313] Referring to Figure 28A, a plurality of gate lines 2802 are formed over a structure 2804, such as over a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, for example, having a dummy gate electrode 2806 and a dielectric cap 2808. Portions of these sacrificial or dummy gate lines may be later replaced in a gate replacement process, for example, following the formation of the dielectric plug as described below. Dielectric spacers 2810 are along the sidewalls of the gate lines 2802. Dielectric material 2812 (such as an inter-dielectric layer) is interposed between the gate lines 2802. A mask 2814 is formed and photolithographically patterned to expose a portion of one of the gate lines 2802.

[0314] Referring to Figure 28B, as the mask 2814 is in place, the central gate line 2802 is removed by an etching process. The mask 2814 is then removed. In one embodiment, the etching process erodes a portion of the dielectric spacer 2810 over which the gate line 2802 has been removed, forming a reduced dielectric spacer 2816. Furthermore, the upper portion of the dielectric material 2812 exposed by the mask 2814 is etched in the etching process, forming an etched dielectric material portion 2818. In a particular embodiment, residual dummy gate material 2820 (such as residual polysilicon) remains in the structure as an artifact of an incomplete etching process.

[0315] Referring to Figure 28C, a hard mask 2822 is formed above the structure of Figure 28B. The hard mask 2822 is conformal with the upper part of the structure of Figure 2B, and in particular, conformal with the etched dielectric material portion 2818.

[0316] Referring to Figure 28D, the residual dummy gate material 2820 is removed, for example, by an etching process that may be chemically similar to the etching process used to remove the central gate line 2802. In one embodiment, a hard mask 2822 protects the etched dielectric material portion 2818 from further erosion during the removal of the residual dummy gate material 2820.

[0317] Referring to Figure 28E, the hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed without further erosion of the dielectric material portion 2818, or substantially without erosion.

[0318] Referring to Figure 28F, a dielectric plug 2830 is formed in the opening of the structure of Figure 28E. The upper portion of the dielectric plug 2830 is located above the eroded dielectric material portion 2818, for example, effectively extending beyond the original spacer 2810. The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, effectively entering but not exceeding the original spacer 2810. As a result, the dielectric plug 2830 has a tapered profile, as shown in Figure 28F. It should be understood that the dielectric plug 2830 can be manufactured from the materials and processes described above for other polysilicon dicing or FTI plugs or fin end stress sources.

[0319] In another embodiment, a portion of the vacant gate structure or dummy gate structure may be left above the trench isolation region beneath the permanent gate structure as protection against erosion of the trench isolation region during the gate replacement process. For example, Figures 29A-29C illustrate a plan view and corresponding cross-sectional view of an integrated circuit structure having residual dummy gate material on a portion at the bottom of a permanent gate stack, according to an embodiment of the present invention.

[0320] Referring to Figures 29A-29C, an integrated circuit structure includes a fin 2902, such as a silicon fin protruding from a semiconductor substrate 2904. The fin 2902 has a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and a sidewall 2902D. An isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulating material 2906C having a top surface 2907. A semiconductor material 2908 is located on a portion of the top surface 2907 of the insulating material 2906C. The semiconductor material 2908 is separated from the fin 2902.

[0321] The gate dielectric layer 2910 is located above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further located on the semiconductor material 2908 on this portion of the top surface 2907 of the insulating material 2906C. An intermediate additional gate dielectric layer 2911 (such as the oxide portion of the fin 2902) may be located between the gate dielectric layers 2910 above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is located above the gate dielectric layer 2910 above the top 2902C of the upper fin portion 2902A and laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is further located above the gate dielectric layer 2910 on the semiconductor material 2908 on this portion of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, while a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side being opposite to the first side. In one embodiment, an example of which is described above, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2906C.

[0322] In one embodiment, the semiconductor material 2908 on this portion of the top surface 2907 of the insulating material 2906C is (or includes) polycrystalline silicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a recess (as shown), and the semiconductor material 2908 is located in the recess. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A and 2906B) along the bottom and sidewalls of the insulating material 2906C. In such an embodiment, this portion of the second insulating material (2906A or 2906B or both 2906A and 2906B) along the sidewalls of the insulating material 2906C has a top surface above the uppermost surface of the insulating material 2906C, as shown. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A and 2906B) is located above or coplanar with the top surface of the semiconductor material 2908.

[0323] In one embodiment, the semiconductor material 2908 on this portion of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910. That is, from a plan view view, the position of the semiconductor material 2908 is confined to the area covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along a first side of the gate electrode 2912. The second dielectric spacer 2922 is along a second side of the gate electrode 2912. In such an embodiment, the gate dielectric layer 2910 further extends along the sidewalls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown in FIG29B.

[0324] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a working function layer). In one such embodiment, the working function layer 2912A includes titanium and nitrogen. In another embodiment, the working function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive filler metal layer 2912B over the working function layer 2912A. In one such embodiment, the conductive filler metal layer 2912B includes tungsten. In a particular embodiment, the conductive filler metal layer 2912B includes 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is located on the gate electrode 2912 and may extend over the gate dielectric layer 2910, as shown in FIG29B.

[0325] Figures 30A-30D illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having residual virtual gate material on a portion of the bottom of a permanent gate stack, according to another embodiment of the invention. The perspective view shows a portion along the a-a' axis of the structure in Figure 29C.

[0326] Referring to FIG. 30A, a method of manufacturing an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and a sidewall 3000D. An isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005. A vacant gate electrode 3006 is located above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The vacant gate electrode 3006 includes a semiconductor material.

[0327] Although not shown in the perspective view of Figure 30A (but its location is shown in Figure 29C), a first source or drain region may be formed adjacent to a first side of the vacant gate electrode 3006, and a second source or drain region may be formed adjacent to a second side of the vacant gate electrode 3006, the second side being opposite to the first side. Furthermore, gate dielectric spacers may be formed along the sidewalls of the vacant gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the vacant gate electrode 3006.

[0328] In one embodiment, the vacant gate electrode 3006 is (or includes) polycrystalline silicon. In one embodiment, the top surface 3005 of the insulating material 3004C of the isolation structure 3004 has a recess, as shown. A portion of the vacant gate electrode 3006 is located in the recess. In one embodiment, the isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A and 3004B) along the bottom and sidewalls of the insulating material 3004C, as shown. In such an embodiment, the portion of the second insulating material (3004A or 3004B or both 3004A and 3004B) along the sidewalls of the insulating material 3004C has a top surface above at least a portion of the top surface 3005 of the insulating material 3004C. In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A and 3004B) is located above the lowest surface of a portion of the occupying gate electrode 3006.

[0329] Referring to Figure 30B, the vacant gate electrode 3006 is etched from above the top 3000C and sidewall 3000D of the upper fin portion 3000B, for example, along direction 3008 of Figure 30A. This etching process may be referred to as a gate replacement process. In one embodiment, the etching or gate replacement process is incomplete, leaving a portion 3012 of the vacant gate electrode 3006 on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0330] Referring to Figures 30A and 30B, in one embodiment, the oxide portion 3010 of the upper fin portion 3000B formed before the formation of the vacant gate electrode 3006 is retained during the etching process, as shown. However, in another embodiment, a vacant gate dielectric layer is formed before the formation of the vacant gate electrode 3006, and this vacant gate dielectric layer is removed immediately after etching the vacant gate electrode.

[0331] Referring to Figure 30C, a gate dielectric layer 3014 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, the gate dielectric layer 3014 is formed on the oxide portion 3010 of the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, as shown. In another embodiment, the gate dielectric layer 3014 is formed directly on the upper fin portion 3000B above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, in the case where the oxide portion 3010 of the upper fin portion 3000B is removed after etching the occupier gate electrode. In any case, in one embodiment, the gate dielectric layer 3014 is further formed on the portion 3012 of the occupied gate electrode 3006 on the top surface 3005 of the insulating material 3004C of the isolation structure 3004.

[0332] Referring to Figure 30D, a permanent gate electrode 3016 is formed above the gate dielectric layer 3014 above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. The permanent gate electrode 3016 is further located above the gate dielectric layer 3014 on the portion 3012 of the occupier gate electrode 3006 on the top surface 3005 of the insulating material 3004C.

[0333] In one embodiment, forming the permanent gate electrode 3016 includes forming a working function layer 3016A. In one such embodiment, the working function layer 3016A includes titanium and nitrogen. In another such embodiment, the working function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive filler metal layer 3016B formed over the working function layer 3016A. In one such embodiment, forming the conductive filler metal layer 3016B includes using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor to form a tungsten-containing film. In one embodiment, an insulating gate cap layer 3018 is formed on the permanent gate electrode 3016.

[0334] In another embodiment, some embodiments of the present invention include an amorphous high-k layer in the gate dielectric structure of the gate electrode. In other embodiments, a partially or fully crystalline high-k layer is included in the gate dielectric structure of the gate electrode. In one embodiment in which a partially or fully crystalline high-k layer is included, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment in which a partially or fully crystalline high-k layer is included, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0335] In one embodiment, various methods are described herein to increase the charge in the device channels and improve sub-threshold behavior by employing ferroelectric or antiferroelectric gate oxides. Ferroelectric and antiferroelectric gate oxides can increase the channel charge to allow for higher currents and can also perform steeper turn-on behavior.

[0336] For background, hafnium or zirconium (Hf or Zr)-based ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT), thus enabling compatibility with highly scalable logic technologies. Two characteristics of FE or AFE materials enhance the performance of logic transistors: (1) higher charge in the channels achieved by FE or AFE polarization and (2) steeper turn-on behavior due to rapid FE or AFE transitions. These properties can be improved by increasing current and reducing subcritical oscillation (SS).

[0337] Figure 31A illustrates a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure, according to an embodiment of the present invention.

[0338] Referring to FIG. 31A, an integrated circuit structure 3100 includes a gate structure 3102 on a substrate 3104. In one embodiment, the gate structure 3102 is located on or above a semiconductor channel structure 3106 comprising a single-crystal material (such as single-crystal silicon). The gate structure 3102 includes a gate dielectric above the semiconductor channel structure 3106 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes metal and may be a barrier layer, a working function layer, or a template layer, which enhances the crystallization of the FE or AFE layer. A gate fill layer or multiple layers 3102C are located on or above the conductive layer 3102B. Source region 3108 and drain region 3110 are located on opposite sides of gate structure 3102. Source or drain contact 3112 is electrically connected to source region 3108 and drain region 3110 at location 3149 and isolated from gate structure 3102 by one or both of interlayer dielectric layer 3114 and gate dielectric spacer 3116. In the example of FIG. 31A, source region 3108 and drain region 3110 are regions of substrate 3104. In one embodiment, source or drain contact 3112 includes barrier layer 3112A and conductive trench filler material 3112B. In one embodiment, ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along dielectric spacer 3116, as shown in FIG. 31A.

[0339] In one embodiment, and as applicable throughout the invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf having a Zr:Hf ratio of 50:50 or more. The ferroelectric effect may increase with increasing orthorhombic crystal content. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystal content.

[0340] In one embodiment, and as applicable throughout the invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf having a Zr:Hf ratio of 80:20 or more (and even up to 100% Zr, ZrO 2). In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystals.

[0341] In one embodiment, and as applicable throughout the invention, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103, such as a natural silicon oxide layer, a high-k dielectric (HfOx, Al₂O₃, etc.), or a combination of oxides and high-k, situated between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In one embodiment, and as applicable throughout the invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness ranging from 1 nanometer to 8 nanometers. In one embodiment, and as applicable throughout the invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size ranging from about 20 nanometers or more.

[0342] In one embodiment, following the deposition of the ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example by atomic layer deposition (ALD), a layer comprising a metal (e.g., layer 3102B, such as 5-10 nanometer titanium nitride, tantalum nitride, or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then performed. In one embodiment, annealing is performed for a duration ranging from 1 millisecond to 30 minutes. In one embodiment, annealing is performed at a temperature ranging from 500 to 1100 degrees Celsius.

[0343] Figure 31B illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure, according to another embodiment of the present invention.

[0344] Referring to FIG. 31B, an integrated circuit structure 3150 includes a gate structure 3152 on a substrate 3154. In one embodiment, the gate structure 3152 is located on or above a semiconductor channel structure 3156 comprising a single-crystal material (such as single-crystal silicon). The gate structure 3152 includes a gate dielectric above the semiconductor channel structure 3156 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or a working function layer. A gate fill layer or multiple layers 3152C are located on or above the conductive layer 3152B. The abrupt source region 3158 and the abrupt drain region 3160 (such as regions of semiconductor material different from that of the semiconductor channel structure 3156) are located on opposite sides of the gate structure 3152. A source or drain contact 3162 is electrically connected to the source region 3158 and drain region 3160 at location 3199 and is isolated from the gate structure 3152 by one or both of an interlayer dielectric layer 3164 and a gate dielectric spacer 3166. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench filler material 3162B. In one embodiment, a ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166, as shown in FIG31B.

[0345] Figure 32A illustrates a plan view of a plurality of gate lines above a pair of semiconductor fins, according to another embodiment of the present invention.

[0346] Referring to Figure 32A, a plurality of active gate lines 3204 are formed above a plurality of semiconductor fins 3200. A dummy gate line 3206 is located at the end of the plurality of semiconductor fins 3200. A spacing 3208 between the gate lines 3204 / 3206 provides a location where trench contacts can be configured to provide conductive contacts leading to source or drain regions (such as source or drain regions 3251, 3252, 3253, and 3254). In one embodiment, the pattern of the plurality of gate lines 3204 / 3206 or the pattern of the plurality of semiconductor fins 3200 is described as a grating structure. In one embodiment, the grating pattern includes the plurality of gate lines 3204 / 3206 or a pattern of the plurality of semiconductor fins 3200 spaced at a constant pitch and having a constant width (or both).

[0347] Figure 32B illustrates a cross-sectional view taken along axis a-a' of Figure 32A, according to an embodiment of the present invention.

[0348] Referring to Figure 32B, a plurality of active gate lines 3264 are formed above a plurality of semiconductor fins 3262 (which are formed on a substrate 3260). A dummy gate line 3266 is located at the end of the semiconductor fin 3262. A dielectric layer 3270 is located outside the dummy gate lines 3266. A trench contact material 3297 is located between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. An embedded source or drain structure 3268 is located within the semiconductor fins 3262 between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0349] The active gate line 3264 includes a gate dielectric structure 3272, a working function gate electrode portion 3274, a filled gate electrode portion 3276, and a dielectric capping layer 3278. Dielectric spacers 3280 fill the sidewalls of the active gate line 3264 and the virtual gate line 3266. In one embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0350] In another embodiment, devices of the same conductivity type (e.g., N-type or P-type) may have distinct gate electrode stacks for the same conductivity type. However, for comparative purposes, devices of the same conductivity type may have a differential voltage threshold (VT) depending on modulation doping.

[0351] Figure 33A illustrates a cross-sectional view of a pair of NMOS devices having differential voltage thresholds based on modulation doping, and a pair of PMOS devices having differential voltage thresholds based on modulation doping, according to an embodiment of the present invention.

[0352] Referring to Figure 33A, a first NMOS device 3302 is adjacent to a second NMOS device 3304 above a semiconductor active region 3300, such as above a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308 (such as a duty function layer), and a gate electrode conductive fill 3310. In one embodiment, the first gate electrode conductive layers 3308 of the first NMOS device 3302 and the second NMOS device 3304 are made of the same material and have the same thickness, thus having the same duty function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In such an embodiment, the first NMOS device 3302 is referred to as a "standard VT" device, and the second NMOS device 3304 is referred to as a "high VT" device. In one embodiment, differential VT is achieved by using modulation or differential implantation doping on region 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0353] Referring to Figure 33A, a first PMOS device 3322 is adjacent to a second PMOS device 3324 above a semiconductor active region 3320, such as above a silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 (such as a duty function layer), and a gate electrode conductive fill 3330. In one embodiment, the first gate electrode conductive layers 3328 of the first PMOS device 3322 and the second PMOS device 3324 are made of the same material and have the same thickness, thus having the same duty function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In such an embodiment, the first PMOS device 3322 is referred to as a "standard VT" device, and the second PMOS device 3324 is referred to as a "low VT" device. In one embodiment, differential VT is achieved by using modulation or differential implantation doping on regions 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0354] In contrast to FIG33A, FIG33B illustrates cross-sectional views of a pair of NMOS devices having differential voltage thresholds according to a differential gate electrode structure and a pair of PMOS devices having differential voltage thresholds according to a differential gate electrode structure, according to another embodiment of the present invention.

[0355] Referring to Figure 33B, a first NMOS device 3352 is adjacent to a second NMOS device 3354 above a semiconductor active region 3350, such as above a silicon fin or substrate. Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. Specifically, the first NMOS device 3352 includes a first gate electrode conductive layer 3358 (such as a first working function layer) and a gate electrode conductive fill 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359 (such as a second working function layer), a first gate electrode conductive layer 3358, and a gate electrode conductive fill 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, differential VT is achieved by using a stack of differential gates for devices of the same conductivity type.

[0356] Referring again to Figure 33B, the first PMOS device 3372 is adjacent to the second PMOS device 3374 above the semiconductor active region 3370, such as above a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. Specifically, the first PMOS device 3372 includes a gate electrode conductive layer 3378A (such as a working function layer) with a first thickness and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B with a second thickness and a gate electrode conductive fill 3380. In one embodiment, gate electrode conductive layer 3378A and gate electrode conductive layer 3378B have the same composition, but the thickness of gate electrode conductive layer 3378B (second thickness) is greater than the thickness of gate electrode conductive layer 3378A (first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In one embodiment, differential VT is achieved by using a differential gate stack for devices of the same conductivity type.

[0357] Referring again to FIG. 33B, according to an embodiment of the present invention, the integrated circuit structure includes a fin (e.g., a silicon fin, such as 3350). It should be understood that the fin has a top (as shown) and sidewalls (entering and exiting the page). A gate dielectric layer 3356 is located above the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode of device 3354 is located above the gate dielectric layer 3356 above the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. As will be understood, a first N-type source or drain region may be adjacent to a first side of the gate electrode (e.g., entering the page), and a second N-type source or drain region may be adjacent to a second side of the gate electrode (e.g., exiting the page), the second side being opposite to the first side.

[0358] In one embodiment, the P-type metal layer 3359 comprises titanium and nitrogen, while the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2-12 angstroms, while in a particular embodiment, the P-type metal layer 3359 has a thickness in the range of 2-4 angstroms. In one embodiment, the N-type gate electrode further comprises a conductive filler metal layer 3360 on the N-type metal layer 3358. In such an embodiment, the conductive filler metal layer 3360 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3360 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0359] Referring again to FIG33B, according to another embodiment of the present invention, the integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), the first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Simultaneously, it includes a second N-type device 3354 having a voltage threshold (VT), the second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0360] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen, while the P-type metal layer 3359 comprises titanium and nitrogen.

[0361] Referring again to FIG33B, according to another embodiment of the present invention, the integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT). The first P-type device 3372 has a first gate dielectric layer 3376 and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. A second P-type device 3374 is also included and has a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than that of the first P-type metal layer 3378A.

[0362] In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B comprise titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is less than the working function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B comprises a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and the seam is located between the first metal film and the second metal film.

[0363] Referring again to FIG33B, according to another embodiment of the present invention, the integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. A second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. A first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. A second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than that of the second P-type metal layer 3378A.

[0364] In one embodiment, a first N-type device 3352 has a voltage threshold (VT), a second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, a first P-type device 3372 has a voltage threshold (VT), a second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, a third P-type metal layer 3378B includes a first metal film on a second metal film, and the seam is located between the first metal film and the second metal film.

[0365] It should be understood that more than two types of VT devices with the same conductivity type can be included in the same structure, such as on the same die. In the first example, FIG34A illustrates a cross-sectional view of a group of three NMOS devices having a differential gate electrode structure and a differential voltage threshold value according to modulation doping, and a group of three PMOS devices having a differential gate electrode structure and a differential voltage threshold value according to modulation doping, according to an embodiment of the present invention.

[0366] Referring to Figure 34A, a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403, above the semiconductor active region 3400, such as above a silicon fin or substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from that of the first NMOS device 3402 and the third NMOS device 3403. Specifically, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 (such as a first working function layer) and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 (such as a second working function layer), a first gate electrode conductive layer 3408, and a gate electrode conductive fill 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In one embodiment, the differential VT is achieved by using a differential gate stack for devices of the same conductivity type. In one embodiment, the third NMOS device 3403 has a VT different from that of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is the same as that of the first NMOS device 3402. In one embodiment, the VT of the third NMOS device 3403 is between the VTs of the first NMOS device 3402 and the second NMOS device 3404. In one embodiment, the differential VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using modulation or differential implantation doping on region 3412 of the third NMOS device 3403. In such an embodiment, the third N-type device 3403 has a channel region having a dopant concentration different from that of the channel region of the first N-type device 3402.

[0367] Referring again to Figure 34A, the first PMOS device 3422 is adjacent to the second PMOS device 3424 and the third PMOS device 3423, above the semiconductor active region 3420, such as above a silicon fin or substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from that of the first PMOS device 3422 and the third PMOS device 3423. Specifically, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3428A (such as a working function layer) having a first thickness, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness and a gate electrode conductive fill 3430. In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the thickness of the gate electrode conductive layer 3428B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3428A (the first thickness). In one embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In such an embodiment, the first PMOS device 3422 is referred to as a "standard VT" device, and the second PMOS device 3424 is referred to as a "low VT" device. In one embodiment, the differential VT is achieved by using a differential gate stack for devices of the same conductivity type. In one embodiment, the third PMOS device 3423 has a VT different from that of the first PMOS device 3422 and the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is the same as that of the first PMOS device 3422. In one embodiment, the VT of the third PMOS device 3423 is between the VTs of the first PMOS device 3422 and the second PMOS device 3424. In one embodiment, the differential VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by modulation or differential implantation doping on region 3432 of the third PMOS device 3423. In such an embodiment, the third P-type device 3423 has a channel region with a dopant concentration different from that of the channel region of the first P-type device 3422.

[0368] In the second example, FIG34B illustrates a cross-sectional view of a group of three NMOS devices having a differential voltage threshold based on a differential gate electrode structure and a differential voltage threshold based on modulation doping, and a group of three PMOS devices having a differential voltage threshold based on a differential gate electrode structure and a differential voltage threshold based on modulation doping, according to another embodiment of the present invention.

[0369] Referring to Figure 34B, a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453, above the semiconductor active region 3450, such as above a silicon fin or substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from that of the second NMOS device 3454 and the third NMOS device 3453. Specifically, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 (such as a first working function layer) and a gate electrode conductive fill 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 (such as a second working function layer), a first gate electrode conductive layer 3458, and a gate electrode conductive fill 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In one embodiment, the differential VT is achieved by using a differential gate stack for devices of the same conductivity type. In one embodiment, the third NMOS device 3453 has a VT different from that of the first NMOS device 3452 and the second NMOS device 3454, even though the gate electrode structure of the third NMOS device 3453 is the same as that of the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is located between the VTs of the first NMOS device 3452 and the second NMOS device 3454. In another embodiment, the differential VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by modulation or differential implantation doping on region 3462 of the third NMOS device 3453. In such an embodiment, the third N-type device 3453 has a channel region with a dopant concentration different from that of the channel region of the second N-type device 3454.

[0370] Referring again to Figure 34B, the first PMOS device 3472 is adjacent to the second PMOS device 3474 and the third PMOS device 3473, above the semiconductor active region 3470, such as above a silicon fin or substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from that of the second PMOS device 3474 and the third PMOS device 3473. Specifically, the first PMOS device 3472 includes a gate electrode conductive layer 3478A (such as a working function layer) having a first thickness, and a gate electrode conductive fill 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness and a gate electrode conductive fill 3480. In one embodiment, the gate electrode conductive layer 3478A and the gate electrode conductive layer 3478B have the same composition, but the thickness of the gate electrode conductive layer 3478B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3478A (the first thickness). In one embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In such an embodiment, the first PMOS device 3472 is referred to as a "standard VT" device, and the second PMOS device 3474 is referred to as a "low VT" device. In one embodiment, the differential VT is achieved by using a differential gate stack for devices of the same conductivity type. In one embodiment, the third PMOS device 3473 has a VT different from that of the first PMOS device 3472 and the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 is the same as that of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VTs of the first PMOS device 3472 and the second PMOS device 3474. In one embodiment, the differential VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by modulation or differential implantation doping on region 3482 of the third PMOS device 3473. In such an embodiment, the third P-type device 3473 has a channel region with a dopant concentration different from that of the channel region of the second P-type device 3474.

[0371] Figures 35A-35D illustrate cross-sectional views of various operations in a method of manufacturing an NMOS device having a differential voltage threshold value according to a differential gate electrode structure, according to another embodiment of the present invention.

[0372] Referring to Figure 35A, where the "Standard VT NMOS" region (STD VT NMOS) and the "High VT NMOS" region (HIGH VT NMOS) are shown branching on a common substrate, a method of manufacturing an integrated circuit structure includes forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504, such as over the first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506, over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0373] Referring to Figure 35B, a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 is retained on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0374] Referring to Figure 35C, an N-type metal layer 3510 is formed on a gate dielectric layer 3506 above a first semiconductor fin 3502 and on a portion 3509 of a P-type metal layer on the gate dielectric layer 3506 above a second semiconductor fin 3504. In one embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) above the first semiconductor fin 3502 and forming a second N-type device having a voltage threshold (VT) above the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0375] Referring to FIG35D, in one embodiment, a conductive filler metal layer 3512 is formed on an N-type metal layer 3510. In one such embodiment, forming the conductive filler metal layer 3512 includes using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor to form a tungsten-containing film.

[0376] Figures 36A-36D illustrate cross-sectional views of various operations in a method of manufacturing a PMOS device having a differential voltage threshold value according to a differential gate electrode structure, according to another embodiment of the present invention.

[0377] Referring to Figure 36A, where the "Standard VT PMOS" region (STD VT PMOS) and the "Low VT PMOS" region (LOW VT PMOS) are shown to branch off on a common substrate, a method of manufacturing an integrated circuit structure includes forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604, such as over the first and second silicon fins. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606, over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0378] Referring to Figure 36B, a portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 is retained on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0379] Referring to FIG36C, a second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602 and on a portion 3609 of the first P-type metal layer on the gate dielectric layer 3606 above the second semiconductor fin 3604. In one embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) above the first semiconductor fin 3602 and forming a second P-type device having a voltage threshold (VT) above the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0380] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, the seam 3611 is located between the first P-type metal layer 3608 and the second P-type metal layer 3610, as shown in the figure.

[0381] Referring to Figure 36D, in one embodiment, a conductive filler metal layer 3612 is formed over a P-type metal layer 3610. In one such embodiment, forming the conductive filler metal layer 3612 includes using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor to form a tungsten-containing film. In one embodiment, an N-type metal layer 3614 is formed on the P-type metal layer 3610 prior to the formation of the conductive filler metal layer 3612, as shown. In one such embodiment, the N-type metal layer 3614 is an artifact of a bimetallic gate substitution process.

[0382] In another embodiment, a metal gate structure for a complementary metal-oxide-semiconductor (CMOS) semiconductor device is described. In one example, FIG37 illustrates a cross-sectional view of an integrated circuit structure with a P / N junction, according to an embodiment of the present invention.

[0383] Referring to Figure 37, the integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 and a P-well region 3708. The N-well region 3704 has a first semiconductor fin 3706 protruding therefrom, and the P-well region 3708 has a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 is isolated from the second semiconductor fin 3710. The N-well region 3704 is directly adjacent to the P-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is located on the semiconductor substrate 3702 outside and between the first fin 3706 and the second fin 3700. The first fin 3706 and the second fin 3710 extend over the trench isolation structure 3712.

[0384] A gate dielectric layer 3714 is located on the first semiconductor fins 3706 and 3710 and on the trench isolation structure 3712. The gate dielectric layer 3714 is connected between the first semiconductor fins 3706 and 3710. A conductive layer 3716 is located above the gate dielectric layer 3714, above the first semiconductor fin 3706 (but not above the second semiconductor fin 3710). In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located above the conductive layer 3716, above the first semiconductor fin 3706 (but not above the second semiconductor fin 3710). The p-type metal gate layer 3718 is further located on a portion (but not all) of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710. The n-type metal gate layer 3720 is located above the second semiconductor fin 3710, above the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the p-type metal gate layer 3718.

[0385] In one embodiment, an interlayer dielectric (ILD) layer 3722 is situated above a trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first 3706 and the second 3710 semiconductor fins. In one such embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along the sidewall 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along the sidewall 3726 of the opening 3724, below the top surface 3719 of the p-type metal gate layer 3718 and the top surface 3721 of the n-type metal gate layer 3720 along the sidewall 3726 of the opening 3724, as shown.

[0386] In one embodiment, the p-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 comprises titanium and aluminum. In one embodiment, a conductive filler metal layer 3730 is located above the n-type metal gate layer 3720, as shown. In such an embodiment, the conductive filler metal layer 3730 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3730 comprises 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer comprising hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is located between the upper portions of the first 3706 and the second 3710 semiconductor fins, as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0387] Referring now only to the right side of Figure 37, according to an embodiment of the present invention, the integrated circuit structure includes a semiconductor substrate 3702, which includes an N-well region 3704 having semiconductor fins 3706 protruding therefrom. A trench isolation structure 3712 is located on the semiconductor substrate 3702 surrounding the semiconductor fins 3706. The semiconductor fins 3706 extend over the trench isolation structure 3712. A gate dielectric layer 3714 is located above the semiconductor fins 3706. A conductive layer 3716 is located above the gate dielectric layer 3714 above the semiconductor fins 3706. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is located above the conductive layer 3716 above the semiconductor fins 3706.

[0388] In one embodiment, an interlayer dielectric (ILD) layer 3722 is situated above a trench isolation structure 3712. The ILD layer has an opening that exposes a semiconductor fin 3706. A conductive layer 3716 and a P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewall of the opening, below the top surface of the P-type metal gate layer 3718 along the sidewall of the opening. In one embodiment, the P-type metal gate layer 3718 is situated on the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 comprises titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is situated above the P-type metal gate layer 3718. In one such embodiment, the conductive fill metal layer 3730 comprises tungsten. In certain embodiments of this type, the conductive filler metal layer 3730 is composed of 95 or greater atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 includes a layer having hafnium and oxygen.

[0389] Figures 38A-38H illustrate cross-sectional views of various operations in a method for manufacturing integrated circuit structures using bimetallic gates instead of gate process flows, according to embodiments of the present invention.

[0390] Referring to Figure 38A, which shows NMOS (N-type) and PMOS (P-type) regions, a method of manufacturing an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 on first 3804 and second 3806 semiconductor fins on a substrate 3800. An opening 3808 is formed in the ILD layer 3802, exposing the first 3804 and second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing a gate occupancy or dummy gate structure initially located above the first 3804 and second 3806 semiconductor fins.

[0391] A gate dielectric layer 3810 is formed in the opening 3808 and over the first 3804 and second 3806 semiconductor fins, as well as on a portion of the trench isolation structure 3812 between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed on a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, which is formed on the first 3804 and second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is formed directly on the first 3804 and second 3806 semiconductor fins.

[0392] A conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed over the conductive layer 3814 formed over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0393] Referring to Figure 38B, a dielectric etch stop layer 3818 is formed on a p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first layer of silicon oxide (e.g., SiO2), an aluminum oxide (e.g., Al2O3) layer on the first silicon oxide layer, and a second layer of silicon oxide (e.g., SiO2) on the aluminum oxide layer.

[0394] Referring to Figure 38C, a mask 3820 is formed on top of the structure in Figure 38B. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0395] Referring to Figure 38D, the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819, a patterned p-type metal gate layer 3817 above a patterned conductive layer 3815 above the first semiconductor fin 3804 (but not above the second semiconductor fin 3806). In one embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0396] Referring to Figure 38E, mask 3820 is removed from the structure of Figure 38D. Referring to Figure 3F, patterned dielectric etch stop layer 3819 is removed from the structure of Figure 3E.

[0397] Referring to FIG. 38G, an n-type metal gate layer 3822 is formed above the second semiconductor fin 3806, above a portion of the trench isolation structure 3812 between the first and second semiconductor fins 3804 and 3806, and above the patterned p-type metal gate layer 3817. In one such embodiment, the patterned conductive layer 3815, the patterned p-type metal gate layer 3817, and the n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808. In one such embodiment, the patterned conductive layer 3815 has a top surface along the sidewall 3824 of the opening 3808, below the top surfaces of the patterned p-type metal gate layer 3817 and the n-type metal gate layer 3822 along the sidewall 3824 of the opening 3808.

[0398] Referring to Figure 38H, a conductive filler metal layer 3826 is formed over an n-type metal gate layer 3822. In one such embodiment, the conductive filler metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with tungsten hexafluoride (WF6) precursor.

[0399] In another embodiment, a double silicide structure for a complementary metal-oxide-semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, Figures 39A-39H illustrate cross-sectional views illustrating various operations in a method of manufacturing a double silicide-based integrated circuit, according to an embodiment of the present invention.

[0400] Referring to Figure 39A, where the NMOS and PMOS regions are shown to branch off on a common substrate, a method of manufacturing an integrated circuit structure includes forming a first gate structure 3902 (which may include dielectric sidewall spacers 3903) over a first fin 3904, such as a first silicon fin. A second gate structure 3952 (which may include dielectric sidewall spacers 3953) is formed over a second fin 3954, such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 over the first fin 3904 and adjacent to the second gate structure 3952 over the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask in a double siliconization process.

[0401] Referring to Figure 39B, a first portion of the insulating material 3906 is removed from above the first fin 3904 but not from above the second fin 3954 to expose the first 3908 and second 3910 source or drain regions adjacent to the first fin 3904 of the first gate structure 3902. In one embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within a recessed portion of the first fin 3904, as shown. In such an embodiment, the first 3908 and second 3910 source or drain regions comprise silicon and germanium.

[0402] Referring to Figure 39C, a first metal silicate layer 3912 is formed on the first 3908 and second 3910 source or drain regions of the first fin 3904. In one embodiment, the first metal silicate layer 3912 is formed by depositing a layer comprising nickel and platinum on the structure of Figure 39B, annealing the layer comprising nickel and platinum, and removing unreacted portions of the layer comprising nickel and platinum.

[0403] Referring to Figure 39D, following the formation of the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from above the second fin 3954 to expose the third 3958 and fourth 3960 source or drain regions adjacent to the second fin 3954 of the second gate structure 3952. In one embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, such as within a second silicon fin, as shown. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within a recessed portion of the second fin 3954. In such an embodiment, the third 3958 and fourth 3960 source or drain regions comprise silicon.

[0404] Referring to Figure 39E, a first metal layer 3914 is formed on the structure of Figure 39D, specifically on the source or drain regions of the first 3908, second 3910, third 3958, and fourth 3960. A second metal silicate layer 3962 is then formed on the source or drain regions of the second fin 3954, specifically on the third 3958 and fourth 3960. The second metal silicate layer 3962 is formed from the first metal layer 3914, for example, using an annealing process. In one embodiment, the second metal silicate layer 3962 has a different composition from the first metal silicate layer 3912. In one embodiment, the first metal layer 3914 is (or includes) a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, for example, conformally to the open trenches of Figure 39D, as shown.

[0405] Referring to FIG39F, in one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 on each of the first 3908, second 3910, third 3958 and fourth 3960 source or drain regions.

[0406] Referring to FIG39G, in one embodiment, a second metal layer 3918 is formed on the U-shaped metal layer 3916 of the structure of FIG39F. In one embodiment, the second metal layer 3918 has a different composition from the U-shaped metal layer 3916.

[0407] Referring to FIG39H, in one embodiment, a third metal layer 3920 is formed on the second metal layer 3918 of the structure of FIG39G. In one embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0408] Referring again to FIG3H, according to an embodiment of the present invention, the integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) on a substrate. The P-type semiconductor device includes a first fin 3904, such as a first silicon fin. It should be understood that the first fin has a top (shown as 3904A) and sidewalls (e.g., entry and exit points). A first gate electrode 3902 includes a first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewall of the first fin 3904, and includes a first gate electrode above the first gate dielectric layer above the top 3904A of the first fin 3904 and laterally adjacent to the sidewall of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite to the first side 3902A.

[0409] The first 3908 and second 3910 semiconductor source or drain regions are individually adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902. The first 3930 and second 3932 trench contact structures are located above the first 3908 and second 3910 semiconductor source or drain regions, which are individually adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902. The first metal silicate layer 3912 is directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions, individually.

[0410] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) on a substrate. The N-type semiconductor device includes a second fin 3954, such as a second silicon fin. It should be understood that the second fin has a top (shown as 3954A) and sidewalls (e.g., entry and exit points). A second gate electrode 3952 includes a second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewall of the second fin 3954, and includes a second gate electrode above the second gate dielectric layer above the top 3954A of the second fin 3954 and laterally adjacent to the sidewall of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite to the first side 3952A.

[0411] The third 3958 and fourth 3960 semiconductor source or drain regions are individually adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952. The third 3970 and fourth 3972 trench contact structures are located above the third 3958 and fourth 3960 semiconductor source or drain regions, which are individually adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952. The second metal silicate layer 3962 is directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions, individually. In one embodiment, the first metal silicate layer 3912 includes at least one metal species not included in the second metal silicate layer 3962.

[0412] In one embodiment, the second metal silicate layer 3962 comprises titanium and silicon. The first metal silicate layer 3912 comprises nickel, platinum, and silicon. In one embodiment, the first metal silicate layer 3912 further comprises germanium. In one embodiment, the first metal silicate layer 3912 further comprises titanium, for example, as incorporated into the first metal silicate layer 3912 during the subsequent formation of the second metal silicate layer 3962 utilizing the first metal layer 3914. In such an embodiment, the silicate layer already formed on the PMOS source or drain region is further modified by an annealing process used to form silicate regions on the NMOS source or drain region. This can result in a silicate layer on the PMOS source or drain region having a small percentage of all siliconized metals. However, in other embodiments, the silicon layer already formed on the PMOS source or drain region is not altered or substantially changed by an annealing process used to form silicon regions on the NMOS source or drain region.

[0413] In one embodiment, the first 3908 and the second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third 3958 and the fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third 3958 and the fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not embedded epitaxial regions.

[0414] In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures each include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures further include a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0415] In another embodiment, trench contact structures (e.g., for the source or drain regions) are described. In one example, FIG40A illustrates a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device, according to an embodiment of the invention. FIG40B illustrates a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device, according to another embodiment of the invention.

[0416] Referring to FIG40A, an integrated circuit structure 4000 includes a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is located above the fin 4002. A gate electrode 4006 is located above the gate dielectric layer 4004. In one embodiment, the conductive electrode 4006 includes a conformal conductive layer 4008 and a conductive filler 4010. In one embodiment, a dielectric cap 4012 is located above the gate electrode 4006 and above the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite to the first side 4006A. A dielectric spacer 4013 is along the sidewall of the gate electrode 4006. In one embodiment, the gate dielectric layer 4004 is further disposed between the first dielectric spacer 4013 and the first side 4006A of the gate electrode 4006, and between the second dielectric spacer 4013 and the second side 4006B of the gate electrode 4006, as shown in the figure. In one embodiment, although not shown, a thin oxide layer (such as a thermally or chemically oxidized silicon or silicon dioxide layer) is disposed between the fin 4002 and the gate dielectric layer 4004.

[0417] The first 4014 and the second 4016 semiconductor source or drain regions are individually adjacent to the first 4006A and the second 4006B sides of the gate electrode 4006. In one embodiment, the first 4014 and the second 4016 semiconductor source or drain regions are located in the fin 4002, as shown in the figure. However, in another embodiment, the first 4014 and the second 4016 semiconductor source or drain regions are embedded epitaxial regions formed in the recess of the fin 4002.

[0418] The first 4018 and second 4020 trench contact structures are located above the first 4014 and second 4016 semiconductor source or drain regions, which are individually adjacent to the first 4006A and second 4006B sides of the gate electrode 4006. Both the first 4018 and second 4020 trench contact structures include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and over the U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In one such embodiment, the U-shaped metal layer 4022 includes titanium, and the T-shaped metal layer 4024 includes cobalt. In one embodiment, both the first 4018 and second 4020 trench contact structures further include a third metal layer 4026 on the T-shaped metal layer 4024. In one such embodiment, the third metal layer 4026 has the same composition as the U-shaped metal layer 4022. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 comprise titanium, while the T-shaped metal layer 4024 comprises cobalt.

[0419] The first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is located on (and coupled to) the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further located above (and in contact with) a portion of one of the dielectric spacers 4013 and above (and in contact with) a portion of the dielectric cap 4012. The second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is located on (and coupled to) the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further located above (and in contact with) a portion of the other dielectric spacer 4013 and above (and in contact with) another portion of the dielectric cap 4012.

[0420] In one embodiment, the metal silicide layer 4032 is directly situated between the first 4018 and second 4020 trench contact structures and the first 4014 and second 4016 semiconductor source or drain regions, individually. In one embodiment, the metal silicide layer 4032 comprises titanium and silicon. In a particular such embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

[0421] Referring to FIG40B, an integrated circuit structure 4050 includes a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is located above the fin 4052. A gate electrode 4056 is located above the gate dielectric layer 4054. In one embodiment, the conductive electrode 4056 includes a conformal conductive layer 4058 and a conductive filler 4060. In one embodiment, a dielectric cap 4062 is located above the gate electrode 4056 and above the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite to the first side 4056A. A dielectric spacer 4063 is along the sidewall of the gate electrode 4056. In one embodiment, the gate dielectric layer 4054 is further disposed between the first dielectric spacer 4063 and the first side 4056A of the gate electrode 4056, and between the second dielectric spacer 4063 and the second side 4056B of the gate electrode 4056, as shown. In one embodiment, although not shown, a thin oxide layer (such as a thermally or chemically oxidized silicon or silicon dioxide layer) is disposed between the fin 4052 and the gate dielectric layer 4054.

[0422] The first 4064 and the second 4066 semiconductor source or drain regions are individually adjacent to the first 4056A and the second 4056B sides of the gate electrode 4056. In one embodiment, the first 4064 and the second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in the recesses 4065 and 4067 of the fin 4052, as shown in the figure. However, in another embodiment, the first 4064 and the second 4066 semiconductor source or drain regions are located in the fin 4052.

[0423] The first 4068 and second 4070 trench contact structures are located above the first 4064 and second 4066 semiconductor source or drain regions, which are individually adjacent to the first 4056A and second 4056B sides of the gate electrode 4056. Both the first 4068 and second 4070 trench contact structures include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 on and over the U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one such embodiment, the U-shaped metal layer 4072 includes titanium, and the T-shaped metal layer 4074 includes cobalt. In one embodiment, both the first 4068 and second 4070 trench contact structures further include a third metal layer 4076 on the T-shaped metal layer 4074. In one such embodiment, the third metal layer 4076 has the same composition as the U-shaped metal layer 4072. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 comprise titanium, while the T-shaped metal layer 4074 comprises cobalt.

[0424] The first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is located on (and coupled to) the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is further located above (and in contact with) a portion of one of the dielectric spacers 4063 and above (and in contact with) a portion of the dielectric cap 4062. The second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is located on (and coupled to) the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further located above (and in contact with) a portion of the other dielectric spacer 4063 and above (and in contact with) another portion of the dielectric cap 4062.

[0425] In one embodiment, the metal silicate layer 4082 is directly situated between the first trench contact structure 4068 and the second 4070 and the first semiconductor source or drain regions 4064 and the second 4066, individually. In one embodiment, the metal silicate layer 4082 comprises nickel, platinum, and silicon. In a particular such embodiment, the first semiconductor source or drain regions 4064 and the second 4066 are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicate layer 4082 further comprises germanium. In one embodiment, the metal silicate layer 4082 further comprises titanium.

[0426] One or more embodiments described herein relate to the use of metal chemical vapor deposition for all-around semiconductor contacts. The embodiments may be applied to or include one or more of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin film fabrication.

[0427] Specific embodiments may include using low-temperature (e.g., less than 500 degrees Celsius, or in the range of 400-500 degrees Celsius) chemical vapor deposition of the contact metal to fabricate a metal-like layer such as titanium to provide a conformal source or drain contact. This implementation of a conformal source or drain contact can enhance the performance of three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS).

[0428] For background information, metal-to-semiconductor contact layers can be deposited using sputtering. Sputtering is a line-of-sight process and may not be very suitable for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-to-semiconductor junctions on the device contact surface, with varying angles of incidence for deposition.

[0429] According to one or more embodiments of the present invention, a low-temperature chemical vapor deposition process is performed on the fabrication of a contact metal to provide three-dimensional conformality and maximize the contact area of ​​the metal-semiconductor junction. The resulting larger contact area can reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having a non-planar topography, wherein the topography of a region refers to the surface shape and features of the region itself, and the non-planar topography includes a non-planar surface shape and features or a portion of a surface shape and features, that is, a surface shape and features that are not completely flat.

[0430] The embodiments described herein may include the fabrication of a surround contact structure. In one such embodiment, the use of pure metal conformally deposited on the source-drain contact of a transistor by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition is described. This conformal deposition can be used to increase the usable area of ​​the metal-semiconductor contact and reduce the resistance value, thereby improving the performance of the transistor device. In one embodiment, the relatively low temperature of the deposition results in a minimized resistance value per unit area of ​​the contact surface.

[0431] It should be understood that various integrated circuit structures can be fabricated using integration methods involving metal layer deposition processes as described herein. According to an embodiment of the invention, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having a feature thereon in an RF source. The method also includes reacting titanium tetrachloride (TiCl₄) with hydrogen (H₂) to form a titanium (Ti) layer on the feature of the substrate.

[0432] In one embodiment, the titanium layer has a total atomic composition comprising 98% or more titanium and 0.5-2% chlorine. In alternative embodiments, a similar process is used to manufacture high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In one embodiment, there is relatively little variation in film thickness; for example, in one embodiment, all coverage is greater than 50% and nominally 70% or greater (i.e., a thickness variation of 30% or less). In one embodiment, the thickness on silicon (Si) or silicon-germanium (SiGe) is measurably thicker than on other surfaces because Si or SiGe reacts during deposition to accelerate Ti uptake. In one embodiment, the film composition includes about 0.5% Cl (or less than 1%) as impurities, with substantially no other observed impurities. In one embodiment, the deposition process enables metal coverage on non-visible surfaces (such as surfaces hidden by sputtering deposition visibility). The embodiments described herein can be implemented to improve transistor device driving by reducing the external resistance of the current driven through the source and drain contacts.

[0433] According to an embodiment of the present invention, the feature of the substrate is a source or drain contact trench, which exposes the semiconductor source or drain structure. A titanium layer (or other high-purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. An exemplary embodiment of this invention is described below in connection with Figures 41A, 41B, 42, 43A-43C and 44.

[0434] Figure 41A illustrates a cross-sectional view of a semiconductor device having conductive contacts on the source or drain regions, according to an embodiment of the present invention.

[0435] Referring to FIG41A, a semiconductor structure 4100 includes a gate structure 4102 on a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a working function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are located on opposite sides of the gate structure 4102. A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110, and is isolated from the gate structure 4102 by one or both of an interlayer dielectric layer 4114 or a gate dielectric spacer 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0436] In one embodiment, the source or drain contact 4112 includes a high-purity metal layer 4112A (such as those described above) and a conductive trench filler material 4112B. In one embodiment, the high-purity metal layer 4112A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal layer 4112A further comprises 0.5-2% chlorine. In one embodiment, the high-purity metal layer 4112A has a thickness variation of 30% or less. In one embodiment, the conductive trench filler material 4112B is composed of a conductive material, such as (but not limited to) Cu, Al, W, or alloys thereof.

[0437] Figure 41B illustrates a cross-sectional view of another semiconductor device having conductive contacts on the raised source or drain region, according to an embodiment of the present invention.

[0438] Referring to FIG41B, a semiconductor structure 4150 includes a gate structure 4152 on a substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a working function layer 4152B, and a gate fill 4152C. A source region 4158 and a drain region 4160 are located on opposite sides of the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160, and is isolated from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in an etch-away region of the substrate 4154. As shown, in one embodiment, the source region 4158 and the drain region 4160 are raised source and drain regions. In certain embodiments of this kind, the elevated source and drain regions are elevated silicon source and drain regions or elevated silicon-germanium source and drain regions.

[0439] In one embodiment, the source or drain contact 4162 includes a high-purity metal layer 4162A (such as those described above) and a conductive trench filler material 4162B. In one embodiment, the high-purity metal layer 4162A has a total atomic composition comprising 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metal layer 4162A further comprises 0.5-2% chlorine. In one embodiment, the high-purity metal layer 4162A has a thickness variation of 30% or less. In one embodiment, the conductive trench filler material 4162B is composed of a conductive material, such as (but not limited to) Cu, Al, W, or alloys thereof.

[0440] Therefore, in one embodiment, collectively referring to Figures 41A and 41B, the integrated circuit structure includes features having a surface (exposing source or drain contact trenches of semiconductor source or drain structures). A high-purity metal layer 4112A or 4162A is located on the surface of the source or drain contact trench. It should be understood that the contact formation process may involve the consumption of exposed silicon or germanium or silicon-germanium material in the source or drain region. This consumption can degrade device performance. Conversely, according to embodiments of the invention, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not etched or consumed, or is not substantially etched or consumed beneath the source or drain contact trench. In one such embodiment, the lack of consumption or etching is due to the low-temperature deposition of the high-purity metal contact layer.

[0441] Figure 42 illustrates a plan view of a plurality of gate lines above a pair of semiconductor fins, according to an embodiment of the present invention.

[0442] Referring to Figure 42, a plurality of active gate lines 4204 are formed above a plurality of semiconductor fins 4200. A virtual gate line 4206 is located at the end of the plurality of semiconductor fins 4200. The gap 4208 between gate lines 4204 / 4206 is the location where trench contacts can be formed to provide conductive contacts to source or drain regions (such as source or drain regions 4251, 4252, 4253, and 4254).

[0443] Figures 43A-43C illustrate cross-sectional views taken along axis a-a' of Figure 42 for various operations in a method of manufacturing an integrated circuit structure, according to an embodiment of the present invention.

[0444] Referring to Figure 43A, a plurality of active gate lines 4304 are formed above a semiconductor fin 4302 (which is formed on a substrate 4300). A dummy gate line 4306 is located at the end of the semiconductor fin 4302. A dielectric layer 4310 is located between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. An embedded source or drain structure 4308 is located in the semiconductor fin 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. The active gate line 4304 includes a gate dielectric layer 4312, a working function gate electrode portion 4314, a filled gate electrode portion 4316, and a dielectric capping layer 4318. The dielectric spacer 4320 fills the sidewalls of the active gate line 4304 and the virtual gate line 4306.

[0445] Referring to Figure 43B, portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 are removed to provide openings 4330 in locations where trench contacts will be formed. This removal of portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate line 4304 can lead to erosion of the embedded source or drain structure 4308 to provide an eroded embedded source or drain structure 4332, which may have an upper saddle-shaped morphology, as shown in Figure 43B.

[0446] Referring to Figure 43C, trench contacts 4334 are formed in openings 4330 between active gate lines 4304 and between virtual gate lines 4306 and active gate lines 4304. Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive filler material 4338.

[0447] Figure 44 illustrates a cross-sectional view of an integrated circuit structure taken along the b-b' axis of Figure 42, according to an embodiment of the present invention.

[0448] Referring to Figure 44, fins 4402 are deposited on a substrate 4404. The portion below the fins 4402 is surrounded by trench isolation material 4404. The portion above the fins 4402 has been removed to allow for the growth of embedded source and drain structures 4406. Trench contacts 4408 are formed in openings in the dielectric layer 4410, which expose the embedded source and drain structures 4406. The trench contacts include a metal contact layer 4412 and a conductive filler material 4414. It should be understood that, according to one embodiment, the metal contact layer 4412 extends to the top of the trench contact 4408, as shown in Figure 44. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact 4408 but is somewhat recessed within the trench contact 4408, for example, similar to the deposition of metal contact layer 4336 in Figure 43C.

[0449] Therefore, collectively referring to Figures 42, 43A-43C and 44, according to an embodiment of the present invention, the integrated circuit structure includes semiconductor fins (4200, 4302, 4402) on a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have a top and sidewalls. Gate electrodes (4204, 4304) are located on the top of a portion of the semiconductor fins (4200, 4302, 4402) and adjacent to the sidewall of that portion of the semiconductor fins (4200, 4302, 4402). The gate electrodes (4204, 4304) define a channel region in the semiconductor fins (4200, 4302, 4402). The first semiconductor source or drain structure (4251, 4332, 4406) is located at the first end of the channel region on the first side of the gate electrode (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-planar morphology. The second semiconductor source or drain structure (4252, 4332, 4406) is located at the second end of the channel region on the second side of the gate electrode (4204, 4304), and the second end is opposite to the first end, and the second side is opposite to the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar morphology. The metal contact materials (4336, 4412) are directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact materials (4336, 4412) are conformally formed with the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and coplanar with the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0450] In one embodiment, the metal contact materials (4336, 4412) have a total atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metal contact materials (4336, 4412) have a total atomic composition comprising 98% or more of titanium. In a particular such embodiment, the total atomic composition of the metal contact materials (4336, 4412) further comprises 0.5-2% chlorine. In one embodiment, the metal contact materials (4336, 4412) have a thickness variation of 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In one embodiment, the non-planar topography of both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) includes a raised central portion and a lower side portion, for example, as shown in FIG44. In another embodiment, the non-planar topography of both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) includes a saddle-shaped portion, for example, as shown in FIG43C.

[0452] In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) include silicon. In another embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) further include germanium, for example, in the form of silicon-germanium.

[0453] In one embodiment, the metal contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) is further along the sidewalls of a trench in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trench decreases from 4336A on the first semiconductor source or drain structure (4332) to a position (4336B) above the first semiconductor source or drain structure (4332), an example of which is shown in FIG43C. In one embodiment, the conductive filler material (4338, 4414) is located on the metal contact material (4336, 4412) within the trench, as shown in Figures 43C and 44.

[0454] In one embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (e.g., fins 4200, 4302, and 4402 in FIG. 42). A gate electrode (4204, 4304) is further located above the top of a portion of the second semiconductor fin and adjacent to the sidewall of that portion of the second semiconductor fin, defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located on the first end of the channel region of the second semiconductor fin on the first side of the gate electrode (4204, 4304), and the third semiconductor source or drain structure has a non-planar topography. The fourth semiconductor source or drain structure (4254, 4332, 4406) is located on the second end of the channel region of the second semiconductor fin on the second side of the gate electrode (4204, 4304). The second end has a non-planar morphology relative to the first end. The metal contact materials (4336, 4412) are directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the four semiconductor source or drain structure (4254, 4332, 4406). The metal contact materials (4336, 4412) are conformal to the non-planar topography of the third semiconductor source or drain structure (4253, 4332, 4406) and the non-planar topography of the four semiconductor source or drain structure (4254, 4332, 4406). In one embodiment, the metal contact materials (4336, 4412) are connected between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, right side 4406), and are connected between the second semiconductor source or drain structure (4252) and the quad semiconductor source or drain structure (4254).

[0455] In another embodiment, a hard shielding material can be used to preserve (prevent corrosion) and can be retained above the dielectric material in the trench line location where the conductive trench contacts are interrupted (e.g., in the contact plug location). For example, Figures 45A and 45B respectively illustrate a plan view and a corresponding cross-sectional view of an integrated circuit structure including trench contact plugs having a hard shielding material thereon, according to an embodiment of the invention.

[0456] Referring to Figures 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes a fin 4052A, such as a silicon fin. A plurality of gate structures 4506 are located above the fin 4502A. Individual gate structures 4506 are arranged along a direction 4508 orthogonal to the fin 4502A and have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of the first pair 4506A / 4506B of the gate structures 4506. A contact plug 4514B is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of the second pair 4506B / 4506C of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard shielding material 4518.

[0457] In one embodiment, the dielectric material 4516 below the contact plug 4516B comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The hard shielding material 4518 above the contact plug 4516B comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0458] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the hard shielding material 4518 on the contact plug 4514B, as shown in the figure.

[0459] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is located on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the hard shielding material 4518 above the contact plug 4514B, as shown. In one embodiment, although not shown, a thin oxide layer (such as a thermally or chemically oxidized silicon or silicon dioxide layer) is located between the fin 4502A and the gate dielectric layer 4526.

[0460] Referring again to Figures 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes a plurality of fins 4052, such as a plurality of silicon fins. Individuals of the plurality of fins 4502 are along a first direction 4504. A plurality of gate structures 4506 are located above the plurality of fins 4502. Individuals of the plurality of gate structures 4506 are along a second direction 4508 orthogonal to the first direction 4504. Individuals of the plurality of gate structures 4506 have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above a first fin 4502A of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506. The contact plug 4514A is located above the second fin 4502B of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the gate structure 4506. Similar to the cross-sectional view of the contact plug 4514B, the contact plug 4514A includes a lower dielectric material 4516 and an upper hard shielding material 4518.

[0461] In one embodiment, the dielectric material 4516 below the contact plug 4516A comprises silicon and oxygen, such as silicon oxide or silicon dioxide. The hard shielding material 4518 above the contact plug 4516A comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0462] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the hard shielding material 4518 on the contact plug 4514A or 4514B, as shown in the figure.

[0463] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is located on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of each of the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the hard shielding material 4518 on the contact plug 4514A or 4514B, as shown. In one embodiment, although not shown, a thin oxide layer (such as a thermally or chemically oxidized silicon or silicon dioxide layer) is located between the fin 4502A and the gate dielectric layer 4526.

[0464] One or more embodiments of the present invention relate to a contact process for gate alignment. This process can be implemented to form a contact structure for semiconductor structure fabrication, such as for integrated circuit fabrication. In one embodiment, the contact pattern is formed to align with an existing gate pattern. Alternatively, other approaches typically involve an additional lithography process with a lithographic contact pattern closely aligned to an existing gate pattern, combined with selective contact etching. For example, another process may include the patterning of a polysilicon (gate) grid with separately patterned contacts and contact plugs.

[0465] According to one or more embodiments described herein, a method of contact formation involves forming a contact pattern that is substantially well aligned with an existing gate pattern while eliminating the use of a lithography operation with extremely stringent registration costs. In one such embodiment, this approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to create the contact opening. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this approach eliminates the need for other critical lithography operations (as used in other approaches) for generating the contact pattern. In one embodiment, the trench contact grid is not patterned separately but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed following gate grating patterning but before gate grating dicing.

[0466] Figures 46A-46D illustrate cross-sectional views of various operations in a method of manufacturing an integrated circuit structure including a trench contact plug having a hard masking material thereon, according to an embodiment of the present invention.

[0467] Referring to Figure 46A, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, individual fins 4602 of which are along a first direction 4604. Individual fins 4602 may include diffusion regions 4606. A plurality of gate structures 4608 are formed above the plurality of fins. Individual gate structures 4508 are along a second direction 4610 orthogonal to the first direction 4604 (e.g., direction 4610 is in and out of the page). A sacrificial material structure 4612 is formed between a first pair of gate structures 4608. A contact plug 4614 is located between a second pair of gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard shielding material 4618 is located on the lower dielectric material 4616.

[0468] In one embodiment, the gate structure 4608 includes a sacrificial or dummy gate stack and a dielectric spacer 4609. The sacrificial or dummy gate stack may be made of polycrystalline silicon or silicon nitride pillars or some other sacrificial material, which may be referred to as a gate dummy material.

[0469] Referring to Figure 46B, the sacrificial material structure 4612 is removed from the structure of Figure 46A to form an opening 4620 between the first pair of gate structures 4608.

[0470] Referring to Figure 46C, a trench contact structure 4622 is formed in an opening 4620 between the first pair of gate structures 4608. Furthermore, in one embodiment, the hard shield 4618 of Figures 46A and 46B is planarized as part of forming the trench contact structure 4622. The finalized contact plug 4614' includes a lower dielectric material 4616 and an upper hard shield material 4624 (formed from the hard shield material 4618).

[0471] In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' comprises silicon and oxygen, and the upper hard shielding material 4624 of each of the contact plugs 4614' comprises silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with the upper surface of the hard shielding material 4624 on the contact plug 4614'.

[0472] Referring to Figure 46D, the sacrificial or dummy gate stack of gate structure 4608 is replaced in a gate replacement process. In this approach, dummy gate materials such as polysilicon or silicon nitride pillars are removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed in this process, unlike in earlier processes.

[0473] Therefore, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Furthermore, in one embodiment, the top portion of the permanent gate structure 4630 is removed, for example, by an etching process, and replaced with a dielectric cap 4636. In one embodiment, the dielectric cap 4636 of an individual permanent gate structure 4630 has an upper surface that is coplanar with the upper surface of the hard masking material 4624 above the contact plug 4614'.

[0474] Referring again to Figures 46A-46D, in one embodiment, the gate replacement process is performed following the formation of the trench contact structure 4622, as shown. However, according to other embodiments, the gate replacement process is performed before the formation of the trench contact structure 4622.

[0475] In another embodiment, a gate-over-gate (COAG) structure and fabrication process are described. One or more embodiments of the present invention relate to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed above the active portion of the gate electrode of the semiconductor structure or device. One or more embodiments of the present invention relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed above the active portion of the gate electrode of the semiconductor structure or device. The manner described herein can be used to reduce standard cell area by enabling the formation of gate contacts above the active gate region. In one or more embodiments, it is fabricated such that the gate contact structure contacting the gate electrode is a self-aligned via structure.

[0476] In one of the technologies that offers slightly more space and layout constraints compared to current generations, the contact leading to the gate structure can be manufactured by forming a contact leading to a portion of the gate electrode disposed above the isolation region. As an example, Figure 47A illustrates a plan view of a semiconductor device having a gate contact disposed above the inactive portion of the gate electrode.

[0477] Referring to Figure 47A, the semiconductor structure or device 4700A includes a diffused or active region 4704 disposed in a substrate 4702 (and within an isolation region 4706). One or more gate lines (also known as polysilicon lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffused or active region 4704 and over a portion of the isolation region 4706. Source or drain contacts (also known as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of the semiconductor structure of device 4700A. Trench contact vias 4712A and 4712B individually provide contacts to trench contacts 4710A and 4710B. A separate gate contact 4714 (and an overlying gate contact via 4716) provides a contact to gate line 4708B. Conversely, the gate contact 4714 is positioned (from a plan view perspective) above the isolation region 4706, but not above the diffusion or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is positioned between the source or drain trench contacts 4710A and 4710B.

[0478] Figure 47B illustrates a cross-sectional view of a nonplanar semiconductor device having a gate contact disposed above an inactive portion of a gate electrode. Referring to Figure 47B, the semiconductor structure or device 4700B (e.g., a nonplanar version of device 4700A of Figure 47A) includes a nonplanar diffused or active region 4704C (e.g., a fin structure) formed from a substrate 4702 (and within an isolation region 4706). A gate line 4708B is disposed above the nonplanar diffused or active region 4704B and above a portion of the isolation region 4706. As shown, the gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752, together with a dielectric capping layer 4754. The gate contact 4714 and the overlying gate contact via 4716 are also visible in this perspective view, together with the overlying metal interconnect 4760, both disposed within an interlayer dielectric stack or layer 4770. As can also be seen from the perspective view of Figure 47B, the gate contact 4714 is positioned above the isolation region 4706, but not above the non-planar diffusion or active region 4704B.

[0479] Referring again to Figures 47A and 47B, the semiconductor structures or devices 4700A and 4700B are configured such that the gate contacts are individually placed above the isolation region. This configuration wastes layout space. However, placing the gate contacts above the active region would require extremely tight budgets or the gate size would have to be increased to provide sufficient space for the gate contacts. Furthermore, historically, contacts leading to the gate above the diffusion region have avoided the risk of contacting the underlying active region through other gate materials (e.g., polysilicon). One or more embodiments described herein address the above problems by providing a feasible manner (and the resulting structure) for fabricating a contact structure that contacts a portion of the gate electrode formed above the diffusion or active region.

[0480] As an example, FIG48A illustrates a plan view of a semiconductor device having a gate contact via disposed above the active portion of the gate electrode, according to an embodiment of the present invention. Referring to FIG48A, the semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in a substrate 4802 (and within an isolation region 4806). One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed above the diffusion or active region 4804 and above a portion of the isolation region 4806. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed above the source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B individually provide contacts leading to trench contacts 4810A and 4810B. The gate contact via 4816 (which does not have an intermediate separate gate contact layer) provides a connection to the gate line 4808B. Conversely, as shown in Figure 47A, the gate contact 4816 is configured (from a plan view) above the diffusion or active region 4804 and between the source or drain contacts 4810A and 4810B.

[0481] Figure 48B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above the active portion of the gate electrode, according to an embodiment of the present invention. Referring to Figure 48B, the semiconductor structure or device 4800B (e.g., a non-planar version of device 4800A of Figure 48A) includes a non-planar diffused or active region 4804B (e.g., a fin structure) formed from a substrate 4802 (and within an isolation region 4806). A gate line 4808B is disposed above the non-planar diffused or active region 4804B and above a portion of the isolation region 4806. As shown, the gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852, together with a dielectric capping layer 4854. The gate contact via 4816, also visible in this perspective view, is disposed within an interlayer dielectric stack or layer 4870, together with an overlay metal interconnect 4860. As can also be seen from the perspective view of Figure 48B, the gate contact via 4816 is positioned above the non-planar diffusion or active region 4804B.

[0482] Therefore, referring again to Figures 48A and 48B, in one embodiment, trench contact vias 4812A and 4812B and gate contact via 4816 are formed in the same layer and are substantially coplanar. Compared to Figures 47A and 47B, the contacts leading to the gate lines will include an additional gate contact layer, for example, which will be perpendicular to the respective gate lines. However, in the structures described in association with Figures 48A and 48B, structures 4800A and 4800B are manufactured individually to enable the placement of contacts directly from the metal interconnect layer on the active gate portion without short-circuiting to adjacent source and drain regions. In one embodiment, this configuration provides a significant reduction in circuit layout area by eliminating the need to extend transistor gates over the isolation layer to form reliable contacts. As used throughout this specification, in one embodiment, a reference to the active portion of a gate refers to that portion of the gate line or structure disposed above the active or diffuser region of the underlying substrate (from a plan view view). In one embodiment, a reference to the inactive portion of a gate refers to that portion of the gate line or structure disposed above the isolation region of the underlying substrate (from a plan view view).

[0483] In one embodiment, the semiconductor structure or device 4800 is a non-planar device, such as (but not limited to) a fin-FET or a three-gate device. In this embodiment, the corresponding semiconductor channel region is composed of or formed as a three-dimensional body. In such an embodiment, the gate electrode stacks of gate lines 4808A-4808C surround at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is formed as a discrete three-dimensional body, such as in a surround-gate device. In such an embodiment, the gate electrode stacks of gate lines 4808A-4808C each completely surround the channel region.

[0484] More generally, one or more embodiments relate to a method (and the resulting structure) for directly placing gate contact vias onto the gate of an active transistor. This eliminates the need for extending gate lines over the isolation for contact purposes. It also eliminates the need for a separate gate contact (GCN) layer to guide signals from the gate line or structure. In one embodiment, this elimination is achieved by recessing contact metal in the trench contact (TCN) and introducing additional dielectric material in the process flow (e.g., TILA). The additional dielectric material is included as a trench contact dielectric capping layer, having different etch characteristics than the gate dielectric capping layer used for trench contact alignment in gate alignment contact process (GAP) solutions (e.g., GILA).

[0485] As an example manufacturing scheme, Figures 49A-49D illustrate cross-sectional views, which show various operations in a method of manufacturing a semiconductor structure having a gate contact structure disposed above the active portion of the gate, according to an embodiment of the present invention.

[0486] Referring to Figure 49A, a semiconductor structure 4900 is provided following the formation of a trench contact (TCN). It should be understood that the specific configuration of structure 4900 is for illustrative purposes only, and various possible layouts may benefit from embodiments of the invention described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E disposed on substrate 4902. The gate stack structure may include a gate dielectric layer and gate electrodes. Trench contacts (e.g., contacts leading to a diffusion region of substrate 4902), such as trench contacts 4910A-4910C, are also included in structure 4900 and isolated from gate stack structures 4908A-4908E by dielectric spacers 4920. An insulating capping layer 4922 may be disposed on gate stack structures 4908A-4908E (e.g., GILA), as also shown in Figure 49A. As also shown in Figure 49A, a contact blocking region or "contact plug" (such as region 4923) made from interlayer dielectric material may be included in the region where the contact formation will be blocked.

[0487] In one embodiment, the provided structure 4900 relates to forming a contact pattern that is substantially well aligned with an existing gate pattern while eliminating the need for a lithography operation with extremely tight registration budgets. In one such embodiment, this enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this eliminates the need for other critical lithography operations (as used in other embodiments) to create the contact pattern. In one embodiment, the trench contact grid is not patterned separately but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed following gate grating patterning but before gate grating dicing.

[0488] Furthermore, the gate stack structures 4908A-4908E can be manufactured using a gate replacement process. In this technique, dummy gate materials, such as polycrystalline silicon or silicon nitride pillars, can be removed and replaced with permanent gate electrode materials. In one such embodiment, a permanent gate dielectric layer is also formed in this process, unlike in earlier processes. In one embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polycrystalline silicon or amorphous silicon and removed by a dry etching process including SF6. In another embodiment, the dummy gate is composed of polycrystalline silicon or amorphous silicon and removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and removed by a wet etching process including aqueous phosphoric acid.

[0489] In one embodiment, one or more of the methods described herein essentially consider a virtual and replacement gate process, combined with a virtual and replacement contact process, to obtain structure 4900. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure (e.g., after the gate dielectric layer is formed) is performed at a temperature greater than about 600 degrees Celsius. Annealing is performed prior to the formation of the permanent contacts.

[0490] Referring to Figure 49B, trench contacts 4910A-4910C of structure 4900 are recessed within spacer 4920 to provide recessed trench contacts 4911A-4911C, which have a height lower than the top surface of spacer 4920 and insulating capping layer 4922. Insulating capping layer 4924 is subsequently formed on the recessed trench contacts 4911A-4911C (e.g., TILA). According to an embodiment of the invention, the insulating capping layer 4924 on the recessed trench contacts 4911A-4911C is composed of a material having etch characteristics different from those of the insulating capping layer 4922 on the gate stack structures 4908A-4908E. As will be seen in subsequent processing operations, this difference can be used to etch one of 4922 / 4924 (selectively from the other of 4922 / 4924).

[0491] The trench contacts 4910A-4910C can be recessed by a process selectively applying materials to the spacer 4920 and the insulating capping layer 4922. For example, in one embodiment, the trench contacts 4910A-4910C are recessed by an etching process (such as a wet etching process or a dry etching process). The insulating capping layer 4924 can be formed by a process adapted to provide a conformal and sealing layer over the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating capping layer 4924 is formed by a chemical vapor deposition (CVD) process as a conformal layer over the entire structure. The conformal layer is then planarized (e.g., by chemical mechanical polishing (CMP)) to provide insulating capping material 4924 only above the trench contacts 4910A-4910C, and to re-expose the spacer 4920 and the insulating capping 4922.

[0492] Regarding a suitable material combination for the insulating capping layers 4922 / 4924, in one embodiment, one of the 4922 / 4924 layers is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment, one of the 4922 / 4924 layers is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the 4922 / 4924 layers is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the 4922 / 4924 layers is composed of silicon nitride and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the 4922 / 4924 layers is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 4922 / 4924 is composed of carbon-doped silicon nitride and the other is composed of silicon carbide.

[0493] Referring to Figure 49C, an interlayer dielectric (ILD) layer 4930 and a hard mask 4932 are stacked and patterned to provide, for example, a metal (0) trench 4934 patterned on the structure of Figure 49B.

[0494] Interlayer dielectric (ILD) 4930 may be composed of a material suitable for electrically isolating the metallic features ultimately formed therein while maintaining a robust structure between front-end and back-end processing. Furthermore, in one embodiment, the composition of ILD 4930 is selected to conform to via etching selectivity for trench contact dielectric capping patterning, as described in more detail below in association with Figure 49D. In one embodiment, ILD 4930 is composed of one or more layers of silicon oxide or one or more layers of carbon-doped oxide (CDO) material. However, in other embodiments, ILD 4930 has a bilayer composition, with its top portion composed of a material different from the bottom portion below ILD 4930. Hard mask layer 4932 may be composed of a material suitable for acting as a subsequent sacrificial layer. For example, in one embodiment, hard mask layer 4932 is substantially composed of carbon, for example, as a layer of cross-linked organic polymer. In other embodiments, silicon nitride or carbon-doped silicon nitride is used as the hard mask 4932. The interlayer dielectric (ILD) 4930 and the hard mask 4932 stack can be patterned by a lithography and etching process.

[0495] Referring to FIG49D, via openings 4936 (e.g., VCT) are formed in interlayer dielectric (ILD) 4930, extending from metal (0) trench 4934 to one or more of recessed trench contacts 4911A-4911C. For example, in FIG49D, via openings are formed to expose recessed trench contacts 4911A and 4911C. The formation of via openings 4936 includes etching of individual portions of both interlayer dielectric (ILD) 4930 and corresponding insulating capping layers 4924. In one such embodiment, a portion of the insulating capping layer 4922 is exposed during patterning of the interlayer dielectric (ILD) 4930 (e.g., a portion of the insulating capping layer 4922 above gate stack structures 4908B and 4908E is exposed). In this embodiment, the insulating capping layer 4924 is etched to form a via opening 4936 that is selective for (e.g., does not significantly etch or affect) the insulating capping layer 4922.

[0496] In one embodiment, the via opening pattern is ultimately transferred to the insulating capping layer 4924 (i.e., the trench contact insulating capping layer) by an etching process without etching the insulating capping layer 4922 (i.e., the gate insulating capping layer). The insulating capping layer 4924 (TILA) may be composed of any or a combination of the following, including silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various metal oxides, and silica (including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof). This layer can be deposited using any of the following techniques, including CVD, ALD, PECVD, PVD, HDP-assisted CVD, and low-temperature CVD. Corresponding plasma dry etching has been developed as a combination of chemical and physical sputtering mechanisms. Overlap polymer deposition can be used to control material removal rate, etching profile, and film selectivity. Dry etching is typically produced by a mixture of gases, including NF3, CHF3, C4F8, HBr, and O2, usually at pressures in the range of 30-100 mTorr and plasma biases of 50-1000 watts. Dry etching can be tuned to achieve significant etch selectivity between the capping 4924 (TILA) and 4922 (GILA) layers, minimizing the loss of 4922 (GILA) during the dry etching of 4924 (TILA) to form contacts leading to the source and drain regions of the transistor.

[0497] Referring again to Figure 49D, it should be understood that a similar approach can be implemented to create a via opening pattern that is ultimately transferred to the insulating capping layer 4922 (i.e., the trench contact insulating capping layer) by an etching process without etching the insulating capping layer 4924 (i.e., the gate insulating capping layer).

[0498] To further demonstrate the concept of contacts above the active gate (COAG) technology, Figure 50 illustrates a plan view and corresponding cross-sectional view of an integrated circuit structure having trench contacts including an overlying insulating cap, according to an embodiment of the present invention.

[0499] Referring to FIG. 50, an integrated circuit structure 5000 includes a gate line 5004 located on a semiconductor substrate or fin 5002 (such as a silicon fin). The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating capping layer 5006 on the gate stack 5005. Dielectric spacers 5008 are along the sidewalls of the gate stack 5005, and in one embodiment, along the sidewalls of the insulating capping layer 5006, as shown.

[0500] The trench contact 5010 is adjacent to the sidewall of the gate line 5004 and has a dielectric spacer 5008 between the gate line 5004 and the trench contact 5010. Individual trench contacts 5010 include conductive contact structures 5011 and trench contact insulating caps 5012 on the conductive contact structures 5011.

[0501] Referring again to Figure 50, a gate contact via 5014 is formed in an opening in the gate insulating capping layer 5006 and electrically contacts the gate stack 5005. In one embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location above the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as shown. In such an embodiment, the trench contact insulating capping layer 5012 on the conductive contact structure 5011 prevents gate-to-source or gate-to-drain short circuits via the gate contact via 5014.

[0502] Referring again to Figure 50, a trench contact via 5016 is formed in an opening of the trench contact insulating capping layer 5012 and electrically contacts individual conductive contact structures 5011. In one embodiment, the trench contact via 5016 electrically contacts individual conductive contact structures 5011 at locations above the semiconductor substrate or fin 5002 and laterally adjacent to the gate stack 5005 of the gate line 5004, as shown. In such an embodiment, the gate insulating capping layer 5006 on the gate stack 5005 prevents source-to-gate or drain-to-gate short circuits via the trench contact via 5016.

[0503] It should be understood that different structural relationships between the insulating gate cap and the insulating trench contact cap can be manufactured. As an example, Figures 51A-51F illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an insulating cap and a gate stack including an insulating cap, according to embodiments of the present invention.

[0504] Referring to Figures 51A, 51B, and 51C, the integrated circuit structures 5100A, 5100B, and 5100C each include a fin 5102, such as a silicon fin. Although shown as a cross-sectional view, it should be understood that the fin 5102 has a top 5102A and sidewalls (enter and exit the page showing the perspective view). First gate dielectric layers 5104 and second gate dielectric layers 5106 are located above the top 5102A of the fin 5102 and laterally adjacent to the sidewalls of the fin 5102. First gate electrodes 5108 and second gate electrodes 5110 are individually located above the first gate dielectric layers 5104 and second gate dielectric layers 5106, above the top 5102A of the fin 5102, and laterally adjacent to the sidewalls of the fin 5102. The first gate electrode 5108 and the second gate electrode 5110 each include a conformal conductive layer 5109A (such as a function setting layer) and a conductive filler material 5109B on the conformal conductive layer 5109A. Both the first gate electrode 5108 and the second gate electrode 5110 have a first side 5112 and a second side 5114 opposite to the first side 5112. Both the first gate electrode 5108 and the second gate electrode 5110 also have an insulating cap 5116, which has a top surface 5118.

[0505] The first dielectric spacer 5120 is adjacent to the first side 5112 of the first gate electrode 5108. The second dielectric spacer 5122 is adjacent to the second side 5114 of the second gate electrode 5110. The semiconductor source or drain region 5124 is adjacent to the first 5120 and the second 5122 dielectric spacers. The trench contact structure 5126 is located above the semiconductor source or drain region 5124 adjacent to the first 5120 and the second 5122 dielectric spacers.

[0506] The trench contact structure 5126 includes an insulating cap 5128 on the conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has a top surface 5129, which is substantially coplanar with the top surface 5118 of the insulating caps 5116 of the first gate electrodes 5108 and the second gate electrode 5110. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into a recess 5132 in the dielectric spacers of the first and second dielectric spacers 5120 and 5122. In this embodiment, the insulating cap 5128 of the trench contact structure 5126 protrudes from the conductive structure 5130 of the trench contact structure 5126. However, in other embodiments, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recess 5132 in the dielectric spacers of the first 5120 and the second 5122, and therefore does not protrude the conductive structure 5130 of the trench contact structure 5126.

[0507] It should be understood that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, as shown in Figures 51A-51C. For example, the conductive structure 5130 of the trench contact structure 5126 may have a cross-sectional geometry that is similar to or the same as the geometry shown for the conductive structure 5130A shown in the projection of Figure 51A.

[0508] In one embodiment, the insulating cap 5128 of the trench contact structure 5126 has a composition different from that of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 comprises a carbide material, such as silicon carbide. The insulating cap 5116 of the first 5108 and second 5110 gate electrodes comprises a nitride material, such as silicon nitride.

[0509] In one embodiment, the insulating caps 5116 of both the first 5108 and the second 5110 gate electrodes have a bottom surface 5117A that is lower than the bottom surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG51A. In another embodiment, the insulating caps 5116 of both the first 5108 and the second 5110 gate electrodes have a bottom surface 5117B that is substantially coplanar with the bottom surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG51B. In another embodiment, the insulating caps 5116 of both the first 5108 and the second 5110 gate electrodes have a bottom surface 5117C that is higher than the bottom surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown in FIG51C.

[0510] In one embodiment, the conductive structure 5130 of the trench contact structure 5128 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 on and above the U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. An insulating cap 5128 of the trench contact structure 5126 is located on the third metal layer 5138. In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 comprise titanium, while the T-shaped metal layer 5136 comprises cobalt. In a particular such embodiment, the T-shaped metal layer 5136 further comprises carbon.

[0511] In one embodiment, the metal silicate layer 5140 is directly situated between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In one such embodiment, the metal silicate layer 5140 comprises titanium and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicate layer 5140 comprises nickel, platinum, and silicon. In a particular such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another particular such embodiment, the metal silicate layer further comprises germanium.

[0512] In one embodiment, referring to FIG51D, a conductive via 5150 is located (and electrically connected) on a portion of a first gate electrode 5108 above the top 5102A of the fin 5102. The conductive via 5150 is located in an opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In one such embodiment, the conductive via 5150 is located on a portion of the insulating cap 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is located in an eroded portion 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0513] In one embodiment, referring to FIG51E, a conductive via 5160 is located (and electrically connected to) a portion of a trench contact structure 5126. The conductive via is located in an opening 5162 of an insulating cap 5128 of the trench contact structure 5126. In one such embodiment, the conductive via 5160 is located on a portion of an insulating cap 5116 of the first 5108 and second 5110 gate electrodes but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular such embodiment, the conductive via 5160 is located in an eroded portion 5164 of the insulating cap 5116 of the first 5108 and second 5110 gate electrodes.

[0514] Referring again to FIG51E, in one embodiment, the conductive via 5160 is a second conductive via having the same structure as the conductive via 5150 as shown in FIG51D. In one such embodiment, this second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, this second conductive via 5160 is merged with the conductive via 5150 to form an electrical short-circuit contact 5170, as shown in FIG51F.

[0515] The methods and structures described herein enable the formation of other structures or devices that are impossible or difficult to manufacture using other methods. In a first example, FIG52A illustrates a plan view of another semiconductor device having a gate contact via disposed above the active portion of the gate, according to another embodiment of the invention. Referring to FIG52A, the semiconductor structure or device 5200 includes a plurality of gate structures 5208A-5208C, which interlock with a plurality of trench contacts 5210A and 5210B (these features are disposed above the active region of the substrate and are not shown). A gate contact via 5280 is formed on the active portion of the gate structure 5208B. The gate contact via 5280 is further disposed on the active portion of the gate structure 5208C, coupling the gate structures 5208B and 5208C. It should be understood that intermediate trench contact 5210B can be isolated from contact 5280 by using a trench contact isolation capping layer (e.g., TILA). The contact configuration of Figure 52A provides an easier way to bundle adjacent gate lines in a layout without having to guide the bundle through the metallized upper layer, thus enabling smaller cell areas or less complex wiring schemes, or both.

[0516] In a second example, FIG. 52B illustrates a plan view of another semiconductor device having a trench contact via coupled to a pair of trench contacts, according to another embodiment of the invention. Referring to FIG. 52B, the semiconductor structure or device 5250 includes a plurality of gate structures 5258A-5258C, which interlock with a plurality of trench contacts 5260A and 5260B (these features are disposed on the active region of the substrate and are not shown). A trench contact via 5290 is formed on the trench contact 5260A. The trench contact via 5290 is further disposed on the trench contact 5260B, coupling the trench contacts 5260A and 5260B. It should be understood that the intermediate gate structure 5258B can be isolated from the trench contact via 5290 by using a gate isolation capping layer (e.g., by a GILA process). The contact configuration in Figure 52B provides an easier way to bundle adjacent trench contacts in a layout without having to guide the bundle through the metallized upper layer, thus enabling smaller cell areas or less complex wiring schemes, or both.

[0517] The insulating capping layer of the gate electrode can be fabricated using several deposition operations, and therefore may include artifacts from multiple deposition processes. As an example, Figures 53A-53E illustrate cross-sectional views showing various operations in a method of fabricating an integrated circuit structure having a gate stack covered by an insulating capping layer, according to an embodiment of the present invention.

[0518] Referring to Figure 53A, the initial structure 5300 includes a gate stack 5304 on a substrate or fin 5302. The gate stack 5304 includes a gate dielectric layer 5306, a conformal conductive layer 5308, and a conductive filler material 5310. In one embodiment, the gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer is a working function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312 (such as a thermal or chemical oxide silicon or silicon dioxide layer) is located between the substrate or fin 5302 and the gate dielectric layer 5306. Dielectric spacers 5314 (such as silicon nitride spacers) are adj...

Claims

1. A method of manufacturing an integrated circuit structure, the method comprising: forming a wire trench in an upper portion of an interlayer dielectric (ILD) material layer, the ILD material layer being formed on a lower metallization layer; forming a via trench in a lower portion of the ILD material layer, the via trench exposing metal lines of the lower metallization layer; forming a sacrificial material on the ILD material layer, in the wire trench, and in the via trench; patterning the sacrificial material to form openings to break the continuity of the sacrificial material in the wire trench; filling the openings in the sacrificial material with a dielectric material to form a dielectric plug having an upper surface on the upper surface of the ILD material; removing the sacrificial material and leaving the dielectric plug intact; filling the wire trench and the via trench with a conductive material; and planarizing the dielectric plug and the conductive material to provide a planarized dielectric plug, which breaks the continuity of the conductive material in the wire trench.

2. The method of claim 1, wherein filling the opening of the sacrificial material with the dielectric material comprises filling it with a metal oxide material.

3. The method of claim 2, wherein the metal oxide material is aluminum oxide.

4. The method of claim 1, wherein filling the opening of the sacrificial material with the dielectric material comprises using atomic layer deposition (ALD) for filling.

5. The method of claim 1, wherein forming the sacrificial material comprises forming a hard masking material comprising carbon.

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