Display device and motherboard

Abstract

According to one embodiment of the present invention, a display device includes: an organic insulating layer disposed over a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering the periphery of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion located on the inorganic insulating layer, and a first upper portion located on the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the inorganic insulating layer having an annular groove surrounding the display area in the peripheral area; and the plurality of peripheral partitions including a pair of first partitions facing each other across the groove.

Description

Technical Field

[0001] The present invention relates to a display device and a mother substrate. Prior Technology

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. These display elements include: pixel circuits containing thin-film transistors, a lower electrode connected to the pixel circuits, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer.

[0003] In the process of manufacturing this display element, there must be technology to suppress the reduction of reliability. Summary of the Invention

[0004] The purpose of this embodiment is to provide a display device and motherboard that can suppress the reduction of reliability.

[0005] According to one embodiment of the present invention, the display device comprises: A substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area further outward from the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer, covering the periphery of the lower electrode; an organic layer disposed on the lower electrode, including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion located on the inorganic insulating layer, and a first upper portion located on the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the inorganic insulating layer having an annular groove surrounding the display area in the peripheral area; and the plurality of peripheral partitions including a pair of first partitions facing each other across the groove.

[0006] According to one embodiment of the present invention, the display device comprises: A substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area further outward from the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer, covering the periphery of the lower electrode; an organic layer disposed on the lower electrode, including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion and a first upper portion located above the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the plurality of peripheral partitions including a second partition disposed in the gap; the second partition disposed along a corner portion of the outer edge of the organic insulating layer, forming an L-shape when viewed from above.

[0007] According to one embodiment of the present invention, the display device comprises: A substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area further outward from the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer, covering the periphery of the lower electrode; an organic layer disposed on the lower electrode, including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion and a first upper portion located above the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the outer edge of the organic insulating layer including a rounded corner portion; the radius of curvature of the rounded corner portion being equal to or greater than the width of the gap portion.

[0008] According to one embodiment, the mother substrate includes: A panel portion having a display area for displaying an image and a peripheral area outside the aforementioned display area; a blank area outside the aforementioned panel portion; an organic insulating layer disposed throughout the aforementioned panel portion and the aforementioned blank area; a lower electrode disposed on the aforementioned organic insulating layer in the aforementioned display area; an inorganic insulating layer disposed on the aforementioned organic insulating layer and covering the peripheral portion of the aforementioned lower electrode; an organic layer disposed on the aforementioned lower electrode and including a light-emitting layer; an upper electrode disposed on the aforementioned organic layer; and a plurality of peripheral partition walls disposed in the aforementioned peripheral area; each of the aforementioned plurality of peripheral partition walls having: a first lower portion located on the aforementioned inorganic insulating layer, and a first upper portion located on the aforementioned first lower portion and protruding from the side of the aforementioned first lower portion; the aforementioned inorganic insulating layer having an annular first groove surrounding the aforementioned display area in the aforementioned peripheral area; the aforementioned plurality of peripheral partition walls including a pair of first partition walls facing each other across the aforementioned first groove.

[0009] According to one embodiment, the mother substrate includes: A panel portion having a display area for displaying an image and a peripheral area extending outward from the display area; a blank area extending outward from the panel portion; an organic insulating layer disposed throughout the panel portion and the blank area; a lower electrode disposed in the display area on the organic insulating layer; an inorganic insulating layer disposed on the organic insulating layer and covering the periphery of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a composite layer. Several peripheral partition walls are disposed in the aforementioned peripheral area; and each of the aforementioned plurality of peripheral partition walls has: a first lower portion located above the aforementioned inorganic insulating layer, and a first upper portion located above the aforementioned first lower portion and protruding from the side of the aforementioned first lower portion; the aforementioned organic insulating layer has a gap along the outer shape of the aforementioned panel portion; the aforementioned plurality of peripheral partition walls includes a second partition wall disposed in the aforementioned gap; the aforementioned second partition wall is disposed along the corner portion of the outer edge of the aforementioned organic insulating layer, forming an L-shape when viewed from above.

[0010] According to one embodiment, the mother substrate includes: The panel portion has a display area for displaying an image and a peripheral area located outside the aforementioned display area; a blank area located outside the aforementioned panel portion; an organic insulating layer disposed throughout the aforementioned panel portion and the aforementioned blank area; a lower electrode disposed on the aforementioned organic insulating layer in the aforementioned display area; an inorganic insulating layer disposed on the aforementioned organic insulating layer and covering the peripheral portion of the aforementioned lower electrode; an organic layer disposed on the aforementioned lower electrode and including a light-emitting layer; an upper electrode disposed on the aforementioned organic layer; and a plurality of peripheral partition walls disposed in the aforementioned peripheral area; each of the aforementioned plurality of peripheral partition walls has: a first lower portion located on the aforementioned inorganic insulating layer, and a first upper portion located on the aforementioned first lower portion and protruding from the side of the aforementioned first lower portion; the aforementioned organic insulating layer has a gap along the outer shape of the aforementioned panel portion; the outer edge of the aforementioned organic insulating layer includes a rounded corner portion; the radius of curvature of the aforementioned rounded corner portion is equal to or greater than 1 / 2 of the width of the aforementioned gap portion.

[0011] Depending on the implementation, a display device and a mother substrate that can suppress the reduction in reliability can be provided. Simple Explanation of the Diagram

[0012] Figure 1 is a diagram illustrating an example of the configuration of a display device DSP. Figure 2 shows an example of the layout of subpixels SP1, SP2, and SP3. Figure 3 is a schematic cross-sectional view of the display device DSP along line AB in Figure 2. Figure 4 is a diagram illustrating the manufacturing method of a display device DSP. Figure 5 is a diagram illustrating the manufacturing method of a display device DSP. Figure 6 is a diagram illustrating the manufacturing method of a display device DSP. Figure 7 is a diagram illustrating the manufacturing method of a display device DSP. Figure 8 is a diagram illustrating the manufacturing method of a display device DSP. Figure 9 is a diagram illustrating the manufacturing method of a display device DSP. Figure 10 is a top view of an example of a mother substrate 100. Figure 11 is a top view showing one configuration example of region 100A of the mother substrate 100 shown in Figure 10. Figure 12 is a top view showing one configuration example of region 100B shown in Figure 11. Figure 13 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 12. Figure 14 is a cross-sectional view showing one configuration example of the mother substrate 100. Figure 15 is a cross-sectional view showing another configuration example of the mother substrate 100. Figure 16 is a cross-sectional view showing another configuration example of the mother substrate 100. Figure 17 is an enlarged cross-sectional view of the area containing slot 5G. Figure 18 is a cross-sectional view illustrating the state in which a laminated film FL1 is formed in the region including the void G shown in Figure 14. Figure 19 is a cross-sectional view illustrating the configuration in which a laminated film FL1 is formed in the region containing the groove 5G shown in Figure 17. Figure 20 is a top view showing another configuration example of region 100B shown in Figure 11. Figure 21 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 20. Figure 22 is a cross-sectional view showing one configuration example of the mother substrate 100. Figure 23 is a cross-sectional view showing another configuration example of the mother substrate 100. Figure 24 is a cross-sectional view showing another configuration example of the mother substrate 100. Figure 25 is a diagram illustrating the adverse conditions that may occur when the peripheral partition wall 9A is not configured. Figure 26 is a top view showing another configuration example of region 100A of the mother substrate 100 shown in Figure 10. Figure 27 is a top view showing one of the configuration examples of region 100B shown in Figure 26. Figure 28 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 27. Implementation

[0013] The implementation method is explained while referring to the diagram.

[0014] The disclosed examples are merely one instance, and appropriate modifications that can be readily conceived by those skilled in the art to maintain the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the drawings schematically show the width, thickness, shape, etc., of each part compared to the actual form, but these are merely one example and are not intended to limit the interpretation of this invention. Also, in this specification and the drawings, sometimes the same reference numerals are used for constituent elements that perform the same or similar functions as the constituent elements described in the previously shown drawings, and repeated detailed descriptions are appropriately omitted.

[0015] Furthermore, in the diagram, mutually orthogonal X-axis, Y-axis, and Z-axis are shown as needed and for ease of understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0016] The display device of this embodiment is an organic electroluminescent display device with an organic light-emitting diode (OLED) as the display element, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, etc.

[0017] Figure 1 is a diagram illustrating an example of the configuration of a display device DSP.

[0018] The display device DSP has a display panel PNL on an insulating substrate 10. The display panel PNL has a display area DA for displaying images and a peripheral area SA located outside the display area DA. The substrate 10 can be glass or a flexible resin film.

[0019] In this embodiment, the shape of the substrate 10 viewed from above is rectangular. However, the shape of the substrate 10 viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an oval.

[0020] The display area DA has a plurality of pixels PX arranged in a matrix along the first direction X and the second direction Y. Pixel PX contains a plurality of sub-pixels SP. In one example, pixel PX contains a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are all different colors. In addition, pixel PX may contain sub-pixels SP of other colors such as white, either together with or in place of any of the sub-pixels SP1, SP2, and SP3.

[0021] The sub-pixel SP includes: a pixel circuit 1, and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes: a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements made of, for example, thin-film transistors.

[0022] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source electrode and drain electrode of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0023] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may include more thin-film transistors and capacitors.

[0024] Display elements, specifically organic light-emitting diodes (OLEDs), are light-emitting elements, sometimes referred to as organic EL elements.

[0025] The surrounding area SA has a plurality of terminals TE arranged along one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends along the second direction Y, but is not limited thereto. For example, a portion of the plurality of terminals TE may extend in an oblique direction. This plurality of terminals TE may be electrically connected, for example, to a flexible printed circuit board or an IC chip.

[0026] Figure 2 shows an example of the layout of subpixels SP1, SP2, and SP3.

[0027] In the example shown, sub-pixels SP2 and SP3 are arranged along the second direction Y. Sub-pixels SP1 and SP2 are arranged along the first direction X, and sub-pixels SP1 and SP3 are arranged along the first direction X.

[0028] With sub-pixels SP1, SP2, and SP3 arranged in this layout, in the display area DA, a row is formed by alternating sub-pixels SP2 and SP3 along the second direction Y, and a row is formed by a plurality of sub-pixels SP1 along the second direction Y. These rows are arranged alternately along the first direction X.

[0029] Furthermore, the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. As another example, the sub-pixels SP1, SP2, and SP3 of each pixel PX can be arranged sequentially along the first direction X.

[0030] An inorganic insulating layer 5 and a partition wall 6 are disposed in the display area DA. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 with these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0031] The partition wall 6 overlaps with the inorganic insulating layer 5 when viewed from above. The partition wall 6 is formed in a grid shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 may also have openings in the sub-pixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and electrically connected to the common potential terminal TE among the plurality of terminals TE shown in FIG1.

[0032] Subpixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively, serving as display elements DE.

[0033] The display element DE1 of sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with the opening AP1. The periphery of the lower electrode LE1 is covered by an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 when viewed from above. The peripheries of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 when viewed from above. The organic layer OR1 includes a light-emitting layer that emits light, for example, in the blue wavelength band.

[0034] The display element DE2 of sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the opening AP2. The periphery of the lower electrode LE2 is covered by an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 when viewed from above. The periphery of each of the organic layer OR2 and the upper electrode UE2 overlaps with the inorganic insulating layer 5 when viewed from above. The organic layer OR2 includes a light-emitting layer that emits light, for example, in the green wavelength band.

[0035] The display element DE3 of sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the opening AP3. The periphery of the lower electrode LE3 is covered by an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 when viewed from above. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap the inorganic insulating layer 5 when viewed from above. The organic layer OR3 includes a light-emitting layer that emits light in, for example, the red wavelength band.

[0036] In the illustrated example, the shapes of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, while the shapes of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are represented by dotted chain lines. Furthermore, the shapes of the lower electrodes, organic layers, and upper electrodes in the illustration are not limited to accurately representing their respective shapes.

[0037] The lower electrodes LE1, LE2, and LE3 correspond to the anode of the display element, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode, and are in contact with the partition wall 6.

[0038] The lower electrode LE1 is electrically connected to pixel circuit 1 of sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to pixel circuit 1 of sub-pixel SP2. The lower electrode LE3 is electrically connected to pixel circuit 1 of sub-pixel SP3.

[0039] In the example shown, the areas of openings AP1, AP2, and AP3 are all different. The area of ​​opening AP1 is larger than that of opening AP2, and the area of ​​opening AP2 is larger than that of opening AP3. In other words, the area of ​​electrode LE1 exposed from opening AP1 is larger than that of electrode LE2 exposed from opening AP2, and the area of ​​electrode LE2 exposed from opening AP2 is larger than that of electrode LE3 exposed from opening AP3.

[0040] Figure 3 is a schematic cross-sectional view of the display device DSP along line AB in Figure 2.

[0041] A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1, and various wirings such as scan lines GL, signal lines SL, and power lines PL. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens the surface created by the circuit layer 11.

[0042] Lower electrodes LE1, LE2, and LE3 are disposed on insulating layer 12 and are separated from each other. Inorganic insulating layer 5 is disposed on insulating layer 12 and lower electrodes LE1, LE2, and LE3. Opening AP1 of inorganic insulating layer 5 overlaps with lower electrode LE1, opening AP2 overlaps with lower electrode LE2, and opening AP3 overlaps with lower electrode LE3. The periphery of lower electrodes LE1, LE2, and LE3 is covered by inorganic insulating layer 5. Lower electrodes LE1, LE2, and LE3 are connected to pixel circuits 1 of sub-pixels SP1, SP2, and SP3 respectively via contact holes provided in insulating layer 12. Furthermore, the contact holes of insulating layer 12 are omitted in Figure 3.

[0043] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. The two ends of the upper portion 62 protrude beyond the sides of the lower portion 61. The shape of this partition wall 6 is described as overhanging.

[0044] In the illustrated example, the lower part 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed to be thinner than the second conductive layer 64. Also, in the illustrated example, both ends of the first conductive layer 63 protrude from the sides of the second conductive layer 64.

[0045] The upper part 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. The two ends of the first thin film 65 and the second thin film 66 protrude from the side of the second conductive layer 64.

[0046] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its periphery is located above the inorganic insulating layer 5. The upper electrode UE1 is covered by the organic layer OR1 and contacts the lower part 61.

[0047] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its periphery is located above the inorganic insulating layer 5. The upper electrode UE2 is covered by the organic layer OR2 and contacts the lower part 61.

[0048] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its periphery is located above the inorganic insulating layer 5. The upper electrode UE3 is covered by the organic layer OR3 and contacts the lower part 61.

[0049] In the illustrated example, sub-pixel SP1 has a capping layer CP1 and a sealing layer SE1, sub-pixel SP2 has a capping layer CP2 and a sealing layer SE2, and sub-pixel SP3 has a capping layer CP3 and a sealing layer SE3. The capping layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the light extraction efficiency emitted by the organic layers OR1, OR2, and OR3. Alternatively, the capping layers CP1, CP2, and CP3 can be omitted.

[0050] The cover layer CP1 is disposed on the upper electrode UE1.

[0051] The cover layer CP2 is configured on the upper electrode UE2.

[0052] The cover layer CP3 is disposed on the upper electrode UE3.

[0053] The sealing layer SE1 is disposed on the cover layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1.

[0054] The sealing layer SE2 is disposed on the cover layer CP2, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP2.

[0055] The sealing layer SE3 is disposed on the cover layer CP3, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP3.

[0056] In the illustrated example, a portion of each of the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is located on the partition wall 6 surrounding the sub-pixel SP1. These portions are separate from the portions of the organic layer OR1, the upper electrode UE1, and the cover layer CP1 located at the opening AP1 (which constitute the display element DE1).

[0057] Similarly, a portion of each of the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is located on the partition wall 6 surrounding the sub-pixel SP2, and these portions are separate from the portions of the organic layer OR2, the upper electrode UE2, and the cover layer CP2 located at the opening AP2 (the portion constituting the display element DE2).

[0058] Similarly, a portion of each of the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is located on the partition wall 6 surrounding the sub-pixel SP3, and these portions are separate from the portions of the organic layer OR3, the upper electrode UE3, and the cover layer CP3 located at the opening AP3 (the portion constituting the display element DE3).

[0059] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as stacked film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as stacked film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as stacked film FL3.

[0060] The ends of sealing layers SE1, SE2, and SE3, and the ends of laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the illustrated example, the laminated film FL1 and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP2 are separate from the laminated film FL2 and sealing layer SE2 on the partition wall 6. Furthermore, the laminated film FL1 and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separate from the laminated film FL3 and sealing layer SE3 on the partition wall 6.

[0061] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15.

[0062] The inorganic insulating layer 5, sealing layers SE1, SE2, SE3, and sealing layer 14 are formed, for example, by inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), and aluminum oxide (Al2O3).

[0063] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed, for example, of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper part 62, for example, of an aluminum-based material such as aluminum or an aluminum compound.

[0064] The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material. The upper part 62 may be formed of a different material than the lower part 61. The first thin film 65 is formed, for example, of a titanium-based material such as titanium or titanium compounds. The second thin film 66 is formed, for example, of an oxide conductive material such as indium tin oxide (ITO).

[0065] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer structures comprising a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a reflective layer between a pair of transparent layers. The lower transparent layer functions as a close-fitting layer to the insulating layer 12.

[0066] Organic layer OR1 contains light-emitting layer EM1. Organic layer OR2 contains light-emitting layer EM2. Organic layer OR3 contains light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, light-emitting layer EM1 is formed of a material that emits light in the blue wavelength band, light-emitting layer EM2 is formed of a material that emits light in the green wavelength band, and light-emitting layer EM3 is formed of a material that emits light in the red wavelength band.

[0067] Furthermore, each of the organic layers OR1, OR2, and OR3 contains multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0068] The upper electrodes UE1, UE2, and UE3 are formed, for example, from metallic materials such as an alloy of magnesium and silver (MgAg).

[0069] The capping layers CP1, CP2, and CP3 are multilayers of multiple thin films. All of the multiple thin films are transparent and have different refractive indices.

[0070] The circuit layer 11, insulating layer 12, and inorganic insulating layer 5 shown in the diagram are arranged around the display area DA and the surrounding area SA.

[0071] Next, the manufacturing method of the display device DSP will be explained. Furthermore, for the figures used to illustrate the manufacturing method, the figures below the insulating layer 12 are omitted.

[0072] First, after forming a circuit layer 11 and an insulating layer 12 on the substrate 10, covering the display area DA and the surrounding area SA, as shown in FIG4, the lower electrode LE1 of sub-pixel SP1, the lower electrode LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are formed on the insulating layer 12.

[0073] Subsequently, an inorganic insulating layer 5 is formed covering the periphery of the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 5 includes silicon oxide, silicon nitride, silicon nitride, etc.

[0074] Next, a partition wall 6 is formed, which has a lower portion 61 located above the inorganic insulating layer 5 and an upper portion 62 located above the lower portion 61. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the side of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as titanium, and the second conductive layer 64 is formed of a conductive material such as aluminum.

[0075] Furthermore, the process of forming openings AP1, AP2, and AP3 in the inorganic insulating layer 5 can be performed before or after the formation of the partition wall 6.

[0076] Subsequently, display element DE1 is formed.

[0077] First, as shown in Figure 5, a multilayer film FL1 comprising an organic layer OR1, an upper electrode UE1, and a capping layer CP1 is formed. The process of forming the multilayer film FL1 includes the following steps: forming an organic layer OR1 in the opening AP1 that contacts the lower electrode LE1; forming an upper electrode UE1 that covers the organic layer OR1 and contacts the lower part 61 of the partition wall 6; and forming a capping layer CP1 located above the upper electrode UE1. Furthermore, the process of forming the organic layer OR1 includes the following steps: forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer, respectively. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by vapor deposition with the partition wall 6 as a mask. The multilayer film FL1 is divided into multiple parts by the suspended partition wall 6. These organic layers OR1, the upper electrode UE1, and the capping layer CP1 are formed continuously while maintaining a vacuum environment.

[0078] Subsequently, an insulating layer SE1 is formed on the laminated film FL1 by depositing an inorganic insulating material. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers the segmented portions of the laminated film FL1 and the partition walls 6.

[0079] Subsequently, as shown in Figure 6, a resist RS patterned into a prescribed shape is formed on the sealing layer SE1. The resist RS overlaps a portion of the sub-pixel SP1 and the surrounding partition wall 6.

[0080] Subsequently, as shown in Figure 7, etching is performed using the resist RS as a mask to sequentially remove the sealing layer SE1 and the stacked film FL1 exposed from the resist RS. In this etching, after removing the sealing layer SE1 exposed from the resist RS, the capping layer CP1 exposed from the sealing layer SE1 is removed. Then, after removing the upper electrode UE1 exposed from the capping layer CP1, the organic layer OR1 exposed from the upper electrode UE1 is removed. This exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3.

[0081] Next, the resist RS is removed. This allows the display element DE1 to be formed on the sub-pixel SP1.

[0082] Next, as shown in Figure 8, display element DE2 is formed. The steps for forming display element DE2 are the same as those for forming display element DE1. That is, on the lower electrode LE2, an organic layer OR2 including the light-emitting layer EM2, an upper electrode UE2, and a capping layer CP2 are sequentially formed to form a multilayer film FL2. Then, a sealing layer SE2 is formed on the multilayer film FL2. Then, a photoresist is formed on the sealing layer SE2, and the sealing layer SE2, the capping layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching with the photoresist as a mask. After this patterning, the photoresist is removed. Herein, display element DE2 is formed on sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 is exposed.

[0083] Next, as shown in Figure 9, display element DE3 is formed. The steps for forming display element DE3 are the same as those for forming display element DE1. That is, on the lower electrode LE3, an organic layer OR3 including the light-emitting layer EM3, an upper electrode UE3, and a capping layer CP3 are sequentially formed to form a multilayer film FL3. Then, a sealing layer SE3 is formed on the multilayer film FL3. Then, a photoresist is formed on the sealing layer SE3, and the sealing layer SE3, capping layer CP3, upper electrode UE3, and organic layer OR3 are patterned by etching with the photoresist as a mask. After this patterning, the photoresist is removed. In this way, display element DE3 is formed on sub-pixel SP3.

[0084] Then, resin layer 13, sealing layer 14, and resin layer 15, as shown in Figure 3, are formed in sequence. This completes the display device DSP.

[0085] Furthermore, in the above manufacturing process, it is conceivable that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0086] Next, the mother substrate (hereinafter referred to as the mother substrate) 100 for use in batch manufacturing of multiple display devices DSPs will be described.

[0087] Figure 10 is a top view of an example of a mother substrate 100.

[0088] The mother substrate 100 has a plurality of panel portions PP and blank portions MP located outside the large substrate 10. The large substrate 10 is formed, for example, rectangular. The plurality of panel portions PP are arranged in a matrix along a first direction X and a second direction Y. Each panel portion PP is removed by cutting along a cutting line through the mother substrate 100. Each removed panel portion PP corresponds to the display panel PNL shown in FIG. 1.

[0089] Figure 11 is a top view showing one configuration example of region 100A of the mother substrate 100 shown in Figure 10.

[0090] Region 100A includes one panel portion PP. The cutting lines CL, indicated by a chain line at a point in the figure, extend, for example, along the first direction X and the second direction Y. These cutting lines CL can be the shape of the display panel PNL shown in Figure 1. Each panel portion PP has a display area DA and a peripheral area SA.

[0091] The organic insulating layer IL includes at least the insulating layer 12 shown in FIG. 3. The organic insulating layer IL is disposed on each panel portion PP and also on the blank portion MP. The organic insulating layer IL has a blank portion G along the outer shape of the panel portion PP. A cutting line CL overlaps the blank portion G. The blank portion G penetrates the area of ​​the organic insulating layer IL with the substrate exposed, forming a grid-like groove surrounding each panel portion PP. In the illustrated example, the blank portion G extends along the first direction X and the second direction Y, respectively. Furthermore, the blank portion G has a terminal portion GE located at the blank portion MP.

[0092] Focusing on a single panel portion PP, the empty portion G is formed as a ring surrounding the panel portion PP. Within the panel portion PP, the display area DA overlaps with an island-shaped organic insulating layer IL. Furthermore, a portion of the peripheral area SA also overlaps with the organic insulating layer IL.

[0093] The inorganic insulating layer 5 has an annular groove (first groove) 5G surrounding the display area DA in the peripheral region SA of the panel portion PP. The groove 5G is formed between the display area DA and the empty portion G. Furthermore, the inorganic insulating layer 5 has a groove (second groove) 5GA in the blank portion MP that includes the terminal portion GE of the empty portion G. The grooves 5G and 5GA penetrate the region of the inorganic insulating layer 5 with the substrate (organic insulating layer IL) exposed. The empty portion G of the organic insulating layer IL is located between the grooves 5G and 5GA.

[0094] The portion of the inorganic insulating layer 5 that overlaps with the display area DA and the portion between the slot 5G and the empty portion G, or the portion between the slot 5G and the slot 5GA, are separated. Furthermore, the portion of the inorganic insulating layer 5 between the slot 5G and the slot 5GA is separated from the portion further outward than the slot 5GA.

[0095] Figure 12 is a top view showing one configuration example of region 100B shown in Figure 11.

[0096] Region 100B includes the intersection of a cutting line CL extending along the first direction X and a cutting line CL extending along the second direction Y.

[0097] Metal layers MT are disposed in the void portion G. In the intersection portion, four metal layers MT are separated from each other and formed in an L-shape along the cutting line CL. The cutting line CL extending along the first direction X is located between two adjacent metal layers MT in the second direction Y. Also, the cutting line CL extending along the second direction Y is located between two adjacent metal layers MT in the first direction X. A cross-shaped space is formed between the four metal layers MT. These four metal layers MT function, for example, as alignment marks for aligning the mother substrate 100.

[0098] Peripheral partitions 7, 8, and 9 are disposed in the peripheral area SA and blank area MP of the panel portion PP, and are separated from each other. In top view, peripheral partitions 7 and 8 overlap the organic insulating layer IL, and peripheral partition 9 overlaps the blank area G. These peripheral partitions 7, 8, and 9 are not described in detail here, but have the same cross-sectional shape as the partition 6 of the display area DA, having a lower part and an upper part located above the lower part and protruding from the side of the lower part.

[0099] The peripheral partition wall 7 is formed in a grid pattern. In one example, the peripheral partition wall 7 is formed with the same pattern as the grid-shaped partition wall 6 shown in Figure 2.

[0100] A plurality of peripheral partition walls (first partition walls) 8 are located between the peripheral partition wall 7 and the vacancy G, and are arranged along the groove 5G. For example, the plurality of peripheral partition walls 8 includes a pair of peripheral partition walls 8 that extend respectively along the first direction X and are arranged along the second direction Y. In this way, the pair of peripheral partition walls 8 arranged along the second direction Y faces each other across the groove 5G extending along the first direction X. Also, the plurality of peripheral partition walls 8 includes a pair of peripheral partition walls 8 that extend respectively along the second direction Y and are arranged along the first direction X. In this way, each of the pair of peripheral partition walls 8 arranged along the first direction X faces each other across the groove 5G extending along the second direction Y. Also, the plurality of peripheral partition walls 8 includes an L-shaped peripheral partition wall 8 arranged along the corner of the groove 5G.

[0101] A plurality of peripheral partition walls (second partition walls) 9 are disposed in the void portion G. In the void portion G, the peripheral partition walls 9 are disposed along the cutting line CL. For example, the plurality of peripheral partition walls 9 includes a peripheral partition wall 9 extending along a first direction X. This peripheral partition wall 9 is disposed along the cutting line CL extending along the first direction X. Also, the plurality of peripheral partition walls 9 includes a peripheral partition wall 9 extending along a second direction Y. This peripheral partition wall 9 is disposed along the cutting line CL extending along the second direction Y. Also, the plurality of peripheral partition walls 9 includes an L-shaped peripheral partition wall 9 disposed along the intersection of the cutting lines CL. In top view, several peripheral partition walls 9 located at the intersection overlap the metal layer MT. However, from the viewpoint of preventing misidentification of alignment marks, it is more ideal for the peripheral partition walls 9 overlapping the metal layer MT not to cross areas where the metal layer MT does not exist. In the void portion G, the metal layer MT and the peripheral partition walls 9 are disposed so as not to overlap the cutting line CL from the viewpoint of preventing poor cutting.

[0102] During the wet etching process for forming peripheral partitions 7, 8, and 9, based on the viewpoint of preventing the disappearance of peripheral partitions 9 due to excessive removal of the peripheral partitions 9 disposed in the void portion G, it is ideal for the width W9 of the peripheral partitions 9 disposed in the void portion G to be larger than the width W7 of the peripheral partitions 7 disposed above the organic insulating layer IL. In the illustrated example, the width W8 of the peripheral partition 8 is larger than the width W7, but it can be equal to the width W7.

[0103] Figure 13 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 12.

[0104] The cutting line CL shown in Figure 12 corresponds to the outer edge 10E of the substrate 10. However, after the mother substrate 100 is cut by the cutting line CL, the panel portion is further cut and shaped into the desired shape. At least a portion of the outer edge 10E is located at a different position than the cutting line CL shown in Figure 12.

[0105] An organic insulating layer IL is disposed throughout the display area DA and the peripheral area SA. In the peripheral area SA, the organic insulating layer IL has a void LP along its outer edge 10E. In the illustrated example, the void LP is formed in a ring shape, extending along the entire circumference of the outer edge 10E. The void LP corresponds to a portion of the void G shown in Figure 12.

[0106] The outer edge ILE of the organic insulating layer IL does not overlap with the outer edge 10E of the substrate 10 when viewed from above, and is located between the outer edge 10E and the display area DA.

[0107] If one corner of the substrate 10 is enlarged, the metal layer MT, which constitutes part of the alignment mark as shown in FIG. 12, and the peripheral partition wall 9 are disposed in the vacancy LP. In other words, the metal layer MT and the peripheral partition wall 9 are located between the outer edge 1LE and the outer edge 10E in top view. The metal layer MT is formed in an L-shape along the corner of the substrate 10. The peripheral partition wall 9 overlapping a portion of the metal layer MT is formed in a straight line along the outer edge 10E. Furthermore, the other peripheral partition walls 9 overlapping the metal layer MT are formed in an L-shape along the corner of the substrate 10.

[0108] In the surrounding area SA, the peripheral partition walls 7 overlapping the organic insulating layer IL form a lattice shape when viewed from above. Furthermore, a pair of peripheral partition walls 8, which are interspersed with gaps in the organic insulating layer IL, face each other across the slot 5G.

[0109] Next, several configuration examples will be described with respect to the cross-sectional structure of the mother substrate 100 along line CD in Figure 12.

[0110] Figure 14 is a cross-sectional view showing one configuration example of the mother substrate 100.

[0111] Insulating layer 111 is an inorganic insulating layer disposed on substrate 10. Insulating layer 112 is an organic insulating layer disposed on insulating layer 111. These insulating layers 111 and 112 are included in circuit layer 11 shown in FIG. 3. Furthermore, insulating layer 111 may be omitted. Additionally, other insulating layers and conductive layers may be disposed between substrate 10 and insulating layer 111. The metal layer MT shown in FIG. 12 is disposed between substrate 10 and insulating layer 111.

[0112] Insulating layer 12 is an organic insulating layer that covers insulating layer 112 and has a vacancy G in the area where it is in contact with insulating layer 111. In the configuration example shown in FIG14, the above-mentioned organic insulating layer IL has insulating layer 112 and insulating layer 12. Considering the cross-sectional shape of this organic insulating layer IL, the organic insulating layer IL has a stepped cross-section in which the thickness decreases towards the vacancy G.

[0113] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 112 and the thickness of the insulating layer 12, which is equivalent to the length along the third direction Z from the upper surface of the insulating layer 111 to the generally flat upper surface 121A of the insulating layer 12.

[0114] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 12, which is equivalent to the length along the third direction Z from the upper surface of the insulating layer 111 to the generally flat upper surface 122A of the insulating layer 12. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the vacancy G, and is located below the upper surface 121A.

[0115] Inorganic insulating layer 5 covers insulating layer 12, and insulating layer 111 covers the vacancy G. Groove 5G extends to the upper surface 121A of insulating layer 12. Groove 5G can be formed, for example, by the same process as opening AP1 shown in FIG2.

[0116] Peripheral partition walls 7 and 8 are disposed above the organic insulating layer IL, and peripheral partition wall 9 is disposed in the vacancy G. In the illustrated example, peripheral partition walls 7 and 8 are disposed above the upper surface 121A, but on the other hand, they are not disposed above the upper surface 122A. However, peripheral partition walls 7 and 8 may be disposed above the upper surface 122A.

[0117] The peripheral partition wall 7 has a lower portion 71 disposed above the inorganic insulating layer 5 and an upper portion 72 disposed above the lower portion 71. The upper portion 72 has a wider width than the lower portion 71. The two ends of the upper portion 72 protrude beyond the sides of the lower portion 71.

[0118] The peripheral partition wall 8 has a lower portion 81 disposed above the inorganic insulating layer 5 and an upper portion 82 disposed above the lower portion 81. The upper portion 82 has a wider width than the lower portion 81. The two ends of the upper portion 82 protrude beyond the sides of the lower portion 81.

[0119] The peripheral partition wall 9 has a lower portion 91 disposed above the inorganic insulating layer 5 and an upper portion 92 disposed above the lower portion 91. The upper portion 92 has a wider width than the lower portion 91. The two ends of the upper portion 92 protrude beyond the sides of the lower portion 91.

[0120] Thus, the peripheral partition walls 7, 8, and 9 are each suspended in the same manner as partition wall 6 shown in Figure 3. Peripheral partition walls 7, 8, and 9 can be formed using the same process as partition wall 6. In this case, the lower parts 71, 81, and 91 are formed from the same material as the lower part 61, and the upper parts 72, 82, and 92 are formed from the same material as the upper part 62.

[0121] Organic insulating layers (ILs) with stepped cross-sections can be formed, for example, by the following method.

[0122] First, an insulating layer 112 is formed on the insulating layer 111. Then, an insulating layer 12 having a vacancy G, an upper surface 121A, and an upper surface 122A is formed. This insulating layer 12 can be formed, for example, by the following method.

[0123] That is, an insulating layer is formed on the entire surface of the mother substrate 100 where the insulating layer 112 is formed, using, for example, a positive organic material. Then, the insulating layer is exposed. In this exposure process, the exposure amount for the vacancy portion G is set to the maximum, and the exposure amount gradually decreases from the vacancy portion G outwards. Then, the exposed insulating layer is developed. Finally, the insulating layer is baked.

[0124] In this way, an organic insulating layer IL with the aforementioned cross-sectional shape is formed. The void G formed at this time is formed as a ring surrounding the display area DA or the panel portion PP, as shown in Figure 11, etc.

[0125] In this configuration example, when the mother substrate 100 is cut by the cutting line CL, the cross section of the display panel PNL along the C'-D' line in FIG13 corresponds to the cross section of the mother substrate 100 shown in FIG14, which is located to the left of the cutting line CL.

[0126] Figure 15 is a cross-sectional view showing another configuration example of the mother substrate 100.

[0127] The configuration example shown in Figure 15 differs from the configuration example shown in Figure 14 in that the insulating layer 112 extends further towards the cutting line CL than the insulating layer 12. The insulating layer 112 has a vacancy G. The insulating layer 12 is disposed on the insulating layer 112. Focusing on the cross-sectional shape of the organic insulating layer IL having the insulating layer 112 and the insulating layer 12, the organic insulating layer IL has a stepped cross-section in which the thickness decreases towards the vacancy G.

[0128] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 112 and the thickness of the insulating layer 12, which is equivalent to the length along the third direction Z from the upper surface of the insulating layer 111 to the generally flat upper surface 12A of the insulating layer 12.

[0129] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 112 exposed from the insulating layer 12, and is equivalent to the length along the third direction Z from the upper surface of the insulating layer 111 to the generally flat upper surface 112A of the insulating layer 112. The thickness T2 is smaller than the thickness T1. The upper surface 112A is located between the upper surface 12A and the vacancy G, and is located below the upper surface 12A.

[0130] Inorganic insulating layer 5 covers insulating layer 12, covers insulating layer 112 exposed from insulating layer 12, and covers insulating layer 111 in the vacancy G. Groove 5G extends to the upper surface 12A of insulating layer 12.

[0131] Peripheral partition walls 7 and 8 are disposed above the organic insulating layer IL, and peripheral partition wall 9 is disposed in the vacancy G. In the illustrated example, peripheral partition walls 7 and 8 are disposed above the upper surface 12A, but on the other hand, they are not disposed above the upper surface 112A. However, peripheral partition walls 7 and 8 may be disposed above the upper surface 112A. The lower portions 71, 81, and 91 of each of the peripheral partition walls 7, 8, and 9 are disposed above the inorganic insulating layer 5.

[0132] Organic insulating layers (ILs) with stepped cross-sections can be formed, for example, by the following method.

[0133] First, an insulating layer 112 having a vacancy G and an upper surface 112A is formed on the insulating layer 111. Then, an insulating layer 12 having an upper surface 12A is formed on the insulating layer 112. At this time, the insulating layer 12 is formed such that a portion of the insulating layer 112 is exposed near the vacancy G.

[0134] In this way, an organic insulating layer IL with the above-mentioned cross-sectional shape is formed.

[0135] In this configuration example, when the mother substrate 100 is cut by the cutting line CL, the cross section of the display panel PNL along the C'-D' line in FIG13 corresponds to the cross section of the mother substrate 100 shown in FIG15, which is located to the left of the cutting line CL.

[0136] Figure 16 is a cross-sectional view showing another configuration example of the mother substrate 100.

[0137] Comparing the configuration example shown in Figure 16 with the configuration example shown in Figure 14, the difference lies in the fact that the organic insulating layer IL with a stepped cross-section is a single layer of insulating layer 12. Insulating layer 112 is absent. Insulating layer 12 is disposed on insulating layer 111 and has a vacancy G. Focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross-section in which the thickness decreases towards the vacancy G.

[0138] The thickness T1 of the organic insulating layer IL corresponds to the length along the third direction Z from the upper surface of insulating layer 111 to the generally flat upper surface 121A of insulating layer 12. The thickness T2 of the organic insulating layer IL corresponds to the length along the third direction Z from the upper surface of insulating layer 111 to the generally flat upper surface 122A of insulating layer 12. Thickness T2 is smaller than thickness T1. The upper surface 122A is located between the upper surface 121A and the vacancy G, and is located below the upper surface 121A.

[0139] Inorganic insulating layer 5 covers insulating layer 12, and insulating layer 111 covers the void G. Groove 5G extends to the upper surface 121A of insulating layer 12.

[0140] Peripheral partition walls 7 and 8 are disposed above the organic insulating layer IL, and peripheral partition wall 9 is disposed in the vacancy G. In the illustrated example, peripheral partition walls 7 and 8 are disposed above the upper surface 121A, but not above the upper surface 122A. However, peripheral partition walls 7 and 8 may also be disposed above the upper surface 122A. The lower portions 71, 81, and 91 of each of the peripheral partition walls 7, 8, and 9 are disposed above the inorganic insulating layer 5.

[0141] An insulating layer 12 with a stepped cross-section can be formed, for example, by the following method.

[0142] That is, an insulating layer is formed on the entire surface of the mother substrate 100 where the insulating layer 111 is formed, using, for example, a positive organic material. Then, the insulating layer is exposed. In this exposure process, the exposure amount of the vacancy portion G is set to the maximum, and the exposure amount is set to decrease in stages from the vacancy portion G towards the outside. Then, the exposed insulating layer is developed. Finally, the insulating layer is baked.

[0143] In this way, an insulating layer 12 with the above-mentioned cross-sectional shape is formed.

[0144] In this configuration example, when the mother substrate 100 is cut along the cutting line CL, the cross-section of the display panel PNL along the C'-D' line in FIG13 corresponds to the cross-section of the area on the left side of the mother substrate 100 shown in FIG16, which is located on the mother substrate 100.

[0145] Figure 17 is an enlarged cross-sectional view of the area containing slot 5G.

[0146] The insulating layer 12 has a recess 12C that overlaps the groove 5G. The recess 12C extends beyond the groove 5G in a direction orthogonal to the extension direction of the groove 5G (the first direction X in the illustrated example). The inorganic insulating layer 5 has an edge 5E along the groove 5G. The edge 5E overlaps the recess 12C and is separate from the insulating layer 12. That is, the inorganic insulating layer 5 is formed in a hanging shape. Furthermore, the peripheral partition wall 8 does not overlap the recess 12C and the edge 5E.

[0147] As described above, the peripheral partition wall 8, like the partition wall 6, is suspended. In the peripheral partition wall 8, the lower part 81 has: a first conductive layer 83 disposed on the inorganic insulating layer 5, and a second conductive layer 84 disposed on the first conductive layer 83. For example, the first conductive layer 83 is formed to be thinner than the second conductive layer 84. Furthermore, in the illustrated example, both ends of the first conductive layer 83 protrude from the sides of the second conductive layer 84.

[0148] The upper part 82 has a first thin film 85 disposed on the second conductive layer 84 and a second thin film 86 disposed on the first thin film 85. The two ends of the first thin film 85 and the second thin film 86 protrude from the side of the second conductive layer 84.

[0149] Since a pair of peripheral partition walls 8 are arranged on both sides of the groove 5G, the inorganic insulating layer 5 is pressed against the insulating layer 12 by the peripheral partition walls 8. Therefore, the rise of the inorganic insulating layer 5 starting from the edge 5E of the inorganic insulating layer 5 and the detachment of the inorganic insulating layer 5 from the insulating layer 12 can be suppressed.

[0150] Figure 18 is a cross-sectional view illustrating the state in which a laminated film FL1 is formed in the region including the void G shown in Figure 14.

[0151] For example, in the process of forming the aforementioned display element DE1, the multilayer film FL1 is formed not only in the display area but also in the blank area MP and the peripheral area SA. The multilayer film FL1 here includes, for example, the organic layer OR1, the upper electrode UE1, and the capping layer CP1 used to form the display element DE1. The multilayer film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition walls 7, 8, and 9.

[0152] The laminated film FL1 is divided by suspended peripheral partition walls 7, 8, and 9. That is, when the organic layer OR1, the upper electrode UE1, and the capping layer CP1 are formed by vapor deposition, the material emitted from the vapor deposition source is blocked by the upper parts 72, 82, and 92 of the peripheral partition walls 7, 8, and 9. Therefore, a portion of each of the organic layer OR1, the upper electrode UE1, and the capping layer CP1 is deposited on the upper parts 72, 82, and 92. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 located on the upper parts 72, 82, and 92 are separated from the organic layer OR1, the upper electrode UE1, and the capping layer CP1 located on the inorganic insulating layer 5. In this way, the laminated film FL1 is partially divided.

[0153] Compared to the case where the laminated film FL1 is not interrupted by the peripheral partition walls 7, 8, and 9, reducing the area of ​​the continuous laminated film FL1 will disperse the stress that may be generated in the laminated film FL1. Furthermore, the inorganic insulating layer 5 and the laminated film FL1 are pressed in by the peripheral partition walls 7, 8, and 9. Therefore, the rise of the inorganic insulating layer 5 from the insulating layer 12 and the rise of the laminated film FL1 from the inorganic insulating layer 5 can be suppressed. Furthermore, when a sealing layer SE1 is formed on the laminated film FL1, the sealing layer SE1, together with the peripheral partition walls 7, 8, and 9, presses the laminated film FL1 in. Therefore, the detachment of the laminated film FL1 and the sealing layer SE1 from the inorganic insulating layer 5 can be suppressed.

[0154] Furthermore, the organic insulating layer IL has a stepped cross-section where the thickness decreases towards the vacancy G. This suppresses the formation of steep steps. The thinner the organic insulating layer IL, the smaller its elongation. Therefore, when a laminated film FL1 is formed on the organic insulating layer IL, the deformation of the laminated film FL1 is small, and local stress concentration can be suppressed within the laminated film FL1. This, in turn, suppresses the detachment of the laminated film FL1 from the inorganic insulating layer 5.

[0155] Here, we will explain the potential defects that may occur if the laminated film FL1 rises from the inorganic insulating layer 5 and breaks off. The inorganic insulating layer 5 detached from the insulating layer 12, and the laminated film FL1 detached from the inorganic insulating layer 5, become foreign matter, floating within the manufacturing apparatus and becoming a source of contamination. Furthermore, if the floating foreign matter adheres to the processed substrate, it may become a cause of various defects.

[0156] In this regard, according to this embodiment, the detachment of the inorganic insulating layer 5 and the laminated film FL1 can be suppressed. This suppresses contamination of the manufacturing apparatus and the generation of unwanted foreign matter. Therefore, it suppresses a decrease in reliability.

[0157] Furthermore, the same effect is achieved even when the multilayer film FL1 is replaced with a multilayer film FL2 that includes an organic layer OR2 for forming the display element DE2, an upper electrode UE2, and a capping layer CP2.

[0158] Furthermore, the same effect is achieved even when the multilayer film FL1 is replaced with a multilayer film FL3 containing an organic layer OR3 for forming the display element DE3, an upper electrode UE3, and a capping layer CP3.

[0159] Here, the effect of suppressing the detachment of the inorganic insulating layer 5 and the laminated film FL1 is explained with reference to the configuration example shown in FIG14, but the same effect is obtained for other configuration examples.

[0160] Figure 19 is a cross-sectional view illustrating the configuration in which a laminated film FL1 is formed in the region containing the groove 5G shown in Figure 17.

[0161] The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition wall 8, and also in the recess 12C of the insulating layer 12. The laminated film FL1 is separated by the suspended inorganic insulating layer 5 and the peripheral partition wall 8. That is, the laminated film FL1 formed on the peripheral partition wall 8 is separate from the laminated film FL1 formed on the inorganic insulating layer 5. Furthermore, the laminated film FL1 formed on the inorganic insulating layer 5 is separate from the laminated film FL1 formed in the recess 12C. Thus, the laminated film FL1 is separated by an inner region and an outer region surrounded by an annular groove 5G.

[0162] This reduces the stress generated in the laminated film FL1, achieving the same effect as illustrated in Figure 18.

[0163] Furthermore, compared to the case where slot 5G is absent, the capacitance of the stacked film FL1 is reduced because it is broken. Therefore, electrostatic discharge from the stacked film FL1 is suppressed. This suppresses damage to the stacked film FL1 and its surrounding areas caused by electrostatic discharge, thus preventing a decrease in reliability.

[0164] Figure 20 is a top view showing another configuration example of region 100B shown in Figure 11.

[0165] Comparing the configuration example shown in Figure 20 with the configuration example shown in Figure 12, the difference lies in the fact that the plurality of peripheral partition walls 9 disposed in the vacancy G include the peripheral partition wall (second partition wall) 9A disposed along the corner portion of the outer edge ILE of the organic insulating layer IL. The corner portion of the outer edge ILE is approximately a right angle when viewed from above. The peripheral partition wall 9A is formed in an L-shape when viewed from above.

[0166] Furthermore, in Figure 20, the illustration of the groove 5G of the inorganic insulating layer 5 and the surrounding partition wall 8 is omitted.

[0167] Furthermore, in the illustrated example, a conductive layer 9B is disposed along the straight portion of the outer edge ILE. This conductive layer 9B is, for example, a residue generated during the formation of the conductive peripheral partitions 7, 8, and 9. Therefore, the conductive layer 9B may not necessarily be present.

[0168] In the illustrated example, the conductive layer 9B is connected to the peripheral partition wall 9A. Viewed from above, the width W9B of the conductive layer 9B is smaller than the width W9A of the peripheral partition wall 9A. In one example, the width W9A is approximately 20 μm, and the width W9B is several μm. The width W9B of the conductive layer 9B is smaller than the width W9 of the other peripheral partition walls 9. The widths W9 and W9A are equal. As mentioned above, based on the viewpoint of suppressing the disappearance of the peripheral partition walls 9 or the poor formation of the peripheral partition walls 9, the widths W9 and W9A are larger than the width W7 of the peripheral partition walls 7.

[0169] Figure 21 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 20.

[0170] If one corner of the substrate 10 is enlarged, the metal layer MT, which constitutes part of the alignment mark as shown in FIG20, and the peripheral partition walls 9, 9A are disposed in the vacancy portion LP. In other words, the metal layer MT and the peripheral partition walls 9, 9A are located between the outer edge ILE and the outer edge 10E when viewed from above. The metal layer MT is formed in an L-shape along the corner of the substrate 10. The peripheral partition wall 9, which overlaps part of the metal layer MT, is formed in a straight line along the outer edge 10E. Furthermore, the peripheral partition wall 9A along the corner of the outer edge ILE is formed in an L-shape.

[0171] Next, several configuration examples will be described with respect to the cross-sectional structure of the mother substrate 100 along line EF in FIG20. In addition, the illustrations of the groove 5G and the peripheral partition wall 8 are omitted in the cross-sectional views shown in FIG22 to FIG24.

[0172] Figure 22 is a cross-sectional view showing one configuration example of the mother substrate 100.

[0173] The configuration shown in Figure 22 is essentially the same as the configuration shown in Figure 14, except that the peripheral partition wall 9A is arranged along the outer edge ILE.

[0174] Insulating layer 111 is an inorganic insulating layer disposed on substrate 10. Insulating layer 112 is an organic insulating layer disposed on insulating layer 111. Insulating layer 12 is an organic insulating layer covering insulating layer 112, and has a vacancy G in the region in contact with insulating layer 111. The organic insulating layer 111 having insulating layer 112 and insulating layer 12 has a stepped cross-section in which the thickness decreases towards the vacancy G.

[0175] The peripheral partition wall 9A has a lower portion 91 disposed above the inorganic insulating layer 5 and an upper portion 92 disposed above the lower portion 91. The upper portion 92 has a wider width than the lower portion 91. The two ends of the upper portion 92 protrude beyond the sides of the lower portion 91. Thus, the cross-sectional shape of the peripheral partition wall 9A is the same as the cross-sectional shape of the peripheral partition wall 9 shown in FIG. 14. This peripheral partition wall 9A can also be formed using the same process as the partition wall 6.

[0176] In this configuration example, when the mother substrate 100 is cut by the cutting line CL, the cross section of the display panel PNL along line E'-F' in FIG21 corresponds to the cross section of the mother substrate 100 shown in FIG22, which is located to the left of the cutting line CL.

[0177] Figure 23 is a cross-sectional view showing another configuration example of the mother substrate 100.

[0178] The configuration shown in Figure 23 is essentially the same as the configuration shown in Figure 15, except that the peripheral partition wall 9A is arranged along the outer edge ILE.

[0179] Insulating layer 112 extends further toward the cutting line CL than insulating layer 12, and has a vacancy G. Insulating layer 12 is disposed on insulating layer 112. The organic insulating layer IL having insulating layer 112 and insulating layer 12 has a stepped cross-section with thickness decreasing toward the vacancy G. The lower part 91 of the peripheral partition wall 9A is disposed on inorganic insulating layer 5.

[0180] In this configuration example, when the mother substrate 100 is cut by the cutting line CL, the cross section of the display panel PNL along line E'-F' in FIG21 corresponds to the cross section of the mother substrate 100 shown in FIG23, which is located to the left of the cutting line CL.

[0181] Figure 24 is a cross-sectional view showing another configuration example of the mother substrate 100.

[0182] The configuration shown in Figure 24 is essentially the same as the configuration shown in Figure 16, except that the peripheral partition wall 9A is arranged along the outer edge ILE.

[0183] Insulating layer 12 is disposed on insulating layer 111 and has a vacancy G. Organic insulating layer IL is a single layer of insulating layer 12, and insulating layer 112 is not present. Considering the cross-sectional shape of organic insulating layer IL, organic insulating layer IL has a stepped cross-section in which the thickness decreases towards the vacancy G. The lower part 91 of peripheral partition wall 9A is disposed on inorganic insulating layer 5.

[0184] In this configuration example, when the mother substrate 100 is cut by the cutting line CL, the cross section of the display panel PNL along line E'-F' in FIG21 corresponds to the cross section of the mother substrate 100 shown in FIG24 that is to the left of the cutting line CL.

[0185] Figure 25 is a diagram illustrating the adverse conditions that may occur when the peripheral partition wall 9A is not configured.

[0186] When a conductive layer 9B is formed along the outer edge ILE as residue generated during the formation of the peripheral partition wall, the conductive layer 9B tends to taper towards the corner of the outer edge ILE. At this time, charge easily concentrates at the sharp tip of the conductive layer 9B. Therefore, there is a risk of electrostatic discharge being induced between adjacent conductive layers 9B, or between the conductive layer 9B and its peripheral portion. Furthermore, when the laminated film FL1 is formed in a subsequent process, there is a risk of electrostatic discharge being induced between the laminated film FL1 and the conductive layer 9B.

[0187] To address this, according to the configuration example shown in Figure 20, by intentionally placing a peripheral partition wall 9A at the corner of the outer edge ILE, even if a conductive layer 9B is formed, the conductive layer 9B is connected to the peripheral partition wall 9A, making it less likely to form a sharp leading edge. Therefore, electrostatic discharge originating from the conductive layer 9B is suppressed. This suppresses damage to the periphery of the conductive layer 9B and the laminated film FL1 caused by electrostatic discharge. Thus, a decrease in reliability is suppressed.

[0188] Figure 26 is a top view showing another configuration example of region 100A of the mother substrate 100 shown in Figure 10.

[0189] The configuration example shown in Figure 26 differs from the configuration example shown in Figure 11 in that the outer edge ILE of the organic insulating layer IL includes a rounded corner. This rounded corner, viewed from above, corresponds to the arc-shaped portion formed within the outer edge ILE of the organic insulating layer IL. In the illustrated example, a rounded corner is formed near the intersection of the cutting lines CL in the peripheral region SA of the panel portion PP. Furthermore, rounded corners are formed near the intersection of the cutting lines CL and at the end portion GE of the blank portion G in the blank portion MP.

[0190] Figure 27 is a top view showing one configuration example of region 100B shown in Figure 26. Furthermore, in Figure 27, the groove 5G of the inorganic insulating layer 5 and the surrounding partition wall 8 are omitted.

[0191] The rounded corners of the outer edge ILE of the organic insulating layer IL are formed into an arc shape with a radius of curvature RIL. The radius of curvature RIL is, for example, equal to or greater than half of the width WG of the vacancy G extending along the first direction X (WG / 2 ≤ RIL). In one example, the radius of curvature RIL is 150 μm or more.

[0192] Furthermore, in the illustrated example, a conductive layer 9B is disposed along the outer edge ILE, including the rounded corner portion. Also, the conductive layer 9B has a generally fixed width. This conductive layer 9B, as described above, is a residue generated during the formation of the conductive peripheral partitions 7, 8, and 9, and may not necessarily be present.

[0193] Figure 28 is a top view of the display panel PNL cut by the cutting line CL shown in Figure 27.

[0194] If one corner of the substrate 10 is enlarged, the metal layer MT, which constitutes part of the alignment mark as shown in FIG. 27, and the peripheral partition wall 9 are disposed in the vacancy portion LP. The metal layer MT is formed in an L-shape along the corner of the substrate 10. The peripheral partition wall 9, which overlaps part of the metal layer MT, is formed in a straight line along the outer edge 10E. The corner of the outer edge ILE is rounded. The conductive layer 9B is disposed along the outer edge ILE.

[0195] The rounded corners of the outer edge ILE are formed into an arc shape with a radius of curvature RIL. The radius of curvature RIL is, for example, equal to or greater than the width WLP of the gap LP extending along the second direction Y along the first direction X (WLP≦RIL).

[0196] In this way, by rounding the corners of the outer edge ILE, even when the conductive layer 9B is formed, the conductive layer 9B has a generally consistent width along the outer edge ILE, making it less likely to form a sharp tip. Therefore, electrostatic discharge originating from the conductive layer 9B is suppressed. This, in turn, suppresses damage to the periphery of the conductive layer 9B and the laminated film FL1 caused by electrostatic discharge.

[0197] Furthermore, the radius of curvature RIL of the rounded corner is equal to or greater than half the width WG of the gap G of the mother substrate 100, or equal to or greater than the width WLP of the gap LP of the display panel PNL. Therefore, it can suppress the lifting or detachment originating near the corner of the laminated film FL1 or the inorganic insulating layer 5. Thus, it suppresses the reduction in reliability.

[0198] In the above-described embodiments, for example, among the peripheral partition walls 7, 8, and 9, the lower parts 71, 81, and 91 correspond to the first lower part, and the upper parts 72, 82, and 92 correspond to the first upper part; peripheral partition wall 8 corresponds to the first partition wall, and peripheral partition walls 9 and 9A correspond to the second partition wall. Also, in partition wall 6, the lower part 61 corresponds to the second lower part, and the upper part 62 corresponds to the second upper part. In the organic insulating layer IL, insulating layer 112 corresponds to the first layer, and insulating layer 12 corresponds to the second layer. In the inorganic insulating layer 5, groove 5G corresponds to the first groove, and groove 5GA corresponds to the second groove.

[0199] As explained above, according to this embodiment, a display device and motherboard capable of suppressing the reduction of reliability can be provided.

[0200] Based on the display device and motherboard described above as embodiments of the present invention, all display devices and motherboards that can be obtained by those skilled in the art through appropriate design modifications and implementations, as long as they contain the essence of the present invention, are also within the scope of the present invention.

[0201] Within the scope of the present invention, various variations can be conceived by those skilled in the art, and such variations should also be understood to be within the scope of the present invention. For example, any addition, deletion, or design change of constituent elements, or the addition, omission, or condition change of steps in the above-described embodiments, provided they possess the essence of the present invention, are also included within the scope of the present invention.

[0202] Furthermore, any other effects resulting from the embodiments described above, which are clear from the description in this specification or which can be reasonably conceived by those skilled in the art, should be understood as effects resulting from the present invention. Cross-reference of related applications

[0203] This invention application claims priority based on Japanese Patent Application No. 2023-179398, filed on October 18, 2023, and incorporates all the contents described in that Japanese Patent Application.

[0204] 1: Pixel circuit 2: Pixel switch 3: Driving transistor 4: Capacitor 5: Inorganic insulating layer 5E: Edge 5G: Slot (Slot 1) 5GA: Slot (Slot 2) 6: Partition wall 7, 9A: Peripheral partition walls 8: Surrounding partition wall 9: Surrounding partition wall 9B: Conductive layer 10:Substrate 10E, ILE: Outer edge 11: Circuit Layer 12, 111, 112: Insulation layer 12A, 121A, 122A, 112A: Upper surface 12C: concave part 13, 15: Resin layer 14: Sealing layer 61, 71, 81, 91: lower part 62, 72, 82, 92: upper part 63, 83: First conductive layer 64, 84: Second conductive layer 65, 85: 1st film 66, 86: 2nd film 100:Mother substrate 100A, 100B: Area AB, CD, C'-D', EF, E'-F': lines AP1, AP2, AP3: Openings CL: Cutting line CP1, CP2, CP3: Overlay layers DA: Display area DE: Display element DE1, DE2, DE3: Display elements DSP: Display device EM1, EM2, EM3: Emissive layers FL1, FL2, FL3: Stacked films G, LP: Vacancy GE: Terminal Division GL: Scan line IL: Organic insulating layer LE1: Lower electrode LE2: Lower electrode LE3: Lower electrode MP: Blank area MT: Metal layer OR1, OR2, OR3: Organic layer PL: Power cord PNL: Display Panel PP: Panel section PX: pixel RIL: Radius of curvature RS: Corrosion resist SA: Surrounding Area SE1, SE2, SE3: Sealing layer SL: Signal line SP: Subpixel SP1: Subpixel / Subpixel of the first color SP2: Subpixel / Subpixel of the second color SP3: Subpixel / Subpixel of the 3rd Color T1, T2: Thickness TE: terminal UE1, UE2, UE3: Upper electrode W7, W8, W9, W9A, W9B, WG, WLP: Width X: Axis / First Direction Y: Axis / Second Direction Z: Axis / Third Direction

Claims

1. A display device comprising: a substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion located on the inorganic insulating layer, and a first upper portion located on the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the inorganic insulating layer having an annular groove surrounding the display area in the peripheral area; and the plurality of peripheral partitions including a pair of first partitions facing each other across the groove.

2. The display device of claim 1, wherein the aforementioned organic insulating layer has a recess that overlaps the aforementioned groove; and the aforementioned inorganic insulating layer overlaps the aforementioned recess along the edge of the aforementioned groove, separate from the aforementioned organic insulating layer.

3. The display device of claim 1, wherein the aforementioned inorganic insulating layer is disposed in the aforementioned vacancy; and the aforementioned plurality of peripheral partitions include a second partition disposed on the aforementioned inorganic insulating layer in the aforementioned vacancy.

4. The display device of claim 3, wherein the aforementioned second partition wall is disposed along the corner portion of the outer edge of the aforementioned organic insulating layer, and is formed in an L-shape when viewed from above.

5. The display device of claim 4, further comprising a conductive layer disposed along a straight portion of the outer edge of the aforementioned organic insulating layer; and the aforementioned conductive layer being connected to the aforementioned second partition wall; the width of the aforementioned conductive layer being smaller than the width of the aforementioned second partition wall.

6. The display device of claim 1, wherein the outer edge of the aforementioned organic insulating layer includes a rounded corner; and the radius of curvature of the aforementioned rounded corner is equal to or greater than the width of the aforementioned void.

7. The display device of claim 6, further comprising a conductive layer disposed along the outer edge of the aforementioned organic insulating layer.

8. A display device comprising: a substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion and a first upper portion located above the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the plurality of peripheral partitions including a second partition disposed in the gap; the second partition being disposed along a corner portion of the outer edge of the organic insulating layer and forming an L-shape in plan view.

9. The display device of claim 8, further comprising a conductive layer disposed along a straight portion of the outer edge of the aforementioned organic insulating layer; and the aforementioned conductive layer being connected to the aforementioned second partition wall; the width of the aforementioned conductive layer being smaller than the width of the aforementioned second partition wall.

10. A display device comprising: a substrate; an organic insulating layer disposed above the substrate, covering a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion and a first upper portion located above the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the outer edge of the substrate in the peripheral area; the outer edge of the organic insulating layer including a rounded corner portion; the radius of curvature of the rounded corner portion being equal to or greater than the width of the gap portion.

11. The display device of claim 10, further comprising a conductive layer disposed along the outer edge of the aforementioned organic insulating layer.

12. The display device of claim 1, 8 or 10, further comprising a partition wall in the aforementioned display area, the partition wall having: a second lower portion disposed on the aforementioned inorganic insulating layer and formed of a conductive material, and a second upper portion disposed on the aforementioned second lower portion and protruding from the side of the aforementioned second lower portion; and the aforementioned lower electrode, the aforementioned organic layer and the aforementioned upper electrode are surrounded by the aforementioned partition wall; the aforementioned upper electrode is in contact with the aforementioned second lower portion of the aforementioned partition wall.

13. The display device of claim 1, 8 or 10, wherein the aforementioned organic insulating layer has a first layer and a second layer covering the aforementioned first layer, and has a stepped cross-section with the thickness decreasing toward the aforementioned vacancy.

14. The display device of claim 1, 8 or 10, wherein the aforementioned organic insulating layer has: a first layer, and a second layer disposed on the first layer and exposing the first layer to the aforementioned void portion, and has a stepped cross-section with a thickness decreasing toward the aforementioned void portion.

15. The display device of claim 1, 8 or 10, wherein the aforementioned organic insulating layer is a single layer having a stepped cross-section in which the thickness decreases toward the aforementioned void.

16. A mother substrate comprising: a panel portion having a display area for displaying an image and a peripheral area outside the display area; a blank portion outside the panel portion; an organic insulating layer disposed over the panel portion and the blank portion; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partition walls disposed in the peripheral area; each of the plurality of peripheral partition walls having: a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from the side of the first lower portion; the inorganic insulating layer having an annular first groove surrounding the display area in the peripheral area; The aforementioned plurality of peripheral partition walls includes one pair of first partition walls facing each other across the aforementioned first groove.

17. The mother substrate of claim 16, wherein the aforementioned organic insulating layer has a recess overlapping the aforementioned first trench; and the aforementioned inorganic insulating layer has a portion along the edge of the aforementioned first trench overlapping the aforementioned recess, separate from the aforementioned organic insulating layer.

18. The mother substrate of claim 16, wherein the aforementioned organic insulating layer has a gap along the outer shape of the aforementioned panel portion; and the aforementioned gap has a terminal portion located in the aforementioned blank portion; the aforementioned inorganic insulating layer has a second groove in the aforementioned blank portion surrounding the aforementioned terminal portion.

19. A mother substrate comprising: a panel portion having a display area for displaying an image and a peripheral area outside the display area; a blanking portion outside the panel portion; an organic insulating layer disposed over the panel portion and the blanking portion; a lower electrode disposed over the organic insulating layer in the display area; an inorganic insulating layer disposed over the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer disposed over the lower electrode and including a light-emitting layer; an upper electrode disposed over the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion located over the inorganic insulating layer and a first upper portion located over the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the shape of the panel portion; the plurality of peripheral partitions including a second partition disposed in the gap. The aforementioned second partition wall is disposed along the corner portion of the outer edge of the aforementioned organic insulating layer, forming an L-shape when viewed from above.

20. A mother substrate comprising: a panel portion having a display area for displaying an image and a peripheral area outside the display area; a blanking portion outside the panel portion; an organic insulating layer disposed over the panel portion and the blanking portion; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions disposed in the peripheral area; each of the plurality of peripheral partitions having: a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from the side of the first lower portion; the organic insulating layer having a gap along the shape of the panel portion; the outer edge of the organic insulating layer including a rounded corner portion; The radius of curvature of the aforementioned rounded corner is equal to or greater than half the width of the aforementioned empty part.

Images