Semiconductor structures and methods for forming the same

Abstract

A method for forming a semiconductor structure is provided. The method includes: a receiving structure, the structure including: a finned active region protruding from a substrate and including a channel region and a source / drain region; and a dummy gate stack on the channel region. The method further includes: etching the source / drain region to form a source / drain trench; forming a dielectric layer on the substrate and in the source / drain trench; epitaxially forming source / drain components in the source / drain trench and on the dielectric layer; replacing the dummy gate stack with a gate structure; performing an etching process to etch the substrate and the dielectric layer to form an opening, the opening exposing the bottom surface of the source / drain components; forming a dielectric liner extending along the surfaces of the dielectric layer and the substrate and exposed by the opening; and forming conductive components in the opening and below the source / drain components.

Description

Technical Field

[0001] The present invention relates to a structure and a method for forming the same, and particularly to a semiconductor structure and a method for forming the same. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to several generations of ICs, each featuring smaller and more complex circuits than the previous generation. During this evolution, functional density (i.e., the number of interconnects per unit wafer area) typically increases while geometry (i.e., the smallest element (or line) that can be manufactured using a process) decreases. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs.

[0003] As integrated circuit (IC) technology advances to smaller technology nodes, the parasitic capacitance between two adjacent conductive components (e.g., back-side vias and gate structures) can have a significant impact on the overall performance of integrated circuit devices. While existing methods for forming back-side vias are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a method for forming a semiconductor structure, comprising: a receiving structure including: a finned active region protruding from a substrate and including a channel region and a source / drain region; and a dummy gate stack on the channel region; etching the source / drain region to form a source / drain trench; forming a dielectric layer on the substrate and in the source / drain trench; epitaxially forming source / drain components in the source / drain trench and on the dielectric layer; replacing the dummy gate stack with a gate structure; performing an etching process to etch the substrate and the dielectric layer to form an opening exposing the bottom surface of the source / drain components; forming a dielectric liner extending along the surfaces of the dielectric layer and the substrate and exposed by the opening; and forming conductive components in the opening and below the source / drain components.

[0005] Other embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a source / drain opening extending into a substrate; forming a semiconductor layer in the bottom of the source / drain opening; forming a dielectric component in the source / drain opening and on the semiconductor layer; forming a source / drain component in the source / drain opening and on the dielectric component; partially etching a portion of the dielectric component, the semiconductor layer, and a portion of the substrate disposed directly beneath the semiconductor layer to form a trench; forming a dielectric barrier layer that pads the sidewall surfaces of the trench, wherein the dielectric barrier layer extends along a portion of the dielectric component; after forming the dielectric barrier layer, forming a silicon layer in the trench; and depositing a conductive layer in the trench and beneath the silicon layer.

[0006] Some embodiments of the present invention provide a semiconductor structure, including: a gate structure surrounding a plurality of nanostructures disposed on a substrate; a source / drain component coupled to the nanostructures and adjacent to the gate structure; a dielectric layer disposed between the source / drain component and the substrate; a back-side via disposed below the source / drain component and electrically coupled to the source / drain component; and a dielectric liner extending through the dielectric layer and the substrate, wherein the back-side via is separated from the dielectric layer by the dielectric liner. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of this disclosure. According to one or more aspects of this disclosure, Figure 1 illustrates a flowchart of a method for forming a semiconductor structure. According to various aspects of this disclosure, Figure 2 illustrates a partial top view of the exemplary structure to illustrate the various operational stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A and 17A (Figures 3A to 17A) illustrate partial cross-sectional views of the structure taken along line A-A' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B and 17B (Figures 3B to 17B) illustrate partial cross-sectional views of the structure taken along line B-B' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figure 3C illustrates a partial cross-sectional view of the structure taken along line C-C' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 18A, 19A and 20A illustrate partial cross-sectional views of the first alternative structure taken along line A-A' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 18B, 19B and 20B illustrate partial cross-sectional views of the first alternative structure taken along line B-B' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 21A and 22A illustrate partial cross-sectional views of a second alternative structure taken along line A-A' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figures 21B and 22B illustrate partial cross-sectional views of a second alternative structure taken along line B-B' of Figure 2 during various manufacturing stages of the method in Figure 1. According to one or more aspects of this disclosure, Figure 23 illustrates an enlarged view of the second alternative structure. Implementation

[0008] The following provides many different embodiments or examples to achieve different features of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the following description, referring to the formation of a first component on or above a second component, may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, the embodiments disclosed may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0009] Spatially relative terms, such as "below," "below," "lower," "above," and "higher," may be used here to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] Furthermore, when using terms such as "approximately" or "around" to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range that includes the number, such as within + / - 10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers.

[0011] As integrated circuit (IC) technology advances towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). A multi-gate device generally refers to a device with a gate structure or a portion thereof located on one or more sides of the channel region. Fin-like field-effect transistors (FFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices, which have become mainstream and promising candidates for high-performance and low-leakage-current applications. The gate structure of a GAA transistor can extend partially or completely around the channel region to provide access to both sides or more of the channel region. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistor alternative names, such as nanosheet transistors or nanowire transistors. The silicate layer and back-side via can be formed from their back sides beneath the epitaxial layer of the source / drain components. However, a reduced distance between the back-side via and the functional gate structure can cause undesirable leakage current.

[0012] This disclosure provides a method for enhancing isolation between a functional gate structure and a back-side via. In the example method, after forming a source / drain opening and refilling the lower portion of the source / drain opening with a semiconductor layer, an insulating layer is formed to block the top surface of the semiconductor layer, and an N-type source / drain component is formed on the insulating layer and in the source / drain opening. After forming the source / drain component, an etching process is performed to form a back-side opening extending from the back side through the substrate, the semiconductor layer, and the insulating layer, and a dielectric barrier layer extending along the sidewall surface of the back-side opening is formed. A silicon layer and a back-side via are then formed below the source / drain component and in the back-side opening. Forming a dielectric barrier layer after forming the back-side opening extending through the insulating layer enhances isolation between the back-side via and adjacent gate structures and reduces leakage current.

[0013] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, according to an embodiment of this disclosure, Figure 1 is a flowchart of a method 100 for forming a semiconductor structure. Method 100 is described below in conjunction with Figures 2 through 23, which, according to an embodiment of method 100, are partial top / cross-sectional views of structure 200 at different manufacturing stages. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail in this disclosure. Because structure 200 will be manufactured into a semiconductor device after the process is completed, structure 200 may also be referred to as semiconductor structure 200, depending on the context. To avoid ambiguity, the X, Y, and Z directions in Figures 2 through 23 are perpendicular to each other and are used consistently throughout this disclosure. In this disclosure, unless otherwise stated, the same reference numerals denote the same parts.

[0014] Referring to Figures 1, 2, and 3A-3C, method 100 includes step 102, receiving a structure 200 including a first region 10 and a second region 20. According to various aspects of this disclosure, Figure 2 shows a partial top view of structure 200 undergoing various operational stages of the method of Figure 1. Figure 3A shows a partial cross-sectional view of structure 200 taken along line A-A' shown in Figure 2, Figure 3B shows a partial cross-sectional view of structure 200 taken along line B-B' shown in Figure 2, and Figure 3C shows a partial cross-sectional view of structure 200 taken along line C-C' shown in Figure 2. As shown in Figures 3A to 3C, structure 200 includes a substrate 202. The substrate 202 can be an elemental (single-element) semiconductor, such as crystalline silicon (Si) or germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); a non-semiconductor material, such as soda-lime glass, fused silica, fused silica, and / or calcium fluoride (CaF2); and / or combinations thereof. In one embodiment, the substrate 202 is a silicon (Si) substrate. The substrate 202 may have a homogeneous composition or may include various layers, some of which may be selectively etched to form finned active regions (e.g., finned active regions 204A-204D). These layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thus modulate device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrate 202. In some such examples, the layers of substrate 202 may include insulators, such as semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, and / or other suitable insulating materials. Doped regions, such as wells, may be formed in substrate 202. In the embodiment of Figure 2, a portion of substrate 202 in the first region 10 is doped with an n-type dopant and may be referred to as an n-type well (not shown), and a portion of substrate 202 in the second region 20 is doped with a p-type dopant and may be referred to as a p-type well (not shown). The n-type dopant may include phosphorus (P) or arsenic (As). p-type dopants may include boron (B), boron difluoride (BF2), or indium (In). The n-type and p-type wells can be formed using ion implantation or thermal diffusion and can be considered as part of the substrate 202. As will be further explained below, the first region 10 is a p-type field-effect transistor (PFET) region for forming a PFET, and the second region 20 is an n-type field-effect transistor (NFET) region for forming an NFET.

[0015] Referring again to Figures 2 and 3A through 3C, structure 200 includes a plurality of finned active regions (e.g., finned active regions 204A, 204B, 204C, 204D) protruding from substrate 202. In some embodiments, a first region 10 includes finned active regions 204A and 204B extending vertically from substrate 202, and a second region 20 includes finned active regions 204C and 204D extending vertically from substrate 202. The number of finned active regions depicted in Figures 2 and 3A through 3C is merely an example, and structure 200 may include any suitable number of active regions. Each finned active region 204A-204D may be formed by a vertical stack 207 of alternating semiconductor layers disposed on the top 202ts of substrate 202 (shown in Figures 3A and 3B) and the top surface 202ts of substrate 202. In one embodiment, the vertical stack 207 includes a plurality of channel layers 208 staggered by a plurality of sacrificial layers 206. Each channel layer 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a different composition from the channel layers 208. In one embodiment, each channel layer 208 includes silicon (Si), and the sacrificial layer 206 includes silicon germanium (SiGe). Although the illustrated example vertical stack 207 includes three channel layers and three sacrificial layers, it should be understood that the vertical stack 207 may include any suitable number (e.g., 2 to 10) of channel layers and any suitable number of sacrificial layers. The top 202t of the vertical stack 207 and the substrate 202 is then patterned to form finned active regions 204A-204D. In some embodiments, the patterned top 202t of the substrate 202 may be referred to as a mesa structure 202t. Each finned active region 204 extends longitudinally along the X direction and is divided into a channel region 204C that overlaps with the dummy gate stack 210 (described below) and a source / drain region 204SD that does not overlap with the dummy gate stack 210. Depending on the context, the source / drain region 204SD may refer to either the source region or the drain region individually or collectively. Each channel region 204C is disposed between the two source / drain regions 204SD along the X direction.

[0016] Structure 200 also includes an isolation member 205 (shown in Figure 3C) formed around the lower portion of the fin active regions to isolate one fin active region from an adjacent fin active region. The isolation member 205 may include a shallow trench isolation (STI) member 205. In some embodiments, the isolation member 205 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In the embodiment shown in Figure 3C, the upper portions of the fin active regions 204A-204D rise above the STI member 205, while the lower portions of the fin active regions 204A-204D remain covered or embedded in the STI member 205. The isolation member 205 may be a single-layer or multi-layer structure.

[0017] Structure 200 also includes dummy gate stacks 210 intersecting with finned active regions 204A-204D. Each dummy gate stack 210 includes a dummy gate dielectric layer 210a, a dummy gate electrode layer 210b on the dummy gate dielectric layer 210a, and a gate-top hard mask layer 210c on the dummy gate electrode layer 210b. The dummy gate dielectric layer 210a may include silicon oxide. The dummy gate electrode layer 210b may include polycrystalline silicon. The gate-top hard mask layer 210c may include a silicon oxide layer, silicon nitride, and / or other suitable materials. Suitable deposition, lithography, and etching processes can be used to form the dummy gate stacks 210. In this embodiment, a gate replacement process (or gate-last process) is employed, wherein the dummy gate stack 210 serves as placeholders for functional gate structures (e.g., gate structure 230 shown in Figures 9A and 9B). In some embodiments, other processes and configurations may also be employed. Figure 2 shows three dummy gate stacks 210, but structure 200 may include any suitable number of dummy gate stacks 210.

[0018] Structure 200 also includes gate spacers 212a extending along the sidewall surfaces of the dummy gate stack 210. Each gate spacer 212a may be a single-layer or multi-layer structure. In one embodiment, the gate spacer 212a comprises a silicon carbonitride (SiCN) layer and silicon nitride (SiN) on the silicon carbonitride (SiCN) layer. In example fabrication processes, spacer layers (not separately labeled) are conformally deposited on structure 200, including on finned active regions 204A-204D, via atomic layer deposition (ALD), chemical vapor deposition (CVD), or any suitable method. The term "conformally" may be used in this disclosure to describe layers having a substantially uniform thickness across the various regions of structure 200. The spacer layer may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, other suitable dielectric materials, or combinations thereof. After the spacer layer is formed, an etching process is performed to remove a portion of the spacer layer on the top surface of structure 200 to form gate spacers 212a extending along the sidewalls of the dummy gate stack 210. The deposition and etching of the spacer layer also form fin sidewall spacers 212b (as shown in Figure 3C) extending along the lower portion of the sidewalls of the fin active regions 204A-204D and disposed on the STI component 205. Gate spacers 212a and fin sidewall spacers 212b have the same composition.

[0019] Referring to Figures 1, 4A, and 4B, method 100 includes step 104, etching the source / drain regions 204SD of the finned active regions 204A-204D to form source / drain openings 214. In some embodiments, the source / drain regions 204SD of the finned active regions 204A-204D are anisotropically etched using plasma etching with suitable etchants, such as oxygen-containing etchants, hydrogen-containing etchants, fluorine-containing etchants (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBR3), iodine-containing etchants, other suitable etchants, and / or combinations thereof. In this embodiment, the source / drain openings 214 extend into the top 202t of the substrate 202.

[0020] Referring to Figures 1, 5A, and 5B, method 100 includes step 106, forming an inner spacer component 216. After forming source / drain openings 214 in the first region 10 and the second region 20, a sacrificial layer 206 exposed in the source / drain openings 214 is selectively and partially etched to form an inner spacer recess (filled by the inner spacer component 216). In some embodiments, selective etching may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent of etching of the sacrificial layer 206 is controlled by the duration of the etching process. After forming the inner spacer recess, an inner spacer material layer is compliantly deposited on the structure 200 (including above and within the inner spacer recess) using CVD or ALD. The inner spacer material layer may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, or silicon oxynitride. The inner spacer material layer is then etched back to form the inner spacer component 216, as shown in Figures 5A and 5B. In some embodiments, the composition of the inner spacer component 216 differs from that of the gate spacer 212a, such that the etchback of the inner spacer material layer will not etch the gate spacer 212a.

[0021] Referring now to Figures 1, 6A, and 6B, method 100 includes step 108, forming a semiconductor layer 218 in the source / drain opening 214. In this embodiment, the semiconductor layer 218 is formed in the source / drain opening 214 using an epitaxial process after the formation of the inner spacer member 216. Each semiconductor layer 218 may be undoped or unintentionally doped. In some embodiments, the semiconductor layer 218 may include undoped silicon (Si), undoped germanium (Ge), undoped silicon-germanium (SiGe), or other suitable materials. In one embodiment, the semiconductor layer 218 is formed simultaneously through a common epitaxial process and includes undoped silicon (Si). In the depicted example, the top surface 218ts of the semiconductor layer 218 is located on the top surface 202ts of the substrate 202 and below the bottom surface of the bottommost layer of the plurality of channel layers 208, and has a convex profile.

[0022] Referring now to Figures 1, 7A, and 7B, method 100 includes step 110, forming an insulating layer 220 in the source / drain opening 214 of the second region 20. In this embodiment, the insulating layer 220 is formed only in the second region 20 for forming an N-type transistor, and not in the first region 10 for forming a P-type transistor. In the example process, a patterned mask (e.g., a photoresist layer) is formed to cover the first region 10, and the second region 20 is not covered by the patterned mask. A dielectric material layer (not shown) can then be deposited on the substrate 202 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, and the deposition thickness of the dielectric material layer can depend on the desired thickness of the insulating layer 220 to be formed in the source / drain opening 214 of the second region 20. In one embodiment, the dielectric material layer is deposited using a physical vapor deposition (PVD) process. Due to the characteristics of the PVD process, the portion of the dielectric material layer formed on the top or flat surface is thicker than the portion formed on the side surfaces. Following deposition, an etching process is performed to etch back the dielectric material layer, thereby forming an insulating layer 220 in the source / drain opening 214 of the second region 20. The dielectric material layer can be formed from any suitable dielectric material, as long as its composition differs from that of the channel layer 208, the sacrificial layer 206, and the gate-top hard mask layer 210c, to allow selective removal through the etching process. In some embodiments, the insulating layer 220 may comprise silicon oxide, silicon nitride, silicon carbide, or other suitable materials.

[0023] In this embodiment, the top surface of the insulating layer 220 is lower than the top surface of the bottommost inner spacer member 216. That is, the insulating layer 220 does not directly contact the bottommost layer of the plurality of channel layers 208. For N-type transistors formed in the second region 20 including the insulating layer 220, the formation of the insulating layer 220 will generally suppress and / or eliminate any parasitic transistors formed between the metal gate structure 230, the source / drain member 222N, and the lower platform structure 202t, thereby reducing and / or blocking leakage current through the platform structure 202t. Furthermore, in this embodiment, the formation of the insulating layer 220 will provide better isolation between the metal gate structure 230 (as shown in Figure 9B) and the back-side via 258b (as shown in Figure 17B) and / or better isolation between the metal gate structure 230 and the back-side silicon layer 256b (as shown in Figure 17B).

[0024] Referring now to Figures 1, 8A, and 8B, method 100 includes step 112, forming source / drain components 222P and 222N in source / drain openings 214 in the first region 10 and the second region 20, respectively. Depending on the context, the source / drain components may refer individually or collectively to a source or a drain. Source / drain component 222P is coupled to a channel layer 208 of channel region 204C in the first region 10. Source / drain component 222N is coupled to a channel layer 208 of channel region 204C in the second region 20. Source / drain components 222N and 222P can each be selectively epitaxially formed from the exposed sidewalls of channel layer 208 using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes.

[0025] The example n-type source / drain component 222N may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing an n-type dopant (e.g., phosphorus, arsenic, or antimony), or out-of-situ doped using a junction implantation process. The example p-type source / drain component 222P may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped during the epitaxial process by introducing a p-type dopant (e.g., boron or gallium), or out-of-situ doped using a junction implantation process. In some embodiments, the n-type source / drain component 222N and the p-type source / drain component 222P may each include multiple semiconductor layers with different doping concentrations. The n-type source / drain component 222N and the p-type source / drain component 222P may be formed in any suitable order.

[0026] Referring now to Figures 1, 9A, and 9B, method 100 includes step 114, where the dummy gate stack 210 and sacrificial layer 206 are replaced by a metal gate structure 230. A contact etch stop layer (CESL) 226 and a first interlayer dielectric (ILD) layer 228 are deposited on structure 200. CESL 226 may comprise silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed via ALD, plasma-assisted chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. In one embodiment, CESL 226 has a uniform thickness. After depositing CESL 226, the first ILD layer 228 is deposited on structure 200 via PECVD or other suitable deposition techniques. The first ILD layer 228 may include materials such as tetraethyl orthosilicate (TES) oxide, undoped silicate glass, or doped silicate such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphoric silicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. A planarization process, such as chemical mechanical polishing (CMP), may be performed on the structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer 210b in the dummy gate stack 210. A first etching process can be performed to selectively remove the dummy gate electrode layer 210b and the dummy gate dielectric layer 210a of the dummy gate stack 210, while largely leaving the gate spacer 212a intact, to form gate trenches in the first region 10 and the second region 20. After removing the dummy gate stack 210, the sacrificial layer 206 in the channel region 204C is selectively removed to release the channel layer 208 as the channel member 208. The selective removal of the sacrificial layer 206 forms a gate opening below the gate trench.

[0027] After removing the dummy gate stack 210 and the sacrificial layer 206, a metallic gate structure 230 is formed in the gate trenches and openings in the first region 10 and the second region 20. The formation of the metallic gate structure 230 includes forming an interface layer to wrap around and over each channel member 208. The interface layer may include silicon oxide or other suitable materials. Suitable methods can be used to form the interface layer, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, or other suitable methods. In one embodiment, the interface layer is formed by thermal oxidation and thus forms only on the surface of the channel member 208. That is, the interface layer does not extend along the sidewall surfaces of the gate spacer 212a and the inner spacer member 216. In another embodiment, the interface layer is formed via ALD and thus compliantly formed on the surface of the structure 200. That is, the interface layer also extends along the sidewall surfaces of the gate spacer 212a and the inner spacer member 216. After the interface layer is formed, a dielectric layer is formed on structure 200 to surround and over each channel member 208. In one embodiment, the dielectric layer is compliantly deposited on structure 200. The term "compliantly" may be used in this disclosure for the convenience of describing a layer having a generally uniform thickness over the various regions. In some embodiments, the dielectric layer is a high-k (dielectric constant) dielectric layer with a dielectric constant greater than that of silicon dioxide (about 3.9). In some embodiments, the dielectric layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), aluminum oxide, zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The dielectric layer and the interface layer may be collectively referred to as the gate dielectric layer.

[0028] The formation of the metal gate structure 230 also includes forming a gate electrode on the gate dielectric layer. The gate electrode can be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may include titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal gate structure 230 formed in the first region 10 may include at least a P-type work function layer. The P-type work function layer may include titanium nitride (TiN), tungsten carbonitride (WCN), tantalum nitride (TaN), or molybdenum nitride (MoN). The metal gate structure 230 formed in the second region 20 may include at least an N-type work function layer. The N-type work function layer may include a titanium-aluminum based metal, such as titanium aluminum carbon (TiAlC) or titanium aluminum (TiAl). The metal filler layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode may be formed via ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, planarization processes, such as chemical mechanical polishing (CMP), may be performed to remove excess material on the first ILD layer 228 to provide a generally flat top surface and facilitate further processing.

[0029] Referring to Figures 1, 10A, and 10B, method 100 includes step 116, forming silicon layers 240a-240b and source / drain contacts 242 on the front side of substrate 202. In the example process, an etch stop layer 236 and a second ILD layer 238 are deposited on structure 200. In terms of composition and formation process, etch stop layer 236 may be similar to contact etch stop layer 226, while the second ILD layer 238 may be similar to the first ILD layer 228. Etch stop layer 236 may indicate etch stop points for forming gate via openings on metal gate structure 230. A combination of lithography and etching processes is used to form source / drain contact openings (currently filled by silicon layers 240a / 240b and source / drain contacts 242) to expose p-type source / drain components 222P or n-type source / drain components 222N. In the example process, a hard mask layer and photoresist are deposited on structure 200. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from the photomask, baked in a post-exposure baking process, developed in a developer, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etch mask to etch the hard mask layer to form a patterned hard mask layer. The patterned hard mask layer is then used as an etch mask to etch the second ILD layer 238, the etch stop layer 236, the first ILD layer 228, and CESL 226. The etching process for etching the second ILD layer 238, the first ILD layer 228, and CESL 226 can be a dry etching process, including the use of argon (Ar), fluorine-containing etchants (e.g., SF6, NF3, CH2F2, CHF3, C4F8 and / or C2F6), oxygen-containing etchants, chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBR3), iodine-containing etchants, or combinations thereof.

[0030] After forming the source / drain contact openings, silicate layers 240a-240b and source / drain contacts 242 are formed therein. To form silicate layers 240a-240b, metal precursors (e.g., titanium, tantalum, nickel, cobalt, or tungsten) are deposited on the exposed surfaces of the structure, including the n-type source / drain components 222N and the p-type source / drain components 222P. An annealing process is then performed to induce silicidation in a second region 20 between the metal precursors and the exposed semiconductor surfaces and to induce germanidation in a first region 10. In some embodiments, unreacted metal precursors are selectively removed after forming silicate layers 240a-240b. In embodiments where the metal precursor includes nickel, nickel can react with germanium silicon in the p-type source / drain component 222P to form a silicide layer 240a, and can react with silicon in the n-type source / drain component 222N to form a silicide layer 240b. Therefore, silicide layer 240b may include nickel silicide, and silicide layer 240a may include nickel silicide, nickel germanide, and nickel germanide.

[0031] A conductive layer is then deposited on structure 200, including in the source / drain contact openings and on silicon layers 240a / 240b. The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as chemical mechanical polishing (CMP), may then be performed to remove excess portions of the conductive layer to form the source / drain contacts 242. The top surface is removed. After the planarization process, the top surface of the source / drain contacts 242 is coplanar with the top surface of the second ILD layer 238. Although not shown, in some embodiments, a dielectric barrier layer may be formed to extend along the sidewall surfaces of the source / drain contacts 242.

[0032] After forming silicate layers 240a and 240b and source / drain contacts 242, other components, such as gate vias and interconnect structures 244, can be formed on structure 200. In some embodiments, interconnect structure 244 may include multiple intermetallic dielectric (IMD) layers and multiple metal lines or contact vias in each IMD layer. In some cases, the IMD layers and the first IMD layer 228 may have similar compositions. The metal lines and contact vias in each IMD layer may be formed of metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be protected by barrier layer pads to insulate them from the IMD layers and prevent electromigration. Because interconnect structure 244 is formed on the front side of structure 200, interconnect structure 244 may also be referred to as front-side interconnect structure 244.

[0033] Referring to Figures 1, 11A, 11B, 12A, and 12B, method 100 includes step 118, forming a dielectric structure 245 on the back side of substrate 202. In one embodiment, referring to Figures 11A and 11B, a carrier substrate (not shown) is bonded to interconnect structure 244. In some embodiments, the carrier substrate may be bonded to structure 200 by fusion bonding, using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may include a semiconductor material (e.g., silicon), sapphire, glass, a polymeric material, or other suitable material. In embodiments using fusion bonding, the carrier substrate includes a bottom oxide layer and the interconnect structure 244 includes a top oxide layer. After processing the bottom and top oxide layers, they are placed in a plush contact with each other for direct bonding at room temperature or high temperature. Once the carrier substrate is bonded to the interconnect structure 244 of structure 200, structure 200 is flipped over. The back side of structure 200 is then planarized to reduce the thickness of substrate 202 from its back side. For ease of description, the following positional relationships will be described using the flipped structure 200, as shown in the figure.

[0034] In this embodiment, referring to Figures 12A and 12B, a dielectric structure 245 is formed on the back side of structure 200 after planarizing substrate 202. To provide an endpoint for subsequent planarization processes, dielectric structure 245 includes a first layer 246 and a second layer 248 having a material composition different from that of the first layer 246. In one embodiment, the first layer 246 includes a nitride layer (e.g., silicon nitride), and the second layer 248 includes an oxide layer (e.g., silicon oxide).

[0035] Referring to Figures 1, 13A, and 13B, method 100 includes step 120, patterning a dielectric structure 245 to form an opening 250a in a first region 10 and an opening 250b in a second region 20. In an example process, photoresist is deposited on the back side of the dielectric structure 245. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from a photomask, baked in a post-exposure baking process, developed in a developer, and then rinsed to form the patterned photoresist layer. The patterned photoresist layer is then used as an etch mask to etch the dielectric structure 245 to form the patterned dielectric structure 245. In this embodiment, the opening 250a is disposed directly above at least a portion of the source / drain component 222P, and the opening 250b is disposed directly above at least a portion of the source / drain component 222N.

[0036] Referring to Figures 1, 14A, and 14B, method 100 includes step 122, forming a first trench 252a in a first region 10 to expose the bottom surface of the source / drain component 222P, and forming a second trench 252b in a second region 20 to expose the bottom surface of the source / drain component 222N. When a patterned dielectric structure 245 is used as an etching mask, an etching process is performed to etch portions of the substrate 202 and semiconductor layer 218 disposed directly above the bottom surface of the source / drain component 222P to vertically extend the opening 250a, thereby forming the first trench 252a in the first region 10. The etching process also etches portions of the substrate 202, semiconductor layer 218, and insulating layer 220 disposed directly above the bottom surface of the source / drain component 222N to vertically extend the opening 250b, thereby forming the second trench 252b in the second region 20.

[0037] In some embodiments, the etching process can etch dielectric components (e.g., insulating layer 220) and semiconductor components (e.g., substrate 202) at similar etching rates. As shown in Figures 14A and 14B, when the etching process is complete, a first trench 252a exposes the bottom surface of the source / drain component 222P and extends through the semiconductor layer 218; a second trench 252b exposes the bottom surface of the source / drain component 222N and extends through both the semiconductor layer 218 and the insulating layer 220. In some embodiments, the etching process is stopped once the insulating layer 220 is broken down. The first trench 252a may extend into the source / drain component 222P, and the second trench 252b may extend into the source / drain component 222N. In this embodiment, in the cross-sectional views shown in Figures 14A and 14B, the first trench 252a exposes a portion of the bottom surface of the source / drain component 222P, and the second trench 252b exposes a portion of the bottom surface of the source / drain component 222N. That is, the width of the surface 252s of the first trench 252a is less than the width of the bottom surface of the source / drain component 222P, and the width of the surface 252s' of the second trench 252b is less than the width of the bottom surface of the source / drain component 222N.

[0038] Referring to Figures 1, 15A, 15B, 16A, and 16B, method 100 includes step 124, forming a dielectric barrier layer 254 extending along the sidewalls of the first trench 252a and the second trench 252b. Referring to Figures 15A and 15B, after the formation of the first trench 252a and the second trench 252b, in this embodiment, to prevent the exposed substrate 202 surface of the trenches 252a-252b from being affected by subsequent siliconization processes, a dielectric layer 253 is compliantly deposited on the back side of the structure 200, including in the first trench 252a and the second trench 252b. In some embodiments, the dielectric layer 253 may include silicon nitride, silicon oxynitride, silicon carbide, or other suitable materials, and may be deposited via ALD, CVD, PEALD, or other suitable processes.

[0039] Referring to Figures 16A and 16B, the dielectric layer 253 is etched back to retain only the portion extending along the sidewall surfaces of trenches 252a-252b, thereby forming a dielectric barrier layer 254a extending along the sidewall of the first trench 252a and a dielectric barrier layer 254b extending along the sidewall of the second trench 252b. The dielectric barrier layer 254a extends through the semiconductor layer 218 in the first region 10 and is in direct contact with the source / drain component 222P. The dielectric barrier layer 254b extends through the semiconductor layer 218 and the insulating layer 220 in the second region 20 and is in direct contact with the source / drain component 222N and the insulating layer 220. As shown in Figure 16B, the dielectric barrier layer 254b is separated from the bottom inner spacer component 216 through the insulating layer 220. The etch-back of the dielectric layer 253 removes portions of the dielectric layer 253 formed on surfaces 252s and 252s'. In some embodiments, the etchback of dielectric layer 253 may slightly etch the exposed surfaces of source / drain components 222P and 222N. In one embodiment, dielectric layer 253 and insulating layer 220 have the same composition. In another embodiment, the composition of dielectric layer 253 differs from that of insulating layer 220. The thicknesses of dielectric barrier layer 254a and dielectric barrier layer 254b are respectively between about 2 nm and about 8 nm. If the thickness is greater than 8 nm, the spacing of the back-side vias may be too small, increasing deposition difficulty and parasitic resistance; if the thickness is less than 2 nm, the thin dielectric barrier layers 254a / 254b may not provide satisfactory electrical isolation between the back-side vias 258a / 258b and the substrate 202.

[0040] Referring to Figures 1, 17A, and 17B, method 100 includes step 126, forming silica layers 256a / 256b and back-side vias 258a / 258b in a first trench 252a and a second trench 252b, respectively. After forming a dielectric barrier layer 254a extending along the sidewall of the first trench 252a and a dielectric barrier layer 254b extending along the sidewall of the second trench 252b, silica layers 256a / 256b and back-side vias 258a / 258b are formed therein. To form silica layers 256a / 256b, a metal precursor (e.g., titanium, tantalum, nickel, cobalt, or tungsten) is compliantly deposited on the back side of structure 200, including on exposed portions of the bottom surface 252s of the p-type source / drain component 222P and exposed portions of the surface 252s' of the n-type source / drain component 222N. An annealing process is then performed to induce silicide formation in a second region 20 between the metal precursor and the exposed semiconductor surface, and to induce germanicide formation in the first region 10. In some embodiments, unreacted metal precursor is selectively removed after the formation of silicide layers 256a-256b. In embodiments where the metal precursor includes nickel, nickel may react with silicon-germanium in the p-type source / drain component 222P to form silicide layer 256a in the first region 10, and may react with silicon in the n-type source / drain component 222N to form silicide layer 256b in the second region 20. In one embodiment, silicide layer 256a is vertically positioned between the dielectric barrier layer 254a and the p-type source / drain component 222P, and silicide layer 256b is vertically positioned between the dielectric barrier layer 254b and the n-type source / drain component 222N. Both silicate layers 256a and 256b may include curved surfaces that bend outward toward the corresponding source / drain components 222P / 222N. In one embodiment, silicate layer 256b extends into the source / drain component 222N, and the bottom surface 256s of silicate layer 256b is located above the top surface of insulating layer 220. In one embodiment, the bottommost surface of silicate layer 256b is in direct contact with dielectric barrier layer 254b.

[0041] Subsequently, a conductive layer is deposited on the back side of structure 200, including in the first and second trenches 252a-252b and on the bottom surface of silicate layers 256a-256b. The conductive layer may include aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) or other suitable materials, and may be formed by any suitable deposition process (e.g., CVD). A planarization process, such as chemical mechanical polishing (CMP), may then be performed to remove excess material on the back side of the patterned first layer 246 to define the final structure of the back-side via 258a in the first region 10 and the final structure of the back-side via 258b in the second region 20.

[0042] As shown in Figures 17A and 17B, in the first region 10, the back-side via 258a is separated from the bottom inner spacer member 216 through the source / drain member 222P and the dielectric barrier layer 254a; and in the second region 20, at least a portion of the back-side via 258b, which is laterally adjacent to the bottom inner spacer member 216, is separated from the bottom inner spacer member 216 by a combination of the insulating layer 220 and the dielectric barrier layer 254b. Therefore, leakage current between the back-side via 258b and the metal gate structure 230 adjacent to the inner spacer member 216 can be advantageously reduced or eliminated. The bottom inner spacer member 216 and the insulating layer 220 together define the width W1. In one embodiment, the width W1 is between about 3 nm and about 15 nm. If the width W1 is less than 3 nm, the leakage current between the back-side via 258b and the metal gate structure 230 may negatively affect device performance. If the width W1 is greater than 15 nm, the back-side via 258b may have a small volume, which may cause high parasitic resistance. In some embodiments, the portion of the back-side via 258b surrounded by the silicon layer 256b spans the width W2. The width W2 can be between about 5 nm and 15 nm. If the width W2 is greater than 15 nm, the width W1 may be too small, and the isolation between the back-side via 258b and the metal gate structure 230 may be insufficient to reduce or even eliminate leakage current. If the width W2 is less than 5 nm, the back-side via 258b may have a small volume and may cause high parasitic resistance.

[0043] Referring to Figure 1, method 100 includes step 128 of performing further processes. These further processes may include forming a back-side interconnect structure on the back side of structure 200. In some embodiments, the back-side interconnect structure may include a plurality of inter-metal dielectric (IMD) layers and a plurality of metal lines or contact vias in each IMD layer. In some cases, the IMD layers and the first IMD layer 228 may have similar compositions. The metal lines and contact vias in each IMD layer may be formed of a metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be protected by a barrier layer pad to insulate the metal lines and contact vias from the IMD layers and prevent electromigration.

[0044] According to one or more aspects of this disclosure, Figures 18A through 20B illustrate cross-sectional views of a first alternative structure during various manufacturing stages of the method in Figure 1. In this alternative embodiment, as shown in Figures 18A and 18B, the source / drain component 222P can be epitaxially grown from bottom to top (i.e., along the Z direction); however, due to the presence of the insulating layer 220, the semiconductor layer 218 in the second region 20 is blocked by the insulating layer 220, and no exposed semiconductor surface can be provided for the epitaxial growth of the source / drain component 222N. Instead, the source / drain component 222N is epitaxially formed from the exposed sidewalls of the channel layer 208 until the semiconductor layers of the source / drain component 222N are merged. The inability to epitaxially grow from bottom to top and the inability to epitaxially grow along the Y direction results in the formation of a void 260 (or air gap 260) surrounded by the source / drain component 222N and the insulating layer 220, as shown in Figure 18B. In other words, a portion of the top surface of the insulating layer 220 does not directly contact the bottom surface of the source / drain component 222N.

[0045] The operations of steps 114-122 of method 100 are then performed to form a first trench 252a in the first region 10 and a second trench 252b in the second region 20, as shown in Figures 19A and 19B. Unlike the structure 200 shown in Figure 14B, in the first alternative embodiment shown in Figure 19B, the formation of the second trench 252b etches through the insulating layer 220 and may disrupt this enclosure because the void 260 is surrounded by the combination of the insulating layer 220 and the source / drain component 222N. Therefore, a portion of the second trench 252b may extend laterally along the X direction. For example, a portion of the second trench 252b may be vertically disposed between the insulating layer 220 and the source / drain component 222N, exposing a portion of the top surface of the insulating layer 220. The second trench 252b merged with the void 260 may be referred to as the second trench 252b'.

[0046] The operations of steps 124-128 of method 100 are then performed to form dielectric barrier layers 254a-254b, silicate layers 256a-256b, and back-side vias 258a-258b, to complete the fabrication of structure 200, as shown in Figures 20A and 20B. In this embodiment, dielectric barrier layer 254b may also substantially fill a portion of the second trench 252b' disposed directly beneath insulating layer 220. In the embodiment shown in Figures 20A and 20B, dielectric barrier layer 254a has a symmetrical profile, and dielectric barrier layer 254b has an asymmetrical profile due to the presence of voids 260 during the formation of source / drain components 222N.

[0047] According to one or more aspects of this disclosure, Figures 21A through 23 illustrate cross-sectional views of a second alternative structure during various manufacturing stages of the method in Figure 1. In this alternative embodiment, as shown in Figures 21A and 21B, misalignment and overlay problems may occur during the patterning of the dielectric structure 245, thus affecting the formation of the first and second trenches 252a-252b. Misalignment and overlay problems during the formation of the first and second trenches 252a-252b may further degrade the process tolerance for forming the back-side vias 258a-258b, and even degrade the performance of the integrated wafer. For example, due to the overlay problem, the distance between the back-side vias 258a / 258b and the metal gate structure 230 may be reduced, which may increase leakage current or even cause reliability problems. The first trench 252a that experiences misalignment and overlap issues is referred to as the first trench 252a” as shown in Figure 21A, and the second trench 252b that experiences misalignment and overlap issues is referred to as the second trench 252b” as shown in Figure 21B. As shown in Figures 21A and 21B, the first trench 252a” exposes a portion of the bottommost inner spacer member 216 in the first region 10, and the second trench 252b” exposes a portion of the bottommost inner spacer member 216 in the second region 20. More specifically, the portion of the bottommost inner spacer member 216 may be removed during the formation of the first trench 252a” and the second trench 252b”.

[0048] The operations of steps 124-128 of method 100 are then performed to form dielectric barrier layers 254a-254b, silicate layers 256a-256b, and back-side vias 258a”-258b” to complete the fabrication of structure 200, as shown in Figures 22A and 22B. In this embodiment, the centerline 258c1 of the back-side via 258a” is offset from the centerline of the source / drain component 222P, and the dielectric barrier layer 254a is in direct contact with one of the bottom inner spacer components 216. The centerline 258c2 of the back-side via 258b” (as shown in Figure 23) is offset from the centerline of the source / drain component 222N, and the dielectric barrier layer 254b is in direct contact with one of the bottom inner spacer components 216. Figure 23 illustrates an enlarged portion of structure 200 in the second region 20. As shown in Figure 23, a silica layer 256b is disposed between the dielectric barrier layer 254b and the source / drain component 222N, and is in direct contact with one of the bottom inner spacer components 216. In some embodiments, a portion 258p of the back-side via 258b” is also in direct contact with one of the bottom inner spacer components 216 and extends from the dielectric barrier layer 254b and the silica layer 256b.

[0049] While not intended to be limiting, one or more embodiments disclosed herein offer numerous benefits for semiconductor structures and their formation. For example, isolation between back-side vias and adjacent gate structures can be enhanced to reduce leakage current.

[0050] This disclosure provides numerous different embodiments. This disclosure provides semiconductor structures and methods for forming them. In one example aspect, this disclosure relates to a method of forming a semiconductor structure, comprising: a receiving structure including: a finned active region protruding from a substrate and including a channel region and a source / drain region; and a dummy gate stack on the channel region; etching the source / drain region to form a source / drain trench; forming a dielectric layer on the substrate and in the source / drain trench; epitaxially forming source / drain components in the source / drain trench and on the dielectric layer; replacing the dummy gate stack with a gate structure; performing an etching process to etch the substrate and the dielectric layer to form an opening exposing the bottom surface of the source / drain components; forming a dielectric liner extending along the surfaces of the dielectric layer and the substrate and exposed by the opening; and forming conductive components in the opening and below the source / drain components.

[0051] In some embodiments, the channel region includes a plurality of staggered channel layers and a plurality of sacrificial layers, and the method further includes: selectively etching the sacrificial layers to form inner spacer recesses after forming source / drain trenches; and forming inner spacer members in the inner spacer recesses. In some embodiments, the method further includes: selectively removing the sacrificial layers, wherein a gate structure further surrounds the channel layers, and a portion of a dielectric liner is laterally disposed between the conductive member and the gate structure. In some embodiments, a portion of the dielectric liner is laterally disposed between the conductive member and the bottommost inner spacer member of the inner spacer member. In some embodiments, the top surface of the dielectric liner is lower than the top surface of the bottommost inner spacer member. In some embodiments, forming the dielectric liner includes: conformally depositing a dielectric material layer in the back side of the substrate and in the opening after performing an etching process; and etching back the dielectric material layer. In some embodiments, the method further includes: epitaxially forming an undoped semiconductor layer in the source / drain trenches before forming the dielectric layer, wherein the openings further extend through the undoped semiconductor layer. In some embodiments, forming the conductive component includes: forming a silicon layer in the opening and below the source / drain component; and forming a conductive layer below the silicon layer to fill the remainder of the opening.

[0052] In another example aspect, this disclosure relates to a method of forming a semiconductor structure, comprising: forming a source / drain opening extending into a substrate; forming a semiconductor layer in the bottom of the source / drain opening; forming a dielectric component in the source / drain opening and on the semiconductor layer; forming a source / drain component in the source / drain opening and on the dielectric component; partially etching a portion of the dielectric component, the semiconductor layer, and a portion of the substrate disposed directly beneath the semiconductor layer to form a trench; forming a dielectric barrier layer that pads the sidewall surfaces of the trench, wherein the dielectric barrier layer extends along a portion of the dielectric component; after forming the dielectric barrier layer, forming a silicon layer in the trench; and depositing a conductive layer in the trench and beneath the silicon layer.

[0053] In other embodiments, the method further includes: forming a first dielectric layer on the back side of the substrate and forming a second dielectric layer on the back side of the first dielectric layer; forming a patterned mask on the back side of the substrate, the patterned mask including an opening disposed directly below the source / drain component; and using the patterned mask as an etching mask to pattern the first dielectric layer and the second dielectric layer.

[0054] In other embodiments, the top surface of the dielectric barrier layer is on the top surface of the dielectric component. In other embodiments, the source / drain component includes an N-type dopant, and the method further includes: forming another source / drain opening extending into the substrate; forming another semiconductor layer in the bottom of the other source / drain opening; and forming a P-type source / drain component in the other source / drain opening, directly contacting the other semiconductor layer. In other embodiments, the method further includes: forming an alternating stack of channel layers and sacrificial layers, wherein the source / drain openings extend through the stack; and after forming the source / drain openings, forming inner spacer components disposed between two adjacent layers of the channel layer and between the bottommost layer of the channel layer and the substrate, wherein the top surface of the dielectric component is lower than the top surface of the bottommost inner spacer component. In other embodiments, the conductive layer is separated from the bottommost inner spacer component by the dielectric barrier layer. In other embodiments, a portion of the dielectric barrier layer is disposed directly above the dielectric component. In other embodiments, the profile of the dielectric barrier layer is asymmetrical in a cross-sectional view passing through the source / drain components and the inner spacer components.

[0055] In yet another example, this disclosure relates to a semiconductor structure comprising: a gate structure surrounding a plurality of nanostructures disposed on a substrate; a source / drain component coupled to and adjacent to the nanostructures; a dielectric layer disposed between the source / drain component and the substrate; a back-side via disposed below the source / drain component and electrically coupled to the source / drain component; and a dielectric liner extending through the dielectric layer and the substrate, wherein the back-side via is separated from the dielectric layer by the dielectric liner.

[0056] In some embodiments, the device further includes a silicon layer disposed between the source / drain component and the back-side via, wherein the bottom surface of the silicon layer is on the top surface of the dielectric layer. In some embodiments, the device further includes an inner spacer disposed between the substrate and the bottommost nanostructure of the nanostructure, wherein the dielectric layer directly contacts the inner spacer. In some embodiments, the device further includes an undoped semiconductor layer disposed between the dielectric layer and the substrate, wherein the back-side via further extends through the undoped semiconductor layer.

[0057] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0058] 10: Area 20: Area 100: Method 102: Steps 104: Steps 106: Steps 108: Steps 110: Steps 112: Steps 114: Steps 116: Steps 118: Steps 120: Steps 122: Steps 124: Steps 126: Steps 128: Steps 200: Structure 202:Substrate 205: Isolation Components / STI Components 206: Sacrifice Layer 207: Stacking 208: Channel Layer / Channel Components 210: Dummy gate stack 214: Opening 216: Internal spacer component 218: Semiconductor layer 220: Insulation layer 226: Contact Etching Stop Layer / CESL 228: Dielectric layer / ILD layer 230: Gate structure 236: Etching Stop Layer 238: ILD layer 242: Contact element 244: Interconnection Structure 245: Dielectric Structure 246: First Floor 248: Second Layer 253: Dielectric layer 254: Barrier Layer 260: Void / Air Gap 202t: Top / Platform Structure 202ts: Surface 204A: Active Zone 204B: Active Zone 204C: Active Area / Channel Area 204D: Active Zone 204SD: Source / Drain Region 210a: Dielectric layer 210b: Electrode layer 210c: Mask layer 212a: Spacers 212b: Spacers 218ts: Surface 222N: Source / Drain Component 222P: Source / Drain Component 240a: Silicon layer 240b: Silicon layer 250a: Open 250b: Opening 252a: Trench 252a'': Groove 252b: Trench 252b': Groove 252b'': Groove 252s: Surface 252s': Surface 254a: Barrier layer 254b: Barrier Layer 256a: Silicon layer 256b: Silicon layer 258a: Guide hole 258a'': Guide hole 258b: Guide hole 258b'': Guide hole 258c1: Centerline 258c2: Centerline A-A': line B-B': line C-C'': Line W1: Width W2: Width

Claims

1. A method for forming a semiconductor structure, comprising: Accept a structure comprising: a finned active region protruding from a substrate and including a channel region and a source / drain region; and a dummy gate stack on the channel region; etching the source / drain region to form a source / drain trench; forming a dielectric layer on the substrate and in the source / drain trench; epitaxially forming a source / drain component in the source / drain trench and on the dielectric layer; replacing the dummy gate stack with a gate structure; performing an etching process to etch the substrate and the dielectric layer to form an opening that exposes a bottom surface of the source / drain component; forming a dielectric liner extending along the surfaces of the dielectric layer and the substrate and exposed through the opening; and forming a conductive component in the opening and below the source / drain component.

2. The method of forming a semiconductor structure as described in claim 1, wherein the channel region comprises an alternating plurality of channel layers and a plurality of sacrificial layers, and the method further comprises: After the source / drain trench is formed, the sacrificial layers are selectively etched to form multiple inner spacer grooves; And a plurality of inner spacer components are formed in these inner spacer grooves.

3. The method for forming a semiconductor structure as described in claim 2 further includes: The sacrificial layers are selectively removed, wherein the gate structure further surrounds the channel layers, and a portion of the dielectric liner is laterally disposed between the conductive component and the gate structure.

4. The method of forming a semiconductor structure as described in claim 2 or 3, wherein a portion of the dielectric liner is disposed laterally between the conductive member and a bottommost inner spacer member of the inner spacer members.

5. The method of forming a semiconductor structure as described in claim 4, wherein a top surface of the dielectric substrate is lower than a top surface of the bottom inner spacer member.

6. A method for forming a semiconductor structure, comprising: A source / drain opening is formed, extending into a substrate; A semiconductor layer is formed at the bottom of the source / drain opening; A dielectric component is formed in the source / drain opening and on the semiconductor layer; a source / drain component is formed in the source / drain opening and on the dielectric component; the dielectric component, the semiconductor layer, and a portion of the substrate disposed directly beneath the semiconductor layer are partially etched to form a trench; a dielectric barrier layer is formed to line the sidewall surface of the trench, wherein the dielectric barrier layer extends along a portion of the dielectric component; after forming the dielectric barrier layer, a silicon layer is formed in the trench; and a conductive layer is deposited in the trench and beneath the silicon layer.

7. The method for forming a semiconductor structure as described in claim 6 further includes: A first dielectric layer is formed on one back side of the substrate, and a second dielectric layer is formed on one back side of the first dielectric layer; A patterned mask is formed on the back side of the substrate. The patterned mask includes an opening located directly below the source / drain component. The patterned mask is used as an etching mask to pattern the first dielectric layer and the second dielectric layer.

8. The method of forming a semiconductor structure as described in claim 7, wherein a top surface of the dielectric barrier layer is on a top surface of the dielectric component.

9. A method of forming a semiconductor structure as described in any one of claims 6 to 8, wherein the source / drain component comprises an N-type dopant, the method further comprising: Another source / drain opening is formed, extending into the substrate; Another semiconductor layer is formed at one bottom of the other source / drain opening; And a P-type source / drain component is formed in the other source / drain opening and directly contacts the other semiconductor layer.

10. The method of forming a semiconductor structure as described in any one of claims 6 to 8 further comprises: A stack is formed with alternating multiple channel layers and multiple sacrificial layers, wherein the source / drain opening extends through the stack; After the source / drain opening is formed, a plurality of inner spacer components are formed and disposed between two adjacent layers of the channel layers and between a bottom layer of the channel layers and the substrate, wherein a top surface of the dielectric component is lower than a top surface of a bottom inner spacer component.

11. The method of forming a semiconductor structure as described in claim 10, wherein the conductive layer is separated from the bottom inner spacer component by the dielectric barrier layer.

12. A semiconductor structure comprising: A gate structure that surrounds a plurality of nanostructures disposed on a substrate; A source / drain component coupled to the nanostructures and adjacent to the gate structure; a dielectric layer disposed between the source / drain component and the substrate; a back-side via disposed below the source / drain component and electrically coupled to the source / drain component; an undoped semiconductor layer disposed between the dielectric layer and the substrate, wherein the back-side via further extends through the undoped semiconductor layer; and a dielectric liner extending through the dielectric layer and the substrate, wherein the back-side via is separated from the dielectric layer by the dielectric liner.

13. The semiconductor structure as described in claim 12, further comprising: A silicon layer is disposed between the source / drain component and the back-side via, wherein a bottom surface of the silicon layer is on a top surface of the dielectric layer.

14. The semiconductor structure as described in claim 12, further comprising: An inner spacer is disposed between the substrate and a bottommost nanostructure of the nanostructures, wherein the dielectric layer is in direct contact with the inner spacer.

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