Manufacturing method of semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device and a method for manufacturing the same, which aim to improve strength and data readability characteristics. The semiconductor memory device of the embodiment includes a stacked body and first to fifth insulators. The stacked body has a plurality of first conductive layers stacked along a first direction, a second conductive layer below the first conductive layers, and a third conductive layer above the first conductive layers. The first and second insulators penetrate the stacked body and extend along a second direction intersecting the first direction. The first insulator divides the plurality of first, second, and third conductive layers in a third direction intersecting the first and second directions. The third insulator is located between the first and second insulators, extends along the second direction, and divides the plurality of first, second, and third conductive layers in the third direction. The fourth and fifth insulators are disposed between adjacent third insulators and extend along the first and second directions, respectively. The fourth and fifth insulators respectively break the second and third conductive layers in the third direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Prior Technology

[0002] NAND (Not AND) type flash memory is known to be obtained by three-dimensional stacking of memory cells. Summary of the Invention

[0003] [Problem to be Solved by the Invention] The embodiments of the present invention provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can achieve improvements in strength and data readout characteristics.

[0004] The semiconductor memory device of the embodiment includes a stacked body, a first columnar body, a first insulator, a second insulator, a third insulator, a fourth insulator, and a fifth insulator. The stacked body has a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is stacked along a first direction. The second conductive layer is disposed below the plurality of first conductive layers. The third conductive layer is disposed above the plurality of first conductive layers. The first columnar body penetrates the stacked body along the first direction and includes a semiconductor layer. The first insulator penetrates the stacked body along the first direction and extends along a second direction intersecting the first direction. The first insulator divides the plurality of first conductive layers, second conductive layers, and third conductive layers in a third direction intersecting the first and second directions. The second insulator is disposed at a position spaced apart from the first insulator in the third direction, penetrates the stacked body along the first direction, and extends along the second direction. The second insulator separates a plurality of first conductive layers, second conductive layers, and third conductive layers in a third direction. The third insulator has a first portion and a second portion disposed separately from the first portion in a second direction. The first portion and the second portion are located between the first insulator and the second insulator in the third direction, penetrate the laminate in the first direction, and extend in the second direction. The first portion and the second portion separate a plurality of first conductive layers, second conductive layers, and third conductive layers in the third direction. A fourth insulator is disposed between the first portion and the second portion and extends in both the first and second directions. The fourth insulator separates the second conductive layer in the third direction. A fifth insulator is disposed between the first portion and the second portion and extends in both the first and second directions. The fifth insulator separates the third conductive layer in the third direction. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram showing the semiconductor memory device and memory controller of the first embodiment. Figure 2 is a diagram showing a portion of the equivalent circuit of the memory cell array of the semiconductor memory device of the first embodiment. Figure 3A is a top view showing a portion of the semiconductor memory device of the first embodiment. Figure 3B is a cross-sectional view showing a portion of the semiconductor memory device of the first embodiment. Figure 3C is a cross-sectional view showing a portion of the semiconductor memory device of the first embodiment. Figure 4A is a cross-sectional view showing the columnar body of the semiconductor memory device of the first embodiment. Figure 4B is a cross-sectional view showing the columnar body of the semiconductor memory device of the first embodiment. Figure 4C is a cross-sectional view magnified near the conductive layer of the semiconductor memory device of the first embodiment. Figure 5A is a top view showing a portion of the semiconductor memory device of the first variation of the first embodiment. Figure 5B is a cross-sectional view showing a portion of the semiconductor memory device of the first variation of the first embodiment. Figure 5C is a cross-sectional view showing a portion of the semiconductor memory device of the first variation of the first embodiment. Figures 6-13 are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14A is a top view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14B is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14C is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figures 15-19 are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first variation of the first embodiment. Figure 20A is a top view illustrating the manufacturing method of the semiconductor memory device according to the first variation of the first embodiment. Figure 20B is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first variation of the first embodiment. Figure 20C is a cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first variation of the first embodiment. Implementation

[0006] The following describes the semiconductor memory device and its manufacturing method with reference to the drawings. In the following description, components having the same or similar functions are labeled with the same symbols. Furthermore, repeated descriptions of these components are sometimes omitted. The drawings are schematic diagrams or conceptual diagrams; the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not be the same as in the actual object. In this application, "connection" is not limited to physical connection, but also includes electrical connection. In this application, "parallel," "orthogonal," or "same" also include "generally parallel," "generally orthogonal," or "generally same," respectively. In this application, "extending along direction A" means, for example, that the dimension in direction A is larger than the smallest dimension among the dimensions in directions X, Y, and Z described below. The "direction A" mentioned here is any direction.

[0007] First, the X, Y, and Z directions are defined. The X and Y directions are directions that are substantially parallel to the surface of the substrate 30 described below. The X and Y directions are orthogonal to each other. The Z direction is orthogonal to the X and Y directions and is away from the substrate 30. However, these expressions are used for convenience and do not specify the direction of gravity. In this embodiment, the Z direction is an example of the "first direction".

[0008] In the following reference figures, for example, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the substrate 30 used to form the semiconductor memory device 1. In the top view, some parts are appropriately shaded for ease of reading. The shaded parts in the top view are not necessarily related to the material or characteristics of the constituent elements to which the shaded parts are attached. In the top view and sectional view, some constituent elements such as wiring, contacts, and interlayer insulating films are appropriately omitted for ease of reading.

[0009] (First Embodiment)

[0010] Figure 1 is a block diagram showing a semiconductor memory device 1 and a memory controller 2. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 includes, for example, a memory cell array 10, a column decoder 11, a sense amplifier 12, and a sequencer 13.

[0011] The memory cell array 10 comprises a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Each block BLK is a collection of non-volatile memory cell transistors MT (see Figure 2). A plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor MT is connected to one bit line and one word line. The detailed structure of the memory cell array 10 will be described below.

[0012] The column decoder 11 selects a block BLK based on the address information ADD received from the external memory controller 2. The column decoder 11 controls the write and read operations of data on the memory cell array 10 by applying the required voltage to a plurality of word lines respectively.

[0013] The sensing amplifier 12 applies the required voltage to each bit line based on the write data DAT received from the memory controller 2. The sensing amplifier 12 determines the data stored in the memory cell transistor MT based on the voltage of the bit line, and sends the determined read data DAT to the memory controller 2.

[0014] The sequencer 13 controls the operation of the entire semiconductor memory device 1 based on the instruction CMD received from the memory controller 2.

[0015] The semiconductor memory device 1 and memory controller 2 described above can also be combined to form a semiconductor device. Examples of semiconductor devices include memory cards such as SD (trademarked) cards or SSDs (Solid State Drives).

[0016] Next, the electrical configuration of the memory cell array 10 will be explained.

[0017] Figure 2 is a diagram showing a portion of the equivalent circuit of the memory cell array 10. Figure 2 shows a block BLK contained in the memory cell array 10. The block BLK contains a plurality of (e.g., 4) strings STR0~STR3.

[0018] Each string STR0~STR3 is a collection of multiple NAND strings NS. One end of each NAND string NS is connected to any one of the bit lines BL0~BLm (m is an integer greater than or equal to 1). The other end of the NAND string NS is connected to the source line SL. Each NAND string NS contains multiple memory cell transistors MT0~MTn (n is an integer greater than or equal to 1), a first selector transistor S1, and a second selector transistor S2.

[0019] A plurality of memory cell transistors MT0~MTn are electrically connected in series. Each memory cell transistor MT includes a control gate and a memory volumetric layer (e.g., a charge storage membrane) to non-volatile stored data. The memory cell transistor MT changes the state of the memory volumetric layer (e.g., storing charge in the charge storage membrane) according to the voltage applied to the control gate. The control gate of the memory cell transistor MT is connected to any one of the corresponding word lines WL0~WLn. The memory cell transistor MT is electrically connected to the column decoder 11 via word lines WL.

[0020] The first select transistor S1 in each NAND string NS is connected between a plurality of memory cell transistors MT0~MTn and any bit line BL0~BLm. The drain of the first select transistor S1 is connected to any bit line BL0~BLm. The source of the first select transistor S1 is connected to the memory cell transistor MTn. The control gate of the first select transistor S1 in each NAND string NS is connected to any select gate line SGD0~SGD3. The first select transistor S1 is electrically connected to the column decoder 11 via the select gate line SGD. When a specific voltage is applied to any one of the select gate lines SGD0~SGD3, the first select transistor S1 connects the NAND string NS to the bit line BL.

[0021] The second select transistor S2 in each NAND string NS is connected between the plurality of memory cell transistors MT0~MTn and the source line SL. The drain of the second select transistor S2 is connected to the memory cell transistor MT0. The source of the second select transistor S2 is connected to the source line SL. The control gate of the second select transistor S2 is connected to the select gate line SGS. The second select transistor S2 is electrically connected to the column decoder 11 via the select gate line SGS. When a specific voltage is applied to the select gate line SGS, the second select transistor S2 connects the NAND string NS and the source line SL.

[0022] Furthermore, the memory cell array 10 can also be configured with other circuits besides those described above. For example, the number of each string STR contained in each block BLK, the number of memory cell transistors MT contained in each NAND string NS, and the number of select transistors STD and STS can also be changed. Also, the NAND string NS can contain more than one dummy transistor.

[0023] Figure 3A is a top view showing a portion of the semiconductor memory device 1 according to the first embodiment. Figure 3B is a cross-sectional view along plane A-A' in Figure 3A. Figure 3C is a cross-sectional view along plane B-B' in Figure 3A.

[0024] As shown in Figure 3A, the semiconductor memory device 1 of the first embodiment includes a memory cell array 10 and stepped portions S, for example, disposed at both ends of the stacked body 20 in the X-axis direction. A first slit ST1 and a second slit ST2 are disposed from one stepped portion S of the stacked body 20 through the memory cell array 10 to the other stepped portion S. Similarly, a third slit SST and a sixth slit SHE are disposed from one stepped portion S of the stacked body 20 through the memory cell array 10 to the other stepped portion S.

[0025] Next, an example of the construction of the memory cell array 10 of the semiconductor memory device 1 will be described. The memory cell array 10 has a cell array region and a peripheral region. A NAND string NS is integrated in the cell array region. Peripheral circuitry for controlling the cell array region is disposed in the peripheral region. The peripheral region may be adjacent to the cell array region in the X or Y direction, or may be stacked relative to the cell array region in the Z direction. The following shows an example of the peripheral region being stacked relative to the cell array region in the Z direction.

[0026] As shown in Figures 3A and 3B, the memory cell array 10 of the semiconductor memory device 1 includes a substrate 30, a circuit layer PE, a stack 20, a plurality of columnar bodies CL, a first insulator 41, a second insulator 42, a third insulator 43, a fourth insulator 44, and a fifth insulator 45. In this embodiment, the columnar body CL is an example of the "first columnar body".

[0027] The substrate 30 is, for example, a silicon substrate. A plurality of component separation regions 30A are present on the surface region of the substrate 30. The component separation regions 30A are, for example, composed of silicon oxide. Between adjacent component separation regions 30A are source and drain regions of a transistor Tr.

[0028] A circuit layer PE is located on substrate 30. The circuit layer PE includes a column decoder 11, a sense amplifier 12, and a sequencer 13 of the semiconductor memory device 1. The circuit layer PE includes, for example, a plurality of transistors Tr, a plurality of wiring layers D0, D1, and a plurality of vias C1, C2. The plurality of transistors Tr, wiring layers D0, D1, and vias C1, C2 are located within an insulating layer E1. The insulating layer E1 includes, for example, silicon oxide. Via C1 connects the source or drain region of transistor Tr to wiring layer D0. Via C2 connects the gate region of transistor Tr to wiring layer D1. Each wiring layer D0 and wiring layer D1 extends in the X and Y directions. Wiring layer D1 is connected to contact plug CP1. Vias C1, C2, and wiring layers D0, D1 include, for example, tungsten.

[0029] The laminate 20 has a conductive layer 21, a plurality of conductive layers 25, an insulating layer 22, and a plurality of insulating layers 24 in the Z direction. The conductive layers 21 and 25 are alternately laminated with the insulating layers 22 and 24. The plurality of conductive layers 21 and 25 extend in the X and Y directions, respectively. The plurality of insulating layers 22 and 24 extend in the X and Y directions, respectively. The plurality of insulating layers 24 and the plurality of conductive layers 25 are alternately laminated in the Z direction.

[0030] Insulating layer 22 and a plurality of insulating layers 24 extend in the X and Y directions, respectively. Insulating layer 22 and the plurality of insulating layers 24 may contain, for example, silicon oxide. Insulating layer 22 is located between conductive layer 21 and conductive layer 25. Insulating layer 24 is located between adjacent conductive layers 25 in the Z direction. Insulating layer 24 insulates between two adjacent conductive layers 25 in the Z direction. The number of insulating layers 24 is determined by the number of conductive layers 25.

[0031] A plurality of conductive layers 25 extend in both the X and Y directions. That is, each conductive layer 25 is formed as a plate extending along both the X and Y directions. The conductive layers 25 are, for example, tungsten or polycrystalline silicon doped with impurities. The number of conductive layers 25 is arbitrary.

[0032] The plurality of conductive layers 25 includes: a plurality of first conductive layers 25A, which are stacked equally along the Z direction; a second conductive layer 25B, which is located in the Z direction between the substrate 30 and the plurality of first conductive layers 25A; and a third conductive layer 25C, which is located in the Z direction on the side opposite to the substrate 30 relative to the plurality of first conductive layers 25A. The plurality of conductive layers 25 may, for example, be functionally divided into three types. The plurality of conductive layers 25 function as any one of the source-side select gate line SGS, word line WL, and drain-side select gate line SGD.

[0033] In the conductive layer 25, at least one second conductive layer 25B, starting from below the stacked body 20, functions as a source-side selective gate line (SGS). The conductive layer 25 functioning as the source-side selective gate line (SGS) can be a single layer or multiple layers. That is, the source-side selective gate line (SGS) can be composed of one conductive layer 25 or multiple conductive layers 25. Furthermore, when the source-side selective gate line (SGS) is composed of multiple layers, each conductive layer 25 can be composed of different conductors.

[0034] In the conductive layer 25, at least one third conductive layer 25C, starting from above the stacked body 20, functions as a drain-side selective gate line (SGD). The third conductive layer 25C functioning as the drain-side selective gate line (SGD) can be a single layer or multiple layers. That is, the drain-side selective gate line (SGD) can be composed of one third conductive layer 25C or multiple third conductive layers 25C. Furthermore, when the drain-side selective gate line (SGD) is composed of multiple layers, each third conductive layer 25C can be composed of different conductors.

[0035] In the conductive layer 25, the conductive layer 25, excluding the source-side selected gate line SGS and the drain-side selected gate line SGD, functions as a word line WL. For example, the conductive layer 25 that functions as a word line WL surrounds the outer periphery of the columnar body CL.

[0036] The plurality of conductive layers 25 may comprise, for example, a conductive metal. The conductive metal may be, for example, tungsten. The plurality of conductive layers 25 may also be, for example, polycrystalline silicon doped with impurities.

[0037] A conductive layer 21 is disposed above the circuit layer PE. The conductive layer 21 includes semiconductor layers 21A, 21B, and 21C. Semiconductor layer 21A is located on the circuit layer PE. Semiconductor layer 21B is located on semiconductor layer 21A. Semiconductor layer 21C is located on semiconductor layer 21B. Details of semiconductor layers 21A, 21B, and 21C will be described below.

[0038] The cover insulating layer 50 is located on the uppermost insulating layer 24 of the laminate 20. The cover insulating layer 50 insulates the laminate 20 from the bit line BL. The cover insulating layer 50 may contain, for example, silicon oxide.

[0039] For example, bit lines BL are formed as lines extending along the Y direction on the covering insulating layer 50, and are electrically connected to any pillar CL and contact plug (not shown). A plurality of bit lines BL are arranged along the X direction in an area not shown.

[0040] A plurality of columnar bodies CL are disposed within the laminate 20. The plurality of columnar bodies CL extend along the Z-direction. For example, the plurality of columnar bodies CL penetrate the laminate 20 along the Z-direction. The lower part of each columnar body CL is in contact with the semiconductor layer 21A. The upper part of each columnar body CL is in contact with the covering insulating layer 50.

[0041] Figure 4A is an enlarged cross-sectional view of the vicinity of the columnar body CL of the semiconductor memory device 1. Figure 4B is a cross-sectional view obtained by cutting along the conductive layer 25 near the columnar body CL of the semiconductor memory device 1. Figure 4A is a cross-section obtained by cutting the columnar body CL with the YZ plane, and Figure 4B is a cross-section obtained by cutting the columnar body CL with the XY plane. A plurality of columnar bodies CL are formed in memory holes MH, and from the inside, they sequentially have an insulating core 60, a semiconductor layer 61, and a memory volume layer film 62.

[0042] The insulating core 60 extends along the Z direction and is columnar. The insulating core 60 may contain, for example, silicon oxide. When viewed from the Z direction, the insulating core 60 is located at the center of the memory hole MH, including the central axis.

[0043] Semiconductor layer 61 extends along the Z direction. Semiconductor layer 61 is formed, for example, in a ring shape, covering the outer surface (outer peripheral surface) of insulating core 60. Semiconductor layer 61 contains, for example, silicon. The silicon is, for example, polycrystalline silicon obtained by crystallizing amorphous silicon. Semiconductor layer 61 functions as a channel for the first selector transistor S1, a plurality of memory cell transistors MT, and the second selector transistor S2. Here, "channel" refers to the carrier flow path between the source side and the drain side.

[0044] The memory volume layer film 62 extends along the Z-direction. The memory volume layer film 62 covers the outer surface (outer peripheral surface) of the semiconductor layer 61. The memory volume layer film 62 is located between the inner surface (inner peripheral surface) of the memory via MH and the outer surface (outer peripheral surface) of the semiconductor layer 61. The memory volume layer film 62 includes, for example, a tunnel insulating film 63, a charge storage film 64, and a cover insulating film 65. These plurality of films are arranged from the semiconductor layer 61 side in the order of tunnel insulating film 63, charge storage film 64, and cover insulating film 65.

[0045] The tunnel insulating film 63 covers the outer surface of the semiconductor layer 61. That is, the tunnel insulating film 63 is located between the charge storage film 64 and the semiconductor layer 61. The tunnel insulating film 63 may contain, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 63 acts as a potential barrier between the semiconductor layer 61 and the charge storage film 64.

[0046] The charge storage film 64 covers the outer surface of the tunnel insulating film 63. That is, the charge storage film 64 is located between each conductive layer 25 and the tunnel insulating film 63. The charge storage film 64 may contain, for example, silicon nitride. The portions where the charge storage film 64 intersects with each of the plurality of conductive layers 25 function as transistors. The memory cell transistor MT stores data based on the presence or absence of charge, or the amount of charge stored, in the portions where the charge storage film 64 intersects with each of the plurality of conductive layers 25 (charge storage sections). The charge storage sections are located between each conductive layer 25 and the semiconductor layer 61, and are surrounded by insulating material. The charge storage sections have a so-called float gate structure.

[0047] As shown in Figure 4A, a cover insulating film 65 is located, for example, between each insulating layer 24 and the charge storage film 64. The cover insulating film 65 comprises, for example, silicon oxide. The cover insulating film 65 protects the charge storage film 64 from etching during processing. The cover insulating film 65 may be absent, or it may be partially retained between the conductive layer 25 and the charge storage film 64 to act as a barrier insulating film.

[0048] Furthermore, barrier insulating films 25a and barrier films 25b may be provided between each conductive layer 25 and the insulating layer 24, and between each conductive layer 25 and the memory volume layer film 62. The barrier insulating film 25a suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the conductive layer 25 towards the memory volume layer film 62. The barrier film 25b improves the adhesion between the conductive layer 25 and the barrier insulating film 25a. The barrier insulating film 25a may be, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. For example, when the conductive layer 25 is tungsten, the barrier film 25b may be a laminated film of titanium nitride and titanium.

[0049] Figure 4C is an enlarged cross-sectional view of the vicinity of the conductive layer 21 of the semiconductor memory device 1. Figure 4C is a cross-section obtained by cutting the conductive layer 21 and the columnar bodies CL along the YZ plane. As described above, the conductive layer 21 includes, for example, semiconductor layers 21A, 21B, and 21C. The conductive layer 21 is connected to each of the plurality of columnar bodies CL. The conductive layer 21 is formed, for example, as a plate extending along the X and Y directions, and functions as a source line SL.

[0050] Semiconductor layer 21A is located on circuit layer PE. Semiconductor layer 21A is, for example, an n-type semiconductor. Semiconductor layer 21A is, for example, polycrystalline silicon doped with impurities. Semiconductor layer 21B is located on semiconductor layer 21A. Semiconductor layer 21B is connected to semiconductor layer 61 of pillar CL. Semiconductor layer 21B is, for example, an epitaxial film doped with impurities. Semiconductor layer 21B contains, for example, phosphorus. Semiconductor layer 21C is located on semiconductor layer 21B. Semiconductor layer 21C is, for example, an n-type or undoped semiconductor.

[0051] Here, as shown in FIG3A, the semiconductor memory device 1 of this embodiment has a plurality of slits when viewed from the Z direction (refer to slits 1 to 5 below). The plurality of slits are grooves that divide the laminate 20 in the Y direction. The plurality of slits all extend in the X direction.

[0052] The multiple slits are roughly divided into slit 1 (ST1), slit 2 (ST2), slit 3 (SST), slit 4 (ST4), slit 5 (ST5), and slit 6 (SHE).

[0053] Both the first slit ST1 and the second slit ST2 are deep slits that penetrate the laminate 20 and extend from the upper surface of the covering insulating layer 50 to the conductive layer 21. The second slit ST2 is located at a position that is spaced apart from the first slit ST1 in the Y direction.

[0054] The third slit SST is a deep slit that penetrates the laminate 20 and extends from the upper surface of the covering insulating layer 50 to the conductive layer 21. When viewed from the Z direction, the third slit SST extends along the X direction and is arranged in a dashed line shape.

[0055] The fourth slit ST4 is located in the stack 20 at a position corresponding to the second conductive layer 25B (source-side selected gate line SGS) and between the adjacent third slit SST in the X direction, dividing the second conductive layer 25B in the Y direction.

[0056] The fifth slit ST5 is located in the laminate 20 at a position corresponding to the third conductive layer 25C (drain-side selected gate line SGD), dividing the third conductive layer 25C in the Y direction. When viewed from the Z direction, the fifth slit ST5 extends along the X direction and is positioned to span between adjacent third slits SST in the X direction. The sixth slit SHE is a shallow slit, extending from the upper surface of the covering insulating layer 50 to the middle of the laminate.

[0057] The first insulator 41 and the second insulator 42 are respectively disposed within the first slit ST1 and the second slit ST2. That is, the first insulator 41 and the second insulator 42 are disposed within the laminate 20 along the Z direction from the upper surface of the covering insulating layer 50 to the conductive layer 21. When viewed from the Z direction, the first insulator 41 extends along the X direction, and the second insulator 42 extends along the X direction at a different position from the first insulator 41 in the Y direction. The first conductive layer 25A, the second conductive layer 25B, and the third conductive layer 25C are separated in the Y direction by the first insulator 41 and the second insulator 42. Each of the first insulator 41 and the second insulator 42 may contain, for example, silicon oxide. The laminate 20 between the first insulator 41 and the second insulator 42 is called a block, which may constitute the smallest unit of data erasure.

[0058] The third insulator 43 is disposed within a deeper third slit SST, which is arranged in a dashed line shape when viewed from above. That is, the third insulator 43 has a plurality of insulators 43a and 43b separated from each other in the X direction between the first insulator 41 and the second insulator 42 in the Y direction. Insulator 43a mentioned here is an example of the first part, and insulator 43b is an example of the second part. Furthermore, the third insulator 43 is disposed within the laminate 20 along the Z direction from the upper surface of the covering insulating layer 50 to the conductive layer 21, and is arranged in a dashed line shape in the X direction. The third insulator 43, for example, comprises silicon oxide.

[0059] A fourth insulator 44 is disposed within a fourth slit ST4, which is located at a position corresponding to the second conductive layer 25B (source-side selected gate line SGS). Specifically, the fourth insulator 44 is disposed in the lower region of the substrate 30 side of the laminate 20, extending along both the Z and X directions, between adjacent third slits SST in the X direction (between insulators 43a and 43b). The fourth insulator 44 divides the second conductive layer 25B in the Y direction. The fourth insulator 44 may also be configured to connect to the ends of insulators 43a and 43b. Furthermore, the fourth insulator 44 is positioned to overlap with the fifth insulator 45 described below when viewed from the Z direction.

[0060] The fifth insulator 45 is disposed within the fifth slit ST5, which is located at a position corresponding to the third conductive layer 25C (drain-side selected gate line SGD). That is, the fifth insulator 45 is disposed in the upper region of the bit line BL side of the laminate 20, spanning between adjacent third slits SST (between insulators 43a and 43b) in the X direction. Furthermore, in Figure 3A, the two ends of the fifth insulator 45 in the X direction are disposed at positions overlapping with the third insulator 43 (insulators 43a and 43b) in the Z direction; however, the two ends of the fifth insulator 45 in the X direction may also be disposed in connection with the ends of insulators 43a and 43b. Additionally, the fifth insulator 45 is disposed in the upper region of the bit line BL side of the laminate 20, extending along both the Z and X directions. The third conductive layer 25C is divided in the Y direction by the fifth insulator 45. Furthermore, the fifth insulator 45 is positioned at the location where it overlaps with the fourth insulator 44 when viewed from the Z direction.

[0061] The widths of the fourth insulator 44 and the fifth insulator 45 in the Y direction should preferably be less than or equal to the width of the third insulator (i.e., the third slit SST) in the Y direction. The third slit SST is formed after the fourth insulator 44 and the fifth insulator 45 are formed, as will be described in detail later. Therefore, by setting the widths of the fourth insulator 44 and the fifth insulator 45 in the Y direction to be less than or equal to the width of the third insulator (the third slit SST), the fourth insulator 44 and the fifth insulator 45 corresponding to the formation position of the third slit SST can be removed. As a result, replacement processing using the third slit SST can be reliably implemented.

[0062] Furthermore, the greater the distance (interval) between adjacent third slits SST in the X direction (between insulators 43a and 43b), the better it prevents finger distortion. However, if the distance is too large, there is a concern that the laminate 20 may flex during replacement processing. Therefore, the distance (interval) between adjacent third slits SST in the X direction (between insulators 43a and 43b) should be set within a range that can prevent the laminate 20 from flexing during replacement processing.

[0063] Furthermore, a fourth insulator 44 and a fifth insulator 45 are respectively provided at positions corresponding to the second conductive layer 25B (source-side selected gate line SGS) and the third conductive layer 25C (drain-side selected gate line SGD). On the other hand, the first conductive layer 25A (word line WL) between the fourth insulator 44 and the fifth insulator 45 in the Z direction extends from the first insulator 41 to the second insulator 42 in the Y direction. That is, although the second conductive layer 25B and the third conductive layer 25C between the third slits SST (between insulators 43a and 43b) are interrupted, the first conductive layer 25A (word line WL) is not interrupted, but is continuously connected between the first insulator 41 and the second insulator 42.

[0064] The sixth insulator 46 is disposed within the sixth slit SHE. The sixth insulator 46 is disposed along the Z direction from the upper end of the laminate 20 to the middle of the laminate 20.

[0065] As described above, the fifth insulator 45, extending to the middle of the laminate 20, penetrates the upper region of the laminate 20 to form the third conductive layer 25C of the drain-side selective gate line SGD. The third conductive layer 25C forming the drain-side selective gate line SGD is separated from each other on both sides in the Y direction by the third insulator 43 (the third slit SST) in the laminate 20 between the first insulator 41 and the second insulator 42 forming one block.

[0066] In this embodiment, when viewed from the Z direction, the area between the first insulator 41 and the second insulator 42 is called "block BLK", the area between the first insulator 41 and the third insulator 43 and the area between the second insulator 42 and the third insulator 43 are called "finger F", and the area separated by adjacent first insulator 41 and sixth insulator 46, adjacent third insulator 43 and sixth insulator 46 or two adjacent sixth insulators 46 is called "string STR".

[0067] In this embodiment, for each of the fingers F, a drain-side selected gate line (SGD) is formed by the third insulator 43. Therefore, during data writing and reading, one finger F in block BLK can be selected by the drain-side selected gate line (SGD). Furthermore, the number of strings STR contained in one finger F is unlimited, and the number of strings STR is, for example, an odd number.

[0068] Furthermore, as shown in Figure 3A, a plurality of columnar bodies CL are arranged in an alternating pattern in the Y direction when viewed from the Z direction. The number of columnar bodies CL arranged in an alternating pattern in the Y direction is, for example, the same in each string of STRs. In each string of STRs shown in Figure 3A, four columnar bodies CL are arranged in an alternating pattern in the Y direction. Moreover, the sixth slit SHE is formed by etching away at least a portion of the columnar body CL at the corresponding position. Therefore, the columnar body CL formed at the position corresponding to the sixth slit SHE sometimes appears partially removed when viewed from above.

[0069] Furthermore, the planar layout of the memory cell array of the semiconductor memory device 1 is not limited to the layout shown in Figure 3A, but can also be other layouts. For example, the number and arrangement of the columnar bodies CL in an adjacent string STR can be appropriately changed.

[0070] The semiconductor memory device 1 of the first embodiment can improve the strength against the twisting of the finger F by using a third insulator 43 (insulators 43a and 43b) arranged in a dotted line shape. Furthermore, a fourth insulator 44 and a fifth insulator 45 are provided between adjacent third insulators 43 (insulators 43a and 43b) in the X direction to separate the second conductive layer 25B (source-side select gate line SGS) and the third conductive layer 25C (drain-side select gate line SGD). With these, during data writing and reading, one finger F in the block BLK can be set to a selected state, and the other finger F separated by the third insulator 43 can be set to a non-selected state. Furthermore, the string STR within the unselected finger F (i.e., the unread finger F) becomes floating. Therefore, when a voltage is applied to the first conductive layer 25A (WL), the string STR also rises, thus maintaining the potential difference between the string STR and the first conductive layer 25A (WL). As a result, the influence of the read voltage of the unselected string STR can be avoided, thereby improving read disturbance.

[0071] Furthermore, in the semiconductor memory device 1 of the first embodiment, instead of the segmented portion of the block BLK (i.e., the first insulator 41 and the second insulator 42), a fourth insulator 44 is provided in the inner region of the block BLK (the region surrounded by the first insulator 41 and the second insulator 42) to segment the second conductive layer 25B (source-side selected gate line SGS). Furthermore, third insulators 43 penetrating the stacked layer 20 are respectively provided on both sides of the fourth insulator 44 in the X direction. This ensures the strength of the entire block BLK (especially its bending strength) and suppresses the read disturbance of the adjacent finger F segmented by the fourth insulator 44.

[0072] The "read interference" mentioned here refers to the generation of an electric field in a memory cell (hereinafter referred to as "non-read target memory cell") that is different from the memory cell of the data being read during the data read operation. The amount of charge held by the non-read target memory cell changes due to the influence of the electric field (e.g., the charge increases).

[0073] (Example 1 of the variations)

[0074] A first variation of the semiconductor memory device 1 according to the first embodiment will be described.

[0075] Figures 5A to 5C are cross-sectional views showing a portion of the semiconductor memory device 1A of the first variation. The semiconductor memory device 1A of the first variation is the same as the semiconductor memory device 1 of the first embodiment, except for the configuration described below.

[0076] The semiconductor memory device 1A of the first variation may also have a plurality of second columnar bodies CLd that penetrate the laminate 20 in the first direction between adjacent third insulators 43 (between insulators 43a and 43b) in the X direction. That is, in the first variation, in addition to the fourth insulator 44 and the fifth insulator 45, a plurality of second columnar bodies CLd are provided in the laminate 20 between adjacent third insulators 43 (between insulators 43a and 43b) in the X direction.

[0077] As described above, the greater the distance (interval) between adjacent third insulators 43 (between insulators 43a and 43b) in the X direction, the better the finger distortion can be prevented. However, if the distance is too large, there is a concern that the laminate 20 may flex during replacement processing. Therefore, in the first variation, by providing a plurality of second columnar bodies CLd as reinforcements between adjacent third insulators 43 in the X direction, finger distortion and bending of the laminate 20 can be prevented. Furthermore, by using a plurality of second columnar bodies CLd to reinforce the laminate 20 between adjacent third insulators 43, the distance (interval) between adjacent third insulators 43 can be made larger than in the first embodiment. As a result, compared to the first embodiment, the semiconductor device of the first variation can further prevent finger distortion.

[0078] Here, the second columnar body CLd functions as a reinforcing material. Therefore, the film composition of the second columnar body CLd is not particularly limited, and from the point of view of manufacturing efficiency, it can be the same as the film composition of the columnar body CL (see Figures 4A and 4B).

[0079] Furthermore, by constructing the first variation, in addition to the effects described above, the influence of the readout voltage of the non-selected string can also be avoided, similar to the first embodiment.

[0080] (Manufacturing method)

[0081] Next, the manufacturing method of the semiconductor memory device 1 according to the first embodiment will be described. Figures 6 to 14C are cross-sectional views or top views used to illustrate the manufacturing method of the semiconductor memory device 1 according to the first embodiment. Furthermore, Figure 14A is a top view showing the manufacturing process of the semiconductor memory device 1. Figure 14B is a cross-sectional view along the X-X' plane in Figure 14A, and Figure 14C is a cross-sectional view along the Y-Y' plane in Figure 14A.

[0082] First, as shown in Figure 6, a component separation region 30A is formed within the substrate 30, and a transistor Tr is formed within the circuit layer PE (refer to Figure 1). The transistor Tr can be fabricated using well-known methods. Furthermore, within the circuit layer PE, within the insulating layer E1, a plurality of wiring layers D0, D1 and a plurality of vias C1, C2 electrically connected to the transistor Tr are formed. The plurality of wiring layers D0, D1 and the plurality of vias C1, C2 can be fabricated using well-known methods.

[0083] Subsequently, a semiconductor layer 21A, an intermediate film 21Ba, a first sacrificial film 21Bb, an intermediate film 21Bc, a semiconductor layer 21C, and an insulating layer 22 are sequentially deposited on the circuit layer PE. The intermediate films 21Ba and 21Bc, for example, comprise silicon oxide. The first sacrificial film 21Bb is, for example, a silicon nitride. The semiconductor layers 21A, 21C, and insulating layer 22 are the same as described above.

[0084] Subsequently, as shown in Figure 7, insulating layers 24 and sacrificial films 85 are alternately deposited on insulating layer 22 to form a first stacked body 20A. At this time, insulating layers 24 and sacrificial films 85 are deposited to the height corresponding to the second conductive layer 25B (source-side selected gate line SGS), that is, the height corresponding to the fourth insulator 44.

[0085] The insulating layer 24 is the insulating layer 24 described above, for example, containing silicon oxide. The sacrificial film 85 contains, for example, silicon nitride.

[0086] Subsequently, a fourth slit ST4 extending in the X direction is formed in the insulating layer 24 and the sacrificial film 85 of the stacked layers, penetrating through the first stacked layer 20A. The fourth slit ST4 extends from the upper surface of the uppermost sacrificial film 85 to the middle of the insulating layer 22. The fourth slit ST4 is formed by etching. For example, anisotropic etching is performed from the upper surface of the uppermost sacrificial film 85 to the insulating layer 22. Anisotropic etching is, for example, reactive ion etching (RIE). Afterward, an insulator is filled into the fourth slit ST4 to form a fourth insulator 44. The fourth insulator 44 contains, for example, silicon oxide.

[0087] Subsequently, as shown in Figure 8, insulating layers 24 and sacrificial films 85 are alternately deposited on the first laminate 20A and the fourth insulator 44, and then an insulating layer 50 is formed on the uppermost sacrificial film 85 to form the second laminate 20B.

[0088] Subsequently, as shown in FIG. 9, a memory via MH is formed in the second stacked layer 20B shown in FIG. 8. The memory via MH extends from the upper surface of the second stacked layer 20B to the midway point of the semiconductor layer 41A. The memory via MH is fabricated by etching. For example, anisotropic etching is performed from the upper surface of the second stacked layer 20B to the semiconductor layer 21A. Anisotropic etching is, for example, reactive ion etching (RIE).

[0089] Subsequently, a memory volumetric layer 62, a semiconductor layer 61, and an insulating core 60 are sequentially formed within the memory hole MH. The memory hole MH is filled with the memory volumetric layer 62, the semiconductor layer 61, and the insulating core 60. This forms a columnar structure CL within the memory hole MH.

[0090] Subsequently, as shown in Figure 10, an insulating layer 51 is formed on the laminate containing the columnar bodies CL. Then, a first slit ST1 and a second slit ST2 are formed in the second laminate 20B, and a third slit SST, as shown in Figures 3A and 3B, is formed. The third slit SST is not shown in Figure 10, but as shown in Figures 3A and 3B, when viewed from the Z direction, it extends along the X direction and is formed as a dashed line. The first slit ST1 and the second slit ST2 are deep slits, both extending from the upper surface of the second laminate 20B to the midpoint of the sacrificial film 21Bb. The third slit SST is also a deep slit, extending from the upper surface of the second laminate 20B to the midpoint of the sacrificial film 21Bb. Therefore, a portion of the fourth insulator 44, which extends along the X direction and is located below the second laminate 20B, is removed by the third slit SST, leaving only the third slit SST between adjacent third slit SSTs in the X direction (see Figure 3A). The first slit ST1, the second slit ST2, and the third slit SST are formed by anisotropic etching. A stop film 86 is formed on the inner wall of each of the first slit ST1, the second slit ST2, and the third slit SST. The stop film 86 is, for example, silicon oxide.

[0091] Subsequently, as shown in Figure 11, the sacrificial film 21Bb is isotropically etched through the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 21Bb is removed by isotropic etching. The isotropic etching is performed using an etchant that can etch silicon nitrides faster than silicon oxides. Furthermore, a portion of the memory volume layer film 62 is also removed by further etching. The portion of the memory volume layer film 62 exposed by the removal of the sacrificial film 21Bb is removed. By removing a portion of the memory volume layer film 62, a portion of the semiconductor layer 61 is exposed. The etching of the memory volume layer film 62 is performed using an etchant that can etch silicon oxides faster than silicon nitrides. During the etching of the memory volume layer film 62, the intermediate films 21Ba, 21Bc, and the stop film 86 are also removed simultaneously with the memory volume layer film 62. A space Sp is formed between semiconductor layer 41A and semiconductor layer 41C.

[0092] Subsequently, as shown in Figure 12, the space Sp is filled with semiconductor material through the first slit ST1, the second slit ST2, and the third slit SST to form a semiconductor layer 21B. This allows the exposed semiconductor layer 61 to contact the semiconductor layer 21B. The material of the semiconductor layer 21B is the material described above. For example, the semiconductor layer 21B contains phosphorus.

[0093] Next, as shown in Figure 13, the sacrificial film 85 is replaced with conductive layers 25 (25A, 25B, 25C). First, the sacrificial film 85 is removed via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 85 is removed by isotropic etching. Isotropic etching uses an etchant that can etch silicon nitrides faster than silicon oxide and polycrystalline silicon. Subsequently, the portion after the removal of the sacrificial film 85 is filled with a conductive material to form conductive layers 25 (25A, 25B, 25C). This forms the laminate 20.

[0094] Subsequently, insulators are used to fill the first slit ST1, the second slit ST2 and the third slit SST, thereby forming the first insulator 41, the second insulator 42 and the third insulator 43 in the first slit ST1, the second slit ST2 and the third slit SST respectively.

[0095] Subsequently, as shown in Figures 14A-14C, the fifth slit ST5 and the sixth slit SHE are formed. Both the fifth slit ST5 and the sixth slit SHE extend from the upper surface of the laminate 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). The fifth slit ST5 is formed across the adjacent third insulators 43 (insulators 43a and 43b) in the X direction. Alternatively, the end of the fifth slit ST5 can be connected to the end of the third insulator 43. That is, both ends of the fifth slit ST5 in the X direction can also be connected to the ends of insulators 43a and 43b. The fifth slit ST5 and the sixth slit SHE are fabricated by etching. For example, anisotropic etching is performed from the upper surface of the laminate 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). Anisotropic etching, for example, is reactive ion etching (RIE).

[0096] Subsequently, insulators are used to fill the fifth slit ST5 and the sixth slit SHE, thereby forming the fifth insulator 45 and the sixth insulator 46 within the fifth slit ST5 and the sixth slit SHE, respectively. At this time, both the fifth insulator 45 and the sixth insulator 46 are formed in a manner that extends along the X direction.

[0097] By following the above steps, the semiconductor memory device 1 of the first embodiment is manufactured. Furthermore, the manufacturing steps shown here are only one example, and other steps can also be inserted between each step.

[0098] Next, the manufacturing method of the semiconductor memory device 1A according to the first variation will be described. Figures 15 to 20C are cross-sectional views or top views used to illustrate the manufacturing method of the semiconductor memory device 1A according to the first variation. Furthermore, Figure 20A is a top view showing the manufacturing process of the semiconductor memory device 1A. Figure 20B is a cross-sectional view along the Z-Z' plane in Figure 20A, and Figure 20C is a cross-sectional view along the W-W' plane in Figure 20A.

[0099] Furthermore, the manufacturing method of the semiconductor memory device 1A in the first variation is the same as that in the first embodiment up to the step of alternately depositing the insulating layer 24 and the sacrificial film 85 as shown in FIG8. Therefore, the following will describe the steps after the step of alternately depositing the insulating layer 24 and the sacrificial film 85, and the steps before this step will be omitted from the illustrations and descriptions.

[0100] After alternatingly depositing insulating layers 24 and sacrificial films 85 to form a second stacked body 20B, a memory hole MH is formed, as shown in FIG15. The memory hole MH extends from the upper surface of the second stacked body 20B shown in FIG8 to the midway point of the semiconductor layer 41A. At this time, in the first embodiment, the memory hole MH is not formed in the stacked body 20 located above the fourth insulator 44, but in the first variation, in order to form a plurality of second columnar bodies CLd, the memory hole MH is also formed at a position that overlaps with the fourth insulator 44 in at least a portion in the Z direction. The memory hole MH is made by etching. For example, anisotropic etching is performed from the upper surface of the second stacked body 20B to the semiconductor layer 21A. Anisotropic etching is, for example, reactive ion etching (RIE).

[0101] Subsequently, a memory volumetric layer film 62, a semiconductor layer 61, and an insulating core 60 are sequentially formed within the memory hole MH. The memory hole MH is filled with the memory volumetric layer film 62, the semiconductor layer 61, and the insulating core 60. At this time, the memory volumetric layer film 62, the semiconductor layer 61, and the insulating core 60 are also sequentially formed within the memory hole MH corresponding to the second columnar body CLd. In this way, columnar bodies CL and the second columnar body CLd are formed within the memory hole MH.

[0102] Subsequently, as shown in FIG16, an insulating layer 51 is formed on the second laminate 20B on which columnar bodies CL and CLd are formed. Then, similarly to the first embodiment, a first slit ST1 and a second slit ST2 are formed in the second laminate 20B, and a third slit SST as shown in FIG5A is formed. Although the third slit SST is not shown in FIG16, as shown in FIG5A, when viewed from the Z direction, it extends along the X direction and is formed as a dashed line. The first slit ST1 and the second slit ST2 are deep slits, and both extend from the upper surface of the laminate to the middle of the sacrificial film 21Bb. The third slit SST is also a deep slit, extending from the upper surface of the second laminate 20B to the middle of the sacrificial film 21Bb. Therefore, a portion of the fourth insulator 44, which extends along the X direction and is located beneath the second laminate 20B, is removed by the third slit SST, leaving only the third slit SST between adjacent third slit SSTs in the X direction (see Figure 5A). The first slit ST1, the second slit ST2, and the third slit SST are formed by anisotropic etching. A stop film 86 is formed on the inner wall of each of the first slit ST1, the second slit ST2, and the third slit SST. The stop film 86 is, for example, silicon oxide.

[0103] Subsequently, as shown in Figure 17, the sacrificial film 21Bb is isotropically etched through the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 21Bb is removed by isotropic etching. The isotropic etching is performed using an etchant that can etch silicon nitrides faster than silicon oxide. Furthermore, a portion of the memory volume layer film 62 is also removed by etching. The portion of the memory volume layer film 62 exposed by the removal of the sacrificial film 21Bb is removed. By removing a portion of the memory volume layer film 62, a portion of the semiconductor layer 61 is exposed. The etching of the memory volume layer film 62 is performed using an etchant that can etch silicon oxides faster than silicon nitride. During the etching of the memory volume layer film 62, the intermediate films 21Ba and 21Bc and the stop film 86 are also removed simultaneously with the memory volume layer film 62. A space Sp is formed between semiconductor layer 41A and semiconductor layer 41C.

[0104] Subsequently, as shown in Figure 18, semiconductor material is used to fill the space Sp through the first slit ST1, the second slit ST2, and the third slit SST to form a semiconductor layer 21B. This allows the exposed semiconductor layer 61 to contact the semiconductor layer 21B. The material of the semiconductor layer 21B is the material described above. For example, the semiconductor layer 21B contains phosphorus.

[0105] Subsequently, as shown in FIG19, the sacrificial film 85 is replaced with conductive layers 25 (25A, 25B, 25C). Specifically, similarly to the first embodiment, the sacrificial film 85 is first removed via the first slit ST1, the second slit ST2, and the third slit SST. The sacrificial film 85 is removed by isotropic etching. The isotropic etching uses an etchant that can etch silicon nitrides faster than silicon oxide and polycrystalline silicon. Afterwards, the portion after the removal of the sacrificial film 85 is filled with a conductive material to form conductive layers 25 (25A, 25B, 25C). Thereby, a laminate 20 is formed.

[0106] Subsequently, insulators are used to fill the first slit ST1, the second slit ST2 and the third slit SST, thereby forming the first insulator 41, the second insulator 42 and the third insulator 43 in the first slit ST1, the second slit ST2 and the third slit SST respectively.

[0107] Next, as shown in Figures 20A-20C, the fifth slit ST5 and the sixth slit SHE are formed. Both the fifth slit ST5 and the sixth slit SHE are formed, similarly to the first embodiment, extending from the upper surface of the laminate 20 to a depth corresponding to the third conductive layer 25C (drain-side selected gate line SGD). The fifth slit ST5 is formed across the adjacent third insulators 43 (insulators 43a and 43b) in the X direction. Alternatively, the end of the fifth slit ST5 can be formed to connect with the end of the third insulator 43. That is, both ends of the fifth slit ST5 in the X direction can also be formed to connect with the ends of insulators 43a and 43b. The fifth slit ST5 and the sixth slit SHE are fabricated by etching in the same manner as in the first embodiment. By forming the fifth slit ST5, a portion of the second columnar body CLd is removed.

[0108] Subsequently, insulators are used to fill the fifth slit ST5 and the sixth slit SHE, thereby forming the fifth insulator 45 and the sixth insulator 46 within the fifth slit ST5 and the sixth slit SHE, respectively. At this time, both the fifth insulator 45 and the sixth insulator 46 are formed in a manner that extends along the X direction.

[0109] By following the above steps, the semiconductor memory device 1A of the first variation is manufactured. Furthermore, the manufacturing steps shown here are only one example, and other steps can also be inserted between each step.

[0110] Several embodiments have been described above, but the embodiments are not limited to the examples described above. For example, the memory volume layer film may also be a ferroelectric film contained in a FeFET (Ferroelectric Field Effect Transistor) memory that stores data according to the polarization direction. The ferroelectric film is, for example, formed of hafnium oxide.

[0111] According to at least one embodiment described above, by configuring the third insulator 43 (insulators 43a, 43b) in a dotted line shape, the strength against finger twisting can be improved. Furthermore, a fourth insulator 44 and a fifth insulator 45 are provided between adjacent third insulators 43 (insulators 43a, 43b) in the X direction, such that the second conductive layer 25B (source-side select gate line SGS) and the third conductive layer 25C (drain-side select gate line SGD) are separated. With these, during data writing and reading, one finger in the block can be set to a selected state, and the other finger separated by the third insulator 43 can be set to a non-selected state. Furthermore, the string within the non-selected fingers (i.e., the unread fingers) becomes floating. Therefore, when a voltage is applied to the first conductive layer 25A (WL), the string also rises in voltage, thereby maintaining the potential difference between the string and the first conductive layer 25A (WL). As a result, the influence of the read voltage of the non-selected string can be avoided, thus improving read disturbance.

[0112] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention described in the claims and their equivalents.

[0113] [Related Applications]

[0114] This application enjoys priority based on Japanese Patent Application No. 2021-151000 (filed on September 16, 2021). This application incorporates the entire contents of the basic application by reference to that basic application.

[0115] 1, 1A: Semiconductor memory device 2: Memory controller 10: Memory Cell Array 11: Column Decoder 12: Sensing Amplifier 13: Sequencer 20: Laminated body 20A: 1st laminated body 20B: Second layer 21: Conductive layer 21A, 21B, 21C: Semiconductor layers 21Ba: Intermediate membrane 21Bb: First sacrificial membrane 21Bc: Intermediate membrane 22: Insulation layer 24: Insulation layer 25: Conductive layer 25A: First conductive layer (WL) 25a: Barrier insulating film 25B: Second conductive layer (SGS) 25b: Barrier film 25C: Third conductive layer (SGD) 30:Substrate 30A: Component Separation Area 41: First Insulator 42: Second Insulator 43: The third insulator 43a: Insulator 43b: Insulator 44: The 4th Insulator 45: The 5th Insulator 46: The 6th Insulator 50, 51: Covering insulation layer 60: Insulating core 61: Semiconductor layer 62: Memory Volume Layer Membrane 63: Tunnel insulation film 64: Charge storage membrane 65: Cover with insulating film 85: Sacrificial membrane 86: Barrier membrane ADD: Address Information BL: Bitline BL0~BLm: Bit lines BLK: Block C1, C2: Through holes CL: First column CLd: 2nd columnar body CMD command D0, D1: Wiring layers DAT: Write Data E1: Insulation layer MH: Memory Hole MT0~MTn: Memory Cell Electron MT: Memory Cell Electron NS: NAND string PE: Circuit layer S: Staircase section S1: First-choice transistor S2: Second-choice transistor SGS: Select gate line (source side) SGD: Select gate line (drain side) SGD0~SGD3: Select gate line SHE: The 6th Slit SL: Source Line SLT: Slit SST: Third Slit STR: string ST1: First Slit ST2: Second slit ST4: Fourth slit ST5: Fifth slit STR0~STR3: strings Tr: transistor WL: Character line WL0~WLn: Character line

Claims

1. A method for manufacturing a semiconductor memory device, comprising the following steps: depositing a plurality of first sacrificial films and a plurality of first insulating layers alternately in a first direction to form a first stacked body; forming a first insulator, the first insulating system extending through the first stacked body and extending in a second direction intersecting the first direction; depositing a plurality of second sacrificial films and a plurality of second insulating layers alternately in the first direction above the first stacked body to form a second stacked body; forming a plurality of first columnar bodies, the first columnar system including a first semiconductor layer extending through the second stacked body; forming a first slit and a second slit extending in the second direction, and a third slit extending in a dashed line shape in the second direction, through the second stacked body; removing the first sacrificial film and the second sacrificial film via the first slit, the second slit, and the third slit. The portions of the first and second sacrificial films are removed and filled with metallic material to form a plurality of first conductive layers; insulating material is filled into the first, second, and third slits to form a second, third, and fourth insulator; and a fifth insulator is formed, wherein the fifth insulating system extends from the upper surface of the third insulator to the depth of at least the uppermost layer of the plurality of first conductive layers, and extends in the second direction in a manner that spans between adjacent fourth insulators in the second direction; wherein at least five of the plurality of first columnar systems are arranged alternately in a third direction perpendicular to the first and second directions between the second and fourth insulators; and at least five of the plurality of first columnar systems are arranged alternately in the third direction between the third and fourth insulators.

2. The method for manufacturing a semiconductor memory device as claimed in claim 1, wherein the width of the fifth insulator along the third direction is narrower than the width of the fourth insulator.

3. A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein, when viewed from above, the first insulator and the fifth insulator at least partially overlap.

4. A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein a sixth insulator is formed, which is disposed between the second insulator and the third insulator, penetrates to the depth of at least the uppermost layer of the plurality of first conductive layers, and extends in the second direction.

5. A method for manufacturing a semiconductor memory device, comprising the following steps: depositing a plurality of first sacrificial films and a plurality of first insulating layers alternately in a first direction to form a first stacked body; forming a first insulator, the first insulating system extending through the first stacked body and extending in a second direction intersecting the first direction; depositing a plurality of second sacrificial films and a plurality of second insulating layers alternately in the first direction above the first stacked body to form a second stacked body; forming a plurality of first columnar bodies, the first columnar bodies comprising a first semiconductor layer extending through the second stacked body; forming a first slit and a second slit extending in the second direction, and a third slit extending in a dashed line shape in the second direction, through the second stacked body; removing the first sacrificial film and the second sacrificial film via the first slit, the second slit, and the third slit. The portions of the first and second sacrificial films removed are filled with a metallic material to form a plurality of first conductive layers; insulating material is filled into the first, second, and third slits to form a second, third, and fourth insulator. A fifth insulator is formed, the fifth insulating system extending from the upper surface of the third insulator to a depth of at least the uppermost layer of the plurality of first conductive layers, and extending in the second direction across the spaces between adjacent fourth insulators in the second direction; and a sixth insulator is formed, disposed between the second and third insulators, extending to a depth of at least the uppermost layer of the plurality of first conductive layers, and extending in the second direction; wherein at least five of the plurality of first columnar systems are arranged alternately in a third direction perpendicular to both the first and second directions between the second and fourth insulators; at least five of the plurality of first columnar systems are arranged alternately in the third direction between the third and fourth insulators; and the width of the fifth insulator along the third direction is narrower than the width of the fourth insulator. The width of the fifth insulator along the third direction is narrower than the width of the first insulator. When viewed from above, the first insulator and the fifth insulator at least partially overlap.

6. A method for manufacturing a semiconductor memory device as claimed in any one of claims 1 to 5, wherein the plurality of first columnar bodies sequentially comprise, from the inside, a first insulating core, the first semiconductor layer, and a first memory volume layer film.

7. A method for manufacturing a semiconductor memory device according to any one of claims 1 to 5, wherein, when forming the plurality of first pillars, a plurality of second pillars are formed at a position overlapping the fifth insulator in the first direction.

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