Semiconductor device

Abstract

A semiconductor device with good electrical properties is provided. The semiconductor device includes: an oxide semiconductor; a first insulator in contact with the oxide semiconductor; and a second insulator in contact with the first insulator, wherein the first insulator contains excess oxygen, the second insulator is configured to trap or fix hydrogen, hydrogen in the oxide semiconductor is bonded to the excess oxygen, the hydrogen bonded to the excess oxygen is trapped or fixed by the second insulator via the first insulator, and the excess oxygen bonded to the hydrogen remains as excess oxygen in the first insulator.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Furthermore, another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also embodiments of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting equipment, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Prior Technology

[0004] In recent years, semiconductor devices have been developed, mainly using LSI, CPU, and memory. A CPU is an assembly of semiconductor elements that include semiconductor integrated circuits (including at least transistors and memory) separated from a semiconductor wafer and formed with electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards such as printed circuit boards and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0007] Furthermore, it is known that the leakage current of oxide semiconductor transistors is extremely low in the non-conducting state. For example, low-power CPUs that utilize the low leakage current characteristic of oxide semiconductor transistors have been disclosed (see Patent Document 1). In addition, for example, storage devices that utilize the low leakage current characteristic of oxide semiconductor transistors to achieve long-term retention of stored content have been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, the demand for high-density integrated circuits has increased. In addition, there is a need to improve the productivity of semiconductor devices that include integrated circuits.

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the Invention

[0010] One objective of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with normally-off electrical characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high reliability. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Additionally, one objective of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device capable of miniaturization or hyper-integration. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0011] One objective of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for an extended period. Another objective of one embodiment of the present invention is to provide a semiconductor device with a fast data write speed. Another objective of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. Another objective of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. Finally, another objective of one embodiment of the present invention is to provide a novel semiconductor device.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above are obvious from the description in the specification, drawings, claims, etc., and may be derived from said description.

[0013] One embodiment of the present invention is a semiconductor device comprising: an oxide semiconductor; a first insulator in contact with the oxide semiconductor; and a second insulator in contact with the first insulator, wherein the first insulator contains excess oxygen, the second insulator is configured to trap or fix hydrogen, hydrogen in the oxide semiconductor is bonded to the excess oxygen, the hydrogen bonded to the excess oxygen is trapped or fixed in the second insulator via the first insulator, and the excess oxygen bonded to the hydrogen remains as excess oxygen in the first insulator.

[0014] One embodiment of the present invention is a semiconductor device comprising: an oxide semiconductor; a first insulator in contact with the oxide semiconductor; a second insulator in contact with the first insulator; and a third insulator in contact with the second insulator, wherein the first insulator contains excess oxygen, the second insulator is configured to trap or fix hydrogen, the third insulator is a barrier to hydrogen, hydrogen bonded to the excess oxygen is trapped or fixed in the second insulator via the first insulator, and the excess oxygen bonded to hydrogen remains as excess oxygen in the first insulator.

[0015] The aforementioned third insulator contains silicon nitride.

[0016] The second insulator mentioned above contains aluminum oxide.

[0017] The above-mentioned alumina was formed by sputtering.

[0018] The aforementioned oxide semiconductor is an In-Ga-Zn oxide.

[0019] One embodiment of the present invention is a memory device, comprising: the semiconductor device described above; and a capacitor device.

[0020] According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with normally-off electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Additionally, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or hyper-integration can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0021] Furthermore, according to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device with fast data write speed can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high design flexibility can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of suppressing power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects to be achieved. Effects other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be derived from said description. Simple Explanation of the Diagram

[0023] In the diagram: [Figure 1] is a cross-sectional view of the stacked structure. [Figure 2A] and [Figure 2B] are diagrams illustrating the diffusion model in an insulator. [Figure 3A] and [Figure 3B] are diagrams illustrating the diffusion model in an insulator. [Figure 4A] is a top view of the semiconductor device, and [Figures 4B] to [Figure 4D] are cross-sectional views of the semiconductor device. [Figure 5A] is a top view of the semiconductor device, and [Figures 5B] to [Figure 5D] are cross-sectional views of the semiconductor device. [Figure 6A] is a top view of the semiconductor device, and [Figures 6B] to [Figure 6D] are cross-sectional views of the semiconductor device. [Figure 7A] is a top view showing a method for manufacturing a semiconductor device, and [Figures 7B] to [Figure 7D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 8A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 8B] to [Fig. 8D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 9A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 9B] to [Fig. 9D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 10A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 10B] to [Fig. 10D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 11A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 11B] to [Fig. 11D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 12A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 12B] to [Fig. 12D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 13A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 13B] to [Fig. 13D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 14A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 14B] to [Fig. 14D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 15A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 15B] to [Fig. 15D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 16A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 16B] to [Fig. 16D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 17A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 17B] to [Fig. 17D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 18A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 18B] to [Fig. 18D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 19A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 19B] to [Fig. 19D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 20A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 20B] to [Fig. 20D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 21A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 21B] to [Fig. 21D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 22A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 22B] to [Fig. 22D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Fig. 23A] is a top view showing a method for manufacturing a semiconductor device, and [Fig. 23B] to [Fig. 23D] are cross-sectional views showing a method for manufacturing a semiconductor device. [Figure 24A] and [Figure 24B] are cross-sectional views of a semiconductor device. [Figure 25] is a cross-sectional view of a semiconductor device. [Figure 26A] is a top view of the semiconductor device, and [Figure 26B] is a cross-sectional view of the semiconductor device. [Figure 27A] and [Figure 27B] are cross-sectional views of a semiconductor device. [Figure 28] is a cross-sectional view of a semiconductor device. [Figure 29] is a cross-sectional view of a semiconductor device. [Figure 30A] and [Figure 30B] are cross-sectional views of a semiconductor device. [Figure 31A] is a diagram illustrating the classification of IGZO crystal structures, [Figure 31B] is a diagram illustrating the XRD pattern of quartz glass, and [Figure 31C] is a diagram illustrating the XRD pattern of crystalline IGZO. [Figure 32] is a cross-sectional view showing the structure of the storage device. [Figure 33] is a cross-sectional view showing the structure of the storage device. [Figure 34A] and [Figure 34B] are cross-sectional views showing the structure of the storage device. [Figure 35] is a cross-sectional view showing the structure of the storage device. [Figure 36] is a diagram showing the hierarchy of various storage devices. [Figure 37A] and [Figure 37B] are block diagrams and perspective views showing examples of the structure of a storage device. Figures 38A to 38H are circuit diagrams illustrating structural examples of storage devices. [Figure 39A] and [Figure 39B] are circuit diagrams illustrating structural examples of storage devices. [Figure 40A] and [Figure 40B] are schematic diagrams of semiconductor devices. Figures 41A to 41E are schematic diagrams of the storage device. Figures 42A to 42C are block diagrams illustrating structural examples of semiconductor devices. [Figure 43A] is a block diagram showing a structural example of a semiconductor device, [Figure 43B] is a circuit diagram showing a structural example of a semiconductor device, and [Figure 43C] is a timing diagram showing an operational example of a semiconductor device. [Figure 44] is a block diagram showing a structural example of a semiconductor device. [Figure 45A] is a circuit diagram showing a structural example of a semiconductor device, and [Figure 45B] is a timing diagram showing an operational example of a semiconductor device. [Figure 46] is a block diagram showing a semiconductor device. [Figure 47] is a circuit diagram showing a semiconductor device. [Figure 48A] and [Figure 48B] are schematic diagrams showing examples of electronic components. Figures 49A, 49B, 49C, 49D, 49E1, 49E2 and 49F are diagrams illustrating electronic devices. [Figure 50A] is a schematic diagram of the sample, and [Figure 50B] is a graph showing the TDS analysis results. [Figure 51] is a schematic diagram of the sample. [Figure 52A] and [Figure 52B] are figures showing the results of the SIMS analysis. [Figure 53A] and [Figure 53B] are graphs of the SIMS analysis results. [Figure 54] is a graph showing the results of the SIMS analysis. Figures 55A to 55C are graphs illustrating the integral values ​​of hydrogen concentration for each structure. [Figure 56] is a schematic diagram of the sample. [Figure 57A] and [Figure 57B] are graphs showing the SIMS analysis results of the samples from the embodiment. [Figure 58A] and [Figure 58B] are graphs showing the SIMS analysis results of the samples from the embodiment. Figures 59A to 59C are cross-sectional views of the sample. Implementation

[0024] The embodiments will now be described with reference to the drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0025] In the drawings, for clarity, sizes, layer thicknesses, or areas are sometimes exaggerated. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples; therefore, the invention is not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or photoresist masks are sometimes unintentionally etched due to etching or other processes, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, in the drawings, the same element symbols are sometimes used across different drawings to represent the same parts or parts with the same function, omitting redundant descriptions. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without specifically adding element symbols.

[0026] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some components are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0027] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the process sequence or stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify an embodiment of the present invention.

[0028] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration and to illustrate the positional relationships of components with reference to diagrams. Furthermore, the positional relationships of components may be appropriately changed depending on the orientation of each component being described. Therefore, the use of terms not limited to those described in the specification may be modified as appropriate.

[0029] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are also disclosed in the drawings or text, not limited to those specified in the drawings or text.

[0030] Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0032] In this specification, depending on the transistor's structure, the actual channel width (hereinafter also referred to as "effective channel width") in the region where the channel is formed (channel forming region) sometimes differs from the channel width shown in the transistor's top view (hereinafter also referred to as "apparent channel width"). For example, when the gate covers the side of the semiconductor, sometimes the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate covers the side of the semiconductor, sometimes the proportion of the channel forming region formed on the side of the semiconductor is increased. In this case, the effective channel width is greater than the apparent channel width.

[0033] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width based on design values ​​requires an assumption: that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately determine the effective channel width.

[0034] In this specification, when simply described as "channel width," it sometimes refers to the visual channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, and visual channel width can be determined by analyzing cross-sectional TEM images, etc.

[0035] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration less than 0.1 atomic% can be considered impurities. Sometimes, the presence of impurities can cause the semiconductor's DOS (Density of States) to increase or its crystallinity to decrease. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water sometimes also acts as an impurity. Furthermore, when the semiconductor is silicon, impurities that alter its properties include, for example, oxygen, and Group 1, Group 2, Group 13, and Group 15 elements other than hydrogen.

[0036] Note that in this specification, silicon oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Furthermore, silicon oxynitride refers to a substance with a nitrogen content greater than its oxygen content.

[0037] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0038] In this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°. Therefore, it also includes a state where the angle is between -5° and 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is between -30° and 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is between 80° and 100°. Therefore, it also includes a state where the angle is between 85° and 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is between 60° and 120°.

[0039] Note that in this specification, a barrier membrane refers to a membrane that has the function of inhibiting the permeation of impurities such as water and hydrogen, as well as oxygen. When the barrier membrane is conductive, it is sometimes called a conductive barrier membrane.

[0040] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS FET or OS transistor can be referred to as a transistor that contains oxides or oxide semiconductors.

[0041] Note that in this specification, "normally off" means that when no gate potential is supplied or the gate is grounded, the current flowing through each channel width 1μm of the transistor is less than 1×10-20A at room temperature, less than 1×10-18A at 85°C, or less than 1×10-16A at 125°C.

[0042] Implementation Method 1 Below, an example of a semiconductor device including a transistor 200 according to an embodiment of the present invention and a method thereof are described.

[0043] <Example 1 of semiconductor device structure> Figures 4A, 4B, 4C and 4D are top views and cross-sectional views of a transistor 200 and the vicinity of the transistor 200 according to an embodiment of the present invention.

[0044] Figure 4A is a top view of the semiconductor device including transistor 200. Furthermore, Figures 4B and 4C are cross-sectional views of the semiconductor device. Here, Figure 4B is a cross-sectional view of the portion indicated by dashed lines A1-A2 in Figure 4A, which is also a cross-sectional view along the channel length direction of transistor 200. Figure 4C is a cross-sectional view of the portion indicated by dashed lines A3-A4 in Figure 4A, which is also a cross-sectional view along the channel width direction of transistor 200. Figure 4D is a cross-sectional view of the portion indicated by dashed lines A5-A6 in Figure 4A. Note that in the top view of Figure 4A, some components are omitted for clarity.

[0045] Here, in transistor 200, it is preferred to use a metal oxide (hereinafter also referred to as oxide semiconductor) that will be used as an oxide semiconductor for the region including the channel forming region (hereinafter also referred to as channel forming region).

[0046] Preferred oxide semiconductors are metal oxides such as In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In addition, In-Ga oxides and In-Zn oxides can also be used as oxide semiconductors.

[0047] Because the leakage current of the transistor 200, which uses oxide semiconductors in the channel formation region, is extremely small in the non-conducting state, a low-power semiconductor device can be provided. Furthermore, since oxide semiconductors can be formed using methods such as sputtering, they can be used to construct transistors 200 for highly integrated semiconductor devices.

[0048] On the other hand, in transistors using oxide semiconductors, their electrical characteristics vary due to impurities and oxygen vacancies in the oxide semiconductor. Therefore, such transistors tend to have always-on characteristics (meaning that the channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0049] Therefore, it is preferable to use an oxide semiconductor in which the impurity concentration and defect state density are reduced. Note that in this specification, the case of low impurity concentration and low defect state density is referred to as high purity or substantially high purity.

[0050] Therefore, it is preferable to minimize the impurity concentration in oxide semiconductors. Other examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0051] In particular, hydrogen, as an impurity contained in oxide semiconductors, sometimes forms oxygen vacancies (also known as VO:oxygen vacancy) in the oxide semiconductor. Furthermore, defects in oxygen vacancies (sometimes referred to below as VOH) may generate electrons that can become carriers. Moreover, a portion of the hydrogen may react with oxygen bonded to a metal atom to generate electrons that can become carriers.

[0052] Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0053] Therefore, as an oxide semiconductor used in transistors, it is preferable to use an oxide semiconductor with high purity by reducing impurities such as hydrogen and oxygen vacancies.

[0054] Therefore, in order to suppress impurities introduced from the outside, it is preferable to use a material that suppresses the diffusion of impurities (hereinafter also referred to as a material that blocks impurities) to seal the transistor 200.

[0055] Note that in this specification, barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the ability to capture and fix the corresponding substance (also known as gettering).

[0056] For example, materials that can inhibit the diffusion of hydrogen and oxygen include alumina, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride. In particular, silicon nitride or silicon oxynitride has high hydrogen barrier properties, so it is preferred as a sealing substrate.

[0057] For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide are materials that can capture and fix hydrogen.

[0058] Here, the structure of the sealed transistor 200 can be provided as a single layer or a stacked structure of two or more layers. In particular, it is preferred to provide the structure of the sealed transistor 200 as a stacked structure, and more preferably as a nested structure.

[0059] Specifically, the structure of the sealed transistor 200 will be described in the case where it has a two-layer structure. The structure of the sealed transistor 200 includes a first structure adjacent to the transistor 200 and a second structure disposed outside the first structure. That is, the transistor 200 and the second structure are disposed with the first structure in between.

[0060] In the above structure, the first structure is preferably made of a material that has the function of capturing and fixing hydrogen, while the second structure is preferably made of a material that has the function of inhibiting the diffusion of hydrogen and oxygen.

[0061] When a material with the function of capturing and fixing hydrogen is used on the side adjacent to the transistor 200, the hydrogen in the transistor 200 or the hydrogen in the interlayer film disposed between the first structure and the transistor 200 is captured and fixed by the first structure, thereby reducing the hydrogen concentration in the transistor 200.

[0062] Specifically, alumina is preferred. In particular, compared to highly crystalline alumina, sometimes less crystalline or amorphous alumina captures and fixes a larger amount of hydrogen. Less crystalline or amorphous alumina has the property of diffusing hydrogen upon heat treatment. That is, when less crystalline or amorphous alumina is placed between regions of high and low hydrogen concentration and then heat-treated, hydrogen from the region of low hydrogen concentration diffuses through the alumina to the region of high hydrogen concentration.

[0063] Therefore, when using alumina with low crystallinity or amorphous properties as the first structure, it is preferable to perform a heat treatment after sealing the transistor 200 using the first structure. Through this heat treatment, hydrogen in the transistor 200 can diffuse to the outside through the interlayer film and the alumina, thereby reducing the hydrogen concentration in the transistor 200 and the alumina. In other words, the absolute amount of hydrogen present in the semiconductor device can be reduced.

[0064] On the other hand, the second structure seals the transistor 200 through the first structure. Therefore, the second structure can suppress the diffusion of hydrogen from the outside of the second structure to its interior (on the transistor 200 side). In other words, the first structure can efficiently capture and immobilize hydrogen present in the structure inside the second structure.

[0065] Specifically, the first structure can be a metal oxide such as aluminum oxide, while the second structure can be a nitride such as silicon nitride. More specifically, it is preferable to place an aluminum oxide film between the transistor 200 and the silicon nitride film.

[0066] Furthermore, as a material used in structures, the hydrogen concentration in the membrane can be reduced by appropriately setting the film formation conditions.

[0067] Generally, membranes formed by CVD have higher coverage than those formed by sputtering. On the other hand, the compound gases used in CVD often contain hydrogen, therefore membranes formed by CVD have a higher hydrogen content than those formed by sputtering.

[0068] Therefore, for example, the film adjacent to the transistor 200 is preferably a film with a reduced hydrogen concentration (specifically, a film formed by sputtering). On the other hand, when a film with high coverage and a high hydrogen concentration (specifically, a film formed by CVD) is used as a film to suppress the diffusion of impurities, it is preferable to place a film with the function of trapping and fixing hydrogen and with a reduced hydrogen concentration between the transistor 200 and the film with a high hydrogen concentration and high coverage.

[0069] In other words, it is preferable to use a membrane with a lower hydrogen concentration as the membrane disposed adjacent to the transistor 200. On the other hand, it is preferable to dispose of the membrane with a higher hydrogen concentration separately from the transistor 200.

[0070] Specifically, when sealing the transistor 200 with a silicon nitride film formed by CVD, it is preferable to place an alumina film formed by sputtering between the transistor 200 and the silicon nitride film formed by CVD. More preferably, it is preferable to place a silicon nitride film formed by sputtering between the silicon nitride film formed by CVD and the alumina film formed by sputtering.

[0071] In addition, when using CVD to form films, the concentration of hydrogen contained in the formed film can be reduced by using a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content.

[0072] The specific structure of the sealed transistor 200 will now be described with reference to Figures 4A to 4D.

[0073] A semiconductor device according to one embodiment of the present invention includes an insulator 211 on a substrate (not shown), an insulator 212 on the insulator 211, an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 287 covering the side of the insulator 280, an insulator 283 covering the insulator 282 and the insulator 287, an insulator 284 on the insulator 283, and an insulator 274 disposed in contact with the insulator 284.

[0074] In addition, insulators 211, 212, 214, 280, 282, 287, 283, 284 and 274 are used as interlayer membranes.

[0075] Here, when a structure including an excess oxygen region is provided near an oxide semiconductor, the oxygen vacancy can be filled by diffusing the excess oxygen in the structure including the excess oxygen region to the oxygen vacancy formed in the oxide semiconductor.

[0076] Note that in this specification, oxygen removed by heating is sometimes referred to as excess oxygen. Additionally, oxygen exceeding the stoichiometric composition is sometimes referred to as excess oxygen. Furthermore, the region containing oxygen exceeding the stoichiometric composition is referred to as the excess oxygen region.

[0077] Here, excess oxygen in the insulator may affect the diffusion of hydrogen in the oxide semiconductor in contact with the insulator. This is clearly illustrated with reference to FIG1. ​​The structure shown in FIG1 includes an oxide semiconductor 10 containing hydrogen, an insulator 12 containing excess oxygen in contact with the oxide semiconductor 10, and a metal oxide 14 in contact with the insulator 12. Note that the metal atoms constituting the metal oxide 14 are referred to as metal atoms X.

[0078] Hydrogen present in the oxide semiconductor 10 diffuses to other structures via the insulator 12 in contact with the oxide semiconductor 10. Excess oxygen in the insulator 12 reacts with hydrogen in the oxide semiconductor 10 to form OH bonds, and this hydrogen diffuses within the insulator 12. Upon reaching the metal oxide 14, the hydrogen atoms with OH bonds react with oxygen atoms of metal atom X bonded to the metal oxide 14, and are captured or fixed within the metal oxide 14. On the other hand, the oxygen atoms of the excess oxygen with OH bonds are estimated to remain as excess oxygen in the insulator 12. In other words, the excess oxygen in the insulator 12 is highly likely to play a bridging role in this hydrogen diffusion.

[0079] In Figures 4A to 4D, the oxide semiconductor 10 corresponds to oxide 230c, and the insulator 12 corresponds to insulator 280. Therefore, the insulator 280 in contact with oxide 230c is preferably deoxygenated by heating.

[0080] Specifically, as an insulator including regions with excess oxygen, it is preferable to use an oxide that allows partial oxygen removal through heating. An oxide that allows partial oxygen removal through heating refers to an oxide in which the amount of oxygen molecules removed in TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10¹⁸ molecules / cm³ or more, preferably 1.0 × 10¹⁹ molecules / cm³ or more, further preferably 2.0 × 10¹⁹ molecules / cm³ or more, or 3.0 × 10²⁰ molecules / cm³ or more. Furthermore, the surface temperature of the membrane during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0081] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0082] Therefore, the insulator 280 is preferably composed of silicon oxide, silicon oxynitride, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with pores.

[0083] In particular, silicon oxide and silicon oxynitride are preferred as insulators 280 because of their thermal stability. Furthermore, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released by heating, which is also preferable. Additionally, insulator 280 can have a structure in which the above-mentioned materials are stacked; for example, a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed by CVD can be used. Furthermore, silicon nitride can also be stacked on top of it.

[0084] When an excess oxygen region is provided in the insulator 280, oxygen (containing at least one of oxygen free radicals, oxygen atoms, and oxygen ions) is introduced into the insulator 280 to form a region containing excess oxygen.

[0085] Specifically, as an example of oxygen introduction treatment, there is a method of stacking metal oxides on insulator 280 using a sputtering apparatus. For example, by forming insulator 282 in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into insulator 280 at the same time as forming insulator 282.

[0086] In particular, silicon oxynitride is preferably used as insulator 280, while aluminum oxide is preferably used as insulator 282. By sputtering an aluminum oxide film onto the silicon oxynitride film, excess oxygen regions can be formed in the formed silicon oxynitride.

[0087] In addition, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulator 280.

[0088] Here, based on quantum molecular dynamics calculations, we specifically investigate the diffusion behavior of excess oxygen and hydrogen, as well as the diffusion behavior of hydroxyl groups in the insulator 280 when silicon oxide is used as the insulator 280 in contact with oxide 230.

[0089] <Computational Models and Methods> First, calculations were performed using a model of the SiO2 structure in the amorphous state as a baseline (a-SiO2 structure model), a model that adds one OH group to the model that serves as a baseline, and a model that adds one H atom and one O atom to the model that serves as a baseline.

[0090] Specifically, the benchmark crystallization model used is the a-SiO2 structure model 20 with multiple interstitial regions shown in Figure 2A. Note that model 20 consists of 24 atoms.

[0091] Model 24, shown in Figure 2B, is a model in which H atoms, equivalent to impurities, and O atoms, equivalent to excess oxygen, are present in model 20. One O atom is placed in interstitial region 21 of model 20, and one H atom is placed in interstitial region 22. Model 26, shown in Figure 3A, is a model in which OH groups, equivalent to impurities, are present in model 20. One OH group is placed in interstitial region 21 of model 20.

[0092] The specific calculations are shown below. Furthermore, the first-principles electronic state calculation program VASP (Vienna ab initio simulation package) is used in the atomic mitigation calculations. The calculation conditions are shown below.

[0093] [Table 1] Calculation program VASP Basis functions plane wave generic functions GGA-PBE Quasi-positional energy PAW Cut-off energy 500eV Number of electrons neutral k-point grid 1×1×1

[0094] In addition, given the process temperature, calculations were performed over a period of 150 ps at a temperature of 700 K (up to 400 °C).

[0095] <Diffusion Action> In model 24 shown in Figure 2B, the O atoms, which correspond to excess oxygen, bond with the H atoms, which correspond to impurities, to form hydroxyl groups (OH groups) shortly after the calculation begins, and then begin to diffuse within the amorphous SiO2 structure. In other words, the generated OH groups are observed to diffuse within the amorphous SiO2 structure and move between multiple interstitial regions.

[0096] In model 26 shown in Figure 3A, the behavior of OH groups diffusing and moving between multiple interstitial regions in the amorphous SiO2 structure was observed.

[0097] Here, Figure 3B shows a schematic diagram of the diffusion behavior between 0 and 50 ps. Note that Figure 3B shows the trajectories of the central coordinates of the O and H atoms of the OH group. Furthermore, the amorphous SiO2 structure is consistently represented as the initial structure. As shown in Figure 3B, it can be confirmed that the OH group diffuses into multiple interstitial regions (the regions surrounded by dashed lines in the diagram).

[0098] As described above, hydrogen present in the oxide semiconductor 10 diffuses to other structures through the insulator 12 in contact with the oxide semiconductor 10. It can be confirmed that excess oxygen in the insulator 12 reacts with hydrogen in the oxide semiconductor 10 to form OH bonds, and this hydrogen diffuses in the insulator 12.

[0099] Furthermore, by using materials that block impurities in insulators 211, 212, 214, 282, 287, 283, and 284, the oxide semiconductor included in transistor 200 can be maintained in a high-purity state.

[0100] Specifically, insulators 214, 287, and 282 have a structure that seals transistor 200 and insulator 280 (hereinafter also referred to as a sealing structure). For example, as shown in Figures 4A to 4D, insulator 214 is disposed below transistor 200, and insulator 282 is disposed above transistor 200. Furthermore, insulator 287 is disposed as a sidewall on the side of transistor 200. Moreover, the lower end of the sidewall-shaped insulator 287 contacts the end of insulator 214, and the upper end of insulator 287 contacts the end of insulator 282.

[0101] Here, insulator 287 and insulator 214 are preferably in firm contact. Therefore, in order to provide an area in which insulator 214 and insulator 287 are in firm contact, insulator 287 is preferably provided in such a way that it contacts the side of insulator 212 located below insulator 214.

[0102] Therefore, the transistor 200 is surrounded by insulators 214, 287 and 282.

[0103] Here, insulators 214, 287, and 282 are made of the same material. Furthermore, insulators 214, 287, and 282 are preferably formed under the same conditions. By bringing insulators 214, 287, and 282, which have the same membrane properties, into contact with each other, a highly sealing structure can be achieved.

[0104] Furthermore, insulators 214, 287, and 282 are preferably made of materials that have the function of capturing and fixing hydrogen. Specifically, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide can be used.

[0105] Insulators 214, 287, and 282, forming a sealed structure, are disposed in contact with transistor 200 or insulator 280. Therefore, by capturing and fixing hydrogen mixed in transistor 200 or insulator 280, the hydrogen concentration of the oxide semiconductor included in transistor 200 can be reduced.

[0106] Furthermore, the insulators 214, 287, and 282, which form the structure of the sealed transistor 200, are surrounded by a sealing structure consisting of insulators 211, 212, and 283.

[0107] For example, as shown in Figures 4A to 4D, insulators 211 and 212 are disposed below insulator 214, and insulator 283 is disposed covering insulators 287 and 282. Furthermore, by bringing insulator 211 into contact with insulator 283 outside the structure of the sealed transistor 200 formed by insulators 214, 287, and 282, a second sealing structure is formed.

[0108] Here, insulators 211, 212, and 283 are preferably made of materials that inhibit the diffusion of hydrogen and oxygen. In particular, since silicon nitride or silicon oxynitride has high hydrogen barrier properties, it is preferred to use it as a sealing substrate.

[0109] Furthermore, it is preferable to provide an insulator 284 with high coverage above the insulator 283 covering the transistor 200. Additionally, it is preferable that the insulator 284 is made of the same material as the insulators 211, 212, and 283.

[0110] For example, when insulators 212 and 283 are formed by sputtering, a sealed structure composed of a membrane with a low hydrogen concentration can be achieved.

[0111] On the other hand, the film formed by sputtering has low coverage. Therefore, by forming insulator 211 and insulator 284 using a CVD method or the like with high coverage, the sealing performance can be further improved.

[0112] Therefore, the hydrogen concentration of insulators 212 and 283 is preferably lower than that of insulators 211 and 284.

[0113] Furthermore, insulators 211, 212, 214, 282, 287, 283, and 284 are preferably made of materials that are oxygen-resistant. Because the aforementioned sealing structure is oxygen-resistant, it can suppress the outward diffusion of excess oxygen from insulator 280 and efficiently supply oxygen to transistor 200.

[0114] Furthermore, in one embodiment of the present invention, the semiconductor device includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to a transistor 200 and used as a plug. An insulator 241 (insulator 241a and insulator 241b) is disposed in contact with the side of the conductor 240 used as a plug. Conductors 246 (conductors 246a and conductor 246b) electrically connected to the conductor 240 and used as wiring are disposed on the insulator 284 and the conductor 240. An insulator 286 is disposed on the conductor 246 and the insulator 274.

[0115] Here, an insulator 241 (insulator 241a or insulator 241b) is provided in contact with the inner wall of the openings of insulators 272, 273, 280, 282, 283 and 284, and a first conductor 240 (conductor 240a or conductor 240b) is provided in contact with its side, and a second conductor 240 is provided inside it.

[0116] Furthermore, the height of the top surface of the conductor 240 can be approximately the same as the height of the top surface of the insulator 284. Additionally, Figures 4A to 4D show the structure of a first conductor and a second conductor of the conductor 240 stacked together, but the present invention is not limited thereto. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0117] Furthermore, conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Additionally, conductors 240a and 240b may also have a laminated structure. Furthermore, while conductors 240a and 240b in Figure 4A appear circular when viewed from above, they are not limited to this. For example, when viewed from above, conductors 240a and 240b may also have a generally circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape with rounded corners.

[0118] When the conductor 240 adopts a multilayer structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. Furthermore, the conductive material with the function of suppressing the permeation of impurities such as water or hydrogen and oxygen can be used as a single layer or in multilayers. By using this conductive material, impurities such as water or hydrogen diffusing from the insulator 280 can be further reduced from entering the oxide 230 through conductors 240a and 240b. In addition, oxygen added to the insulator 280 can be prevented from being absorbed into conductors 240a and 240b.

[0119] For example, silicon nitride, aluminum oxide, or silicon oxynitride can be used as insulators 241a and 241b. Because insulators 241a and 241b are disposed in contact with insulators 274, 283, 282, 280, 273, and 272, impurities such as water or hydrogen from insulator 280 can be prevented from entering the oxide 230 through conductors 240a and 240b. In particular, silicon nitride is preferred due to its high hydrogen barrier properties. Furthermore, the absorption of oxygen contained in insulator 280 by conductors 240a and 240b can be prevented.

[0120] Alternatively, the conductors 246 (conductors 246a and 246b) used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. The conductors 246 are preferably made of conductive materials with tungsten, copper, or aluminum as the main component. Furthermore, the conductors 246 can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material. Additionally, the conductors 246 can be formed by embedding them into openings in an insulator.

[0121] [Transistor 200] As shown in Figures 4A to 4D, transistor 200 includes insulator 216, conductor 205 (conductor 205a and conductor 205b), insulator 222, insulator 224, oxide 230 (oxide 230a, oxide 230b and oxide 230c), conductor 242 (conductor 242a and conductor 242b), oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a and conductor 260b).

[0122] In transistor 200, conductor 260 is used as the first gate of the transistor, while conductor 205 is used as the second gate of the transistor. In addition, conductors 242a and 242b are used as source electrodes or drain electrodes.

[0123] Oxide 230 is used as a semiconductor including the channel formation region.

[0124] Insulator 250 is used as the first gate insulator, and insulators 222 and 224 are used as the second gate insulators.

[0125] Here, in the transistor 200 shown in Figures 4A to 4D, a conductor 260 is formed in self-alignment in the opening of the interlayer film provided in the insulator 280, etc., with the insulator 250 in between.

[0126] In other words, the conductor 260 is formed by being embedded in an opening in the interlayer film including the insulator 280, with the insulator 250 in between. Therefore, the alignment of the conductor 260 is not required in the region between the conductor 242a and the conductor 242b.

[0127] Preferably, oxide 230c is disposed within an opening in the interlayer film including insulator 280. Therefore, insulator 250 and conductor 260 include regions overlapping the stacked structures of oxide 230c with oxides 230b and 230a. By employing this structure, oxide 230c and insulator 250 can be continuously formed, thereby maintaining the cleanliness of the interface between oxide 230 and insulator 250. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in high on-state current and high frequency characteristics for transistor 200.

[0128] In the transistor 200 shown in Figures 4A to 4D, the bottom and side surfaces of the conductor 260 are in contact with the insulator 250. Furthermore, the bottom and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0129] Furthermore, as shown in Figures 4B, 4C, and 4D, the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact. By employing this structure, the diffusion of oxygen contained in the insulator 280 into the conductor 260 can be suppressed.

[0130] Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to oxides 230a and 230b by oxide 230c, thereby reducing oxygen vacancies in oxides 230a and 230b and improving the electrical characteristics and reliability of transistor 200.

[0131] The detailed structure of a semiconductor device including a transistor 200 according to one embodiment of the present invention will now be described.

[0132] Alternatively, it is preferable that the metal oxide (hereinafter, sometimes referred to as oxide semiconductor) used as an oxide semiconductor is used in the transistor 200 for the oxide 230 (oxide 230a, oxide 230b and oxide 230c) including the channel forming region.

[0133] For example, the bandgap of the metal oxide used as an oxide semiconductor is 2 eV or higher, preferably 2.5 eV or higher. By using a metal oxide with a wider bandgap, the leakage current (off-state current) of the transistor 200 in the non-conducting state can be minimized. By employing such a transistor, low-power semiconductor devices can be provided.

[0134] Specifically, the oxide 230 is preferably an In-M-Zn oxide (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M. Furthermore, In oxide, In-M oxide, In-Zn oxide, or M-Zn oxide can also be used as oxide 230.

[0135] As shown in Figures 4A to 4D, oxide 230 preferably includes oxide 230a on insulator 224, oxide 230b on oxide 230a, and oxide 230c disposed on oxide 230b, with at least a portion therein contacting the top surface of oxide 230b. Preferably, oxide 230c is disposed such that its side surface contacts oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 272, insulator 273, and insulator 280.

[0136] In other words, oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0137] Note that in transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in and around the channel forming region, but the present invention is not limited thereto. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers can be provided. For example, oxide 230c can also have a double-layer structure to form a four-layer stacked structure.

[0138] Furthermore, oxide 230 is preferably a layered structure having multiple oxide layers with different ratios of the number of metal atoms. Specifically, the ratio of the number of atoms of element M in the constituent elements of the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of element M in the constituent elements of the metal oxide used for oxide 230b. Furthermore, the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the ratio of the number of atoms of In relative to element M in the metal oxide used for oxide 230b is preferably greater than the ratio of the number of atoms of In relative to element M in the metal oxide used for oxide 230a. Additionally, oxide 230c can use a metal oxide that can be used for oxide 230a or oxide 230b.

[0139] Specifically, oxide 230a can be a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, or an In:Ga:Zn ratio of 1:1:0.5 or similar. Furthermore, oxide 230b can be a metal oxide with an In:Ga:Zn ratio of 4:2:3 or similar, or an In:Ga:Zn ratio of 1:1:1 or similar. Furthermore, oxide 230c can be a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, an In:Ga:Zn ratio of 4:2:3 or similar, an In:Ga:Zn ratio of 5:1:3 or similar, an In:Ga:Zn ratio of 10:1:3 or similar, a Ga:Zn ratio of 2:1 or similar, or a Ga:Zn ratio of 2:5 or similar. Specific examples of oxide 230c with a multilayer structure include: multilayer structures with an In:Ga:Zn ratio of 4:2:3 or similar [atomic ratio] and an In:Ga:Zn ratio of 1:3:4 or similar [atomic ratio]; multilayer structures with an In:Ga:Zn ratio of 4:2:3 or similar [atomic ratio] and an In:Ga:Zn ratio of 5:1:3 or similar [atomic ratio]; multilayer structures with a Ga:Zn ratio of 2:1 or similar [atomic ratio] and an In:Ga:Zn ratio of 4:2:3 or similar [atomic ratio]; multilayer structures with a Ga:Zn ratio of 2:5 or similar [atomic ratio] and an In:Ga:Zn ratio of 4:2:3 or similar [atomic ratio]; and multilayer structures with gallium oxide and an In:Ga:Zn ratio of 4:2:3 or similar [atomic ratio]. Note that "similar" includes a range of ±30% of the desired atomic ratio.

[0140] Furthermore, oxide 230b can also be crystalline. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferred. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from oxide 230b at the source or drain electrode can be suppressed. In addition, even with heat treatment, oxygen extraction from oxide 230b can be reduced, so transistor 200 is also stable at high temperatures (so-called thermal budget) during the process.

[0141] Conductor 205 is arranged to overlap with oxide 230 and conductor 260. Alternatively, conductor 205 is preferably disposed in an insulator 216.

[0142] Here, conductor 260 is sometimes used as the first gate (also called the top gate). In addition, conductor 205 is sometimes used as the second gate (also called the bottom gate).

[0143] When conductor 205 is used as a gate, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0144] Furthermore, as shown in FIG4A, the conductor 205 is preferably larger than the area in oxide 230 that does not overlap with conductors 242a and 242b. In particular, as shown in FIG4C, the conductor 205 preferably extends to the outer side of the end of oxide 230 that intersects with the channel width direction. That is, preferably, the conductor 205 and conductor 260 overlap with an insulator on the outer side of the side of oxide 230 in the channel width direction. Alternatively, by making the conductor 205 large, local charging (also known as charge up) can sometimes be mitigated in the plasma processing of the process after the conductor 205 is formed. However, one embodiment of the present invention is not limited to this. It is sufficient that the conductor 205 overlaps at least with the oxide 230 located between conductors 242a and 242b.

[0145] Furthermore, taking the bottom surface of insulator 224 as a standard, the bottom surface of conductor 260 in the region where oxides 230a and 230b do not overlap with conductor 260 is preferably located at a position lower than the bottom surface of oxide 230b.

[0146] As shown in Figure 4C, by having the conductor 260, used as a gate, have a structure in which the side and top surfaces of the oxide 230b, which is separated from the oxide 230c and the insulator 250, cover the channel-forming region, it is easy for the electric field generated from the conductor 260 to act on the entire channel-forming region formed in the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased to improve the frequency characteristics. In this specification, the structure of the transistor in which the electric fields of the first gate and the second gate surround the channel-forming region is referred to as a surrounded channel (S-channel) structure.

[0147] Conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, as well as oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Furthermore, conductor 205b is preferably a conductive material with tungsten, copper, or aluminum as its main components. Although a conductor 205 with a double-layer structure is shown, conductor 205 can also have a multilayer structure with three or more layers.

[0148] Here, by continuously forming different types of films in a manner that does not expose them to the atmosphere, an oxide semiconductor film with substantially high purity and reduced impurity (especially hydrogen and water) concentration can be formed, which is preferable.

[0149] At least one of insulators 222, 272, and 273 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into the transistor 200 from one side or above the substrate. Therefore, at least one of insulators 222, 272, and 273 is preferably an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0150] For example, silicon nitride or silicon oxynitride is preferably used as insulator 273, while aluminum oxide or hafnium oxide is preferably used as insulator 272.

[0151] Therefore, impurities such as water or hydrogen can be suppressed from diffusing from the substrate side to the transistor 200 side through the insulator 222. Alternatively, oxygen contained in the insulator 224 and the like can be suppressed from diffusing from the insulator 222 to the substrate side.

[0152] Furthermore, it can also suppress the diffusion of impurities such as water or hydrogen from the insulator 280, which is disposed between insulator 272 and insulator 273, to the transistor 200 side. Thus, it is preferable to adopt a structure in which the transistor 200 is surrounded by insulator 272 and insulator 273, which have the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0153] Insulators 222 and 224 function as gate insulators.

[0154] Here, the insulator 224 in contact with the oxide 230 is preferably heated to remove oxygen. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 224. By providing an insulator containing excess oxygen in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0155] Specifically, the insulator 224 is preferably an oxide material that allows for partial oxygen removal upon heating. The oxide that allows for oxygen removal upon heating refers to an oxide in which the amount of oxygen molecules removed during thermal desorption spectroscopy (TDS) analysis is 1.0 × 10¹⁸ molecules / cm³ or more, preferably 1.0 × 10¹⁹ molecules / cm³ or more, further preferably 2.0 × 10¹⁹ molecules / cm³ or more, or 3.0 × 10²⁰ molecules / cm³ or more. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0156] Insulator 222 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into the transistor 200 from the substrate side. For example, the hydrogen permeability of insulator 222 is preferably lower than that of insulator 224. By surrounding insulator 224 and oxide 230 with insulator 222 and insulator 283, impurities such as water or hydrogen from the outside can be prevented from entering the transistor 200.

[0157] Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate). For example, the oxygen permeability of insulator 222 is preferably lower than that of insulator 224. By enabling insulator 222 to inhibit the diffusion of oxygen or impurities, the diffusion of oxygen from oxide 230 to the underside of insulator 222 can be reduced, which is therefore preferable. In addition, the reaction between conductor 205 and oxygen from insulator 224 and oxide 230 can be suppressed.

[0158] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as insulating materials. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred. When this material is used to form the insulator 222, the insulator 222 serves as a layer to suppress the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0159] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the above-mentioned insulator. Alternatively, the above-mentioned insulator can be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be laminated on the above-mentioned insulator.

[0160] Furthermore, as the insulator 222, high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used as single layers or in stacks. When miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using high-k materials as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0161] In addition, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0162] Alternatively, oxide 243 (oxide 243a and oxide 243b) can be disposed between oxide 230b and conductor 242 (conductor 242a and conductor 242b) used as source or drain electrodes. Since conductor 242 does not contact oxide 230, the absorption of oxygen from oxide 230 by conductor 242 can be suppressed. In other words, by preventing oxidation of conductor 242, the decrease in conductivity of conductor 242 can be suppressed. Therefore, oxide 243 preferably has the function of suppressing oxidation of conductor 242.

[0163] Therefore, oxide 243 preferably has the function of suppressing oxygen permeation. When oxide 243 with the function of suppressing oxygen permeation is disposed between the conductor 242, which is used as the source electrode or drain electrode, and oxide 230b, the resistance between the conductor 242 and oxide 230b decreases, which is preferable. By adopting this structure, the electrical characteristics and reliability of transistor 200 can be improved.

[0164] As oxide 243, a metal oxide containing element M can also be used. In particular, aluminum, gallium, yttrium, or tin are preferably used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. In addition, gallium oxide can also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the number of atoms of element M relative to In in the metal oxide used for oxide 243 is preferably greater than the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230b. In addition, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, and preferably 1 nm or more and 3 nm or less. In addition, oxide 243 is preferably crystalline. When oxide 243 is crystalline, it is possible to better suppress the release of oxygen from oxide 230. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen from oxide 230 can sometimes be suppressed.

[0165] Furthermore, oxide 243 is not necessarily required. In this case, because conductor 242 (conductors 242a and 242b) is in contact with oxide 230, oxygen in oxide 230 diffuses into conductor 242, thereby sometimes oxidizing conductor 242. The possibility of the conductivity of conductor 242 decreasing due to oxidation increases. Note that the diffusion of oxygen from oxide 230 into conductor 242 can also be referred to as conductor 242 absorbing oxygen from oxide 230.

[0166] Furthermore, when oxygen diffuses from oxide 230 into conductor 242 (conductors 242a and 242b), another layer may form between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. Because this other layer contains more oxygen than conductor 242, it is presumed that this other layer has insulating properties. In this case, the three-layer structure of conductor 242, this other layer, and oxide 230b can be considered a metal-insulator-semiconductor three-layer structure, sometimes referred to as a MIS (Metal-Insulator-Semiconductor) structure or a diode structure dominated by MIS.

[0167] Note that the other layer is not limited to being formed between conductor 242 and oxide 230b. For example, another layer may be formed between conductor 242 and oxide 230c, or between conductor 242 and oxide 230b and between conductor 242 and oxide 230c.

[0168] Conductors 242 (conductors 242a and conductors 242b) used as source and drain electrodes are disposed on oxide 243. The thickness of conductor 242 can be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0169] As the conductor 242, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred.

[0170] An insulator 272 is disposed in contact with the top surface of the conductor 242, and the insulator 272 is preferably used as a barrier layer. By adopting this structure, the absorption of excess oxygen contained in the insulator 280 by the conductor 242 can be suppressed. In addition, by suppressing the oxidation of the conductor 242, the increase in contact resistance between the transistor 200 and the wiring can be suppressed. Thus, the transistor 200 can be endowed with good electrical characteristics and reliability.

[0171] Therefore, insulator 272 preferably has the function of suppressing oxygen diffusion. For example, insulator 272 is preferably more effective at suppressing oxygen diffusion than insulator 280. As insulator 272, for example, it is preferably an insulator that forms an oxide containing one or both of aluminum and hafnium. In addition, as insulator 272, for example, an insulator containing aluminum nitride can be used.

[0172] As shown in Figures 4B and 4D, insulator 272 is in contact with a portion of the top surface and the side surface of conductor 242b. Insulator 272 is also in contact with a portion of the top surface and the side surface of conductor 242a. Furthermore, insulator 273 is disposed on insulator 272. By employing this structure, for example, it is possible to suppress the absorption of oxygen added to insulator 280 by conductor 242.

[0173] Insulator 250 is used as a gate insulator. Insulator 250 is preferably configured to contact the top surface of oxide 230c with ground. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0174] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating in contact with the top surface of oxide 230c as insulator 250, oxygen can be efficiently supplied to the channel-forming region of oxide 230b. Similar to insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0175] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide is preferably configured to suppress the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0176] Furthermore, this metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a high-k metal oxide, which is a material with a high relative permittivity, as the metal oxide. By making the gate insulator have a stacked structure of insulator 250 and the metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0177] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, it is preferred to use aluminum oxide, hafnium oxide, or oxides containing aluminum and hafnium (hafnium aluminate) as insulators containing one or both of aluminum and hafnium.

[0178] Alternatively, the metal oxide is sometimes used as part of the gate. In this case, it is preferable to place an oxygen-containing conductive material on one side of the channel forming region. By placing an oxygen-containing conductive material on one side of the channel forming region, oxygen detached from the conductive material can be easily supplied to the channel forming region.

[0179] In particular, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel as the conductor used as the gate. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0180] Although the conductor 260 has a double-layer structure in Figures 4A to 4D, it can also have a single-layer structure or a stacked structure of three or more layers.

[0181] The conductor 260a is preferably a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, it is preferable to use a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0182] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide are preferably used, for example.

[0183] Furthermore, it is preferable to use a conductive material with tungsten, copper, or aluminum as the main component as the conductor 260b. Additionally, since the conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper, or aluminum as the main component can be used. Furthermore, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0184] <<Example 1 of a Semiconductor Device>> Hereinafter, an example of a semiconductor device including a transistor 200 according to an embodiment of the present invention will be described with reference to FIGS. 5A to 5D.

[0185] Here, Figure 5A shows a top view. Figure 5B is a cross-sectional view corresponding to the portion indicated by dashed lines A1-A2 in Figure 5A. Figure 5C is a cross-sectional view corresponding to the portion indicated by dashed lines A3-A4 in Figure 5A. Figure 5D is a cross-sectional view corresponding to the portion indicated by dashed lines A5-A6 in Figure 5A. In the top view of Figure 5A, some components have been omitted for clarity.

[0186] The semiconductor devices shown in Figures 5A to 5D differ from those shown in Figures 4A to 4D in that insulators 212 and 283 are in contact. Specifically, it is preferable that insulator 212 extends below insulator 273. Furthermore, in insulator 212, the thickness of the region overlapping with transistor 200 is sometimes greater than the thickness of the region in contact with insulator 283.

[0187] <<Example 2 of a Semiconductor Device>> Hereinafter, an example of a semiconductor device including a transistor 200 according to an embodiment of the present invention will be described with reference to FIGS. 6A to 6D.

[0188] Here, Figure 6A shows a top view. Figure 6B is a cross-sectional view corresponding to the portion indicated by dashed lines A1-A2 in Figure 6A. Figure 6C is a cross-sectional view corresponding to the portion indicated by dashed lines A3-A4 in Figure 6A. Figure 6D is a cross-sectional view corresponding to the portion indicated by dashed lines A5-A6 in Figure 6A. In the top view of Figure 6A, some components are omitted for clarity.

[0189] For example, as shown in Figures 6A to 6D, when using a compound gas that does not contain hydrogen atoms or contains a small amount of hydrogen atoms and forming insulators 211 and 284 by CVD, it is not necessary to set insulators 212 and 284.

[0190] For example, insulators 211, 212, 283, and 284 can be formed using a compound gas that does not contain hydrogen atoms or contains very few hydrogen atoms via CVD. In other words, reducing the hydrogen concentration contained in insulators 211, 212, 283, and 284 reduces the amount of hydrogen mixed into the channel-forming region of the oxide semiconductor.

[0191] For example, when forming silicon-containing films such as silicon nitride films, a gas containing molecules containing silicon atoms is primarily used as the deposition gas. To reduce the amount of hydrogen contained in the film to be formed, the silicon-containing molecules preferably contain few hydrogen atoms, and more preferably, the silicon-containing molecules do not contain any hydrogen atoms. Of course, the deposition gas other than the gas containing silicon atoms also preferably contains few hydrogen atoms, and more preferably, the deposition gas does not contain any hydrogen atoms.

[0192] When the molecule containing silicon atoms is represented by Six-Ry, for example, at least one of the following functional groups, such as isocyanate (-N=C=O), cyanate (-OC≡N), cyano (-C≡N), diazo (=N2), azide (-N3), nitroso (-NO), and nitro (-NO2), can be used as the functional group R. For example, 1≤x≤3 and 1≤y≤8 can be specified. Examples of such silicon-containing molecules include tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, octaisocyanate silane, etc. This example illustrates a molecule in which silicon atoms are bonded to the same type of functional group, but this embodiment is not limited to this. Silicon atoms can also be bonded to different types of functional groups.

[0193] Furthermore, halogens (Cl, Br, I, or F) can be used as functional groups R, for example. For instance, the halogens can be set to 1 ≤ x ≤ 2 and 1 ≤ y ≤ 6. Examples of molecules containing silicon atoms include tetrachlorosilane (SiCl4) and hexachlorodisilane (Si2Cl6). An example using chlorine as a functional group is shown, but halogens other than chlorine, such as bromine, iodine, and fluorine, can also be used as functional groups. Furthermore, silicon atoms can be bonded to different types of halogens.

[0194] Insulators 211, 212, 283, and 284 can be formed using the aforementioned chemical vapor deposition (CVD) method with a gas containing silicon atoms. Because CVD has a relatively fast deposition rate, it is suitable for forming thick insulators.

[0195] As a CVD method, plasma-enhanced CVD (PECVD) or thermal CVD (TCVD) are preferred. When using thermal CVD, either atmospheric pressure CVD (APCVD) or low pressure CVD (LPCVD) can be employed, where film formation is carried out at atmospheric pressure.

[0196] When forming insulators 211, 212, 283, and 284 using the CVD method, it is preferable to use an oxidizing agent. Preferably, the oxidizing agent is a gas that does not contain hydrogen atoms, such as O2, O3, NO, NO2, N2O, N2O3, N2O4, N2O5, CO, or CO2.

[0197] Alternatively, insulators 211, 212, 283, and 284 can be formed using the ALD (Atomic Layer Deposition) method. In the ALD method, a first raw material gas (hereinafter referred to as the precursor, also known as the metal precursor) and a second raw material gas (hereinafter referred to as the reactant, also known as the non-metal precursor) are alternately introduced into the chamber, and this raw material gas is repeatedly introduced to form a film.

[0198] In the ALD method, film formation is performed simultaneously with the switching of feed gas, utilizing the self-regulating properties of atoms to deposit atoms in each layer. Therefore, the ALD method can form extremely thin and relatively thick films, can form films for structures with high aspect ratios, can form films with few defects such as pinholes, and can form films with excellent coverage. Therefore, in addition to the formation of insulators 211, 212, 283, and 284, the ALD method is also suitable for the formation of insulators 250 and 224 included in the transistor 200.

[0199] As an ALD method, it can be either the thermal ALD method, which uses only thermal energy to react the precursors and reactants, or the PEALD method, which uses plasma-enhanced reactants.

[0200] When using the ALD method, the aforementioned gas containing molecules containing silicon atoms can be used as a precursor, and the aforementioned oxidant can be used as a reactant. This significantly reduces the amount of hydrogen introduced into insulators 216, 274, 280, 224, and 250.

[0201] Note that the example shown above illustrates a molecule containing silicon atoms but not hydrogen atoms. However, this embodiment is not limited to this; a structure in which a portion of the functional groups bonded to silicon atoms in the aforementioned silicon-containing molecule are replaced by hydrogen atoms may also be used. However, it is preferable that the aforementioned silicon-containing molecule has fewer hydrogen atoms than silane (SiH4). That is, in the aforementioned silicon-containing molecule, each silicon atom preferably has three or fewer hydrogen atoms. Furthermore, in a gas containing the aforementioned silicon-containing molecule, it is more preferable that each silicon atom has three or fewer hydrogen atoms.

[0202] As described above, by forming at least one of insulators 211, 212, 283 and 284 using a film-forming method that uses hydrogen atoms to reduce or remove gases, the amount of hydrogen contained in these insulators can be reduced.

[0203] Thus, by using a first sealing structure made of a material that captures or fixes impurities such as hydrogen and a second sealing structure made of a material that inhibits the diffusion of impurities such as hydrogen to double-seal the transistor 200 and the insulator 280, the insulator 283 and the insulator 212 can reduce the hydrogen concentration in the sealed area and also reduce the amount of hydrogen mixed in from the outside.

[0204] <<Metal Oxides>> As oxide 230, a metal oxide that is used as an oxide semiconductor is preferred. Hereinafter, a metal oxide that can be used for oxide 230 according to the present invention will be described.

[0205] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it is preferred to also contain gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0206] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0207] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0208] [Composition of metal oxides] The structure of CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) and CAAC-OS (c-axis Aligned Crystal Oxide Semiconductor) of metal oxide transistors disclosed according to one embodiment of the present invention will be described.

[0209] CAC-OS or CAC-metal oxide possesses conductive properties in one part of the material and insulating properties in another, thus functioning as a semiconductor as a whole. Furthermore, when CAC-OS or CAC-metal oxide is used as the active layer of a transistor, the conductive function allows electrons (or holes) used as carriers to flow through, while the insulating function prevents electrons from flowing through. Through the complementary effects of conductivity and insulation, CAC-OS or CAC-metal oxide can possess switching functionality (controlling on / off operation). By separating these functions within CAC-OS or CAC-metal oxide, each function can be maximized.

[0210] Furthermore, CAC-OS or CAC-metal oxide comprises conductive and insulating regions. The conductive regions possess the aforementioned conductive function, and the insulating regions possess the aforementioned insulating function. Moreover, in the material, the conductive and insulating regions are sometimes separated at the nanoparticle level. Additionally, the conductive and insulating regions are sometimes unevenly distributed within the material. Furthermore, conductive regions with blurred edges and cloud-like connections are sometimes observed.

[0211] Furthermore, in CAC-OS or CAC-metal oxide, conductive and insulating regions are sometimes dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0212] Furthermore, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap originating from an insulating region and a component with a narrow gap originating from a conductive region. In this configuration, when carriers flow through, they mainly flow through the component with the narrow gap. Moreover, the component with the narrow gap, through complementary interaction with the component with the wide gap, causes carriers to flow through the component with the wide gap. Therefore, when the aforementioned CAC-OS or CAC-metal oxide is used in the channel forming region of a transistor, a high current driving force, i.e., a large on-state current and a high field-effect mobility, can be obtained in the transistor's conducting state.

[0213] In other words, CAC-OS or CAC-metal oxide can also be referred to as matrix composite or metal matrix composite.

[0214] [Structure of metal oxides] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0215] When considering crystal structure, oxide semiconductors are sometimes classified into different categories than those described above. Here, the classification of crystal structures in oxide semiconductors is illustrated with reference to Figure 31A. Figure 31A is a diagram illustrating the classification of crystal structures in oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0216] As shown in Figure 31A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Crystal includes single crystal and poly crystal.

[0217] Note that the structure within the thick box in Figure 31A belongs to the New crystalline phase. This structure exists in the boundary region between Amorphous and Crystalline. In other words, the energetically unstable Amorphous and Crystalline can be considered completely different structures.

[0218] Note that the crystalline structure of the film or substrate can be evaluated using X-ray diffraction (XRD) images. Here, Figures 31B and 31C show the XRD spectra of IGZO (also known as Crystalline IGZO) using quartz glass and having a crystalline structure classified as Crystalline. Furthermore, Figure 31B is the XRD spectrum of quartz glass, and Figure 31C is the XRD spectrum of crystalline IGZO. Note that the crystalline IGZO shown in Figure 31C has an In:Ga:Zn ratio of 4:2:3 [atomic number ratio]. Furthermore, the thickness of the crystalline IGZO shown in Figure 31C is 500 nm.

[0219] As shown by the arrow in Figure 31B, quartz glass exhibits approximately symmetrical XRD peaks. On the other hand, as shown by the arrow in Figure 31C, crystalline IGZO exhibits asymmetrical XRD peaks. The presence of asymmetrical XRD peaks clearly indicates the presence of crystals. In other words, when the XRD peaks are not bilaterally symmetrical, the analyte (in this case, crystalline IGZO) cannot be considered amorphous.

[0220] CAAC-OS exhibits c-axis alignment, with its multiple nanocrystals connected along the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the change in the orientation of the lattice arrangement between regions with consistent lattice alignment and other regions with consistent lattice alignment within the region where multiple nanocrystals are connected.

[0221] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons; some are not. Furthermore, pentagonal or heptagonal lattice arrangements are sometimes observed in distortions. Additionally, in CAAC-OS, clear grain boundaries (also known as grain boundaries) are not observed even near the distortion. That is, it is known that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can contain distortions due to the low density of oxygen atoms along the ab plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0222] Furthermore, CAAC-OS tends to have a layered crystal structure (also called a layered structure) consisting of layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers). Additionally, indium and element M can substitute for each other; when element M in a (M,Zn) layer is replaced by indium, the layer can also be represented as an (In,M,Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In,M) layer.

[0223] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of a decrease in electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the introduction of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess high heat resistance and high reliability.

[0224] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no alignment is observed in the overall film. Consequently, nc-OS is sometimes indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0225] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is a nanocrystal as described above. In particular, IGZO tends to not easily grow crystals in the atmosphere, so it may be structurally stable when IGZO is a small crystal (e.g., the nanocrystal described above) compared to when IGZO is a large crystal (here, a few mm or a few cm crystals).

[0226] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0227] Oxide semiconductors (metal oxides) have various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0228] [Impurities] Here, we will explain the effects of various impurities in metal oxides.

[0229] When impurities are incorporated into oxide semiconductors, they sometimes form defect energy levels or oxygen vacancies. Therefore, when impurities are present in the channel formation region of an oxide semiconductor, the electrical characteristics of the transistors using oxide semiconductors are prone to change, sometimes leading to decreased reliability. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor tends to exhibit always-on characteristics.

[0230] Furthermore, the aforementioned defect energy levels sometimes include trap energy levels. The charge trapped by the trap energy levels of metal oxides requires a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical properties of transistors with channel-forming regions in metal oxides with high trap state densities are sometimes unstable.

[0231] Furthermore, when impurities are present in the channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may decrease, or the crystallinity of the oxide disposed in contact with the channel formation region may decrease. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to decrease. In addition, when the crystallinity of the oxide disposed in contact with the channel formation region is low, interface energy levels may sometimes form, leading to a decrease in the stability or reliability of the transistor.

[0232] Therefore, reducing the impurity concentration in and around the channel formation region of an oxide semiconductor is effective in improving the stability or reliability of transistors. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0233] Specifically, the concentration of the impurities obtained by SIMS in the channel formation region and vicinity of the oxide semiconductor is set to 1 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁶ atoms / cm³ or less. Alternatively, the concentration of the impurities obtained by elemental analysis using EDX in the channel formation region and vicinity of the oxide semiconductor is set to 1.0 atomic% or less. Furthermore, when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurities in the channel formation region and vicinity of the oxide semiconductor relative to element M is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used to calculate the above concentration ratio can be either the concentration of the region where the impurity concentration is calculated or the concentration in the oxide semiconductor itself.

[0234] Because metal oxides with reduced impurity concentrations have low defect state densities, their trap state densities are sometimes also low.

[0235] When hydrogen enters an oxygen vacancy in a metal oxide, sometimes the oxygen vacancy and hydrogen bond to form a VOH. Sometimes the VOH acts as a donor, generating electrons as carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen atoms bonded to the metal atom, generating electrons as carriers.

[0236] Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, since hydrogen in oxide semiconductors is easily moved by heat, electric fields, etc., a large amount of hydrogen in an oxide semiconductor may also lead to a decrease in transistor reliability.

[0237] In other words, it is preferable to minimize the VOH in the oxide semiconductor to make the metal oxide inherently high-purity or substantially high-purity. To obtain such an oxide semiconductor with sufficiently reduced VOH, it is important to: remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes described as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes also called oxidation treatment). By using an oxide semiconductor with sufficiently reduced VOH and impurities in the channel formation region of a transistor, stable electrical properties can be imparted.

[0238] Furthermore, it is preferable to use oxide semiconductors with low carrier concentrations as transistors. To reduce the carrier concentration of an oxide semiconductor, the impurity concentration in the oxide semiconductor can be reduced to decrease the defect state density. In this specification, a state with both low impurity concentration and low defect state density is referred to as high-purity nature or substantially high-purity nature. Examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0239] In particular, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies in oxide semiconductors. When the channel-forming region in an oxide semiconductor contains oxygen vacancies, the transistor may have always-on characteristics. Furthermore, sometimes hydrogen entering a defect in an oxygen vacancy acts as a donor, generating electrons as carriers. Sometimes, a portion of the hydrogen bonds with oxygen bonded to a metal atom, generating electrons as carriers. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics.

[0240] Defects where hydrogen enters oxygen vacancies (VOH) are sometimes used as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate these defects. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification, etc., the carrier concentration under the assumption of no applied electric field is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is, the "carrier concentration" described in this specification, etc., may sometimes be referred to as "donor concentration".

[0241] Therefore, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, in the oxide semiconductor film, the hydrogen concentration, as measured by secondary ion mass spectrometry (SIMS), is less than 1 × 10²⁰ atoms / cm³, more preferably less than 1 × 10¹⁹ atoms / cm³, even more preferably less than 5 × 10¹⁸ atoms / cm³, and further preferably less than 1 × 10¹⁸ atoms / cm³. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical properties can be imparted.

[0242] The carrier concentration of the oxide semiconductor in the channel formation region is preferably below 1×10¹⁸ cm⁻³, more preferably below 1×10¹⁷ cm⁻³, further preferably below 1×10¹⁶ cm⁻³, even more preferably below 1×10¹³ cm⁻³, and even more preferably below 1×10¹² cm⁻³. Furthermore, there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the channel formation region; for example, it can be 1×10⁻⁹ cm⁻³.

[0243] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device capable of miniaturization or hyper-integration can be provided. According to one embodiment of the present invention, a low-power semiconductor device can be provided.

[0244] <<Other Semiconductor Materials>> The semiconductor materials that can be used for oxide 230 are not limited to the aforementioned metal oxides. As oxide 230, semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used. For example, it is preferable to use semiconductors of a single element such as silicon, compound semiconductors such as gallium arsenide, or layered materials used as semiconductors (also called atomic-layer materials, two-dimensional materials, etc.). In particular, it is preferable to use layered materials used as semiconductors as semiconductor materials.

[0245] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended for use as a semiconductor, in the channel-forming region, transistors with large on-state currents can be provided.

[0246] As layered materials, examples include graphene, silicon, and chalcogenides. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0247] As oxide 230, a transition metal chalcogenide, which is used as a semiconductor, is preferably used. Examples of transition metal chalcogenides that can be used as oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0248] <Methods for Manufacturing Semiconductor Devices> Next, a method for manufacturing the semiconductor device including the transistor 200 according to the present invention shown in Figures 4A to 4D will be described with reference to Figures 7A to 23D. In Figures 7A to 23D, A in each figure shows a top view. Additionally, B in each figure shows a cross-sectional view along the portion of A with the dotted line A1-A2, which corresponds to a cross-sectional view along the channel length direction of the transistor 200. C in each figure shows a cross-sectional view along the portion of A with the dotted line A3-A4, which corresponds to a cross-sectional view along the channel width direction of the transistor 200. D in each figure shows a cross-sectional view along the portion of A with the dotted line A5-A6. For clarity, some components are omitted in the top view of A in each figure.

[0249] First, a substrate (not shown) is prepared, and an insulator 211 is formed on the substrate. The insulator 211 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD.

[0250] Note that CVD methods can be categorized into plasma CVD (PECVD), thermal CVD, and photochemical CVD. Furthermore, CVD methods can be classified based on the source gas used, such as metal CVD and organometallic CVD. Additionally, CVD methods can be further classified based on the pressure at which film is formed, such as atmospheric pressure CVD (forming film at atmospheric pressure) and depressurized pressure CVD (forming film at reduced pressure below atmospheric pressure).

[0251] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a film deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components in the semiconductor device. On the other hand, since thermal CVD does not produce this plasma damage, the yield of semiconductor devices can be improved. Additionally, since thermal CVD does not generate plasma damage during film deposition, films with fewer defects can be obtained.

[0252] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to react the precursors and reactants, and PEALD (Plasma Enhanced ALD) methods that use reactants excited by plasma.

[0253] The ALD method utilizes the self-regulating properties of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films formed at low temperatures. In the PEALD method, the use of plasma allows for film deposition at even lower temperatures, making it sometimes preferable. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0254] Unlike film deposition methods that deposit particles released from a target or similar material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed using ALD exhibit excellent step coverage and thickness uniformity, making ALD suitable for applications requiring coverage of surfaces with high aspect ratio openings. Note that ALD deposition rates are relatively slow, so it is sometimes preferable to combine it with other film deposition methods with faster deposition rates, such as CVD.

[0255] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for example, when using CVD and ALD, films with continuously varying compositions can be formed by simultaneously changing the source gas flow rate ratio during film formation. When film formation is performed while changing the source gas flow rate ratio, the time required for pressure transfer and adjustment is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0256] In this embodiment, silicon nitride is formed as insulator 211 by CVD. Next, insulator 212 is formed on insulator 211. Insulator 212 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon nitride is formed as insulator 212 using sputtering.

[0257] Next, a film serving as insulator 214 is formed on insulator 212. The film serving as insulator 214 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, alumina is used as the film serving as insulator 214.

[0258] By using silicon nitride or other insulators that do not easily allow copper to pass through as insulators 211 and 212, and by depositing a film as insulator 214 on insulator 212, even if a metal that easily diffuses, such as copper, is used as the conductor in the layer below insulator 211 (not shown), the diffusion of that metal through insulator 211 and insulator 212 to the upper layer can be suppressed. Furthermore, by using an insulator such as silicon nitride that impurities such as water or hydrogen do not easily pass through, the diffusion of impurities such as water or hydrogen from the lower layer of insulator 211 can be prevented.

[0259] The hydrogen concentration of insulator 212 is preferably lower than that of insulator 211. The hydrogen concentration of the film that becomes insulator 214 is preferably lower than that of insulator 212. Silicon nitride is formed as insulator 212 by sputtering, thereby forming silicon nitride with a lower hydrogen concentration than that of insulator 211 formed by CVD. Furthermore, by using alumina as the film that becomes insulator 214, its hydrogen concentration can be lower than that of insulator 212.

[0260] In subsequent processes, a transistor 200 is formed on a film that serves as insulator 214. The hydrogen concentration of the film adjacent to the transistor 200 is preferably low, and it is also preferable to place the film with a higher hydrogen concentration away from the transistor 200.

[0261] Next, a film becoming insulator 216 is formed on the film becoming insulator 214. The film becoming insulator 216 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon oxide or silicon oxynitride is used as the film becoming insulator 216. Furthermore, the film becoming insulator 216 is preferably formed using the above-described film-forming method that uses hydrogen atoms to reduce or remove gases. This reduces the hydrogen concentration of the film becoming insulator 216.

[0262] Next, an opening is formed in the film that serves as insulator 216, leading to the film that serves as insulator 214. The opening may include, for example, a groove or a slit. Furthermore, the area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. The film that serves as insulator 214 is preferably an insulator that acts as an etch stop film when etching the film that serves as insulator 216 to form a groove. For example, when a silicon oxide film or a silicon oxynitride film is used as the film that forms the groove as insulator 216, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the film that serves as insulator 214.

[0263] After the opening is formed, a conductive film serving as conductor 205a is formed. This conductive film preferably contains a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film serving as conductor 205a can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0264] In this embodiment, the conductive film that serves as conductor 205a has a multilayer structure. First, tantalum nitride is deposited using a sputtering method, and titanium nitride is stacked on top of the tantalum nitride. By using this metal nitride as the lower layer of conductor 205b, even if a metal that easily diffuses, such as copper, is used as the conductive film that serves as conductor 205b as described later, the diffusion of this metal from conductor 205a to the outside can be suppressed.

[0265] Next, a conductive film is formed to become the conductor 205b. This conductive film can be formed using electroplating, sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to become the conductor 205b.

[0266] Next, by performing CMP (Chemical Mechanical Polishing), the conductive film that becomes conductor 205a and a portion of the conductive film that becomes conductor 205b are removed, exposing the film that becomes insulator 216. As a result, conductors 205a and 205b remain only at the opening. Thus, a conductor 205 with a flat top surface can be formed. Note that sometimes a portion of the film that becomes insulator 216 is removed due to this CMP process (see Figures 7A to 7D).

[0267] Furthermore, in the above description, the conductor 205 is formed by embedding it into the opening of the film that serves as insulator 216, but this embodiment is not limited to this. For example, the conductor 205 may be formed on the film that serves as insulator 214, the film that serves as insulator 216 may be formed on the conductor 205, and a portion of the film that serves as insulator 216 may be removed by performing CMP treatment on the film that serves as insulator 216 to expose the surface of the conductor 205.

[0268] Next, an insulator 222 is formed on the film 216 and the conductor 205. Preferably, the insulator 222 is an oxide containing one or both of aluminum and hafnium. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred as the insulator containing one or both of aluminum and hafnium. The insulator containing one or both of aluminum and hafnium oxides provides barrier properties against oxygen, hydrogen, and water. When the insulator 222 provides barrier properties against hydrogen and water, it can suppress the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0269] Insulator 222 can be formed by sputtering, CVD, MBE, PLD or ALD.

[0270] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 224. Furthermore, the insulator 224 is preferably formed using the film-forming method described above, which uses hydrogen atoms to reduce or remove gases. This reduces the hydrogen concentration of the insulator 224. Since the insulator 224 becomes the insulator 224 that contacts the oxide 230a in subsequent processes, it is preferable to reduce its hydrogen concentration as described above.

[0271] Next, it is preferable to perform a heat treatment. The heat treatment can be performed at a temperature of 250°C or higher and 650°C, preferably 300°C or higher and 500°C, and more preferably 320°C or higher and 450°C. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0272] In this embodiment, the process is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a continuous process at 400°C for 1 hour under an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0273] Alternatively, heat treatment can be performed after the insulator 222 has been formed. This heat treatment can be performed under the conditions described above.

[0274] To form an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, it may include applying a high-frequency power supply, such as RF, to one side of the substrate. High-density plasma can generate high-density oxygen radicals, and applying RF to one side of the substrate can efficiently introduce these oxygen radicals into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the lost oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heating treatment may not be necessary.

[0275] Here, for example, aluminum oxide can be formed on insulator 224 by sputtering, and CMP can be performed on the aluminum oxide until it reaches insulator 224. By performing this CMP, the surface of insulator 224 can be planarized and smoothed. By placing the aluminum oxide on insulator 224 and performing CMP, the endpoint of CMP can be easily detected. Furthermore, sometimes the thickness of insulator 224 becomes thinner due to polishing of a portion of it by CMP, but this can be corrected by adjusting the thickness during film formation on insulator 224. By planarizing and smoothing the surface of insulator 224, it is sometimes possible to prevent a decrease in the coverage of the oxide film to be formed underneath and to prevent a decrease in the yield of the semiconductor device. Moreover, forming aluminum oxide on insulator 224 by sputtering allows for the addition of oxygen to insulator 224, which is preferable.

[0276] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see Figures 7A to 7D). Preferably, the oxide films are formed continuously without exposure to the atmospheric environment. By forming the oxide films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface between oxide films 230A and 230B clean.

[0277] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD or ALD.

[0278] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. Furthermore, when forming the aforementioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0279] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas of the oxide film 230A can be 70% or more, preferably 80% or more, and more preferably 100%.

[0280] Furthermore, when forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the oxygen content in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. Transistors using the oxygen-deficient oxide semiconductor in the channel formation region can exhibit higher field-effect mobility. Additionally, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited thereto. When forming the oxide film 230B by sputtering, an oxygen-excess oxide semiconductor is formed by setting the oxygen content in the sputtering gas to more than 30% and less than 100%, preferably 70% or more and less than 100%. Transistors using the oxygen-excess oxide semiconductor in the channel formation region exhibit higher reliability.

[0281] In this embodiment, an oxide film 230A is formed using a sputtering method with an In:Ga:Zn ratio of 1:1:0.5 (2:2:1) or 1:3:4. Alternatively, an oxide film 230B is formed using a sputtering method with an In:Ga:Zn ratio of 4:2:4.1 or 1:1:1. The formation conditions and atomic ratios of the aforementioned oxide films can be appropriately selected based on the desired characteristics of the oxide 230.

[0282] Next, heat treatment can be performed. The aforementioned heat treatment conditions can be used as the conditions for heat treatment. By performing heat treatment, impurities such as water and hydrogen in oxide films 230A and 230B can be removed. In this embodiment, the treatment is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by continuous treatment at 400°C for 1 hour under an oxygen atmosphere.

[0283] Next, an oxide film 243A is formed on the oxide film 230B (see Figures 7A to 7D). The oxide film 243A can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Preferably, the ratio of Ga atoms relative to In in the oxide film 243A is greater than the ratio of Ga atoms relative to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio].

[0284] Next, a conductive film 242A is formed on the oxide film 243A (see Figures 7A to 7D). The conductive film 242A can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0285] Next, oxide films 230A, 230B, 243A, and conductive film 242A are processed into island shapes using photolithography to form oxides 230a, 230b, oxide layer 243B, and conductor layer 242B (see Figures 8A to 8D). Here, oxides 230a, 230b, oxide layer 243B, and conductor layer 242B are formed such that at least a portion of them overlap with conductor 205. Furthermore, this processing can be performed using dry etching or wet etching. Processing performed by dry etching is suitable for microfabrication. Additionally, during this process, the thickness of the region in insulator 224 that does not overlap with oxide 230a sometimes becomes thinner.

[0286] In photolithography, the photoresist is first exposed using a mask. Then, a developing solution is used to remove or leave the exposed area, forming a photoresist mask. Next, etching is performed through the photoresist mask to process the conductor, semiconductor, or insulator into the desired shape. For example, a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light can be used to expose the photoresist to form the photoresist mask. Alternatively, immersion technology can be used, where exposure is performed with the space between the substrate and the projection lens filled with liquid (e.g., water). Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron beams or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0287] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material can be formed on the conductive film 242A, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film 242A, etc., can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may disappear during etching. The hard mask can be removed by etching after etching the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask.

[0288] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure that applies high-frequency power to one of the parallel planar electrodes. Alternatively, it can employ a structure that applies multiple different high-frequency powers to one of the parallel planar electrodes. Alternatively, it can employ a structure that applies the same high-frequency power to each of the parallel planar electrodes. Alternatively, it can employ a structure that applies different high-frequency power to each of the parallel planar electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, as a dry etching apparatus with a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0289] Furthermore, the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B are preferably approximately perpendicular to the top surface of insulator 222. When the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B are approximately perpendicular to the top surface of insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. However, this is not a limitation; a structure in which the angle formed between the sides of oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B and the top surface of insulator 222 is smaller can also be used.

[0290] Next, an insulator 272 is formed on insulator 224, oxide 230a, oxide 230b, oxide layer 243B, and conductor layer 242B (see Figures 9A to 9D). Insulator 272 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, aluminum oxide is formed as insulator 272 using sputtering. Oxygen can be implanted into insulator 224 by forming aluminum oxide using sputtering.

[0291] Next, insulator 273 is formed on insulator 272. Insulator 273 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, silicon nitride is formed as insulator 273 using sputtering (see Figures 9A to 9D).

[0292] Next, an insulating film, which becomes insulator 280, is formed. The insulating film, which becomes insulator 280, can be formed using sputtering, CVD, MBE, PLD, or ALD methods. For example, as insulator 280, a silicon oxide film can be formed by sputtering, and then a silicon oxide film can be formed on it using PEALD or thermal ALD. Furthermore, the insulating film, which becomes insulator 280, is preferably formed using the aforementioned film-forming method that uses hydrogen atoms to reduce or remove gases. This reduces the hydrogen concentration of insulator 280.

[0293] Next, the insulating film that becomes insulator 280 is subjected to CMP treatment to form an insulator 280 with a flat top surface (see Figures 10A to 10D). In addition, similar to insulator 224, for example, aluminum oxide can be formed on insulator 280 by sputtering, and the aluminum oxide can be subjected to CMP until it reaches insulator 280.

[0294] Next, a portion of insulator 280, a portion of insulator 273, a portion of insulator 272, a portion of conductive layer 242B, and a portion of oxide layer 243B are processed to form an opening reaching oxide 230b (see Figures 11A to 11D). This opening is preferably formed overlapping with conductor 205. By forming this opening, conductor 242a, conductor 242b, oxide 243a, and oxide 243b are formed.

[0295] A portion of insulator 280, a portion of insulator 273, a portion of insulator 272, a portion of oxide layer 243B, and a portion of conductive layer 242B can be processed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing can be performed under different conditions. For example, a portion of insulator 280 can be processed using dry etching, a portion of insulator 273 using wet etching, a portion of insulator 272 using dry etching, and portions of oxide layer 243B and conductive layer 242B using dry etching.

[0296] During the aforementioned dry etching process, impurities such as etching gases sometimes adhere to or diffuse into the surface or interior of oxides 230a and 230b. Examples of such impurities include fluorine or chlorine.

[0297] To remove the aforementioned impurities, washing is performed. Washing methods include wet washing using a washing liquid, plasma treatment using a plasma electrode, and washing using a heat treatment; combinations of these methods may also be appropriate.

[0298] As a wet cleaning method, an aqueous solution prepared by diluting oxalic acid, phosphoric acid, ammonia, or hydrofluoric acid with carbonated water or pure water can be used for washing. Alternatively, ultrasonic cleaning can be performed using pure water or carbonated water.

[0299] Due to the aforementioned dry etching or washing processes, the thickness of the region in oxide 230b that does not overlap with oxides 243a and 243b is sometimes thinner than the thickness of the region in oxide 230b that overlaps with oxides 243a and 243b (see Figures 11A to 11D).

[0300] Heat treatment can be performed after the etching or washing described above. For example, heat treatment can be performed at a temperature above 100°C and below 450°C, more preferably above 350°C and below 400°C. Alternatively, heat treatment can be performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby reducing oxygen vacancies (VO). Furthermore, heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0301] Next, an oxide film 230C is formed (see Figures 12A to 12D). Alternatively, a heat treatment can be performed before forming the oxide film 230C. This heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed continuously without exposure to the atmosphere. Furthermore, this heat treatment is preferably performed in an atmosphere containing oxygen. By performing this treatment, moisture and hydrogen adhering to the surface of oxide 230b can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower, more preferably 150°C or higher and 350°C or lower. In this embodiment, the heat treatment temperature is 200°C, and the heat treatment is performed under reduced pressure.

[0302] Preferably, the oxide film 230C is formed in contact with at least a portion of the top surface of the oxide 230b, a portion of the side surface of the oxide 243, a portion of the side surface of the conductor 242, a portion of the side surface of the insulator 272, a portion of the side surface of the insulator 273, and a portion of the side surface of the insulator 280. Since the conductor 242 is surrounded by the oxide 243, the insulator 272, the insulator 273, and the oxide film 230C, the decrease in conductivity caused by the oxidation of the conductor 242 can be suppressed in subsequent processes.

[0303] The oxide film 230C can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Preferably, the ratio of Ga atoms relative to In in the oxide film 230C is greater than that in the oxide film 230B. In this embodiment, the oxide film 230C is formed using a sputtering method with a target material having an In:Ga:Zn ratio of 1:3:4 [atomic ratio].

[0304] Alternatively, the oxide film 230C can also be a stack. For example, it can be formed by sputtering using a target with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio], followed by continuous film formation using a target with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio].

[0305] During the formation of oxide film 230C, sometimes a portion of the oxygen contained in the sputtering gas is supplied to oxides 230a and 230b. Alternatively, during the formation of oxide film 230C, a portion of the oxygen contained in the sputtering gas is supplied to insulator 280. Therefore, the oxygen content in the sputtering gas of oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0306] Next, a heat treatment can be performed. This heat treatment can also be carried out under reduced pressure, wherein an insulating film 250A is continuously formed without exposure to the atmosphere. By performing this heat treatment, moisture and hydrogen adhering to the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxides 230a, 230b, and oxide film 230C are reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C.

[0307] Next, an insulating film 250A is formed on the oxide film 230C (see Figures 12A to 12D). The insulating film 250A can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Furthermore, it is preferable to form the insulating film 250A using the aforementioned film-forming method that uses hydrogen atoms to reduce or remove gases. This reduces the hydrogen concentration of the insulating film 250A. Since the insulating film 250A becomes the insulator 250 that comes into contact with the oxide 230C in subsequent processes, it is preferable to reduce its hydrogen concentration as described above.

[0308] Next, high-frequency irradiation, such as microwaves or RF, can be applied. The irradiated high-frequency microwaves or RF penetrate into the insulator 280, oxide 230b, and oxide 230a, removing hydrogen from them. Specifically, in oxide 230a and oxide 230b, a reaction occurs where the VOH bond is broken, causing dehydrogenation. Some of the hydrogen produced at this time is sometimes removed from oxide 230 and insulator 280. Furthermore, some of the hydrogen is sometimes getted by conductor 242. In this way, by irradiating with high-frequency microwaves or RF, the hydrogen concentration in insulator 280, oxide 230b, and oxide 230a can be reduced.

[0309] Alternatively, oxygen free radicals can be formed by plasma treatment of oxygen gas using high frequencies such as microwaves or RF. That is, insulator 280, oxide 230b, and oxide 230a can be plasma-treated in an oxygen-containing atmosphere. This treatment is sometimes referred to as oxygen plasma treatment. Furthermore, the oxygen free radicals formed can supply oxygen to insulator 280, oxide 230b, and oxide 230a. Additionally, when plasma-treating insulator 280, oxide 230b, and oxide 230a in an oxygen-containing atmosphere, structures where oxide 230 is not easily irradiated by microwaves or RF can be employed.

[0310] Oxygen plasma treatment is preferably performed using a microwave processing apparatus, for example, a power supply that generates high-density plasma using microwaves. Furthermore, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. By using high-density plasma, high-density oxygen free radicals can be generated. By applying RF to one side of the substrate, oxygen ions generated by the high-density plasma are efficiently introduced into the insulator 280 and the oxide 230. The above-mentioned oxygen plasma treatment is preferably performed under reduced pressure, and the pressure is 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and more preferably 400 Pa or more. An oxygen flow ratio (O2 / O2+Ar) of 50% or less is used, preferably 10% or more and 30% or less. A processing temperature of around 400°C is acceptable, for example. Alternatively, after the oxygen plasma treatment, continuous heating treatment can be performed without exposure to external gas.

[0311] Next, conductive films 260A (conductive films 260Aa and 260Ab) are formed (see Figures 13A to 13D). Conductive films 260Aa and 260Ab can be formed using sputtering, CVD, MBE, PLD, or ALD methods. For example, CVD is preferred. In this embodiment, conductive film 260Aa is formed using ALD, and conductive film 260Ab is formed using CVD.

[0312] Next, the oxide film 230C, insulating film 250A, conductive film 260Aa and conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, forming oxide 230c, insulator 250 and conductor 260 (conductor 260a and conductor 260b) (see Figures 14A to 14D).

[0313] Next, a heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280. Furthermore, after the above heat treatment, insulator 282 is continuously formed without exposure to the atmosphere.

[0314] Next, insulator 282 is formed on conductor 260, oxide 230c, insulator 250, and insulator 280. Insulator 282 can be formed by sputtering, CVD, MBE, PLD, or ALD (see Figures 15A to 15D).

[0315] As the insulator 282, aluminum oxide is preferably formed by sputtering, for example. By forming the insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 during film formation. In this case, it is preferable to form the insulator 282 while heating the substrate. Furthermore, by forming the insulator 282 in contact with the top surface of the conductor 260, it is preferable to suppress the absorption of oxygen contained in the insulator 280 by the conductor 260 during subsequent heat treatment.

[0316] Here, before forming insulator 282, a metal oxide can be formed in an oxygen-containing atmosphere using sputtering, and then the process of removing the metal oxide can be repeated more than once. This process allows excess oxygen to be injected into insulator 280. Furthermore, by repeating this process multiple times, the amount of excess oxygen in insulator 280 can be appropriately adjusted.

[0317] Furthermore, it is preferable to perform heat treatment after the insulator 282 is formed (the curve shown in Figure 15B represents the heat treatment). Specifically, the heat treatment is performed at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and even more preferably 8 hours or more.

[0318] Through this heat treatment, hydrogen in oxide 230 can diffuse to the outside through insulators 280 and 282. In other words, hydrogen in transistor 200 can diffuse to the outside through insulators 280 and 282, thereby reducing the hydrogen concentration in transistor 200 and insulator 282. This means that the absolute amount of hydrogen present in the semiconductor device can be reduced.

[0319] Next, a portion of insulator 282, a portion of insulator 280, a portion of insulator 273, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, a portion of the film that becomes insulator 216, a portion of the film that becomes insulator 214, and a portion of insulator 212 are processed to form insulator 216 and insulator 214, thereby forming an opening reaching insulator 211 (see Figures 16A to 16D). This opening is sometimes formed around transistor 200. Alternatively, the opening is sometimes formed around multiple transistors 200. Therefore, in this opening, a portion of the side surface of insulator 282, a portion of the side surface of insulator 280, a portion of the side surface of insulator 273, a portion of the side surface of insulator 272, a portion of the side surface of insulator 224, a portion of the side surface of insulator 222, a portion of the side surface of insulator 216, a portion of the side surface of insulator 214, and a portion of the side surface of insulator 212 are exposed.

[0320] A portion of insulator 282, a portion of insulator 280, a portion of insulator 273, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, a portion of the film forming insulator 216, a portion of the film forming insulator 214, and a portion of insulator 212 can be processed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, this processing can also be performed under different conditions.

[0321] At this time, the insulator 280 can also be irradiated with microwaves or RF or other high-frequency signals. The irradiated microwaves or RF or other high-frequency signals penetrate into the insulator 280, oxide 230b, and oxide 230a, thereby removing hydrogen from them. For example, in oxide 230a and oxide 230b, a reaction occurs in which the VOH bond is cleaved, causing them to be dehydrogenated. At this time, some of the hydrogen produced is sometimes removed from oxide 230 and insulator 280. In addition, some of the hydrogen is sometimes getted by conductor 242.

[0322] Next, insulator 287A is formed by covering insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212 (see Figures 17A to 17D). Preferably, insulator 287A is formed under the same conditions as insulator 282. For example, insulator 287A can be formed by sputtering, CVD, MBE, PLD, or ALD methods.

[0323] Specifically, the insulator 287A is preferably formed by sputtering, for example. By sputtering the insulator 287A in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during film formation. In this case, it is preferable to form the insulator 287A while heating the substrate. Furthermore, since the insulator 282 is formed in contact with the top surface of the conductor 260, it is preferable to prevent the absorption of oxygen contained in the insulator 280 by the conductor 260 during the film formation process of the insulator 287A.

[0324] Then, anisotropic etching is performed on insulator 287A to form insulator 287 on the side surfaces of insulator 282, insulator 280, insulator 273, insulator 272, insulator 224, insulator 222, insulator 216, insulator 214 and insulator 212 (see Figures 18A to 18D).

[0325] Here, when the side end of insulator 282 contacts the top end of insulator 287 and the side end of insulator 214 contacts the bottom end of insulator 287, a structure of sealed transistor 200 and insulator 280 can be formed.

[0326] As a method of anisotropic etching, dry etching is preferred. This removes the insulating film formed on a surface substantially parallel to the substrate surface, thereby forming an insulator 287 in a self-aligned manner.

[0327] Furthermore, it is preferable to perform heat treatment after the insulator 287 is formed (the curve shown in Figure 18B represents the heat treatment). Specifically, the heat treatment is performed at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and even more preferably 8 hours or more.

[0328] Through this heat treatment, hydrogen in oxide 230 can diffuse to the outside through insulators 280, 282, and 287. In other words, hydrogen in transistor 200 can diffuse to the outside through insulators 280, 282, and 287, thereby reducing the hydrogen concentration in transistor 200, insulators 282, and 287. This means that the absolute amount of hydrogen present in the semiconductor device can be reduced.

[0329] Additionally, an insulator 283 is formed covering insulators 282, 287, and 211 (see Figures 19A to 19D). The insulator 283 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Furthermore, the insulator 283 can also have a multilayer structure. For example, silicon nitride can be formed by sputtering, and then silicon nitride can be formed on top of this silicon nitride using CVD. As shown in Figures 19A to 19D, the insulator 283 contacts the insulator 211 at the bottom surface of the aforementioned opening. That is, the top and side surfaces of the transistor 200 are surrounded by the insulator 283, while the bottom surface is surrounded by the insulator 211. In this way, by surrounding the transistor 200 with highly barrier-resistant insulators 283 and 211, moisture and hydrogen can be prevented from entering from the outside.

[0330] Next, a heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment allows the oxygen added during the formation of insulator 282 to diffuse into insulator 280, and the oxygen is supplied to oxides 230a and 230b via oxide 230c. In this way, oxide 230 is subjected to an oxidation treatment to fill the oxygen vacancies in oxide 230 (oxide 230b) with oxygen.

[0331] Furthermore, the hydrogen remaining in oxide 230 diffuses through insulator 280 to insulator 282 and insulator 287, where it is captured or fixed by insulator 287. In other words, the recombination of hydrogen remaining in oxide 230 with oxygen vacancies to form VOH can be suppressed. Additionally, this heat treatment is not limited to being performed after the formation of insulator 283, but can also be performed after the formation of insulator 282.

[0332] Alternatively, insulator 284 can be formed on insulator 283 (see Figures 20A to 20D). Preferably, insulator 284 is formed using a film-forming method with high coverage. For example, insulator 284 can be formed by sputtering, CVD, MBE, PLD, or ALD. Insulator 284 is preferably made of the same material as insulator 212 and insulator 283.

[0333] Specifically, silicon nitride is preferably formed by CVD. In particular, it is preferred to use a compound gas that does not contain hydrogen atoms or has a low hydrogen atom content and to form the insulator 284 by CVD.

[0334] By forming the insulator 284 using a film-forming method that reduces or removes hydrogen atoms, the amount of hydrogen contained in the insulator 284 can be reduced. In other words, the hydrogen concentration contained in the insulator 284 can be reduced to decrease the amount of hydrogen mixed into the channel-forming region of the oxide semiconductor.

[0335] Next, an insulating film, which becomes insulator 274, is formed on insulator 284. The insulating film, which becomes insulator 274, can be formed by sputtering, CVD, MBE, PLD, or ALD methods. Furthermore, it is preferable to form the insulating film, which becomes insulator 274, using the aforementioned film-forming method that reduces or removes hydrogen atoms. This reduces the hydrogen concentration in the insulating film, which becomes insulator 274.

[0336] Next, the insulating film that becomes insulator 274 is subjected to CMP treatment to form an insulator 274 with a flat top surface (see Figures 21A to 21D).

[0337] Next, openings leading to the conductor 242 are formed in insulators 272, 273, 280, 282, 283, and 284 (see Figures 22A to 22D). These openings can be formed using photolithography. Note that in Figure 22A, the opening is circular in top view, but it is not limited to this. For example, in top view, the opening can also have a generally circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape with rounded corners.

[0338] Next, an insulating film is formed to become insulator 241, and the insulating film is anisotropically etched to form insulator 241 (see Figures 22A to 22D). The insulating film to become insulator 241 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. As the insulating film to become insulator 241, it is preferable to use an insulating film that has the function of inhibiting oxygen permeation. For example, it is preferable to form aluminum oxide by the PEALD method. Alternatively, similar to the formation of insulator 283, it is preferable to form silicon nitride by the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferable.

[0339] Furthermore, anisotropic etching of the insulating film, which serves as insulator 241, can be performed, for example, by dry etching. By providing insulator 241 on the sidewall of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0340] Next, conductive films serving as conductors 240a and 240b are formed. Preferably, the conductive films serving as conductors 240a and 240b are multilayer structures comprising conductors that suppress the permeation of impurities such as water and hydrogen. For example, they can be multilayers of tantalum nitride, titanium nitride, tungsten, molybdenum, copper, etc. The conductive films serving as conductors 240a and 240b can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0341] Next, by performing CMP processing, a portion of the conductive film that forms conductors 240a and 240b is removed, exposing the top surfaces of insulators 284 and 274. As a result, the conductive film remains only at the openings, thereby forming conductors 240a and 240b with flat top surfaces (see Figures 22A to 22D). Note that sometimes a portion of the top surface of insulator 284 and a portion of the top surface of insulator 274 are removed due to this CMP processing.

[0342] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD or ALD, etc.

[0343] Next, the conductive film that becomes conductor 246 is processed by photolithography to form conductor 246a, which is in contact with the top surface of conductor 240a, and conductor 246b, which is in contact with the top surface of conductor 240b. At this time, a portion of the insulator 284 in the area where conductor 246a and conductor 246b do not overlap with insulator 284 is sometimes removed (see Figures 23A to 23D).

[0344] Next, insulator 286 is formed on conductor 246 and insulator 284 (see Figures 4A to 4D). Alternatively, insulator 286 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Insulator 286 can also have a multilayer structure. For example, silicon nitride can be formed by sputtering, and silicon nitride can be formed on this silicon nitride by CVD. When insulator 286 is formed on conductor 246 and insulator 284, the top and side surfaces of conductor 246 are in contact with insulator 286, while the bottom surface of conductor 246 is in contact with insulator 284. That is, conductor 246 can have a structure surrounded by insulator 284 and insulator 286. By adopting this structure, the permeation of oxygen from the outside can be suppressed to prevent oxidation of conductor 246. Furthermore, it is preferable to prevent impurities such as water and hydrogen from diffusing outward from conductor 246.

[0345] Using the above-described process, a semiconductor device including the transistor 200 shown in Figures 4A to 4C can be manufactured. As shown in Figures 7A to 23D, the transistor 200 can be manufactured using the semiconductor device manufacturing method shown in this embodiment.

[0346] <Application Examples of Semiconductor Devices> Hereinafter, with reference to FIGS. 24A and 24B to 29, an example of a semiconductor device according to an embodiment of the present invention, including a transistor 200, will be described, which differs from the semiconductor device shown in <Structure Example 1 of Semiconductor Device> described above. Note that in the semiconductor devices shown in FIGS. 24A and 24B to 29, the same element symbols are added to the structures having the same components as those constituting the semiconductor device shown in <Structure Example 1 of Semiconductor Device> (refer to FIGS. 4A to 4D). In this section, the materials used as constituent materials of the transistor 200 may be the materials described in detail in <Structure Example 1 of Semiconductor Device>.

[0347] <<Application Examples of Semiconductor Devices 1>> Figures 24A and 24B show a structure in which multiple transistors 200_1 to 200_n (where n represents a natural number greater than 3) are sealed by insulators 283 and 211. Figures 24A and 24B show transistors 200_1 to 200_n arranged along the length of the channel, but are not limited to this arrangement. Transistors 200_1 to 200_n can be arranged either along the width of the channel or configured in a matrix. Furthermore, they can be arranged irregularly depending on the design.

[0348] As shown in Figure 24A, a portion (hereinafter sometimes referred to as sealing portion 265) in contact with insulator 283 and insulator 211 is formed on the outer side of multiple transistors 200_1 to 200_n. Sealing portion 265 is formed to surround multiple transistors 200_1 to 200_n. By adopting this structure, multiple transistors 200_1 to 200_n can be surrounded by insulator 283 and insulator 211. Therefore, a group of multiple transistors surrounded by sealing portion 265 is provided on the substrate.

[0349] Alternatively, a cutting line (sometimes called a dividing line, slit line, or cut-off line) may be provided overlapping the sealing portion 265. Because the substrate is divided by the cutting line, the transistor group surrounded by the sealing portion 265 is taken out as a wafer.

[0350] Figure 24A shows an example of a plurality of transistors 200_1 to 200_n surrounded by a sealing portion 265, but it is not limited to this. As shown in Figure 24B, the plurality of transistors 200_1 to 200_n can also be surrounded by multiple sealing portions. In Figure 24B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a, and the transistors are also surrounded by an outer sealing portion 265b.

[0351] In this way, when multiple sealing portions surround multiple transistors 200_1 to 200_n, the contact area between insulator 283 and insulator 211 increases, thus further improving the tightness of the connection between insulator 283 and insulator 211. Therefore, the multiple transistors 200_1 to 200_n can be sealed more securely.

[0352] In this case, the cutting line can be provided overlapping with the sealing part 265a or the sealing part 265b, or the cutting line can be provided between the sealing part 265a and the sealing part 265b.

[0353] <<Application Examples of Semiconductor Devices 2>> Figure 25 is a cross-sectional view of transistor 200. The structure of transistor 200 shown in Figure 25 differs from that of transistor 200 shown in Figures 4A to 4D in that it does not include oxide 230b. That is, in transistor 200 shown in Figure 25, oxide 230 is composed of oxide 230a, oxide 230c1, and oxide 230c2. Furthermore, the bottom surface of conductor 242a and the bottom surface of conductor 242b are in contact with oxide 230a.

[0354] When oxide 230 adopts a stacked structure of oxide 230a, oxide 230c1 and oxide 230c2, it has the following excellent effects.

[0355] For example, when oxide 230a has an In:Ga:Zn ratio of 1:3:4, oxide 230c1 has an In:Ga:Zn ratio of 4:2:3, and oxide 230c2 has an In:Ga:Zn ratio of 1:3:4, a channel forming region can be provided in oxide 230c1. When this structure is adopted, U-shaped oxides 230c1 and 230c2 are formed along the openings formed in insulators 280, 272, 273, conductors 242 (conductors 242a and 242b), and oxide 230a. Furthermore, the side surfaces of conductors 242a and 242b can be in contact with the side surfaces of oxide 230c1. Furthermore, the top surface of oxide 230c1 is in contact with oxide 230c2, thus preventing insulator 250 from contacting oxide 230c1.

[0356] By adopting the above structure, the contact area between conductors 242 (conductors 242a and 242b) and oxide 230c1 can be reduced. Reducing the contact area between conductors 242 and oxide 230c1 reduces the junction drain current generated between them. Furthermore, by adjusting the thickness of conductor 242, the contact area with oxide 230c1 can be arbitrarily adjusted.

[0357] For example, the semiconductor device including transistor 200 shown in Figure 25 is suitable for use in outer space, such as in space shuttles or artificial satellites. In outer space, cosmic rays or electrons or protons emitted by the sun can enter the semiconductor device and affect its properties. Because the junction drain current is reduced in the transistor 200 shown in Figure 25, it can be said that the transistor 200 has high resistance to cosmic rays and other harmful substances, and its reliability is high.

[0358] <<Application Examples of Semiconductor Devices 3>> Figures 26A, 26B, 27A, and 27B are diagrams illustrating the memory device 290. Figure 26A is a top view of the memory device 290, and Figure 26B is a cross-sectional view along the dotted line A1-A2 shown in Figure 26A. Note that the cross-sectional view shown in Figure 26B corresponds to a cross-sectional view along the channel length direction of the transistor.

[0359] Figure 27A is a cross-sectional view along the dotted line A3-A4 shown in Figure 26A, and Figure 27B is a cross-sectional view along the dotted line A5-A6 shown in Figure 26A. Note that the cross-sectional view shown in Figure 27A corresponds to a cross-sectional view along the channel width direction of the transistor.

[0360] The memory device 290 shown in Figures 26A, 26B, 27A, and 27B includes a transistor, a capacitor device 292, and wiring connected to the transistor. Specifically, the memory device 290 includes an insulator 211, an insulator 212 on the insulator 211, an insulator 214 on the insulator 212, conductors 205 (conductors 205a and 205b), an insulator 216 on the insulator 214, an insulator 222, an insulator 224, oxides 230 (oxides 230a, 230b, and 230c), conductors 242 (conductors 242a and 242b), oxides 243 (oxides 243a and 243b), an insulator 272, an insulator 273, an insulator 250, and conductors 260 (conductors 260a and 260b).

[0361] An insulator 280 and an insulator 282 on the insulator 280 are disposed above the oxide 230. An insulator 287 is disposed in contact with the sides of insulators 212, 214, 216, 222, 224, 272, 273, 280, and 282. An insulator 283 and an insulator 284 on the insulator 283 are disposed to cover the insulator 282.

[0362] The memory device 290 is electrically connected to the conductor 242a and includes a conductor 240a that serves as a plug. Note that an insulator 241a is provided in contact with the side of the conductor 240a. A conductor 246a, electrically connected to the conductor 240a and used as wiring, is provided on the insulator 284 and the conductor 240a. An insulator 286 is provided on the conductor 246a and the insulator 274.

[0363] The memory device 290 includes a capacitor device 292. The capacitor device 292 includes a conductor 242b, insulators 272 and 273 disposed on the conductor 242b, and a conductor 294 disposed on the insulator 273. In other words, the capacitor device 292 constitutes a Metal-Insulator-Metal (MIM) capacitor. Note that one of the pair of electrodes included in the capacitor device 292, namely the conductor 242b, can also serve as the source or drain electrode of the transistor. The dielectric layer included in the capacitor device 292 can also serve as a protective layer disposed in the transistor, namely, the insulators 272 and 273. Therefore, the manufacturing process of the capacitor device 292 can also incorporate a portion of the transistor manufacturing process, enabling the production of highly productive semiconductor devices.

[0364] As shown in Figure 27B, in the cross-section along the channel width direction of the transistor, the capacitor device 292 has a region overlapping with the conductor 294 on the side of the conductor 242b. An electrostatic capacitance can be formed in this region, thus increasing the electrostatic capacitance value even with a small area.

[0365] As conductor 294, for example, a material that can be used for conductor 242 can be used.

[0366] In memory device 290, conductor 260 is used as the first gate of the transistor, and conductor 205 is used as the second gate of the transistor. In addition, conductors 242a and 242b are used as source electrodes or drain electrodes.

[0367] Oxide 230 is used as a semiconductor including the channel forming region of the transistor. Insulator 250 is used as a first gate insulator, and insulators 222 and 224 are used as second gate insulators.

[0368] Insulators 214, 272, and 273 are used as interlayer films. Insulators 214, 272, and 273 are preferably formed using materials that block oxygen or are capable of absorbing hydrogen. By using materials capable of absorbing hydrogen in insulators 214, 272, and 273, the amount of hydrogen within the memory device 290 can be kept constant. Materials suitable for insulators 214, 272, and 273 can be Al compounds or compounds containing Al and element Ma (element Ma is a low electronegativity element (a highly reactive element) such as Mg, Zr, Si, B, etc.).

[0369] As shown in Figures 26B, 27A, and 27B, the transistor included in the memory device 290 has a structure in which the insulator 282 is in direct contact with the oxide 230c. By employing this structure, the diffusion of oxygen contained in the insulator 280 towards the conductor 260 can be suppressed. Furthermore, the oxygen contained in the insulator 280 can be efficiently supplied to oxides 230a and 230b via the oxide 230c, thereby reducing oxygen vacancies in oxides 230a and 230b and improving the electrical characteristics and reliability of the transistor.

[0370] Furthermore, in the transistors included in the memory device 290 shown in Figures 26A and 26B, a conductor 260 is formed in a self-aligned manner with the insulator 250 in the opening of the interlayer film provided in the insulator 280, etc. That is, the conductor 260 is formed by embedding it into the opening of the interlayer film including the insulator 280 with the insulator 250 in between; therefore, alignment of the conductor 260 is not required in the region between the conductors 242a and 242b.

[0371] Preferably, oxide 230c is disposed within an opening in the interlayer film including insulator 280. Therefore, insulator 250 and conductor 260 include regions overlapping the stacked structures of oxide 230c with oxides 230b and 230a. By employing this structure, oxide 230c and insulator 250 can be continuously formed, thereby maintaining the cleanliness of the interface between oxide 230 and insulator 250. Therefore, the influence of interface scattering on carrier conduction is reduced, allowing the transistors included in memory device 290 to achieve high on-state current and high frequency characteristics.

[0372] Furthermore, the transistors included in the memory device 290 shown in Figures 26A and 26B primarily form channel forming regions at or near the interfaces of oxides 230c and 230b. Note that oxide 230c forms a U-shape along the openings formed in insulators 280, 272, 273, conductors 242 (conductors 242a, conductors 242b), oxides 243 (oxides 243a, oxides 243b), and oxide 230b.

[0373] For example, when miniaturizing the channel length of a transistor (typically 5 nm or more and shorter than 60 nm, preferably 10 nm or more and less than 30 nm), the effective channel length can be extended by employing the transistor structure of the memory device 290 shown in Figures 26A and 26B. As an example, when the distance between conductors 242a and 242b is 20 nm, the effective channel length can be set to 40 nm or more and less than 60 nm, that is, the distance between conductors 242a and 242b is approximately 2 to 3 times the minimum feature size. Therefore, the memory device 290 shown in Figures 26A and 26B can be considered one of the structures superior to miniaturized transistor and capacitor devices.

[0374] <<Application Examples of Semiconductor Devices 4>> Next, with reference to Figures 28 and 29, an application example of the memory device 290 shown in Figures 26A, 26B, 27A, and 27B will be described.

[0375] Figures 28 and 29 are examples of cross-sectional views of a memory device having a structure in which multiple memory devices 290 are stacked in the longitudinal direction.

[0376] Figure 28 illustrates the structure of stacked memory devices 290_1, 290_2, and 290_n (where n represents a natural number greater than 3). Note that, as shown in Figure 28, memory device 290_2 has a structure where the position of the conductor 240a, used as a connector, differs from that of memory device 290_1. This structure has the effect of reducing parasitic capacitance between adjacent memory devices or improving the flexibility of circuit design. Note that although Figure 28 shows a structure where the position of the conductor 240a, used as a connector, is different from that of the memory devices above and below it, it is not limited to this. For example, the conductor 240a and capacitor 292 can be arranged in a 1 / 4-degree rotation around conductor 260 when viewed from above.

[0377] Furthermore, in the cross-section along the channel width, the conductor 240a, which serves as a plug, can be positioned at the same location. Figure 29 shows an example of this structure. With the structure shown in Figure 29, for example, write bit lines can be shared between adjacent memory devices. That is, bit lines can be shared among multiple memory devices 290, thus this structure is advantageous for miniaturization. Note that although Figure 29 shows a structure where the conductor 240a, which serves as a plug, shares an electrical connection to a bit line with adjacent memory devices, it is not limited to this. For example, a structure in which the back gate electrode of a transistor is shared between adjacent memory devices can be used.

[0378] In Figures 28 and 29, memory devices 290_1, 290_2, and 290_n are covered by insulators 287, 283, and 284. Insulator 283 and insulator 211 are in contact with the outer edge of memory device 290_1. Above insulator 284, insulator 284 is in contact with insulator 286.

[0379] An insulator 282, an insulator 296, an insulator 298 and an insulator 214 are provided between the memory device 290_1 and the memory device 290_2.

[0380] As insulators 296 and 298, the same materials as insulator 211 can be used, for example. For example, alumina can be used to form insulators 282 and 214, and silicon nitride can be used to form insulators 286 and 298.

[0381] In the transistor 200 shown in Figures 4A to 4D, a three-layer structure of insulators 211, 212, and 214 is present below the conductor 205. However, in the transistors included in the memory devices 290_2 to 290_n shown in Figures 28 and 29, a portion of the top layer of the transistors included in the lower memory device can be shared, thereby reducing one or two layers of the three-layer structure. In other words, by sharing a portion of the insulator between a memory device and the memory devices above and below it, highly productive semiconductor devices can be manufactured.

[0382] According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with normally-off electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device capable of miniaturization or hyper-integration can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0383] At least a portion of this embodiment can be implemented in combination with other embodiments and examples described in this specification.

[0384] Implementation Method 2 In this embodiment, one embodiment of a semiconductor device that can be used in other embodiments of the present invention is described. Structural examples of the semiconductor device are described below.

[0385] <Structure Example of a Semiconductor Device 2> Figure 30A is a cross-sectional view of the 2100A transistor along its channel length.

[0386] Transistor 2100A is disposed on substrate 2102 and includes insulating layers 2121, 2122, 2123, conductive layer 2106, insulating layer 2103, semiconductor layer 2108, insulating layer 2110, metal oxide layer 2114, conductive layer 2112, insulating layer 2124, insulating layer 2125, and insulating layer 2126. Insulating layers 2121, 2122, and 2123 are sequentially disposed on substrate 2102. Conductive layer 2106 is disposed on insulating layer 2123, and insulating layer 2103 is disposed on both insulating layers 2123 and conductive layer 2106. Island-shaped semiconductor layer 2108 is disposed on insulating layer 2103 and includes a region overlapping a portion of conductive layer 2106. Insulating layer 2110 is disposed on semiconductor layer 2108. The metal oxide layer 2114 and the conductive layer 2112 are sequentially stacked on the insulating layer 2110 and have a region that overlaps with a portion of the semiconductor layer 2108 and a portion of the conductive layer 2106.

[0387] Insulating layer 2124 has a region in contact with a portion of insulating layer 2123 and is disposed on conductive layer 2106, insulating layer 2103, semiconductor layer 2108, insulating layer 2110, metal oxide layer 2114, and conductive layer 2112. Insulating layer 2125 has a region in contact with a portion of insulating layer 2122 and insulating layer 2121 and is disposed on insulating layer 2124. Furthermore, insulating layer 2126 is disposed on insulating layer 2125.

[0388] In transistor 2100A, preferably, at least semiconductor layer 2108 is disposed between insulating layer 2123 and insulating layer 2124, with insulating layer 2123 and insulating layer 2124 in contact with each other on the outer side of semiconductor layer 2108. Insulating layer 2123 and insulating layer 2124 are disposed between insulating layer 2121 and insulating layer 2122 and insulating layer 2125 and insulating layer 2126. In this case, insulating layer 2125 is preferably in contact with at least insulating layer 2122, and more preferably in contact with insulating layer 2121.

[0389] In other words, in transistor 2100A, semiconductor layer 2108 is surrounded by insulating layers 2123 and 2124, and semiconductor layer 2108, insulating layers 2123 and 2124 are surrounded by insulating layers 2122 and 2125. Furthermore, since semiconductor layer 2108, insulating layers 2123, 2124, 2122 and 2125 are arranged in a manner sandwiched between insulating layer 2121 and insulating layer 2126, they can be said to be surrounded by insulating layer 2121 and insulating layer 2126.

[0390] In other words, the sealing structure provided using insulating layers 2123 and 2124 is equivalent to the sealing structure provided using insulators 214, 287, and 282 as described in the above embodiment. Therefore, insulating layers 2123 and 2124 can be referred to the descriptions of insulators 214, 287, and 282.

[0391] Furthermore, the sealing structure provided using insulating layers 2121, 2122, and 2125 is equivalent to the sealing structure provided using insulators 211, 212, and 283 described in the above embodiment. Therefore, insulating layers 2122 and 2125 can be referred to the descriptions of insulators 211, 212, and 283.

[0392] Furthermore, the insulating layer 2126 corresponds to the insulator 284 described in the above embodiment. Therefore, the insulating layer 2126 can be described with reference to the description of the insulator 284.

[0393] The ends of the conductive layer 2112 and the metal oxide layer 2114 are located inside the ends of the insulating layer 2110. In other words, the insulating layer 2110 has at least a portion on the semiconductor layer 2108 that protrudes to the outside of the ends of the conductive layer 2112 and the metal oxide layer 2114.

[0394] The end of the conductive layer 2112 is preferably located inside the end of the metal oxide layer 2114. The insulating layer 2124 is provided in such a way that it contacts a portion of the top surface and the side surface of the metal oxide layer 2114.

[0395] In transistor 2100A, the end of conductive layer 2112 is located inside the end of metal oxide layer 2114. In other words, metal oxide layer 2114 has at least a portion on insulating layer 2110 that protrudes to the outside of the end of conductive layer 2112.

[0396] When the end of the conductive layer 2112 is located inside the end of the metal oxide layer 2114, the steps on the sides of the conductive layer 2112 and the metal oxide layer 2114 are gentle, and the step coverage of the layers (e.g., insulating layer 2124, insulating layer 2125, insulating layer 2126) formed on the conductive layer 2112 and the metal oxide layer 2114 is improved, thereby suppressing problems such as breaks or voids in the layer.

[0397] To form the conductive layer 2112 and the metal oxide layer 2114, a wet etching method can be appropriately used. By using a material in the metal oxide layer 2114 with a lower etching rate than the conductive layer 2112, the end of the conductive layer 2112 can be located inside the end of the metal oxide layer 2114. Furthermore, by forming the metal oxide layer 2114 and the conductive layer 2112 using the same process, productivity can be improved.

[0398] Note that this embodiment is not limited to the description above. The end of the conductive layer 2112 may be aligned with the end of the metal oxide layer 2114. Furthermore, the side surface of the conductive layer 2112 and the side surface of the metal oxide layer 2114 may be on the same plane.

[0399] Semiconductor layer 2108 includes a pair of regions 2108L sandwiching the channel forming region and a pair of regions 2108N outside the channel forming region. Region 2108L is a region in semiconductor layer 2108 that overlaps with insulating layer 2110 but does not overlap with metal oxide layer 2114 and conductive layer 2112.

[0400] Region 2108C is used as a channel forming region. Here, the metal oxide layer 2114, when conductive, is used as part of the gate electrode, and thus the gate electrode applies an electric field to region 2108C through the insulating layer 2110, which serves as the gate insulating layer, forming a channel in region 2108C. However, this embodiment is not limited to this. Sometimes, a channel is also formed in the portion that overlaps with the conductive layer 2106 but not with the metal oxide layer 2114 (the portion having regions 2108L and 2108N).

[0401] Region 2108L is used as a buffer region to mitigate the drain electric field. Region 2108L does not overlap with conductive layer 2112 and metal oxide layer 2114, and forms almost no channel when a gate voltage is supplied to conductive layer 2112. The carrier concentration in region 2108L is preferably higher than that in region 2108C. Therefore, region 2108L can be used as an LDD region.

[0402] Compared to region 2108C, region 2108L can be described as a region with the same or lower electrical resistance, the same or higher carrier concentration, the same or higher oxygen vacancy density, and the same or higher impurity concentration.

[0403] Compared to region 2108N, region 2108L can be described as a region with the same or higher electrical resistance, the same or lower carrier concentration, the same or lower oxygen vacancy density, and the same or lower impurity concentration.

[0404] Thus, by setting a region 2108L, which is used as an LDD region, between region 2108C of the channel forming region and region 2108N of the source region or drain region, a highly reliable transistor that can simultaneously achieve high drain voltage and high on-state current can be realized.

[0405] Region 2108N is used as a source or drain region, and its resistance is lower than that of other regions of semiconductor layer 2108. In addition, compared with other regions of semiconductor layer 2108, region 2108N can be said to be the region with the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration.

[0406] The lower the resistance of the 2108N, the better. For example, the chip resistance of the 2108N is preferably above 1Ω / □ and less than 1×103Ω / □, and more preferably above 1Ω / □ and less than 8×102Ω / □.

[0407] Furthermore, the higher the resistance of region 2108C in the state where no channel is formed, the better. For example, the sheet resistance of region 2108C is 1×10⁹ Ω / □ or higher, preferably 5×10⁹ Ω / □ or higher, and even more preferably 1×10¹⁰ Ω / □ or higher.

[0408] When no channel is formed, the higher the resistance of region 2108C, the better, and there is no particular upper limit. However, if an upper limit is set, the chip resistance of region 2108C should be, for example, 1×10⁹ Ω / □ or higher and 1×10¹² Ω / □ or lower, preferably 5×10⁹ Ω / □ or higher and 1×10¹² Ω / □ or lower, and more preferably 1×10¹⁰ Ω / □ or higher and 1×10¹² Ω / □ or lower.

[0409] The chip resistance value of region 2108L is, for example, 1×10³ Ω / □ or higher and 1×10⁹ Ω / □ or lower, preferably 1×10³ Ω / □ or higher and 1×10⁸ Ω / □ or lower, and more preferably 1×10³ Ω / □ or higher and 1×10⁷ Ω / □ or lower. By setting the chip resistance value within the above range, a transistor with good electrical characteristics and high reliability can be achieved. Note that the chip resistance can be calculated from the resistance value. By setting region 2108L between regions 2108N and 2108C, the source-drain breakdown voltage of transistor 2100A can be improved.

[0410] Furthermore, the resistance of region 2108C in the state where no channel is formed can be more than 1×10⁶ times and less than 1×10¹² times the resistance of region 2108N, preferably more than 1×10⁶ times and less than 1×10¹¹ times, and even more preferably more than 1×10⁶ times and less than 1×10¹⁰ times.

[0411] The resistance of region 2108C in the state where no channel is formed can be more than 1×100 times and less than 1×109 times the resistance of region 2108L, preferably more than 1×101 times and less than 1×108 times, and more preferably more than 1×102 times and less than 1×107 times.

[0412] The resistance of region 2108L is more than 1×100 and less than 1×109 times the resistance of region 2108N, preferably more than 1×101 and less than 1×108 times, and even more than 1×101 and less than 1×107 times.

[0413] By placing the region 2108L with the aforementioned resistance between the region 2108N and the channel forming region, the source-drain breakdown voltage of the transistor 2100A can be improved.

[0414] The carrier concentration of semiconductor layer 2108 preferably has a distribution that increases sequentially in the order of region 2108C, region 2108L, and region 2108N. By setting region 2108L between region 2108C and region 2108N, for example, even if impurities such as hydrogen diffuse from region 2108N during the process, the carrier concentration of region 2108C can be kept extremely low.

[0415] The lower the carrier concentration of region 2108C used as the channel forming region, the better, preferably below 1×10¹⁸ cm⁻³, more preferably below 1×10¹⁷ cm⁻³, more preferably below 1×10¹⁶ cm⁻³, more preferably below 1×10¹³ cm⁻³, and more preferably below 1×10¹² cm⁻³. Note that there is no particular limitation on the lower limit of the carrier concentration of region 2108C, for example, it can be 1×10⁻⁹ cm⁻³.

[0416] On the other hand, the carrier concentration in region 2108N can be, for example, 5 × 10¹⁸ cm⁻³ or more, preferably 1 × 10¹⁹ cm⁻³ or more, and even more preferably 5 × 10¹⁹ cm⁻³ or more. There is no particular limit to the upper limit of the carrier concentration in region 2108N, for example, it can be 5 × 10²¹ cm⁻³ or 1 × 10²² cm⁻³, etc.

[0417] The carrier concentration in region 2108L can be set to a value between that in regions 2108C and 2108N. For example, it can be set to a value greater than 1 × 10¹⁴ cm⁻³ and less than 1 × 10²⁰ cm⁻³.

[0418] Note that the carrier concentration in region 2108L does not necessarily need to be uniform; sometimes it has a gradient where the carrier concentration decreases as it approaches the channel from the region 2108N side. For example, one or both of the hydrogen concentration or oxygen vacancy concentration in region 2108L may have a gradient where the concentration decreases as it approaches the channel from the region 2108N side.

[0419] Semiconductor layer 2108 preferably comprises a metal oxide. Metal oxides such as oxide 230 can be used for semiconductor layer 2108, and other embodiments or structural examples can be referred to. Furthermore, insulating layers 2103 and 2110, which are in contact with the channel formation region of semiconductor layer 2108, are preferably oxide films. For example, oxide films such as silicon oxide films, silicon oxynitride films, and aluminum oxide films can be used. Thus, oxygen detached from insulating layer 2103 or insulating layer 2110 is supplied to the channel formation region of semiconductor layer 2108, thereby reducing oxygen vacancies in semiconductor layer 2108.

[0420] A portion of the end of the insulating layer 2110 is located on the semiconductor layer 2108. The insulating layer 2110 includes a portion that overlaps with the conductive layer 2112 and is used as a gate insulating layer, and a portion that does not overlap with the conductive layer 2112 and the metal oxide layer 2114 (that is, the portion that overlaps with region 2108L).

[0421] The insulating layer 2110 can have a stacked structure of two or more layers. Figure 30A shows an example of a three-layer structure where the insulating layer 2110 has an insulating layer 2110a, an insulating layer 2110b on the insulating layer 2110a, and an insulating layer 2110c on the insulating layer 2110b. Note that insulating layers 2110a, 2110b, and 2110c can use insulating films of the same material, and sometimes it is not possible to clearly identify the interfaces of each insulating layer 2110a, 2110b, and 2110c. Therefore, in this embodiment, the interfaces of insulating layers 2110a, 2110b, and 2110c are shown by dashed lines.

[0422] Insulating layer 2110a has a region in contact with the channel forming region of semiconductor layer 2108. Insulating layer 2110c has a region in contact with metal oxide layer 2114. Insulating layer 2110b is located between insulating layer 2110a and insulating layer 2110c.

[0423] Each of insulating layers 2110a, 2110b, and 2110c is preferably an insulating film containing oxides. In this case, insulating layers 2110a, 2110b, and 2110c are preferably formed continuously using the same film-forming apparatus.

[0424] For example, as insulating layers 2110a, 2110b, and 2110c, one or more insulating layers selected from silicon oxide film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film may be used.

[0425] Furthermore, the insulating layer 2110 in contact with the semiconductor layer 2108 is preferably a stacked structure having an oxide insulating film, and more preferably has a region having an oxygen content exceeding the stoichiometric composition. In other words, the insulating layer 2110 has an insulating film capable of releasing oxygen. For example, by forming the insulating layer 2110 in an oxygen atmosphere, subjecting the formed insulating layer 2110 to heat treatment, plasma treatment, or forming an oxide film on the insulating layer 2110 in an oxygen atmosphere, oxygen can be supplied to the insulating layer 2110. In particular, the insulating layer 2110A in contact with the semiconductor layer 2108 preferably contains excess oxygen, similar to the insulator 280 described in the above embodiment.

[0426] For example, insulating layers 2110a, 2110b, and 2110c can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD.

[0427] In particular, insulating layers 2110a, 2110b and 2110c are preferably formed by plasma CVD.

[0428] Similar to insulator 250, insulating layer 2110c is preferably an extremely dense film with reduced surface defects compared to insulating layer 2110b, and which is less susceptible to adsorption of impurities in the atmosphere such as water.

[0429] The insulating layer 2110b is preferably formed to be thicker than the insulating layers 2110a and 2110c. For example, by using a deposition rate that is faster than that of the insulating layers 2110a and 2110c, the insulating layer 2110b can be formed to be thicker. As a result, the time required for the film formation process of the insulating layer 2110 can be shortened.

[0430] Here, because the boundaries between insulating layers 2110a and 2110b, and between insulating layers 2110b and 2110c, are sometimes unclear, these boundaries are clearly indicated by dashed lines in Figure 30A. Note that when the film densities of insulating layers 2110a and 2110b differ, these boundaries are sometimes observed as differences in contrast in images such as transmission electron microscopy (TEM) images of cross-sections of insulating layer 2110. Similarly, the boundaries between insulating layers 2110b and 2110c can sometimes also be observed.

[0431] When the conductive layer 2112 and the metal oxide layer 2114 are formed, the thickness of the insulating layer 2110 in the region that does not overlap with the conductive layer 2112 sometimes becomes thinner. Figure 30A shows a structure in which the insulating layer 2110c in the region that does not overlap with the metal oxide layer 2114 is removed, leaving insulating layers 2110a and 2110b. Compared to the region of insulating layer 2110b that overlaps with the metal oxide layer 2114, the thickness of the insulating layer 2110b in the region that does not overlap with the metal oxide layer 2114 sometimes becomes thinner.

[0432] By reducing the thickness of the insulating layer 2110 in the region that does not overlap with the metal oxide layer 2114, the step at the end of the insulating layer 2110 is reduced, and the step coverage of the layers formed on the insulating layer 2110 (e.g., insulating layer 2124, insulating layer 2125, insulating layer 2126) is improved, thereby suppressing problems such as breaks or voids in the layer.

[0433] The insulating layer 2110 can have a structure different from that in FIG. 30A, that is, a structure in which insulating layers 2110a, 2110b, and 2110c remain in the region not overlapping with the metal oxide layer 2114. Furthermore, the thickness of the insulating layer 2110c in the region not overlapping with the metal oxide layer 2114 can be thinner than that of the insulating layer 2110c in the region not overlapping with the metal oxide layer 2114. By employing a structure in which the insulating layer 2110c remains in the region not overlapping with the metal oxide layer 2114, water adsorption to the insulating layer 2110 can be suppressed. The thickness of the insulating layer 2110c in the region overlapping with the metal oxide layer 2114 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less.

[0434] Note that insulating layer 2110 may have a two-layer structure consisting of insulating layer 2110a and insulating layer 2110c on insulating layer 2110a. Alternatively, insulating layer 2110 may have a single-layer structure. As insulating layer 2110, any one of the aforementioned insulating layers 2110a, 2110b, and 2110c may be appropriately selected as needed.

[0435] The insulating layer 2103 may have a stacked structure. Figure 30A shows an example in which insulating layers 2103a, 2103b, 2103c, and 2103d are stacked sequentially from the conductive layer 2106 side in the insulating layer 2103. The insulating layer 2103a is in contact with the conductive layer 2106. In addition, the insulating layer 2103d is in contact with the semiconductor layer 2108.

[0436] The insulating layer 2103 preferably satisfies one or more of the following conditions, and more preferably satisfies all of the following conditions: high withstand voltage, low film stress, low susceptibility to hydrogen or water release, few defects in the film, and suppression of diffusion of the metal elements contained in the conductive layer 2106.

[0437] Of the four insulating layers included in insulating layer 2103, insulating layers 2103a, 2103b, and 2103c located on the side of conductive layer 2106 are preferably nitrogen-containing insulating films. On the other hand, insulating layer 2103d, which is in contact with semiconductor layer 2108, is preferably an oxygen-containing insulating film. Furthermore, it is preferable that all four insulating layers included in insulating layer 2103 are continuously formed using a plasma CVD apparatus in a manner that avoids contact with the atmosphere.

[0438] As insulating layers 2103a, 2103b, and 2103c, it is preferable to use insulating films containing nitrogen, such as silicon nitride film, silicon oxynitride film, aluminum nitride film, hafnium nitride film, etc. As insulating layer 2103d, an insulating film that can be used for insulating layer 2110 can be used.

[0439] The insulating layers 2103a and 2103c are preferably dense films that prevent impurities from diffusing from beneath them. The insulating layer 2103a is preferably a film capable of blocking the metallic elements contained in the conductive layer 2106, and the insulating layer 2103c is preferably a film capable of blocking hydrogen or water contained in the insulating layer 2103b. Therefore, insulating films formed at a lower deposition rate than insulating layer 2103b can be used as the insulating layers 2103a and 2103c.

[0440] On the other hand, insulating layer 2103b is preferably an insulating film formed under conditions of very low stress and high deposition rate. In addition, insulating layer 2103b is preferably formed to be thicker than insulating layers 2103a and 2103c.

[0441] For example, even when insulating layers 2103a, 2103b, and 2103c each use silicon nitride films formed by plasma CVD, the film density of insulating layer 2103b can be lower than that of the other two insulating layers. Therefore, this difference in contrast is sometimes observed in images such as transmission electron microscope images of the cross-section of insulating layer 2103. Note that because the boundaries between insulating layers 2103a and 2103b, and between insulating layers 2103b and 2103c, are sometimes unclear, these boundaries are clearly indicated by dashed lines in Figure 30A.

[0442] As the insulating layer 2103d in contact with the semiconductor layer 2108, it is preferable to use a dense insulating film that is not easily adsorbed by impurities such as water onto its surface. Furthermore, it is preferable to use an insulating film with as few defects as possible and with reduced impurities such as water or hydrogen. For example, as the insulating layer 2103d, the same insulating film as the insulating layer 2110c included in the aforementioned insulating layer 2110 can be used.

[0443] In cases where a metal film or alloy film, which is not easy to diffuse the component to the insulating layer 2103, is used as the conductive layer 2106, a structure can be adopted in which the three insulating layers 2103b, 2103c and 2103d are stacked without the insulating layer 2103a.

[0444] By using this layered insulating layer 2103, highly reliable transistors can be achieved.

[0445] As insulating layers 2123 and 2124, it is preferable to use materials that absorb impurities such as hydrogen contained in semiconductor layer 2108, insulating layer 2103, and insulating layer 2110. For example, materials containing aluminum oxide can be used as insulating layers 2123 and 2124. In this case, insulating layers 2123 and 2124 are used as getter layers for impurities such as hydrogen. Note that hydrogen as described herein includes hydrogen atoms, hydrogen molecules, hydrogen bonded to oxygen, and their ionized products.

[0446] Even better, the materials used for insulating layers 2123 and 2124 have the effect of inhibiting oxygen permeation.

[0447] As shown in Figure 30A, along the channel length direction, the insulating layer 2124 is provided to cover the top and side surfaces of the conductive layer 2112, the metal oxide layer 2114, the insulating layer 2110, the semiconductor layer 2108, and the side surface of the insulating layer 2103. Furthermore, the insulating layer 2123 is in contact with the outer side of the insulating layer 2103. Here, the end of the insulating layer 2103 is approximately aligned with the end of the semiconductor layer 2108. Additionally, the side surface of the insulating layer 2103 and the side surface of the semiconductor layer 2108 are on the same plane.

[0448] Furthermore, although not shown in the figure, in the channel width direction, the insulating layer 2123 in the area that does not overlap with the insulating layer 2110 is preferably provided in a manner that contacts the insulating layer 2124.

[0449] By employing the above structure, impurities such as hydrogen contained in the semiconductor layer 2108, insulating layer 2103, and insulating layer 2110 can be efficiently absorbed into the insulating layer 2123 and insulating layer 2124, thereby absorbing impurities such as hydrogen. Furthermore, the diffusion of oxygen contained in the semiconductor layer 2108, insulating layer 2103, and insulating layer 2110 to the outer surface of the insulating layer 2123 and insulating layer 2124 can be suppressed.

[0450] As insulating layers 2121, 2122, 2125, and 2126, materials that inhibit hydrogen permeation are preferably used. For example, materials containing silicon nitrides or nitrogen-containing silicon oxides can be used as insulating layers 2121, 2122, 2125, and 2126. Silicon nitride is preferred as such material. In this case, insulating layers 2121, 2122, 2125, and 2126 serve as protective layers against impurities such as hydrogen. Note that hydrogen, as described herein, includes hydrogen atoms, hydrogen molecules, hydrogen bonded to oxygen, and their ionized forms.

[0451] Insulating layer 2125 is provided to cover insulating layer 2124. Preferably, insulating layer 2125 contacts insulating layer 2122 in a manner surrounding insulating layers 2123 and 2124. Furthermore, insulating layer 2125 preferably contacts insulating layer 2121 on the outside of insulating layers 2123 and 2124. Insulating layer 2126 is provided on insulating layer 2125.

[0452] By having the above structure, impurities such as hydrogen can be suppressed from mixing into the semiconductor layer 2108 from the outside of insulating layers 2121, 2122, 2125, and 2126. In other words, in transistor 2100A, by having at least semiconductor layer 2108 surrounded by insulating layers 2121, 2122, 2125, and 2126, the mixing of impurity elements such as hydrogen from the outside can be suppressed.

[0453] Note that this illustration shows a protective layer with a laminated structure of insulating layers 2125 and 2126, but either insulating layer 2125 or insulating layer 2126 may be omitted if not required. Furthermore, insulating layer 2125 may have two or more laminated layers. Similarly, this illustration shows a protective layer with a laminated structure of insulating layers 2121 and 2122, but either insulating layer 2121 or insulating layer 2122 may be omitted if not required. Furthermore, insulating layer 2122 may have two or more laminated layers.

[0454] Preferably, the ends of the insulating layer 2110, the metal oxide layer 2114, and the conductive layer 2112 are each tapered. Furthermore, the tapered angle of the end of the metal oxide layer 2114 is preferably smaller than the tapered angle of the end of the insulating layer 2110, and the tapered angle of the end of the conductive layer 2112 is preferably smaller than the tapered angle of the end of the metal oxide layer 2114. By employing this structure, the coverage of the layers (e.g., insulating layers 2124, 2125, and 2126) formed on the insulating layer 2110, the metal oxide layer 2114, and the conductive layer 2112 is improved, and problems such as breaks or voids in the layers can be suppressed.

[0455] Furthermore, in this specification, the cone angle refers to the angle of inclination formed by the side and bottom surfaces of the layer when the intended layer is viewed from a direction perpendicular to the cross-section (e.g., a surface orthogonal to the surface of the substrate).

[0456] A portion of conductive layer 2106 functions as a first gate electrode (also known as a bottom gate electrode), and a portion of conductive layer 2112 functions as a second gate electrode (also known as a top gate electrode). Furthermore, a portion of insulating layer 2103 is used as a first gate insulating layer, and a portion of insulating layer 2110 is used as a second gate insulating layer.

[0457] Furthermore, conductive layer 2106 can be electrically connected to conductive layer 2112. Thus, conductive layer 2106 and conductive layer 2112 can be supplied with the same potential.

[0458] Furthermore, although not shown, it is preferable that the conductive layer 2112 and conductive layer 2106 protrude to the outer side of the end of the semiconductor layer 2108 in the channel width direction. In this case, the conductive layer 2112 and conductive layer 2106 cover the entire channel width direction of the semiconductor layer 2108 through the insulating layer 2110 and insulating layer 2103.

[0459] By employing the above structure, an electric field generated by a pair of gate electrodes can be used to surround the semiconductor layer 2108. In this case, it is particularly preferable to supply the same potential to the conductive layers 2106 and 2112. This allows for the effective application of an electric field to induce channels in the semiconductor layer 2108, thereby increasing the on-state current of the transistor 2100A. Therefore, miniaturization of the transistor 2100A can be achieved.

[0460] Furthermore, conductive layer 2112 may not be connected to conductive layer 2106. In this case, a fixed potential can be supplied to one of the pair of gate electrodes, and a signal for driving transistor 2100A can be supplied to the other. In this case, the threshold voltage for driving transistor 2100A with the other gate electrode can be controlled by using the potential supplied to one gate electrode.

[0461] Furthermore, as shown in Figure 30A, the transistor 2100A may also have conductive layers 2120a and 2120b on the insulating layer 2126. Conductive layers 2120a and 2120b are used as source electrodes or drain electrodes. Conductive layers 2120a and 2120b are electrically connected to region 2108N via openings 2119a and 2119b respectively provided in insulating layers 2124, 2125, and 2126.

[0462] As the semiconductor layer 2108, oxides such as metal oxides that can be used as oxide 230, as shown in other embodiments or other structural examples, can be used. For example, the semiconductor layer 2108 preferably comprises indium, M (M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. In particular, M is preferably selected from one or more of aluminum, gallium, yttrium, or tin.

[0463] In particular, the semiconductor layer 2108 is preferably an oxide containing indium, gallium and zinc.

[0464] The semiconductor layer 2108 can also be a stacked structure with layers of different compositions, different crystallinity, or different impurity concentrations.

[0465] As the conductive layer 2112, a low-resistance material is preferably used. By using a low-resistance material as the conductive layer 2112, parasitic resistance can be reduced, allowing the transistor to have a high on-state current, thereby realizing a semiconductor device with high on-state current. Furthermore, by reducing wiring resistance in large display devices and high-definition display devices, signal delay can be suppressed, enabling high-speed driving. Since the conductive layer 2112 is used as the gate electrode, conductive materials that can be used as gate electrodes for conductors 260 or 205, as described in other embodiments or other structural examples, can be used. For example, copper, silver, gold, or aluminum can be used as the conductive layer 2112. Copper is particularly preferred because it has the advantages of low resistance and high mass production.

[0466] The conductive layer 2112 may have a stacked structure. When the conductive layer 2112 has a stacked structure, a second conductive layer is disposed on top of and / or at the bottom of the low-resistance first conductive layer. Preferably, the second conductive layer is a conductive material that is less prone to oxidation (has oxidation resistance) compared to the first conductive layer. Furthermore, the second conductive layer is preferably a material that suppresses the diffusion of components from the first conductive layer. For example, metal oxides such as indium oxide, indium zinc oxide, indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO), and zinc oxide, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, and tungsten nitride can be used as the second conductive layer.

[0467] The metal oxide layer 2114, located between the insulating layer 2110 and the conductive layer 2112, serves as a barrier film to prevent oxygen contained in the insulating layer 2110 from diffusing to the conductive layer 2112 side. Furthermore, the metal oxide layer 2114 also serves as a barrier film to prevent hydrogen or water contained in the conductive layer 2112 from diffusing to the insulating layer 2110 side. The metal oxide layer 2114 can be, for example, made of a material that is at least less permeable to oxygen and hydrogen than the insulating layer 2110.

[0468] By utilizing the metal oxide layer 2114, even if a metal material that easily absorbs oxygen, such as aluminum or copper, is used in the conductive layer 2112, oxygen diffusion from the insulating layer 2110 to the conductive layer 2112 can be prevented. Furthermore, even if the conductive layer 2112 contains hydrogen, hydrogen diffusion from the conductive layer 2112 to the semiconductor layer 2108 via the insulating layer 2110 can be prevented. As a result, the carrier concentration in the channel-forming region of the semiconductor layer 2108 can be extremely low.

[0469] The metal oxide layer 2114 can be made of either an insulating or conductive material. When the metal oxide layer 2114 is insulating, it is used as part of the gate insulating layer. On the other hand, when the metal oxide layer 2114 is conductive, it is used as part of the gate electrode.

[0470] As the metal oxide layer 2114, it is preferable to use an insulating material with a higher dielectric constant than silicon oxide. In particular, it is preferable to use an alumina film, a hafnium oxide film, or a hafnium aluminate film, because the driving voltage can be reduced.

[0471] Metal oxides can be used as the metal oxide layer 2114. For example, indium oxide, indium zinc oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) and other indium-containing oxides can be used. Conductive oxides containing indium are preferred because of their high conductivity. Furthermore, because silicon-containing ITSO is not easily crystallized and has high flatness, the adhesion between ITSO and the film on it is improved. Zinc oxide, gallium-containing zinc oxide, and other metal oxides can be used as the metal oxide layer 2114. Furthermore, a structure in which these are stacked can be used as the metal oxide layer 2114.

[0472] Furthermore, as the metal oxide layer 2114, it is preferable to use an oxide material containing one or more elements identical to those in the semiconductor layer 2108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the aforementioned semiconductor layer 2108. In this case, by using a metal oxide film formed using the same sputtering target as the semiconductor layer 2108 as the metal oxide layer 2114, equipment can be shared, which is preferable.

[0473] Furthermore, when both the semiconductor layer 2108 and the metal oxide layer 2114 use metal oxide materials containing indium and gallium, it is preferable to use a material with a higher gallium content (containment ratio) than the semiconductor layer 2108 to improve oxygen barrier properties. In this case, by using a material with a higher indium content than the metal oxide layer 2114 in the semiconductor layer 2108, the field-effect mobility of the transistor 2100A can be improved.

[0474] Furthermore, the metal oxide layer 2114 is preferably formed using a sputtering apparatus. For example, when forming an oxide film using a sputtering apparatus, oxygen can be appropriately added to the insulating layer 2110 or the semiconductor layer 2108 by forming the oxide film in an atmosphere containing oxygen gas.

[0475] As conductive layer 2106, the same material as conductive layer 2112, conductive layer 2120a, or conductive layer 2120b can be used. In particular, it is preferable to use a material containing copper for conductive layer 2106, as this can reduce wiring resistance. Furthermore, when a high-melting-point material such as tungsten or molybdenum is used for conductive layer 2106, high-temperature processing can be performed in subsequent processes.

[0476] Region 2108N is a region containing an impurity element (the first element). Examples of such impurity elements include, for instance, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, or noble gas elements. Typical examples of noble gas elements may also include helium, neon, argon, krypton, and xenon. In particular, it is preferable to include boron, phosphorus, magnesium, or aluminum. Furthermore, two or more of these elements may be included.

[0477] To add the aforementioned impurity elements, methods such as ion implantation and ion doping can be used. Furthermore, by forming an insulating layer 2124 that contacts region 2108N, the aforementioned impurity elements can be added to region 2108N.

[0478] The process of adding impurity elements to region 2108N can be performed using the insulating layer 2110 as a mask. Therefore, region 2108N can be formed in a self-aligned manner.

[0479] Region 2108N preferably contains an impurity concentration of 1×10¹⁹ atoms / cm³ or more and 1×10²³ atoms / cm³ or less, more preferably 5×10¹⁹ atoms / cm³ or more and 5×10²² atoms / cm³ or less, and even more preferably 1×10²⁰ atoms / cm³ or more and 1×10²² atoms / cm³ or less.

[0480] For example, the concentration of impurities contained in region 2108N can be analyzed using analytical techniques such as Secondary Ion Mass Spectrometry (SIMS) and X-ray Photoelectron Spectroscopy (XPS). When using XPS analysis, by combining ion sputtering from one side of the surface or the back side with XPS analysis, the concentration distribution along the depth direction can be determined.

[0481] Furthermore, the impurity elements in region 2108N are preferably present in an oxidized state. For example, elements that are easily oxidized, such as boron, phosphorus, magnesium, aluminum, and silicon, are preferably used as impurity elements. These easily oxidized elements can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 2108, thus suppressing desorption even when high temperatures (e.g., above 400°C, 600°C, or 800°C) are applied in subsequent processes. In addition, the impurity elements abstract oxygen from the semiconductor layer 2108, thereby generating many oxygen vacancies in region 2108N. These oxygen vacancies bond with hydrogen in the film to become carrier supply sources, making region 2108N a state with extremely low resistance.

[0482] Furthermore, when high-temperature processing is performed in subsequent processes, sometimes a large amount of oxygen is supplied to region 2108N from the outside or the film near region 2108N, which can sometimes cause an increase in resistance. Therefore, it is preferable to perform high-temperature processing with the semiconductor layer 2108 covered by an insulating layer 2124 that has high oxygen barrier properties.

[0483] The insulating layer 2124 is provided in such a way that it contacts the region 2108N of the semiconductor layer 2108.

[0484] As the insulating layer 2124, for example, an insulating film containing aluminum oxide can be used.

[0485] Region 2108N is in a state where impurity elements have been added as described above to include a large number of oxygen vacancies.

[0486] By adopting the above structure, a transistor 2100A with good electrical characteristics and high reliability can be realized.

[0487] <Structure Example of a Semiconductor Device 3> Figure 30B is a cross-sectional view of the 2100B transistor along its channel length.

[0488] Transistor 2100B is disposed on substrate 2102 and includes insulating layers 2121, 2122, 2123, conductive layers 2134, 2136, semiconductor layer 2138, conductive layers 2142a, 2142b, 2144, 2146, 2124, 2125, and 2126. Insulating layers 2121, 2122, and 2123 are sequentially disposed on substrate 2102, and conductive layer 2134 is disposed on insulating layer 2123. Insulating layer 2136 is disposed to cover conductive layer 2134. Semiconductor layer 2138 has an island-like shape and is disposed on insulating layer 2136. Conductive layers 2142a and 2142b are respectively in contact with the top surface of semiconductor layer 2138 and are disposed separately on semiconductor layer 2138. Furthermore, an insulating layer 2144 is provided covering the insulating layer 2136, conductive layer 2142a, conductive layer 2142b, and semiconductor layer 2138, and an insulating layer 2146 is provided on the insulating layer 2144. An insulating layer 2124 is provided on the insulating layer 2146 and has a region in contact with a portion of the insulating layer 2123. An insulating layer 2125 has a region in contact with a portion of the insulating layers 2122 and 2121 and is provided on the insulating layer 2124. Furthermore, an insulating layer 2126 is provided on the insulating layer 2125.

[0489] In transistor 2100B, preferably, at least semiconductor layer 2138 is disposed between insulating layers 2123 and 2124, with insulating layers 2123 and 2124 in contact with each other on the outside of semiconductor layer 2108. Insulating layers 2123 and 2124 are disposed between insulating layers 2121 and 2122 and insulating layers 2125 and 2126. Preferably, insulating layer 2125 is in contact with at least insulating layer 2122, and more preferably with insulating layer 2121. In other words, in transistor 2100B, semiconductor layer 2138 is surrounded by insulating layers 2123 and 2124, and semiconductor layer 2108, insulating layers 2123 and 2124 are surrounded by insulating layers 2122 and 2125. Furthermore, since the semiconductor layer 2138, insulating layer 2123, insulating layer 2124, insulating layer 2122 and insulating layer 2125 are arranged in such a way that they are sandwiched between insulating layer 2121 and insulating layer 2126, they can be said to be surrounded by insulating layer 2121 and insulating layer 2126.

[0490] Conductive layer 2134 is used as the gate electrode. A portion of insulating layer 2136 is used as the gate insulating layer. Conductive layer 2142a is used as one of the source electrode and the drain electrode, and conductive layer 2142b is used as the other. The region of semiconductor layer 2138 that overlaps with conductive layer 2134 is used as the channel forming region. Transistor 2100B has a gate electrode on the side closer to the formed surface (substrate 2102 side) than semiconductor layer 2138, which is a so-called bottom-gate type transistor. Here, the side of semiconductor layer 2138 opposite to the side of conductive layer 2134 is sometimes referred to as the back channel side. Transistor 2100B is a so-called channel etch structure transistor in which no protective layer is provided between the back channel side of semiconductor layer 2138 and the source and drain electrodes.

[0491] Semiconductor layer 2138 has a stacked structure in which semiconductor layer 2138a and semiconductor layer 2138b are sequentially stacked from the side of the formed surface. Preferably, both semiconductor layer 2138a and semiconductor layer 2138b contain metal oxide. In addition, it is preferable that the semiconductor layer 2138b located on the back channel side has a higher crystallinity than the semiconductor layer 2138a located on the conductive layer 2134 side. Thus, when processing conductive layer 2142a and conductive layer 2142b, it is possible to prevent a portion of semiconductor layer 2138 from being etched away.

[0492] As the semiconductor layer 2138, oxides such as metal oxides, such as oxide 230, as shown in other embodiments or other structural examples, can be used. For example, the semiconductor layer 2138 preferably comprises indium, M (M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0493] In particular, as the semiconductor layer 2138, it is preferable to use an oxide containing indium, gallium and zinc.

[0494] Semiconductor layer 2138a and semiconductor layer 2138b can be composed of different layers, have different crystallinity, or have different impurity concentrations. In addition, a stacked structure of three or more layers can be used.

[0495] The conductive layers 2142a and 2142b each have a stacked structure in which conductive layers 2143a, 2143b and 2143c are stacked sequentially from the side of the surface to which they are formed.

[0496] As the conductive layer 2143b, it is preferable to use a low-resistance conductive material containing copper, silver, gold, or aluminum. In particular, the conductive layer 2143b is preferably made of copper or aluminum. The conductive layer 2143b is preferably made of a conductive material with a lower resistance than that of the conductive layers 2143a and 2143c. As a result, the conductive layers 2142a and 2142b can have extremely low resistance.

[0497] Furthermore, conductive layers 2143a and 2143c may each use a different conductive material than conductive layer 2143b. For example, conductive layers 2143a and 2143c are preferably made of conductive materials including titanium, tungsten, molybdenum, chromium, tantalum, zinc, indium, platinum, or ruthenium, respectively.

[0498] Thus, by sandwiching a conductive layer 2143b containing copper or aluminum between conductive layers 2143a and 2143c, oxidation of the surface of conductive layer 2143b can be suppressed, and the diffusion of elements from conductive layer 2143b into the surrounding layers can be prevented. In particular, by providing conductive layer 2143a between semiconductor layer 2138 and conductive layer 2143b, the diffusion of metal elements from conductive layer 2143b into semiconductor layer 2138 can be prevented, thereby achieving a highly reliable transistor 2100B.

[0499] Here, an insulating layer 2144 is provided in such a way that it contacts the end of the conductive layer 2143b.

[0500] Furthermore, the structure of conductive layers 2142a and 2142b is not limited to a three-layer structure; it can also be a two-layer or four-layer structure containing conductive layers of copper, silver, gold, or aluminum. For example, conductive layers 2142a and 2142b can be a two-layer structure consisting of stacked conductive layers 2143a and 2143b, or a two-layer structure consisting of stacked conductive layers 2143b and 2143c.

[0501] The conductive layer 2134 may suitably use the aforementioned conductive materials that can be used in conductive layers 2143a, 2143b, and 2143c. In particular, it is preferred to use a conductive material containing copper.

[0502] The insulating layers 2136 and 2144 that are in contact with the semiconductor layer 2138 are preferably made of an insulating material containing oxides. Alternatively, when the insulating layers 2136 and 2144 are in a stacked structure, the layers in contact with the semiconductor layer 2138 are made of an insulating material containing oxides.

[0503] Alternatively, the insulating layer 2136 can also be a silicon nitride or aluminum nitride insulating film. When using an insulating material that does not contain oxides, it is preferable to perform an oxygen-adding treatment on the top of the insulating layer 2136 to form an oxygen-containing region. Examples of oxygen-adding treatments include heat treatment in an oxygen-containing atmosphere, plasma treatment, and ion doping treatment.

[0504] Insulating layer 2146 is used as a protective layer for transistor 2100B. Insulating layer 2146 can be made of inorganic insulating materials such as silicon nitride, silicon oxynitride, silicon oxide, silicon oxynitride, aluminum oxide, and aluminum nitride. In particular, using materials such as silicon nitride or aluminum oxide, which do not readily allow oxygen to diffuse, as insulating layer 2146 prevents oxygen from escaping from semiconductor layer 2138 or insulating layer 2144 to the outside via insulating layer 2146 due to heating during the manufacturing process, which is preferable.

[0505] Alternatively, an organic insulating material with planarization film function can be used as the insulating layer 2146. Alternatively, a laminated film containing an inorganic insulating material and an organic insulating material can be used as the insulating layer 2146.

[0506] Furthermore, the semiconductor layer 2138, located in and near the contact area with conductive layers 2142a and 2142b, may have a pair of low-resistance regions formed therein, serving as source and drain regions. This region, being part of the semiconductor layer 2138, is a region with even lower resistance than the channel formation region. Alternatively, the low-resistance region may be referred to as a high-carrier-density region or an n-type region, etc. Within the semiconductor layer 2138, the region sandwiched between the pair of low-resistance regions and overlapping with the conductive layer 2134 is used as the channel formation region.

[0507] The materials shown in the above structural example can be used as insulating layers 2123 and 2124.

[0508] As shown in Figure 30B, along the channel length direction, insulating layers 2136, 2144, and 2146 are partially removed outside the conductive layers 2134, semiconductor layer 2138, conductive layers 2142a, and conductive layers 2142b. At this time, the ends of insulating layers 2136, 2144, and 2146 can be approximately aligned. Furthermore, the side surfaces of insulating layers 2136, 2144, and 2146 can each have surfaces on the same plane. Therefore, insulating layers 2136, 2144, and 2146 have regions that do not overlap with insulating layer 2123.

[0509] The insulating layer 2124 is provided in such a way that it covers the top and side surfaces of the insulating layer 2146, the side surface of the insulating layer 2144, and the side surface of the insulating layer 2136, and has an area in contact with a portion of the insulating layer 2123.

[0510] Furthermore, although not shown in the figure, in the channel width direction, the insulating layer 2123 in the area that does not overlap with the insulating layer 2136, the insulating layer 2144 and the insulating layer 2146 is preferably provided in a manner that contacts the insulating layer 2124.

[0511] By employing the above structure, impurities such as hydrogen contained in semiconductor layer 2138, insulating layer 2136, insulating layer 2144, and insulating layer 2146 can be efficiently absorbed into insulating layer 2123 and insulating layer 2124, thereby absorbing impurities such as hydrogen. Furthermore, the diffusion of oxygen contained in semiconductor layer 2138, insulating layer 2136, insulating layer 2144, and insulating layer 2146 to the outer surface of insulating layer 2123 and insulating layer 2124 can be suppressed.

[0512] The materials shown in the above structural examples can be used as insulating layers 2121, 2122, 2125, and 2126.

[0513] Insulating layer 2125 is provided to cover insulating layer 2124. Preferably, insulating layer 2125 contacts insulating layer 2122 in a manner surrounding insulating layers 2123 and 2124. Furthermore, insulating layer 2125 preferably contacts insulating layer 2121 on the outside of insulating layers 2123 and 2124. Insulating layer 2126 is provided on insulating layer 2125.

[0514] By having the above structure, impurities such as hydrogen can be suppressed from mixing into the semiconductor layer 2138 from the outside of insulating layers 2121, 2122, 2125, and 2126. In other words, in transistor 2100B, by having at least semiconductor layer 2138 surrounded by insulating layers 2121, 2122, 2125, and 2126, the mixing of impurity elements such as hydrogen from the outside can be suppressed.

[0515] Note that this illustration shows a protective layer with a laminated structure of insulating layers 2125 and 2126, but either insulating layer 2125 or insulating layer 2126 may be omitted if not required. Furthermore, insulating layer 2125 may have two or more laminated layers. Similarly, this illustration shows a protective layer with a laminated structure of insulating layers 2121 and 2122, but either insulating layer 2121 or insulating layer 2122 may be omitted if not required. Furthermore, insulating layer 2122 may have two or more laminated layers.

[0516] By adopting the above structure, a transistor 2100B with good electrical characteristics and high reliability can be realized.

[0517] At least a portion of this embodiment can be implemented in combination with other embodiments and examples described in this specification.

[0518] Implementation Method 3 In this embodiment, an embodiment of the semiconductor device will be described with reference to Figures 32 to 35.

[0519] [Storage Device 1] Figure 32 shows an example of a semiconductor device (memory device) according to an embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, a transistor 200 is disposed above a transistor 300, and a capacitor 100 is disposed above both the transistor 300 and the transistor 200. Furthermore, the transistor 200 described in the above embodiment can be used as the transistor 200. Alternatively, the transistor 2100A or transistor 2100B described in the above embodiment can also be used as the transistor 200. Furthermore, the transistor 200 and the capacitor 100 are respectively disposed in the transistor and capacitor device 292 of the memory device 290 described in the above embodiment with reference to Figures 26A and 26B and Figures 27A and 27B.

[0520] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because the off-state current of transistor 200 is small, its use in storage devices can maintain stored content for a long time. In other words, since no update operation is required or the update operation frequency is extremely low, the power consumption of the storage device can be significantly reduced.

[0521] In the semiconductor device shown in Figure 32, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Additionally, the other of the gate of transistor 300 and the source and drain of transistor 200 is electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0522] Furthermore, by arranging the storage devices shown in Figure 32 in a matrix configuration, a memory cell array can be formed.

[0523] <Transistor 300> Transistor 300 is disposed on substrate 311 and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311; and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0524] In the transistor 300 shown in FIG. 32, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. The conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also referred to as a FIN-type transistor. Furthermore, an insulator used to form a shield for the convex portion may be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0525] Note that the structure of transistor 300 shown in Figure 32 is only an example and is not limited to the above structure. Appropriate transistors can be used according to the circuit structure or driving method.

[0526] <Capacitor 100> A capacitor 100 is disposed above a transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 shown in the above embodiment.

[0527] Alternatively, conductors 112 and 110 may be formed simultaneously on conductor 240. Furthermore, conductor 112 serves as a plug or wiring for electrical connection with capacitor 100, transistor 200, or transistor 300.

[0528] In Figure 32, conductors 112 and 110 have a single-layer structure, but are not limited to this structure and may also have a stacked structure of two or more layers. For example, a conductor with high adhesion between the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0529] In addition, the insulator 130 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride, etc., and may be provided in a stacked or single layer.

[0530] For example, the insulator 130 is preferably a multilayer structure using materials with high dielectric strength, such as silicon oxynitride, and materials with high dielectric constant (high-k). By adopting this structure, the capacitor 100 can include an insulator with high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high dielectric strength to improve dielectric strength, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0531] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0532] On the other hand, materials with high insulation and pressure resistance (materials with relatively low permittivity) include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin, etc.

[0533] <Wiring Layer> Wiring layers, including interlayer films, wiring, and plugs, can also be provided between various structures. Furthermore, multiple wiring layers can be configured according to the design. Here, in conductors that function as plugs or wiring, the same component symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be a single component. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0534] For example, on transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 or transistor 200, are embedded in insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as plugs or wiring.

[0535] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by planarization treatment using chemical mechanical polishing (CMP) or the like.

[0536] A wiring layer can be provided on the insulator 326 and the conductor 330. For example, in FIG32, insulators 350, 352 and 354 are stacked sequentially. Furthermore, a conductor 356 is formed in the insulators 350, 352 and 354. The conductor 356 serves as a plug or wiring.

[0537] Similarly, conductors 218 and conductors constituting transistor 200 (conductor 205) are embedded in insulators 210, 211, 212, 214, and 216. Furthermore, conductor 218 serves as a plug or wiring for electrical connection with capacitor 100 or transistor 300. Additionally, insulator 150 is provided on conductor 120 and insulator 130.

[0538] Here, similar to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side of the conductor 218 used as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. In addition, the conductor 205 may be formed parallel to the conductor 218, so the insulator 217 may also be formed in contact with the side of the conductor 205.

[0539] Insulator 217 can be made of materials such as silicon nitride, aluminum oxide, or silicon oxynitride. Since insulator 217 is disposed in contact with insulators 211, 212, 214, and 222, impurities such as water or hydrogen from insulators 210 or 216 can be prevented from entering oxide 230 via conductor 218. Silicon nitride is particularly preferred due to its high hydrogen barrier properties. Furthermore, oxygen from insulators 210 or 216 can be prevented from being absorbed by conductor 218.

[0540] Insulator 217 can be formed in the same way as insulator 241. For example, silicon nitride can be formed using the PEALD method and then anisotropic etching can be used to form the opening reaching conductor 356.

[0541] Insulators that can be used as interlayer films include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, all of which possess insulating properties.

[0542] For example, by using materials with relatively low permittivity as insulators for interlayer films, parasitic capacitances generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0543] For example, it is preferable to use an insulator with a low relative permittivity in insulators 150, 210, 352, and 354. For example, the insulator is preferably a silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, carbon and nitrogen-containing silicon oxide, porous silicon oxide, or resin. Alternatively, the insulator is preferably a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, carbon and nitrogen-containing silicon oxide, or porous silicon oxide and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with resin, a laminated structure with thermal stability and a low relative permittivity can be achieved. Examples of resins include polyesters, polyolefins, polyamides (nylon, aromatic polyamides, etc.), polyimides, polycarbonates, or acrylics.

[0544] Furthermore, by surrounding the transistor using an oxide semiconductor with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators with the function of suppressing the permeation of impurities such as hydrogen and oxygen can be used as insulators 214, 211, 212 and 350.

[0545] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in layers. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0546] The conductor used for wiring and plugs is preferably a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurities like phosphorus, and silicides such as nickel silicates can also be used.

[0547] For example, conductors 328, 330, 356, 218, and 112 can be made of conductive materials such as metallic materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above-mentioned materials, either in a single layer or in layers. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which possess both heat resistance and conductivity; tungsten is particularly preferred. Alternatively, it is preferable to use low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0548] <Wires or connectors with oxide semiconductor layers> When an oxide semiconductor is used for the transistor 200, an insulator including an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator including the excess oxygen region and the conductor provided in the insulator including the excess oxygen region.

[0549] For example, in Figure 32, it is preferable to provide an insulator 241 between the insulator 224 and the conductor 240, which have excess oxygen. By providing the insulator 241 in contact with the insulators 222, 272, 273, 282, 283, and 284, a structure in which the insulator 224 and the transistor 200 are sealed by a barrier insulator can be achieved.

[0550] In other words, by providing insulator 241, the absorption of excess oxygen present in insulators 224 and 280 by conductor 240 can be suppressed. Furthermore, by including insulator 241, the diffusion of hydrogen as an impurity through conductor 240 to transistor 200 can be suppressed.

[0551] As the insulator 241, it is preferable to use an insulating material that can suppress the diffusion of impurities such as water or hydrogen and oxygen. For example, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide are preferred. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0552] Furthermore, similar to the embodiments described above, it is preferable that the transistor 200 is sealed by insulators 211, 212, 214, 287, 282, 283, and 284. By employing this structure, the mixing of hydrogen contained in insulators 274, 150, etc., into insulator 280, etc., can be reduced.

[0553] Here, although insulators 284, 283, and 282 are penetrated by conductor 240, and insulators 214, 212, and 211 are penetrated by conductor 218, as described above, insulator 241 is disposed in contact with conductor 240, and insulator 217 is disposed in contact with conductor 218. Therefore, hydrogen mixed into the inside of insulators 211, 212, 214, 287, 282, 283, and 284 by conductors 240 and 218 can be reduced. By this method, the transistor 200 can be more securely sealed by insulators 211, 212, 214, 287, 282, 283, 284, 241, and 217, thereby reducing the mixing of impurities such as hydrogen contained in insulator 274 from the outside.

[0554] Furthermore, as shown in the previous embodiments, insulators 216, 224, 280, 250, and 274 are preferably formed using a film-forming method employing a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in insulators 216, 224, 280, 250, and 274.

[0555] This method can reduce the hydrogen concentration of the silicon insulating film near the transistor 200, thereby reducing the hydrogen concentration of oxide 230.

[0556] <<cutting line>> The following describes the dicing lines (also called dividing lines, separation lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in wafer shape by dividing each semiconductor element. As a dicing method, for example, sometimes a groove (dicing line) for separating semiconductor elements is first formed in the substrate, and then the substrate is cut at the dicing line to obtain multiple semiconductor devices that have been separated (divided).

[0557] Here, for example, as shown in FIG32, it is preferable to design the cutting line in such a way that it overlaps with the area in contact with insulator 283 and insulator 211. That is, an opening is provided in insulator 282, insulator 280, insulator 273, insulator 272, insulator 224, insulator 222, insulator 216, insulator 214 and insulator 212 near the area that forms the cutting line at the edge of the memory cell including multiple transistors 200.

[0558] In other words, insulator 211 and insulator 283 are in contact through openings provided in insulators 282, 280, 273, 272, 224, 222, 216, 214, and 212. Alternatively, openings can be provided in insulators 282, 280, 273, 272, 224, 222, 216, and 214 to achieve contact between insulators 212 and 283 within these openings. For example, in this case, insulators 212 and 283 can be formed using the same material and the same method. By using the same material and the same method to form insulators 212 and 283, the sealing performance can be improved. For example, silicon nitride is preferably used.

[0559] By employing this structure, insulators 211, 212, 214, 287, 282, 283, and 284 can surround the transistor 200. At least one of insulators 211, 212, 214, 287, 282, 283, and 284 has the function of suppressing the diffusion of oxygen, hydrogen, and water. Therefore, even if the substrate is divided into multiple wafers according to the circuit region where semiconductor elements are formed, as shown in this embodiment, impurities such as hydrogen or water can be prevented from mixing in and diffusing into the transistor 200 from the side direction of the truncated substrate.

[0560] By employing this structure, excess oxygen in insulators 280 and 224 can be prevented from diffusing to the outside. Therefore, excess oxygen in insulators 280 and 224 is efficiently supplied to the oxide forming the channel in transistor 200. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200. Consequently, the oxide forming the channel in transistor 200 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, reliability can be improved while suppressing variations in the electrical characteristics of transistor 200.

[0561] Although the capacitor 100 in the storage device shown in FIG. 32 is planar, the storage device shown in this embodiment is not limited to this. For example, as shown in FIG. 33, the capacitor 100 may also be cylindrical. In addition, the structure of the insulator 150 and below in the storage device shown in FIG. 33 is the same as that in the semiconductor device shown in FIG. 32.

[0562] The capacitor 100 shown in FIG33 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, a conductor 125 on the insulator 145, and a conductor 125 on the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0563] Conductor 115 is used as the lower electrode of capacitor 100, conductor 125 is used as the upper electrode of capacitor 100, and insulator 145 is used as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other by a dielectric material not only on the bottom surface but also on the side surfaces within the openings of insulators 150 and 142, thus increasing the electrostatic capacitance per unit area. The deeper the opening, the greater the electrostatic capacitance of capacitor 100. Therefore, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or hyper-integration of semiconductor devices can be advanced.

[0564] As insulator 152, an insulator that can be used as insulator 280 can be used. Alternatively, as insulator 142, it is preferable to use an insulator that is used as an etch stop layer when forming the opening of insulator 150 and can be used as insulator 214.

[0565] Furthermore, the top-view shape of the openings formed in insulators 150 and 142 can be a quadrilateral, a polygon other than a quadrilateral, a polygon with rounded corners, or a circular shape such as an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. By adopting this structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0566] The conductor 115 is disposed in contact with openings formed in the insulators 142 and 150. Preferably, the height of the top surface of the conductor 115 is approximately the same as the height of the top surface of the insulator 142. Furthermore, the bottom surface of the conductor 115 is contacted by a conductor 110 in an opening in the insulator 130. The conductor 115 is preferably formed by an ALD or CVD method, for example, using a conductor suitable for conductor 205.

[0567] The insulator 145 is configured to cover both the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD or CVD method. The insulator 145 can be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, etc., and can be a multilayer or single-layer structure. For example, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 145.

[0568] For example, insulator 145 is preferably made of a material with high dielectric strength, such as silicon oxynitride, or a material with a high dielectric constant (high-k). Alternatively, a multilayer structure of materials with high dielectric strength or high dielectric constant (high-k) can also be used.

[0569] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such a high-k material, even if the insulator 145 is thickened, the electrostatic capacitance of the capacitor 100 can be sufficiently ensured. By thickening the insulator 145, leakage current generated between the conductors 115 and 125 can be suppressed.

[0570] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or resins. For example, an insulating film can be used that sequentially layers silicon nitride (SiNx) formed by the ALD method, silicon oxide (SiOx) formed by the PEALD method, and silicon nitride (SiNx) formed by the ALD method. By using such an insulator with high dielectric strength, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0571] Conductor 125 is disposed in such a way that it is embedded in openings formed in insulator 142 and insulator 150. Furthermore, conductor 125 is electrically connected to wiring 1005 via conductor 140 and conductor 153. Conductor 125 is preferably formed by ALD or CVD methods, for example, a conductor suitable for conductor 205 can be used.

[0572] Furthermore, conductor 153 is disposed on insulator 154 and covered by insulator 156. Conductor 153 can be any conductor that can be used for conductor 112, and insulator 156 can be any insulator that can be used for insulator 152. Here, conductor 153 is in contact with the top surface of conductor 140 and is used as a terminal of capacitor 100, transistor 200, or transistor 300.

[0573] Additionally, Figures 32 and 33 show a structure in which one layer of transistor 200 is stacked on transistor 300, but this embodiment is not limited to this. For example, memory devices 290 as shown in Figures 26A and 26B and Figures 27A and 27B, or multiple memory devices 290 stacked in the vertical direction as shown in Figures 28 and 29, may also be provided on transistor 300.

[0574] Figures 34A and 34B show examples of storage devices with memory devices 290_1 to 290_n (n is a natural number greater than or equal to 2) stacked on top of each other. Note that this embodiment illustrates a structure with memory device 290_n, but is not limited thereto. For example, memory device 290_n may not be provided. Furthermore, there are no particular limitations on the value of n, but it can be 2 or more and less than 200, preferably 2 or more and less than 100, and even more preferably 2 or more and less than 10. Figure 34B shows a cross-sectional view along the channel length direction of the transistor included in the memory device 290. Figure 34A shows a cross-sectional view along the channel width direction of the transistor along the portion of the dotted line AB in Figure 34B. Furthermore, the structure of the storage device shown in Figures 34A and 34B, including insulator 354 and below, is the same as that shown in Figure 32.

[0575] As shown in Figures 34A and 34B, memory devices 290_1 to 290_n are stacked on the insulator 354. Each layer, including the memory device 290, is provided with a capacitor 292 and a conductor 240. The memory devices 290 in each layer are electrically connected to the conductors 240 of adjacent layers via the conductors 240 of each layer, and are also electrically connected to the transistor 300. In Figure 34B, the hidden portions in the channel width direction of conductors 240_1 to 240_n are indicated by dashed lines.

[0576] The memory device 290 shown in Figures 34A and 34B has a different structure than the memory device 290 shown in Figures 26A and 26B. In the memory device 290 shown in Figures 34A and 34B, the conductor 240 is formed across the oxide 230b, etc., and an insulator 241 is formed on the side of the conductor 240. Here, because the insulator 241 is not formed on the bottom surface of the conductor 240, the bottom surface of each layer of conductor 240 is in contact with the conductor 242a of that layer and the conductor 246a of the next layer. Thus, each layer of memory device 290 can be electrically connected to the conductor 246a of the next layer.

[0577] Note that the storage device shown in this embodiment is not limited to the structure shown in Figures 34A and 34B. For example, an oxide 230b may be inserted between the upper conductor 246a and the lower conductor 246a. Furthermore, for example, conductors 240_1 to 240_n may be formed by a single through electrode.

[0578] Furthermore, because the capacitor devices 292 are formed as planar structures in each layer, excessive increases in the height of each layer can be suppressed. Therefore, it is easier to increase the number of layers in the memory device 290. For example, the memory device 290 can have approximately 100 layers.

[0579] The above is an explanation of the structural examples. By adopting this structure, reliability can be improved while suppressing electrical characteristic variations in semiconductor devices using transistors containing oxide semiconductors. Furthermore, a transistor containing an oxide semiconductor with a large on-state current can be provided. Furthermore, a transistor containing an oxide semiconductor with a small off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0580] [Storage device 2] Figure 35 illustrates an example of a storage device using a semiconductor device as an embodiment of the present invention. The storage device shown in Figure 35 includes a transistor 400 in addition to the semiconductor device comprising transistor 200, transistor 300, and capacitor 100 shown in Figure 32.

[0581] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure can be adopted in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. When the second gate of transistor 200 is maintained at a negative potential in this structure, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even if no power is supplied to transistors 200 and 400. Therefore, a storage device including transistors 200 and 400 can retain stored content for a long period.

[0582] Therefore, in Figure 35, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the back gate of transistor 200. Moreover, the other of the gate of transistor 300 and the source and drain of transistor 200 is electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the back gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008 and wiring 1009 are electrically connected.

[0583] Furthermore, by arranging the storage devices shown in FIG35 and FIG32 in a matrix configuration, a memory cell array can be constructed. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200. In addition, the storage devices shown in FIG35 and FIG32 can be sealed with insulators 211, 212, 214, 287, 282, 283, and 284, just like the storage devices shown in FIG32.

[0584] <Transistor 400> Transistor 400 and transistor 200 are formed on the same layer and can be manufactured together. Transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) serving as a first gate, a conductor 405 serving as a second gate, insulators 222, 224, and 450 serving as gate insulating layers, an oxide 430c including a channel forming region, conductors 442a, oxides 443a, 431a, and 431b serving as sources, and conductors 442b, oxides 443b, 432a, and 432b serving as drains. Furthermore, similar to transistor 200, a conductor used as a plug is disposed in contact with conductors 442a and 442b.

[0585] In transistor 400, conductor 405 and conductor 205 are in the same layer. Oxides 431a and 432a are in the same layer as oxide 230a, and oxides 431b and 432b are in the same layer as oxide 230b. Conductor 442 and conductor 242 are in the same layer. Oxide 443 and oxide 243 are in the same layer. Oxide 430c and oxide 230c are in the same layer. Insulator 450 and insulator 250 are in the same layer. Conductor 460 and conductor 260 are in the same layer.

[0586] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing an oxide film that has become oxide 230c.

[0587] Similar to oxide 230, the oxide 430c used as the active layer of transistor 400 has fewer oxygen vacancies and impurities such as hydrogen or water. Therefore, the critical voltage of transistor 400 can be greater than 0V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are both 0V can be made very small.

[0588] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0589] Implementation Method 4 In this embodiment, referring to FIGS. 37A to 38H, a storage device (hereinafter sometimes referred to as an OS memory device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to an embodiment of the present invention will be described. An OS memory device is a storage device that includes at least a capacitor and an OS transistor for controlling the charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0590] Generally speaking, various storage devices (memory) can be used as semiconductor devices in computers and other applications, depending on their purpose. Figure 36 shows the hierarchy of various storage devices. Upper-level storage devices require high access speeds, while lower-level storage devices require large storage capacitors and high recording densities. In Figure 36, from the top layer, the following are shown in sequence: memory installed as temporary storage in arithmetic processing devices such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0591] Because memory, which is installed as a temporary register in arithmetic processing devices such as CPUs, is used for the temporary storage of calculation results, it is accessed very frequently from the processing device. Therefore, a higher operating speed than storage capacitors is required. Furthermore, the temporary register also has the function of holding settings information of the processing device.

[0592] SRAM is used, for example, in cache memory. Cache memory has the function of copying and storing a portion of the information held in main memory. By copying frequently used data into cache memory, the speed of data access can be improved.

[0593] DRAM is used, for example, in main memory. Main memory has the function of holding programs or data read from memory. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm².

[0594] 3D NAND memory is used, for example, in storage devices. Storage devices have the function of storing data that needs to be preserved for a long time and various programs used by computing devices. Therefore, storage devices are required to have larger storage capacitance and higher recording density compared to their operating speed. The recording density of storage devices used in storage devices is approximately 0.6 to 6.0 Gbit / mm².

[0595] One embodiment of the present invention is a storage device that operates at high speed and can retain data for a long period of time. The storage device of one embodiment of the present invention can be suitably used as a storage device located in the boundary region 901 between the hierarchy including cache memory and the hierarchy including main memory. Furthermore, the storage device of one embodiment of the present invention can be suitably used as a storage device located in the boundary region 902 between the hierarchy including main memory and the hierarchy including memory.

[0596] <Example of a storage device structure> Figure 37A shows an example of the structure of an OS memory device. The storage device 1400 includes peripheral circuitry 1411 and a memory cell array 1470. The peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0597] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the storage device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0598] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives externally input control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0599] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0600] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0601] Furthermore, although an example showing the peripheral circuitry 1411 and the memory cell array 1470 forming on the same plane is illustrated in FIG. 37A, this embodiment is not limited thereto. For example, as shown in FIG. 37B, the memory cell array 1470 may also be arranged in a manner overlapping a portion of the peripheral circuitry 1411. For example, a structure in which the sense amplifier is arranged overlapping the memory cell array 1470 may also be adopted.

[0602] Figures 38A to 38H illustrate structural examples of memory cells suitable for use in the aforementioned memory cell MC.

[0603] [DOSRAM] Figures 38A to 38C show examples of circuit structures for DRAM memory cells. In this specification, etc., DRAM using 1OS transistor and 1 capacitor type memory cells is sometimes referred to as DOSRAM (Dynamic Oxide Memory RAM). (Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 38A includes a transistor M1 and a capacitor CA. In addition, the transistor M1 includes a gate (sometimes called the front gate) and a back gate.

[0604] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0605] The BIL wiring is used as the bit line, and the WOL wiring is used as the word line. The CAL wiring is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential to the CAL wiring. The BGL wiring is used to apply a potential to the back gate of the transistor M1. By applying any potential to the BGL wiring, the threshold voltage of the transistor M1 can be increased or decreased.

[0606] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt a structure like memory cell 1472 shown in Figure 38B, where the back gate of transistor M1 is not connected to wiring BGL, but to wiring WOL. Additionally, for example, the memory cell MC can also be a memory cell like memory cell 1473 shown in Figure 38C, composed of a single-gate transistor, that is, a memory cell consisting of transistor M1 without a back gate.

[0607] When the semiconductor device shown in the above embodiment is used in memory cell 1471, etc., transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. Furthermore, transistor M1 and capacitor CA are respectively provided in the transistor and capacitor device 292 of the memory device 290 described in the above embodiment with reference to FIGS. 26A, 26B, 27A, and 27B. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be kept extremely low. In other words, because the data written can be retained by transistor M1 for a long time, the update frequency of the memory cell can be reduced. Furthermore, memory cell update operations can be eliminated. Moreover, due to the extremely low leakage current, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0608] Furthermore, in DOSRAM, when the sense amplifier is arranged in a structure overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0609] Here, Figure 39A shows an example of a storage device 1400, in which a memory cell array 1470 is provided on a peripheral circuit 1411, and a plurality of memory cells 1471 are provided in the memory cell array 1470.

[0610] In the memory cell array 1470, multiple memory cells 1471 are configured in a matrix, and wiring WOL, wiring BGL, etc., also extend on the memory cell array 1470 in the row or column direction. Wiring BIL is connected to the column circuit 1430 disposed in the peripheral circuit 1411. The memory cell array 1470 is electrically connected to the sense amplifier, etc., through wiring BIL.

[0611] The memory cell array 1470 preferably includes an OS transistor and is sealed by insulators 211, 212, 214, 287, 282, 283, and 284, as shown in the above embodiment. For example, as shown in Figures 24A and 24B, the top, side, and bottom surfaces of the memory cell array 1470 are preferably sealed by insulators 211, 212, 214, 287, 282, 283, and 284.

[0612] Furthermore, as shown in Figure 39B, multiple memory cell arrays 1470_1 to 1470_n (where n represents a natural number greater than 2) can also employ a stacked structure. The structure of each memory cell array 1470 is almost identical to that shown in Figure 38A, but the column circuit 1430 and the memory cells 1471 of each memory cell array 1470 are connected by wiring BIL. Additionally, as shown in Figures 34A and 34B, the wiring BIL can also be formed by using one or more conductors 240 to pass through the memory cell arrays 1470_1 to 1470_n.

[0613] The multiple memory cell array 1470 preferably includes an OS transistor and is sealed together by insulators 211, 212, 214, 287, 282, 283, and 284 as shown in the above embodiments. For example, as shown in FIG28, FIG29, or FIG33, the top, side, and bottom surfaces of the multiple memory cell array 1470 are preferably sealed by insulators 211, 212, 214, 287, 282, 283, and 284. Furthermore, as shown in FIG28 and FIG29, it is preferable that insulators 282, 296, 298, and 214 are stacked on the boundaries of each memory cell array 1470.

[0614] [NOSRAM] Figures 38D to 38H show examples of circuit structures for a gain-cell memory cell consisting of two transistors and one capacitor. The memory cell 1474 shown in Figure 38D includes transistor M2, transistor M3, and capacitor CB. Furthermore, transistor M2 includes a front gate (sometimes simply referred to as the gate) and a back gate. In this specification, etc., a storage device including a gain-cell memory cell using an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide-based RAM). Semiconductor RAM).

[0615] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0616] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. It is preferable to apply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying any potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0617] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt a structure like memory cell 1475 shown in FIG. 38E, where the back gate of transistor M2 is not connected to wiring BGL, but connected to wiring WOL. Furthermore, for example, the memory cell MC can also be a memory cell composed of a single-gate transistor structure, like memory cell 1476 shown in FIG. 38F, that is, a memory cell composed of transistor M2 excluding the back gate. Furthermore, for example, the memory cell MC can also have a structure like memory cell 1477 shown in FIG. 38G, where wiring WBL and wiring RBL are combined into a wiring BIL.

[0618] When the semiconductor device shown in the above embodiment is used in memory cell 1474, transistor M2 can be transistor 200, transistor M3 can be transistor 300, and capacitor CB can be capacitor 100. Furthermore, transistor M2 and capacitor CB are respectively provided in the transistor and capacitor device 292 of the memory device 290 described in the above embodiment with reference to FIGS. 26A, 26B, 27A, and 27B. By using an OS transistor, the leakage current of transistor M2 can be extremely low. Therefore, since the written data can be retained by transistor M2 for a long time, the update frequency of the memory cell can be reduced. Furthermore, memory cell updates can be eliminated. In addition, due to the extremely low leakage current, multi-valued data or analog data can be stored in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0619] Furthermore, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor can be n-channel or p-channel. The field-effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, a Si transistor can also be used as the readout transistor M3. In addition, by using a Si transistor in transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the occupied area of ​​the memory cell and achieving high integration of the storage device.

[0620] Furthermore, transistor M3 can also be an OS transistor. When using OS transistors for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0621] Furthermore, Figure 38H shows an example of a gain-cell type memory cell with 3 transistors and 1 capacitor. The memory cell 1478 shown in Figure 38H includes transistors M4 to M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. Wiring GNDL is the wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wirings RBL and WBL without being electrically connected to wiring BIL.

[0622] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to the wiring BGL. Alternatively, the back gate and the main gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0623] Furthermore, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Alternatively, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0624] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor 100 can be used as capacitor CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be kept extremely low. Furthermore, transistor M4 and capacitor CC are respectively provided in transistor and capacitor device 292 of the memory device 290 described with reference to FIGS. 26A and 26B and FIGS. 27A and 27B in the above embodiment.

[0625] Note that the structure of the peripheral circuit 1411 and memory cell array 1470 shown in this embodiment is not limited to the structure described above. The configuration or function of these circuits and the wiring, circuit elements, etc. connected to them can be changed, removed, or added as needed.

[0626] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0627] Implementation Method 5 In this embodiment, an example of a wafer 1200 on which the semiconductor device of the present invention is mounted is described with reference to FIGS. 40A and 40B. Multiple circuits (systems) are mounted on the wafer 1200. Thus, the technology of integrating multiple circuits (systems) on a single wafer is sometimes referred to as a System on Chip (SoC).

[0628] As shown in Figure 40A, the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0629] A bump (not shown) is provided on the chip 1200, which is connected to the first side of the printed circuit board (PCB) 1201 as shown in FIG40B. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0630] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0631] CPU 1211 preferably has multiple CPU cores. Similarly, GPU 1212 preferably has multiple GPU cores. Furthermore, CPU 1211 and GPU 1212 may each have memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0632] Furthermore, since the CPU1211 and GPU1212 are mounted on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation results from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0633] The analog operation unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog operation unit 1213.

[0634] The memory controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0635] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, video recording devices, and controllers. Controllers include mice, keyboards, and game console controllers. Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI) (registered trademark), etc., can be used as the aforementioned interface.

[0636] Network circuit 1216 includes network circuits such as local area network (LAN). Additionally, it may include network security circuits.

[0637] The aforementioned circuits (systems) can be formed on the chip 1200 using the same process. Therefore, even if the number of circuits required for the chip 1200 increases, no additional process is needed, and the chip 1200 can be manufactured at a low cost.

[0638] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0639] The GPU module 1204 can reduce its size due to the presence of a chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product operation circuitry of the GPU 1212, it can perform operations such as Deep Neural Networks (DNNs), Convolutional Neural Networks (CNNs), Recursive Neural Networks (RNNs), autoencoders, Deep Boltzmann Machines (DBMs), and Deep Belief Networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, or the GPU module can be used as an AI system module.

[0640] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0641] Implementation Method 6 In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, laptops, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 41A to 41E schematically illustrate several structural examples of removable storage devices. For example, the semiconductor device described in the above embodiments is fabricated into a packaged memory chip and used in various memory devices or removable memory.

[0642] Figure 41A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled on the substrate 1104, such as the memory chip 1105.

[0643] Figure 41B is a schematic diagram of the external appearance of the SD card, and Figure 41C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, through wireless communication between the host device and the SD card 1110, data can be read from and written to the memory chip 1114. The semiconductor devices shown in the above embodiments can be assembled on the substrate 1113, such as the memory chip 1114.

[0644] Figure 41D is a schematic diagram of the external appearance of the SSD, and Figure 41E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor devices shown in the above embodiments can be assembled onto the memory chip 1154 on the substrate 1153.

[0645] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0646] Implementation Method 7 In this embodiment, Figures 42A to 45B are used as an example of a semiconductor device using an OS transistor and capacitor, to illustrate an FPGA (Field Programmable Gate Array). In the FPGA of this embodiment, OS memory is used for configuring memory and temporary registers. Here, the FPGA is referred to as an "OS-FPGA".

[0647] < <os-fpga>> Figure 42A illustrates an example of the OS-FPGA architecture. The OS-FPGA 3110 shown in Figure 42A is capable of performing context switching using a multi-context structure and NOFF (normally off) operations based on fine-grained power gate control for each PLE. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

[0648] Programmable region 3115 includes two input / output blocks (IOBs) 3117 and core 3119. IOB 3117 includes multiple programmable input / output circuits. Core 3119 includes multiple logic array blocks (LABs) 3120 and multiple switch array blocks (SABs) 3130. LAB 3120 includes multiple PLEs 3121. Figure 42B shows an example of using five PLEs 3121 to construct LAB 3120. As shown in Figure 42C, SAB 3130 includes multiple switch blocks (SBs) 3131 arranged in an array. LAB 3120 is connected to LAB 3120 in four directions (up, down, left, and right) via its input terminals and SAB 3130.

[0649] The SB3131 will be described with reference to Figures 43A to 43C. The SB3131 shown in Figure 43A has inputs data, datab, the signal context[1:0], and the signal word[1:0]. data and datab are configuration data, and their logic is complementary. The OS-FPGA3110 has two contexts, and the signal context[1:0] is the context selection signal. The signal word[1:0] is the word line selection signal; the wiring input to the signal word[1:0] is word lines. Note that the input shown in Figure 43A corresponds to the input terminals of the SB3131, and the output corresponds to the output terminals of the SB3131.

[0650] SB3131 includes PRS (Programmable Router Switch) 3133[0] and 3133[1]. PRS3133[0] and 3133[1] include configuration memory (CM) capable of storing complementary data. Note that PRS3133[0] and PRS3133[1] are referred to as PRS3133 without distinguishing between them. This also applies to other components.

[0651] Figure 43B shows an example of the circuit structure of PRS3133[0]. PRS3133[0] and PRS3133[1] have the same circuit structure. The input context selection signal and word line selection signal are different between PRS3133[0] and PRS3133[1]. Signals context[0] and word[0] are input to PRS3133[0], and signals context[1] and word[1] are input to PRS3133[1]. For example, in SB3131, PRS3133[0] becomes active when signal context[0] becomes "H".

[0652] The PRS3133[0] includes a CM3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM3135. The CM3135 includes memory circuits 3137 and 3137B. Memory circuits 3137 and 3137B have the same circuit structure. Memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32. Memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.

[0653] When the semiconductor device described in the above embodiment is used in the SAB3130, the transistors shown in the above embodiment can be used as OS transistors MO31 and MOB31. This reduces the off-state current of the OS transistors MO31 and MOB31, thereby allowing configuration data to be maintained for a longer period. Furthermore, the top-view footprint of each group consisting of a transistor and a capacitor can be reduced, thus achieving high integration of the semiconductor device of this embodiment.

[0654] OS transistors MO31, MO32, MOB31, and MOB32 include back gates that are electrically connected to power lines that supply a fixed voltage.

[0655] The gate of Si transistor M31 corresponds to node N31, the gate of OS transistor MO32 corresponds to node N32, and the gate of OS transistor MOB32 corresponds to node NB32. Nodes N32 and NB32 are charge-holding nodes of CM3135. OS transistor MO32 controls the conduction state between node N31 and the signal context[0] using the signal line. OS transistor MOB32 controls the conduction state between node N31 and the low-potential power line VSS.

[0656] The logic of the data held by memory circuits 3137 and 3137B is complementary. Therefore, either OS transistor MO32 or MOB32 is in the ON state.

[0657] Referring to Figure 43C, a working example of PRS3133[0] is described. PRS3133[0] has been written with configuration data. Node N32 of PRS3133[0] is "H" and node NB32 is "L".

[0658] During the period when the signal context[0] is "L", PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] switches to "H", the gate of the Si transistor M31 remains "L" and the output terminal of PRS3133[0] also remains "L".

[0659] During the period when the signal context[0] is "H", PRS3133[0] is active. When the signal context[0] changes to "H", the gate of the Si transistor M31 changes to "H" according to the configuration data stored in CM3135.

[0660] During the active state of PRS3133[0], when the potential shift of the input terminal is "H", the gate voltage of the Si transistor M31 rises by boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving capability, and the gate of the Si transistor M31 becomes floating.

[0661] In the PRS3133, which has a multi-context function, the CM3135 is also used as a multiplexer.

[0662] Figure 44 shows a structural example of PLE3121. PLE3121 includes a LUT (Look-Up Table) block 3123, a register block 3124, a selector 3125, and a CM 3126. LUT block 3123 selects its internal data based on inputs inA-inD and outputs it. Selector 3125 selects either the output of LUT block 3123 or the output of register block 3124 based on the configuration data stored in CM 3126.

[0663] The PLE3121 is electrically connected to the voltage VDD via a power switch 3127. The opening and closing of the power switch 3127 is determined by the configuration data stored in the CM3128. By configuring the power switch 3127 according to each PLE3121, fine-grained power throttling can be performed. Due to the fine-grained power throttling function, power throttling can be performed on PLE3121s that are not used after context switching, thus effectively reducing standby power.

[0664] To implement the NOFF operation, the register block 3124 is constructed using non-volatile registers. The non-volatile registers in PLE3121 are flip-flops (hereinafter referred to as "OS-FF") that include OS memory.

[0665] The temporary register block 3124 includes OS-FF3140[1] and 3140[2]. The signals user_res, load, and store are input to OS-FF3140[1] and 3140[2]. The clock signal CLK1 is input to OS-FF314...

Claims

1. A semiconductor device comprising: a transistor on a first region of a first insulator, the transistor comprising: an oxide semiconductor; a gate insulator on the oxide semiconductor; and a gate electrode on the gate insulator; a second insulator on the transistor, the second insulator including an opening; a third insulator on the second insulator; and a fourth insulator on the first insulator, a first region of the fourth insulator disposed on the third insulator, wherein the gate electrode is positioned inside the opening of the second insulator, wherein the semiconductor device further comprises: a second region of the first insulator and a second region of the fourth insulator in contact with each other and a first sealing portion of the second insulator is absent; and a third region of the first insulator and a third region of the fourth insulator in contact with each other and a second sealing portion of the second insulator is absent, wherein the first sealing portion surrounds the transistor, and wherein the second sealing portion surrounds the first sealing portion.

2. The semiconductor device of claim 1, wherein the second insulator contains excess oxygen, wherein the third insulator is configured to trap or fix hydrogen, and wherein the fourth insulator is a barrier to hydrogen.

3. The semiconductor device of claim 1, wherein the oxide semiconductor comprises indium, gallium, and zinc.

4. The semiconductor device of claim 1, wherein the second insulator comprises silicon oxynitride, and wherein the third insulator comprises aluminum oxide.

5. The semiconductor device of claim 1, wherein the fourth insulator comprises silicon nitride.

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