Integrated circuit device and method for forming the same

Abstract

An integrated circuit element includes a pair of stacked active region structures extending in a first direction. The integrated circuit also includes a first switching gate conductor, a first complementary field-effect transistor (FET) gate conductor, a second complementary field-effect transistor (FET) gate conductor, and a second switching gate conductor, intersecting the pair of stacked active region structures and aligned with gate rails extending in a second direction. A first complementary field-effect transistor terminal conductor extending in the second direction between the first and second gate rails is conductively connected to the second complementary field-effect transistor gate conductor. A second complementary field-effect transistor terminal conductor extending in the second direction between the third and fourth gate rails is conductively connected to the first complementary field-effect transistor gate conductor.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit element, and more particularly to a method for forming an integrated circuit element. Prior Technology

[0002] An integrated circuit (IC) typically comprises multiple IC elements fabricated according to one or more IC layouts. IC elements sometimes include complementary field-effect transistor (CFET) devices. A CFET typically has an upper FET that overlays the lower FET in a stacked configuration. Both the upper and lower FETs in a CFET are positioned above the conductive lines in the lower conductive layer but below the conductive lines in the upper conductive layer. Summary of the Invention

[0003] This disclosure relates to an integrated circuit element having a complementary field-effect transistor (FET). The integrated circuit element includes: a first pair of stacked active region structures extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of first gate track, second gate track, third gate track, and fourth gate track; a first switching gate conductor aligned with the first gate track and serving as the gate of a first switching transistor intersecting with the first pair of stacked active region structures; a first complementary FET gate conductor aligned with the second gate track and serving as the connecting gate of the first complementary FET device intersecting with the first pair of stacked active region structures; a second complementary FET gate conductor aligned with the third gate track and serving as the connecting gate of the second complementary FET device intersecting with the first pair of stacked active region structures; and a second switching gate conductor aligned with the fourth gate track and serving as the gate of the second switching transistor intersecting with the first pair of stacked active region structures. The component also includes a first complementary field-effect transistor (FET) terminal conductor, which serves as the junction drain of the first complementary field-effect transistor element and intersects with a first pair of stacked active region structures between a first gate rail and a second gate rail. The first complementary field-effect transistor terminal conductor is conductively connected to a second complementary field-effect transistor gate conductor. The component also includes a second complementary field-effect transistor (FET) terminal conductor, which serves as the junction drain of the second complementary field-effect transistor element and intersects with a first pair of stacked active region structures between a third gate rail and a fourth gate rail. The second complementary field-effect transistor terminal conductor is conductively connected to the first complementary field-effect transistor gate conductor.

[0004] Another aspect disclosed relates to an integrated circuit element having complementary field-effect transistor (FET) elements. The integrated circuit element includes: a first pair of stacked active region structures and a second pair of stacked active region structures, extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of first gate track, second gate track, third gate track, and fourth gate track; a first switching gate conductor, a first complementary FET gate conductor, a second complementary FET gate conductor, and a second switching gate conductor, all intersecting with the first pair of stacked active region structures; and a third switching gate conductor, a third complementary FET gate conductor, and a third complementary FET gate conductor. The first complementary field-effect transistor (FET) gate conductor, the fourth complementary FET gate conductor, and the fourth switching gate conductor all intersect with the second pair of stacked active region structures. Specifically, the first and third switching gate conductors are aligned with the first gate track, the first and third complementary FET gate conductors are aligned with the second gate track, the second and fourth complementary FET gate conductors are aligned with the third gate track, and the second and fourth switching gate conductors are aligned with the fourth gate track. The element also includes a first complementary FET terminal conductor, which serves as the junction drain of the first complementary FET element and intersects with the first pair of stacked active region structures between the first and second gate tracks. The first complementary FET terminal conductor is conductively connected to the second complementary FET gate conductor. The element also includes a second complementary field-effect transistor terminal conductor, which serves as the junction drain terminal of the second complementary field-effect transistor element and intersects with the first pair of stacked active region structures between the third gate track and the fourth gate track, wherein the second complementary field-effect transistor terminal conductor is electrically connected to the first complementary field-effect transistor gate conductor.

[0005] Another aspect disclosed herein relates to a method. The method includes fabricating a lower active region structure extending in a first direction on a substrate. The method also includes forming four lower gate conductors intersecting the lower active region structure, wherein the four lower gate conductors include a second lower gate conductor and a third gate conductor located between a first lower gate conductor and a fourth lower gate conductor. The method also includes forming three lower end conductors intersecting the lower active region structure, wherein the three lower end conductors include a first lower end conductor located between the first and second lower gate conductors, a second lower end conductor located between the second and third lower gate conductors, and a third lower end conductor located between the third and fourth lower gate conductors, wherein the second lower end conductor is located between the first and third lower end conductors. The method also includes fabricating an upper active region structure extending in the first direction and stacked with the lower active region structure. The method also includes forming four upper gate conductors intersecting the upper active region structure, wherein the four upper gate conductors include a second upper gate conductor and a third upper gate conductor located between a first upper gate conductor and a fourth upper gate conductor, and wherein the second upper gate conductor is stacked with a second lower gate conductor and electrically connected to the second lower gate conductor, and the third upper gate conductor is stacked with a third lower gate conductor and electrically connected to the third lower gate conductor. The method also includes forming three upper end conductors intersecting the upper active region structure, wherein the three upper end conductors include a first upper end conductor stacked with a first lower end conductor and electrically connected to the first lower end conductor, a second upper end conductor stacked with a second lower end conductor, and a third upper end conductor stacked with a third lower end conductor and electrically connected to the third lower end conductor. The method also includes forming a first node connection structure extending in a first direction, the first node connection structure electrically connecting one of the first upper end conductor and the first lower end conductor to one of the third upper gate conductor and the third lower gate conductor. The method also includes forming a second node connection structure extending in the first direction, the second node connection structure electrically connecting one of the third upper conductor and the third lower conductor to one of the second upper gate conductor and the second lower gate conductor. Simple Explanation of the Diagram

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the features disclosed herein. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. [ ] Figure 1A is a layout diagram of an integrated circuit according to some embodiments, which has a static random access memory circuit implemented in circuit cells using complementary field-effect transistor (CFET) elements. Figure 1B is a schematic diagram of an integrated circuit in Figure 1A, labeled with various components according to some embodiments. Figure 1C is a circuit diagram of a memory cell according to some embodiments. Figures 2A to 2C are cross-sectional views of the integrated circuit in Figure 1A according to some embodiments, along various cut planes. Figure 3A is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having a layout pattern specifying additional components in layers above or below the components shown in Figure 1A. Figure 3B is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having a layout pattern specifying additional components in a layer above the components shown in Figures 3A and 1A. Figure 4 is a cross-sectional view of an integrated circuit according to some embodiments along the cutting plane C-C' in Figure 1A. Figure 5A is a layout diagram of an integrated circuit according to some embodiments, which has a static random access memory circuit implemented in a circuit cell by complementary field-effect transistor (CFET) elements. Figure 5B is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having a layout pattern specifying additional components in layers above or below the components shown in Figure 5A. Figures 6A to 6B are exemplary variations of the layout configuration in Figure 5B according to some embodiments. Figures 7A to 7C correspond to the upper and lower portions of a layout diagram of a circuit unit 700 according to some embodiments, the circuit unit 700 having four SRAM circuits implemented with CFET elements. Figure 8 is the upper part of a layout diagram of a circuit unit according to some embodiments, which has four SRAM circuits implemented with CFET elements. Figure 9 is a schematic diagram of some portions of a matrix of circuit units according to some embodiments. Figure 10 is a flowchart of a method for fabricating an integrated circuit (IC) with CFET elements according to some embodiments. Figure 11 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 12 is a block diagram of an integrated circuit (IC) fabrication system and associated IC fabrication process according to some embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements, materials, values, steps, operations, configurations, or the like are described below to simplify this disclosure. Of course, these elements, materials, values, steps, operations, configurations, or the like are merely examples and not limiting. Other elements, values, operations, materials, configurations, or the like may be contemplated. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower," "above," "upper," and the like are used herein to describe the relationship between one component or feature and another component or feature(s) illustrated in the diagrams. In addition to the orientations depicted in the diagrams, spatial relative terms are also intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein will be interpreted accordingly.

[0009] In some embodiments, a static random-access memory (SRAM) bit cell circuit with complementary field-effect transistors (CFETs) is implemented based on a pair of stacked active region structures. The pair of stacked active region structures includes an upper active region structure and a lower active region structure stacked on top of each other in a direction perpendicular to the substrate. Each CFET element includes a PMOS transistor and an NMOS transistor stacked on top of each other on the substrate. The SRAM bit cell circuit includes a first switching transistor, a first CFET element, a second CFET element, and a second switching transistor.

[0010] The stacked active region structure extends in the X direction and passes through four gate rails, each of which extends in the Y direction. The four gate rails are uniformly distributed along the X direction in the order of first gate rail, second gate rail, third gate rail, and fourth gate rail. The gate conductors of the first switching transistor, the first CFET gate conductor, the second CFET gate conductor, and the second switching transistor gate conductor are aligned with the first, second, third, and fourth gate rails respectively. The junction drain of the first CFET element extending in the Y direction is located between the first and second gate rails. The junction drain of the second CFET element extending in the Y direction is located between the third and fourth gate rails. A first node connection structure extending in the first direction electrically connects the junction drain of the first CFET element to the gate conductor of the first CFET gate conductor. A second node connection structure extending in the first direction electrically connects the junction drain of the second CFET element to the gate conductor of the first CFET gate conductor.

[0011] The first bit line conductor is coupled to a first node in the SRAM bit cell circuit through a channel of a first switching transistor, and the second bit line conductor is coupled to a second node in the SRAM bit cell circuit through a channel of a second switching transistor. In some embodiments, based on the layout design of the SRAM bit cell circuit disclosed herein, the current carrying capacity of the bit line conductors used for writing bit values ​​into the SRAM bit cell circuit or reading bit values ​​from the SRAM bit cell circuit is improved compared to some existing layout designs. In some embodiments, the parasitic capacitive coupling between the first bit line conductor and the second bit line conductor is also reduced.

[0012] Figure 1A is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having SRAM bit cell circuits implemented with CFET elements in the circuit cells. Figure 1B is a schematic diagram of the integrated circuit in Figure 1A according to some embodiments, labeled with various components. The integrated circuit in Figures 1A to 1B has a circuit cell 100 having cell boundaries 101 and 109 extending in the Y direction and cell boundaries 102 and 108 extending in the X direction. A dividing boundary 105 divides the circuit cell 100 into two parts. The circuit cell 100 is implemented with two SRAM bit cell circuits. A first SRAM bit cell circuit SRAM1 is implemented in a first part of the circuit cell 100 between cell boundary 102 and dividing boundary 105. A second SRAM bit cell circuit SRAM2 is implemented in a second part of the circuit cell 100 between dividing boundary 105 and cell boundary 108. The first SRAM bit cell circuit SRAM1 is implemented with transistors in a first pair of stacked active region structures 80A. The second SRAM bit cell circuit SRAM2 is implemented using transistors in the second pair of stacked active region structures 80B. Cross-sectional views of the stacked active region structures are shown in Figures 2A through 2C.

[0013] Figures 2A to 2C are cross-sectional views of the integrated circuit in Figure 1A according to some embodiments, along various cutting planes. Specifically, Figures 2A, 2B, and 2C respectively depict cross-sectional views of the integrated circuit along cutting planes as specified by lines A-A', B-B', and C-C' in Figure 1A.

[0014] In Figures 1A to 1B and 2A to 2C, the first pair of stacked active region structures 80A extending in the X direction includes an upper active region structure 82A and a lower active region structure 84A stacked on top of each other along the Z direction, with the lower active region structure 84A located between the upper active region structure 82A and the substrate 30. The second pair of stacked active region structures 80B extending in the X direction includes an upper active region structure 82B and a lower active region structure 84B stacked on top of each other along the Z direction, with the lower active region structure 84B located between the upper active region structure 82A and the substrate 30. Here, the Z direction is the normal direction of the substrate 30.

[0015] Each of the upper active region structures 82A and 82B contains a channel region and a source / drain region of a first type of transistor, and each of the lower active region structures 84A and 84B contains a channel region and a source / drain region of a second type of transistor. In some embodiments, the first type of transistor is a PMOS transistor, and the second type is an NMOS transistor. In some embodiments, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. In some embodiments, each of the upper active region structures 82A and 82B and each of the lower active region structures 84A and 84B includes one or more nanosheets, and therefore, each of the PMOS and NMOS transistors in Figure 1A is a nanosheet transistor. In some embodiments, each of the upper active region structures 82A and 82B and each of the lower active region structures 84A and 84B includes one or more nanowires, and therefore, each of the PMOS and NMOS transistors in Figure 1A is a nanowire transistor.

[0016] In Figures 1A to 1B and 2A to 2C, each of the first pair of stacked active region structures 80A and the second pair of stacked active region structures 80B is implemented to support two or more CFET elements. Each of the CFET elements includes PMOS transistors and NMOS transistors stacked on top of each other on the substrate 30.

[0017] The layout diagram in Figure 1A includes an upper part and a lower part of the layout. The upper part of the layout shows various gate conductors and various terminal conductors that intersect with the upper active region structures 82A and 82B. The lower part of the layout shows various gate conductors and various terminal conductors that intersect with the lower active region structures 84A and 84B.

[0018] As shown in the upper part of the layout, the four gate conductors 152UA, 154A, 156A, and 158UA intersect with the upper active region structure 82A in the first pair of stacked active region structures 80A, and the four gate conductors 152UB, 154B, 156B, and 158UB intersect with the upper active region structure 82B in the second pair of stacked active region structures 80B. Each of the four gate conductors 152UA, 154A, 156A, and 158UA is aligned with the gate stack extending in the Y direction. Each of the four gate conductors 152UB, 154B, 156B, and 158UB is also aligned with the gate stack extending in the Y direction. The gate stacks specify the permissible positions for placing the gate conductors. In Figure 1A, the four gate stacks extending in the Y direction are uniformly distributed along the X direction. Gate conductors 152UA and 152UB are aligned with the first gate track, gate conductors 154A and 154B are aligned with the second gate track, gate conductors 156A and 156B are aligned with the third gate track, and gate conductors 158UA and 158UB are aligned with the fourth gate track. The pitch between two adjacent gate conductors is a contact poly pitch (CPP), which is also the spacing between two adjacent gate stacks.

[0019] As shown in the lower part of the layout, the four gate conductors 152DA, 154A, 156A, and 158DA intersect with the lower active region structure 84A in the first pair of stacked active region structures 80A, and the four gate conductors 152DB, 154B, 156B, and 158DB intersect with the lower active region structure 84B in the second pair of stacked active region structures 80B. Each of the four gate conductors 152DA, 154A, 156A, and 158DA is aligned with one of the four gate stacks extending in the Y direction. Each of the four gate conductors 152DB, 154B, 156B, and 158DB is also aligned with one of the four gate stacks extending in the Y direction. In detail, gate conductors 152DA and 152DB are aligned with the first gate track, gate conductors 154A and 154B are aligned with the second gate track, gate conductors 156A and 156B are aligned with the third gate track, and gate conductors 158DA and 158DB are aligned with the fourth gate track.

[0020] The upper portion of the layout also includes layout patterns for specifying end conductors 132UA, 134A, 135UA, 136A, and 138UA extending in the Y direction, and layout patterns for specifying end conductors 132UB, 134B, 135UB, 136B, and 138UB extending in the Y direction. The integrated circuit in Figure 1A includes an upper conductive layer located above the upper active region structure (i.e., 82A and 82B). The upper portion of the layout in Figure 1A includes layout patterns for specifying node connection structures 122A and 122B extending in the X direction in the upper conductive layer, layout patterns for specifying bit line conductors 162A, 168A, 162B, and 168B extending in the X direction in the upper conductive layer, and layout patterns for specifying power line conductors 182A and 182B extending in the X direction in the upper conductive layer.

[0021] The lower portion of the layout also includes layout patterns for specifying end conductors 132DA, 134A, 135DA, 136A, and 138DA extending in the Y direction, and layout patterns for specifying end conductors 132DB, 134B, 135DB, 136B, and 138DB extending in the Y direction. The integrated circuit in Figure 1A includes a lower conductive layer located below the lower active region structure (i.e., 84A and 84B). The lower portion of the layout in Figure 1A includes layout patterns for specifying node connection structures 124A and 124B extending in the X direction in the lower conductive layer, layout patterns for specifying switch selection conductors 165A and 165B extending in the X direction in the lower conductive layer, and layout patterns for specifying power line conductors 184A and 184B extending in the X direction in the lower conductive layer.

[0022] As shown in Figures 1A to 1B, the first SRAM bit cell circuit SRAM1 is implemented by various components in the first part of the circuit cell 100 between cell boundary 102 and partition boundary 105, while the second SRAM bit cell circuit SRAM2 is implemented in the second part of the circuit cell 100 between partition boundary 105 and cell boundary 108. Each of the first SRAM bit cell circuit SRAM1 and the second SRAM bit cell circuit SRAM2 is implemented by two first-type transistors TU1 and TU2, two second-type transistors TD1 and TD2, and two switching transistors PG1 and PG2. Since the implementation of the first SRAM bit cell circuit SRAM1 and the second SRAM bit cell circuit SRAM2 is similar, the implementation of the first SRAM bit cell circuit SRAM1 will be described in more detail with reference to Figures 1A to 1B and Figures 2A to 2C.

[0023] As shown in Figures 1A to 1B, the first SRAM bit cell circuit SRAM1 is implemented by transistors in the first pair of stacked active region structures 80A. In Figure 1A, the gate conductor 154A (which is a CFET gate conductor) intersects with the first pair of stacked active region structures 80A as the connecting gate of the first CFET element CFET1. That is, the upper gate conductor in the gate conductor 154A intersects with the upper active region structure 82A at the channel region of the first type transistor TU1, and the lower gate conductor in the gate conductor 154A intersects with the lower active region structure 84A at the channel region of the second type transistor TD1. The upper and lower gate conductors in the gate conductor 154A are electrically connected together. The first type transistor TU1 and the second type transistor TD1 are stacked on top of each other to form the first CFET element CFET1.

[0024] Furthermore, the terminal conductor 134A (which is a CFET terminal conductor) intersects with the first pair of stacked active region structures 80A at the junction drain terminal of the first CFET element CFET1. That is, the upper terminal conductor of the terminal conductor 134A intersects with the upper active region structure 82A at the drain region of the first type transistor TU1 in the first CFET element CFET1, and the lower terminal conductor of the terminal conductor 134A intersects with the lower active region structure 84A at the drain region of the second type transistor TD1 in the first CFET element CFET1. The upper and lower terminal conductors of the terminal conductor 134A are electrically connected together.

[0025] Furthermore, gate conductor 152UA (which acts as a switch gate conductor) intersects with upper active region structure 82A at the channel region of the first switching transistor PG1. Terminal conductor 132UA intersects with upper active region structure 82A at the terminal region (i.e., source or drain region) of the first switching transistor PG1. The channel of the first switching transistor PG1 is coupled between terminal conductor 132UA and terminal conductor 134A. Terminal conductor 132UA (which acts as the first bit input-output (IO) terminal conductor BL) is further connected to bit line conductor 162A through via connection structure VD.

[0026] In Figure 1A, the gate conductor 156A (which is the CFET gate conductor) serves as the connecting gate of the second CFET element CFET2 and intersects with the first pair of stacked active region structures 80A. Specifically, the upper gate conductor of gate conductor 156A intersects with the upper active region structure 82A at the channel region of the first type transistor TU2, and the lower gate conductor of gate conductor 156A intersects with the lower active region structure 84A at the channel region of the second type transistor TD2. The upper and lower gate conductors of gate conductor 156A are electrically connected together. The first type transistor TU2 and the second type transistor TD2 are stacked on top of each other to form the second CFET element CFET2.

[0027] Furthermore, the terminal conductor 136A (which is the CFET terminal conductor) intersects with the first pair of stacked active region structures 80A at the junction drain terminal of the second CFET element CFET2. That is, the upper terminal conductor of terminal conductor 136A intersects with the upper active region structure 82A at the drain region of the first type transistor TU2 in the second CFET element CFET2, and the lower terminal conductor of terminal conductor 136A intersects with the lower active region structure 84A at the drain region of the second type transistor TD2 in the second CFET element CFET2. The upper and lower terminal conductors of terminal conductor 136A are electrically connected together.

[0028] Furthermore, the gate conductor 158UA (which acts as the switch gate conductor) intersects with the upper active region structure 82A at the channel region of the second switching transistor PG2. The terminal conductor 138UA intersects with the upper active region structure 82A at the terminal region (i.e., the source or drain region) of the second switching transistor PG2. The channel of the second switching transistor PG2 is coupled between the terminal conductor 138UA and the terminal conductor 136A. The terminal conductor 138UA (which acts as the second bit IO terminal conductor BLB) is further coupled to the bit line conductor 168A through the via connection structure VD.

[0029] In Figure 1A, the terminal conductor 135UA (which acts as the first power terminal conductor) intersects with the upper active region structure 82A at the source regions of the first type transistors TU1 and TU2. Therefore, the terminal conductor 135UA acts as the source terminal for both the first type transistor TU1 in the first CFET element CFET1 and the first type transistor TU2 in the second CFET element CFET2. The terminal conductor 135UA is further connected to the power line conductor 182A, which receives the first supply voltage.

[0030] Terminal conductor 135DA (which acts as a second power terminal conductor) intersects with the lower active region structure 84A at the source regions of the second type transistors TD1 and TD2. Therefore, terminal conductor 138UA acts as the source terminal for both the second type transistor TD1 in the first CFET element CFET1 and the second type transistor TD2 in the second CFET element CFET2. Terminal conductor 135DA is further connected to power line conductor 184A, which receives a second supply voltage.

[0031] In Figures 1A and 1B, each SRAM bit cell circuit (i.e., SRAM1 or SRAM2) is implemented by a first CFET element CFET1, a second CFET element CFET2, a first switching transistor PG1, and a second switching transistor PG2. The first CFET element CFET1 includes a first type transistor TU1 and a second type transistor TD1. The second CFET element CFET2 includes a first type transistor TU2 and a second type transistor TD2. The first type transistors TU1, TU2, PG1, and PG2 are identified in the upper part of the layout diagram in Figure 1B. The second type transistors TD1 and TD2 are identified in the lower part of the layout diagram in Figure 1B. Node connection structures 122A and 124A extending in the X direction for implementing the first SRAM bit cell circuit SRAM1 are also identified in Figure 1B. The circuit diagram in Figure 1C depicts the electrical connections of various components in the first SRAM bit cell circuit SRAM1 (or similarly, in the second SRAM bit cell circuit SRAM2).

[0032] Node connection structure 124A is conductively connected to end conductor 134A through via connection structure VD and conductively connected to gate conductor 156A through via connection structure VG. Therefore, the junction drain end of the first CFET element CFET1 (at end conductor 134A) and the junction gate (gate conductor 156A) of the second CFET element CFET2 are conductively connected together, forming the first connection node Node1. To form the junction drain end of the first CFET element CFET1, the drain ends of the first type transistor TU1 and the second type transistor TD1 are conductively connected together. To form the junction gate of the second CFET element CFET2, the gates of the first type transistor TU2 and the second type transistor TD2 are conductively connected together.

[0033] Node connection structure 122A is conductively connected to gate conductor 154A through via connection structure VG and conductively connected to terminal conductor 136A through via connection structure VD. Therefore, the junction gate of the first CFET element CFET1 (at gate conductor 154A) and the junction drain end of the second CFET element CFET2 (at terminal conductor 136A) are conductively connected together to form the second connection node Node2. To form the junction gate of the first CFET element CFET1, the gates of the first type transistor TU1 and the second type transistor TD1 are conductively connected together. To form the junction drain end of the second CFET element CFET2, the drain ends of the first type transistor TU2 and the second type transistor TD2 are conductively connected together.

[0034] In Figure 1A, since bit line conductor 162A is connected to terminal conductor 132UA, the conductive connection between bit line conductor 162A and the first connection node Node1 (at terminal conductor 134A) is determined by the connection state of the first switching transistor PG1. Therefore, the voltage applied to the gate conductor 152UA controls whether bit line conductor 162A is conductively connected to the first connection node Node1 or electrically isolated from the first connection node Node1.

[0035] Since bit line conductor 168A is connected to terminal conductor 138UA, the conductive connection between bit line conductor 168A and the second connection node Node2 (at terminal conductor 136A) is determined by the connection state of the second switching transistor PG2. Therefore, the voltage applied to gate conductor 158UA controls whether bit line conductor 168A is conductively connected to the second connection node Node2 or electrically isolated from the second connection node Node2.

[0036] In Figure 1A, the switch selection conductor 165A is electrically connected to each of the gate conductors 152DA and 158DA via corresponding through-hole connection structures (BVG). Gate conductors 152DA and 158DA, which intersect with the lower active region structure 84A, are correspondingly connected to gate conductors 152UA and 158UA, which intersect with the upper active region structure 82A. Therefore, the voltage applied to the switch selection conductor 165A controls whether the connection nodes Node1 and Node2 are correspondingly connected to the bit line conductors 162A and 168A for reading or writing bit values ​​stored in the first SRAM bit cell circuit SRAM1 (implemented by the first pair of stacked active region structures 80A).

[0037] In some embodiments, the first type transistors TU1 and TU2 in the upper active region structure 82A are NMOS transistors, while the second type transistors TD1 and TD2 in the lower active region structure 84A are PMOS transistors. The power line conductor 182A in the upper conductive layer is used to maintain a lower power supply voltage VSS, while the power line conductor 184A in the lower conductive layer is used to maintain a higher power supply voltage VDD. Figure 1C shows the equivalent circuit of the first SRAM bit cell circuit SRAM1 implemented by the first pair of stacked active region structures 80A. Node connection structures 124A and 122A are respectively labeled BCT1 and BCT2 in Figures 1C and 1B.

[0038] In some alternative embodiments, the first type transistors TU1 and TU2 in the upper active region structure 82A are PMOS transistors, while the second type transistors TD1 and TD2 in the lower active region structure 84A are NMOS transistors. The power line conductor 182A in the upper conductive layer is used to maintain a higher supply voltage VDD, while the power line conductor 184A in the lower conductive layer is used to maintain a lower supply voltage VSS. Those skilled in the art will understand that the equivalent circuit of the first SRAM bit cell circuit SRAM1 used in the alternative embodiments is a modification of the equivalent circuit in Figure 1C.

[0039] The cross-sectional views in Figures 2A to 2C also depict some of the components used to implement the first SRAM bit cell circuit SRAM1 in the first pair of stacked active region structures 80A in Figure 1A, as well as the interconnections between some of the components.

[0040] Figures 2A to 2C are cross-sectional views of the integrated circuit in Figure 1A according to some embodiments, corresponding to the cutting planes A-A', B-B', and C-C'. The CFET gate conductor of the first CFET element CFET1 is gate conductor 154A. The upper and lower gate conductors of gate conductor 154A intersect with the upper active region structure 82A and the lower active region structure 84A respectively at the corresponding channel regions of the first type transistor TU1 or the second type transistor TD1. The upper and lower gate conductors of gate conductor 154A are electrically connected together.

[0041] In Figures 2A to 2C, the gate conductor of the second CFET element CFET2 is gate conductor 156A. The upper and lower gate conductors of gate conductor 156A intersect with the upper active region structure 82A and the lower active region structure 84A respectively at the corresponding channel regions of the first type transistor TU2 or the second type transistor TD2. The upper and lower gate conductors of gate conductor 156A are electrically connected together.

[0042] In Figures 2A to 2C, the gate conductor of the first switching transistor PG1 is gate conductor 152UA, and the gate conductor of the second switching transistor PG2 is gate conductor 158UA.

[0043] In Figures 2A to 2C, the CFET terminal conductor of the first CFET element CFET1 is terminal conductor 134A. The upper and lower terminal conductors of terminal conductor 134A intersect with the upper active region structure 82A and the lower active region structure 84A respectively at the corresponding drain regions of the first type transistor TU1 or the second type transistor TD1. The upper and lower terminal conductors of terminal conductor 134A are electrically connected together through the inter-terminal connection line MDLI. The upper terminal conductor of terminal conductor 134A also enters the source / drain region of the first switching transistor PG1 (which has a channel region defined by the gate conductor 152UA).

[0044] In Figures 2A to 2C, the CFET terminal conductor of the second CFET element CFET2 is terminal conductor 136A. The upper and lower terminal conductors of terminal conductor 136A intersect with the upper active region structure 82A and the lower active region structure 84A respectively at the corresponding drain regions of the first type transistor TU2 or the second type transistor TD2. The upper and lower terminal conductors of terminal conductor 136A are electrically connected together through the inter-terminal connection line MDLI. The upper terminal conductor of terminal conductor 136A also enters the source / drain region of the second switching transistor PG2 (which has a channel region defined by the gate conductor 158UA).

[0045] The source terminals for both type 1 transistors TU1 and TU2 are located at the end conductor 135UA, which intersects with the upper active region structure 82A. The source terminals for both type 2 transistors TD1 and TD2 are located at the end conductor 135DA, which intersects with the lower active region structure 84A.

[0046] In Figure 2A, gate conductor 154A is electrically connected to node connection structure 122A through via connection structure VG, and terminal conductor 136A is electrically connected to node connection structure 122A through via connection structure VD. Therefore, node connection structure 122A connects gate conductor 154A and terminal conductor 136A while passing through gate conductor 156A without conducting electricity. Additionally, terminal conductor 135DA is electrically connected to power line conductor 184A through via connection structure BVD.

[0047] In Figure 2B, the terminal conductor 135UA is electrically connected to the power line conductor 182A through the through-hole connection structure VD. The gate conductor 156A is electrically connected to the node connection structure 124A through the through-hole connection structure BVG, and the terminal conductor 134A is electrically connected to the node connection structure 124A through the through-hole connection structure BVD. Therefore, the node connection structure 124A connects the terminal conductor 134A and the gate conductor 156A, while passing through the gate conductor 154A without conducting electricity.

[0048] In Figure 2C, terminal conductor 132UA intersects with the upper active region structure 82A at the terminal region (i.e., source or drain region) of the first switching transistor PG1, and terminal conductor 132UA is connected to bit line conductor 162A through via connection structure VD. Terminal conductor 138UA intersects with the upper active region structure 82A at the terminal region (i.e., source or drain region) of the second switching transistor PG2, and terminal conductor 138UA is connected to bit line conductor 168A through via connection structure VD. Gate conductor 152UA is connected to gate conductor 152DA, which is connected to switch selection conductor 165A through via connection structure BVG. Gate conductor 158UA is connected to gate conductor 158DA, which is connected to switch selection conductor 165A through via connection structure BVG. Therefore, each of the switching gate conductors of the first switching transistor PG1 and the second switching transistor PG1 is electrically connected to the switch selection conductor 165A.

[0049] In Figure 2A, node connection structure 122A is located in the upper conductive layer, and electric field conductor 184A is located in the lower conductive layer. In Figure 2B, electric field conductor 182A is located in the upper conductive layer, and node connection structure 124A is located in the lower conductive layer. In Figure 2C, bit line conductor 162A and bit line conductor 168A are each located in the upper conductive layer, and switch selection conductor 165A is located in the lower conductive layer.

[0050] In some embodiments, the upper conductive layer is a first front-side metal layer (such as a first metal layer MO) above the upper active region structure 82A, and each of the via conductors VD and VG in Figures 2A to 2C passes through the interlayer dielectric ILD0 between the first front-side metal layer and the upper active region structure. The lower conductive layer is a first back-side metal layer (such as a first back-side metal layer BMO) below the lower active region structure 84A, and each of the via conductors BVD and BVG in Figures 2A to 2C passes through the substrate 30. In some alternative embodiments, the lower conductive layer is a buried metal layer between the lower active region structures (i.e., 84A and 84B) and the substrate 30. Each of the via conductors BVD and BVG passes through the dielectric between the lower active region structures (i.e., 84A and 84B) and the buried metal layer.

[0051] In some embodiments, each of the active region structures in Figures 2A to 2C includes a plurality of nanosheets extending in the X direction. For example, as shown in Figures 2A to 2C, the upper active region structure 82A includes nanosheets 82A1, 82A2, and 82A3 extending in the X direction, and the lower active region structure 84A includes nanosheets 84A1, 84A2, and 84A3 extending in the X direction. Other embodiments of the active region structure (such as those utilizing nanowires) are within the scope of this disclosure.

[0052] In Figures 2A to 2C, boundary isolation regions i101UA and i109UA are implemented in the upper active region structure 82A, and boundary isolation regions i101DA and i109DA are implemented in the lower active region structure 84A. Due to boundary isolation regions i101UA, i109UA, i101DA, and i109DA, the active regions (e.g., channel regions, or source / drain regions) of the transistors in the first SRAM bit cell circuit SRAM1 are isolated from other active regions outside the circuit cell 100 but within the first pair of stacked active region structures 80A. Similarly, as shown in Figure 1A, due to boundary isolation regions i101UB, i109UB, i101DB, and i109DB, the active regions of the transistors in the second SRAM bit cell circuit SRAM2 are isolated from other active regions outside the circuit cell 100 but within the second pair of stacked active region structures 80B.

[0053] The bit line conductors (e.g., 162A, 168A, 162B and 168B) and switch selection conductors (e.g., 165A and 165B) in the SRAM bit cell circuits SRAM1 and SRAM2 are connected to various conductors in other conductive layers, as depicted in Figures 3A to 3B and Figure 4.

[0054] Figure 3A is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having a layout pattern specifying additional components in a layer above or below the components shown in Figure 1A. Figure 3B is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having a layout pattern specifying additional components in a layer above the components shown in Figures 3A and 1A. Figure 4 is a cross-sectional view of an integrated circuit according to some embodiments along the cutting plane C-C' in Figure 1A, and includes various components as specified in Figures 1A, 3A through 3B, and 4.

[0055] The layout diagram in Figure 3A includes an upper portion and a lower portion of the layout. The lower portion of the layout includes a layout pattern for specifying node connection structures 124A and 124B in the lower conductive layer and switch selection conductors 165A and 165B in the lower conductive layer. In some embodiments, the lower conductive layer containing node connection structures and switch selection conductors extending in the X direction is a first backside metal layer BMO on the back side of the substrate (located below the CFET in the integrated circuit). The lower portion of the layout further includes a layout pattern for specifying word lines 375A and 375B extending in the Y direction in a second backside metal layer BM1 below the first backside metal layer BMO. Switch selection conductor 165A is connected to word line 375A in the second backside metal layer BM1 through a via connection structure BV0. Switch selection conductor 165B is connected to word line 375B in the second backside metal layer BM1 through a via connection structure BV0. The cross-sectional view in Figure 4 depicts the through-hole connection structure BV0 connecting the switch select conductor 165A and the character line 375A. The through-hole connection structure BV0 passes through the interlayer dielectric between the first back metal layer BM0 and the second back metal layer BM1.

[0056] In Figure 3A, the upper portion of the layout includes a layout pattern for specifying node interconnect structures 122A and 122B in the upper conductive layer and bit line conductors 162A, 168A, 162B, and 168B in the upper conductive layer. In some embodiments, the upper conductive layer containing node interconnect structures and bit line conductors extending in the X direction is a first metal layer M0 above a CFET in an integrated circuit. The upper portion of the layout further includes a layout pattern for specifying bit line interconnect extensions 372 and 378 extending in the Y direction in a second metal layer M1 above the first metal layer M0. Each of the bit line conductors 162A and 162B in the first metal layer M0 is connected to the bit line interconnect extension 372 in the second metal layer M1 through a corresponding via connection structure V0. Each of the bit line conductors 168A and 168B in the first metal layer M0 is connected to the bit line interconnect extension 378 in the second metal layer M1 through a corresponding via connection structure V0.

[0057] Furthermore, as shown in Figure 3B, each of the bit line interconnect extensions 372 and 378 in the second metal layer M1 is connected to a corresponding bit line (i.e., 362A or 368B) extending in the X direction in the third metal layer M2 above the second metal layer M1. The bit line interconnect extensions 372 and 378 are correspondingly connected to bit lines 362A and 368B via corresponding via connection structures V1. Therefore, through bit line conductors 162A and 162B and bit line interconnect extension 372, both end conductors 132UA and 132UB (in Figure 1A) are electrically connected to bit line 362A. Through bit line conductors 168A and 168B and bit line interconnect extension 378, both end conductors 138UA and 138UB (in Figure 1A) are electrically connected to bit line 368B. Each of the terminal conductors 132UA and 132UB serves as the first bit IO terminal conductor BL for the corresponding SRAM bit cell circuit (i.e., SRAM1 or SRAM2). Each of the terminal conductors 138UA and 138UB serves as the second bit IO terminal conductor BLB for the corresponding SRAM bit cell circuit (i.e., SRAM1 or SRAM2).

[0058] The cross-sectional view in Figure 4 depicts the conductive connection from end conductor 132UA to bit line 362A. The via connection structure VD between end conductor 132UA and bit line conductor 162A passes through the interlayer dielectric ILD0 beneath the first metal layer M0. The via connection structure V0 between bit line conductor 162A and bit line interconnect extension 372 passes through the interlayer dielectric ILD1 between the first metal layer M0 and the second metal layer M1. The via connection structure V1 between bit line interconnect extension 372 and bit line 362A passes through the interlayer dielectric ILD2 between the second metal layer M1 and the third metal layer M2.

[0059] The cross-sectional view in Figure 4 also depicts the conductive connection from the end conductor 138UA to the bit line interconnect extension 378. The via connection structure VD between the end conductor 138UA and the bit line conductor 168A passes through the interlayer dielectric ILD0 beneath the first metal layer M0. The via connection structure V0 between the bit line conductor 168A and the bit line interconnect extension 378 passes through the interlayer dielectric ILD1 between the first metal layer M0 and the second metal layer M1.

[0060] In Figure 3A, each of the bit line conductors 162A and 162B in circuit unit 100 extends through unit boundary 101 and merges with the corresponding bit line conductors in adjacent circuit units. The bit line interconnection extension 372 located at unit boundary 101 overlaps with two circuit units adjacent to each other at unit boundary 101. Each of the bit line conductors 168A and 168B in circuit unit 100 extends through unit boundary 109 and merges with the corresponding bit line conductors in adjacent circuit units. The bit line interconnection extension 378 located at unit boundary 109 overlaps with two circuit units adjacent to each other at unit boundary 109. Furthermore, each of the power line conductors 182A and 182B extends in the X direction and passes through both unit boundaries 101 and 109.

[0061] In some alternative embodiments, each of the bit line conductors 162A and 162B in circuit cell 100 does not extend through cell boundary 101. In some alternative embodiments, the bit line interconnect extension 372 does not overlap with adjacent circuit cells sharing cell boundary 101 with circuit cell 100. In some alternative embodiments, each of the bit line conductors 168A and 168B in circuit cell 100 does not extend through cell boundary 109. In some alternative embodiments, the bit line interconnect extension 378 does not overlap with adjacent circuit cells sharing cell boundary 109 with circuit cell 100.

[0062] In the embodiment shown in Figure 1A, each of the SRAM bit cell circuits SRAM1 and SRAM2 in circuit unit 100 includes a first node connection structure (e.g., 122A or 122B) in the upper conductive layer and a second node connection structure (e.g., 124A or 124B) in the lower conductive layer. In some alternative embodiments, each of the SRAM bit cell circuits SRAM1 and SRAM2 in circuit unit includes two node connection structures in the upper conductive layer (implemented to serve as node connection structures BCT1 and BCT2 in Figure 1C). In some alternative embodiments, each of the SRAM bit cell circuits SRAM1 and SRAM2 in circuit unit includes two node connection structures in the lower conductive layer (implemented to serve as node connection structures BCT1 and BCT2 in Figure 1C).

[0063] In the embodiment shown in Figure 1A, even though each of end conductors 135UA and 135UB is used to receive the same first power supply voltage (e.g., a lower power supply VSS), end conductors 135UA and 135UB are separated by a gap in the Y direction. In some alternative embodiments, end conductors 135UA and 135UB are connected together in the Y direction. Similarly, in the embodiment shown in Figure 1A, even though each of end conductors 135DA and 135DB is used to receive the same second power supply voltage (e.g., a lower high power supply VDD), end conductors 135DA and 135DB are separated by a gap in the Y direction. In some alternative embodiments, end conductors 135DA and 135DB are connected together in the Y direction.

[0064] In the embodiment shown in Figure 1A, end conductors 132UA and 132UB are separated by a gap in the Y direction, and end conductors 138UA and 138UB are also separated by a gap in the Y direction. In some alternative embodiments, end conductors 132UA and 132UB are joined together in the Y direction. In some alternative embodiments, end conductors 138UA and 138UB are joined together in the Y direction.

[0065] Figures 5A to 5B and 6A to 6B depict some variations of the circuit unit 100 in Figures 1A to 1B. Figure 5A is a layout diagram of an integrated circuit according to some embodiments, which has a static random access memory circuit implemented in the circuit unit by CFET elements. The circuit unit 500 in Figure 5A is a modification of the circuit unit 100 in Figure 1A. Terminal conductors 135UA and 135UB in Figure 1A are connected together in the upper part of Figure 5A as terminal conductor 135U, and terminal conductor 135U intersects with both the upper active region structure 82A and the upper active region structure 82B. Terminal conductors 135DA and 135DB in Figure 1A are connected together in the lower part of Figure 5A as terminal conductor 135D, and terminal conductor 135D intersects with both the lower active region structure 84A and the lower active region structure 84B. Furthermore, in Figure 1A, end conductors 132UA and 132UB are connected together in the upper part of Figure 5A to form end conductor 132U, and end conductor 132U intersects with both the upper active region structure 82A and the upper active region structure 82B. Similarly, in Figure 1A, end conductors 138UA and 138UB are connected together in the upper part of Figure 5A to form end conductor 138U, and end conductor 138U intersects with both the upper active region structure 82A and the upper active region structure 82B.

[0066] Another difference between circuit unit 500 in Figure 5A and circuit unit 100 in Figure 1A is the implementation of node connection structures 122A and 122B. In circuit unit 500 of Figure 5A, node connection structures 122A and 122B are implemented in the lower conductive layer. For comparison, in circuit unit 100 of Figure 1A, node connection structures 122A and 122B are implemented in the upper conductive layer. In both Figure 1A and Figure 5A, node connection structure 122A is conductively connected between gate conductor 154A and terminal conductor 136A, and node connection structure 122B is conductively connected between gate conductor 154B and terminal conductor 136B.

[0067] The layout of the bit line conductors and power line conductors in circuit unit 500 of Figure 5A is also different from that in circuit unit 100 of Figure 1A. In circuit unit 500, as shown in the upper part of Figure 5A, the bit line conductor 162 extending in the X direction overlaps with the first pair of stacked active region structures 80A, and the bit line conductor 168 extending in the X direction overlaps with the second pair of stacked active region structures 80B. The bit line conductor 162 is conductively connected to the end conductor 132U through a corresponding via connection structure VD, and the bit line conductor 168 is conductively connected to the end conductor 138U through a corresponding via connection structure VD, while each of the bit line conductors 162 and 168 passes through both the end conductors 132U and 138U.

[0068] In circuit unit 500, as shown in the upper part of Figure 5A, two electric field conductors 182 extending in the X direction are correspondingly positioned at unit boundaries 101 and 109, and an electric field conductor 184 in the X direction is positioned between the first pair of stacked active region structures 80A and the second pair of stacked active region structures 80B. Each of the three electric field conductors 182 is connected to the end conductor 135U through a corresponding through-hole connection structure VD.

[0069] Additionally, bit line conductors 162 and 168 are interleaved with three power line conductors 182. With one of the three power line conductors extending parallel in the X direction between bit line conductors 162 and 168, the power line conductor between two bit line conductors in the same conductive layer provides signal ground, thus reducing parasitic capacitive coupling between the two bit line conductors. Each of the bit line conductors 162 and 168 in circuit unit 500 of Figure 5A has a wider width than any of the bit line conductors in circuit unit 100 of Figure 1A because there is more layout space between the power lines available for implementing bit line conductors 162 and 168 compared to the available layout space in circuit unit 100.

[0070] In circuit unit 500, as shown in the lower part of Figure 5A, two electric field conductors 184 extending in the X direction are correspondingly positioned at unit boundaries 101 and 109, and one electric field conductor 184 in the X direction is positioned between the first pair of stacked active region structures 80A and the second pair of stacked active region structures 80B. Each of the three electric field conductors 184 is connected to the end conductor 135D through a corresponding through-hole connection structure BVD.

[0071] In circuit unit 500, the upper part of Figure 5B depicts the connection of bit line conductors 162 and 168 to bit line interconnection extensions in another conductive layer, and the lower part of Figure 5B depicts the connection of switch selection conductors 365A and 365B to word lines in another conductive layer.

[0072] In the upper part of the layout diagram in Figure 5B, a bit line conductor 162 extending in the X direction in an upper conductive layer (e.g., a first metal layer M0) is connected via a corresponding via connection structure V0 to a bit line interconnect extension 372 extending in the Y direction in another upper conductive layer (e.g., a second metal layer M1). A bit line conductor 168 extending in the X direction in an upper conductive layer (e.g., a first metal layer M0) is connected via a corresponding via connection structure V0 to a bit line interconnect extension 378 extending in the Y direction in another upper conductive layer (e.g., a second metal layer M1).

[0073] In the lower part of the layout diagram in Figure 5B, a switch selection conductor 165A extending in the X direction in a lower conductive layer (e.g., a first back metal layer BM0) is connected via a corresponding via connection structure BV0 to a word line 375A extending in the Y direction in another lower conductive layer (e.g., a second back metal layer BM1). Similarly, a switch selection conductor 165B extending in the X direction in a lower conductive layer (e.g., a first metal layer BM1) is connected via a corresponding via connection structure BV0 to a word line 375B extending in the Y direction in another lower conductive layer (e.g., a second back metal layer BM1).

[0074] In circuit unit 500, as shown in the lower portion of Figure 5A, switch selection conductor 165A extends in the X direction between node connection structure 122A and node connection structure 124A, and switch selection conductor 165B extends in the X direction between node connection structure 122B and node connection structure 124B. Other layout configurations of the switch selection conductors and node connection structures are within the scope of this disclosure. Various example variations of the layout configuration are depicted in Figures 6A to 6B, each of which specifies the lower portion of the layout diagram of circuit unit 500.

[0075] In Figure 6A, node connection structure 122A extends in the X direction between switch selection conductor 165A and node connection structure 124A, while node connection structure 122B extends in the X direction between switch selection conductor 165B and node connection structure 124B. In Figure 6B, node connection structure 124A extends in the X direction between node connection structure 122A and switch selection conductor 165A, while node connection structure 124B extends in the X direction between node connection structure 122B and switch selection conductor 165B.

[0076] In Figures 1A and 5A, each of circuit unit 100 and circuit unit 500 includes two SRAM bit cell circuits: a first SRAM bit cell circuit SRAM1 implemented by transistors in a first pair of stacked active region structures (e.g., 80A) and a second SRAM bit cell circuit SRAM2 implemented by transistors in a second pair of stacked active region structures (e.g., 80B). In some alternative embodiments, exemplary circuit units specified by the layout diagrams in Figures 7A to 7B include more than two SRAM bit cell circuits.

[0077] Figures 7A and 7B correspond to the upper and lower portions of a layout diagram of a circuit cell 700 according to some embodiments, which has four SRAM circuits implemented by CFET elements. In Figures 7A and 7B, the circuit cell 700 is bounded by cell boundaries 701 and 709 extending in the Y direction and cell boundaries 702 and 708 extending in the X direction. Similar to the isolation regions at cell boundaries 101 and 109 in Figure 1A, the boundary isolation regions in the active region structures at cell boundaries 701 and 709 in Figures 7A and 7B isolate the active regions of the transistors in the SRAM circuits of the circuit cell 700 from other active regions outside the circuit cell 700.

[0078] In Figures 7A and 7B, circuit unit 700 includes four SRAM bit cell circuits: two SRAM bit cell circuits SRAM1 and SRAM1b implemented by transistors in the first pair of stacked active region structures 80A, and two SRAM bit cell circuits SRAM2 and SRAM2b implemented by transistors in the second pair of stacked active region structures 80B. Similar to the SRAM bit cell circuits SRAM1 and SRAM2 in circuit unit 500 of Figure 5A, each of SRAM bit cell circuits SRAM1 and SRAM1b is implemented by two CFET elements (i.e., CFET1 and CFET2) and two switching transistors (i.e., PG1 and PG2) in the first pair of stacked active region structures 80A, and each of SRAM bit cell circuits SRAM2 and SRAM2b is implemented by two CFET elements (i.e., CFET1 and CFET2) and two switching transistors (i.e., PG1 and PG2) in the second pair of stacked active region structures 80B. Each CFET element CFET1 includes a first type transistor TU1 and a second type transistor TD1, and each CFET element CFET2 includes a first type transistor TU2 and a second type transistor TD2.

[0079] In each of the SRAM bit cell circuits SRAM1, SRAM2, SRAM1b, and SRAM2b, as shown in Figure 7B, node connection structure BCT1 electrically connects the drain terminal of type-2 transistor TD1 to the gate terminal of type-2 transistor TD2, while node connection structure BCT2 electrically connects the gate terminal of type-2 transistor TD1 to the drain terminal of type-2 transistor TD2. Additionally, the switch selection conductor WL in each of the SRAM bit cell circuits electrically connects the gate terminal of switching transistor PG1 to the gate terminal of switching transistor PG2.

[0080] In Figures 7A and 7B, SRAM bit cell circuits SRAM1 and SRAM2 are implemented in the first half of circuit cell 700 near cell boundary 701. SRAM bit cell circuits SRAM1b and SRAM2b are implemented in the second half of circuit cell 700 near cell boundary 709.

[0081] In Figure 7A, terminal conductor 135U (which serves as the source terminals of the first type transistors TU1 and TU2 in both SRAM cell circuits SRAM1 and SRAM2) is connected to the three power line conductors 182 via a via connection structure. Terminal conductor 135UB (which serves as the source terminals of the first type transistors TU1 and TU2 in both SRAM cell circuits SRAM1b and SRAM2b) is also connected to the three power line conductors 182 via a via connection structure.

[0082] In Figure 7B, terminal conductor 135D (which serves as the source terminals of the second type transistors TD1 and TD2 in both SRAM cell circuits SRAM1 and SRAM2) is connected to the three power line conductors 184 via a via connection structure. Terminal conductor 135DB (which serves as the source terminals of the second type transistors TD1 and TD2 in both SRAM cell circuits SRAM1b and SRAM2b) is also connected to the three power line conductors 184 via a via connection structure.

[0083] In Figure 7A, terminal conductor 132U (which serves as the source / drain terminal of the switching transistor PG1 adjacent to cell boundary 701 in each of the SRAM cell circuits SRAM1 and SRAM2) is conductively connected to bit line conductor 162 via via connection structure VD. Terminal conductor 132UB (which serves as the source / drain terminal of the switching transistor PG1 adjacent to cell boundary 709 in each of the SRAM cell circuits SRAM1b and SRAM2b) is also conductively connected to bit line conductor 162 via via connection structure VD. Therefore, for each of the SRAM cell circuits SRAM1, SRAM2, SRAM1b, and SRAM2b, bit line conductor 162 is conductively connected to the first cell IO terminal conductor BL.

[0084] Furthermore, in Figure 7A, the terminal conductor 138U (which serves as the source / drain terminal of the switching transistor PG2 in each of the SRAM bit cell circuits SRAM1, SRAM2, SRAM1b, and SRAM2b) is conductively connected to the bit line conductor 168 through the via connection structure VD. Therefore, for each of the SRAM bit cell circuits SRAM1, SRAM2, SRAM1b, and SRAM2b, the bit line conductor 168 is conductively connected to the second bit IO terminal conductor BLB.

[0085] In Figure 7B, each switch selection conductor WL is implemented to select or deselect the corresponding bit cell circuit for reading or writing. In operation, a voltage signal applied to the switch selection conductor WL determines which of the four bit cell circuits (i.e., SRAM1, SRAM2, SRAM1b, or SRAM2b) is selected for reading or writing. The first connection node Node1 in the selected bit cell circuit is conductively connected to bit line conductor 162, while the second connection node Node2 in the selected bit cell circuit is conductively connected to bit line conductor 168. Connection nodes Node1 and Node2 in the remaining three unselected bit cell circuits are decoupled from bit line conductors 162 and 168. Figure 7C depicts the connections between the switch selection conductor WL and some of the word lines passing through circuit cell 700.

[0086] Figure 7C is the lower portion of a layout diagram of a circuit unit 700 according to some embodiments, the circuit unit 700 having a layout pattern for specifying word lines connected to switch selection conductors WL. In some embodiments, the switch selection conductors WL (all extending in the X direction) are fabricated in a first back-side metal layer BMO (located below the CFET in the integrated circuit) on the back side of the substrate. Word lines 375A, 375B, 375Ab, and 375Bb (all extending in the Y direction) are fabricated in a second back-side metal layer BM1 below the first back-side metal layer BMO. The switch selection conductors WL in the SRAM bit cell circuits SRAM1, SRAM2, SRAM1b, and SRAM2b are correspondingly connected to word lines 375A, 375B, 375Ab, and 375Bb via via connection structures BV0.

[0087] During operation, a selection voltage signal is applied to one of the four word lines 375A, 375B, 375Ab, and 375Bb, while a deselection voltage signal is applied to the remaining three word lines. Its switch selection conductor WL is connected to the SRAM bit cell circuit with the word line containing the selection voltage signal, becoming the selected bit cell circuit for reading or writing.

[0088] Figure 8 illustrates an alternative implementation of the integrated circuit in Figure 7A. The integrated circuit shown in Figure 8 is a modification of the integrated circuit in Figure 7A by changing the positions of bit line conductors 162 and 168 along the Y direction. In Figure 8, each of the bit line conductors 162 and 168 extending in the X direction is asymmetrically positioned between two electric field conductors. In some embodiments, a first distance along the Y direction separating bit line conductor 162 from electric field conductor 182L is at least twice the second distance along the Y direction separating bit line conductor 162 from electric field conductor 182C. A first distance along the Y direction separating bit line conductor 168 from electric field conductor 182C is at least twice the second distance along the Y direction separating bit line conductor 168 from electric field conductor 182R.

[0089] In some embodiments, the transistors in circuit cells 100, 500, or 700 (corresponding to layout designs as shown in Figures 1A, 5A, and 7A) are not always implemented with the same threshold values. In some modifications, transistors TU1, TU2, TD1, and TD2 in each SRAM bit cell circuit of the circuit cells (e.g., 100, 500, and 700) have a first threshold value Vth1, while transistors PG1 and PG2 in the same SRAM bit cell circuit have a second threshold value Vth2. In integrated circuits formed by matrices of circuit cells, where each circuit cell is implemented based on one of the currently disclosed layout designs (such as those in Figures 1A, 5A, and 7A), transistors with the same threshold values ​​are grouped into a larger layout area compared to some existing layout designs.

[0090] Figure 9 is a schematic diagram of some portions of a matrix of circuit cells according to some embodiments. In one example, the matrix of circuit cells in Figure 9 is formed by circuit cells as shown in Figure 1B. The circuit cells in Figure 9 are arranged in multiple columns (along the Y direction). Three columns of circuit cells (i.e., columns L, M, and N) are schematically identified in Figure 9. Two circuit cells 100MA and 100MB in column M are shown in more detail, but the remaining circuit cells in column M (such as 100MC, etc.) are not explicitly shown. Only transistors PG1 in selected circuit cells (i.e., 100LA and 100LB) in column L are depicted, and only transistors PG2 in selected circuit cells (i.e., 100NA and 100NB) in column N are depicted. The transistors in layout area 910 (between edges 901 and 902 extending in the Y direction) are manufactured by a first threshold value Vth1. The transistors in layout region 910 include transistors TU1, TU2, TD1, and TD2 in each SRAM bit cell circuit of the circuit cell in column M (note that transistors TD1 and TD2 are not explicitly shown in Figure 9). The transistors in layout region 920 (between edges 901 and 903 extending in the Y direction) are manufactured using the second threshold value Vth2, and the transistors in layout region 920 include transistor PG1 in each SRAM bit cell circuit of the circuit cell in column M. The transistors in layout region 930 (between edges 903 and 904 extending in the Y direction) are manufactured using the second threshold value Vth2, and the transistors in layout region 930 include transistor PG2 in each SRAM bit cell circuit of the circuit cell in column N.

[0091] In some embodiments, during component manufacturing, each layout region (910, 920, or 930) of a single threshold value is defined by one or more masks. Since each layout region (910, 920, or 930) of a single threshold value forms strips parallel to the columns of the matrix along the Y direction, the layout design of circuit cells 100, 500, and 700 (correspondingly in Figures 1A, 5A, and 7A) enables a more user-friendly manufacturing process for defining the layout regions of the single threshold values, compared to some existing layout designs where the layout regions of the single threshold values ​​intersect each other in a checkerboard pattern.

[0092] Figure 10 is a flowchart of a method 1000 for fabricating an integrated circuit (IC) with CFET elements according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1000 depicted in Figure 10, and only some other processes may be briefly described herein.

[0093] In operation 1010 of method 1000, a lower active region structure extending in the X direction is formed on a substrate. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, a lower active region structure 84A is formed on substrate 30.

[0094] In operation 1012 of method 1000, four lower gate conductors intersecting with the lower active region structure are formed. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, lower portions of gate conductors 152DA and 158DA, as well as gate conductors 154A and 156A, intersecting with the lower active region structure 84A are formed.

[0095] In operation 1014 of method 1000, three lower end conductors intersecting with the lower active region structure are formed. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, the lower portions of end conductors 135DA and end conductors 134A and 136A intersecting with the lower active region structure 84A are formed.

[0096] In operation 1020 of method 1000, an upper active region structure extending in the X direction is manufactured, and the upper active region structure is stacked with the lower active region structure. In the exemplary embodiments shown in Figures 1A to 1B and Figures 2A to 2C, an upper active region structure 82A is manufactured, and the upper active region structure 82A is stacked with the lower active region structure 84A.

[0097] In operation 1022 of method 1000, four upper gate conductors intersecting with the upper active region structure are formed. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, upper portions of gate conductors 152UA and 158UA and gate conductors 154A and 156A intersecting with the upper active region structure 82A are formed.

[0098] In operation 1024 of method 1000, three upper conductors intersecting with the upper active region structure are formed. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, the upper portions of end conductor 135UA and end conductors 134A and 136A intersecting with the upper active region structure 82A are formed.

[0099] In operation 1030 of method 1000, a first node connection structure extending in the X direction is formed in the lower conductive layer, and the first node connection structure conductively connects the first lower end conductor to the third lower gate conductor. In the exemplary embodiments shown in Figures 1A to 1B and Figures 2A to 2C, a node connection structure 124A is formed in the lower conductive layer, and the node connection structure 124A conductively connects the lower part of the end conductor 134A to the lower part of the gate conductor 156A.

[0100] In operation 1040 of method 1000, a second node connection structure extending in the X direction is formed in the upper conductive layer, and the second node connection structure conductively connects the third upper conductor to the second upper gate conductor. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, a node connection structure 122A is formed in the front metal layer M0, and the node connection structure 122A conductively connects the upper part of the end conductor 136A to the upper part of the gate conductor 154A.

[0101] In operation 1050 of method 1000, a first switch selection conductor extending in the X direction is formed, and the first switch selection conductor is electrically connected between a first lower gate conductor and a fourth lower gate conductor. In the exemplary embodiment shown in Figures 1A to 1B and Figures 2A to 2C, a switch selection conductor 165A is formed in the back metal layer BMO, and the switch selection conductor 165A is electrically connected between gate conductor 152DA and gate conductor 158DA.

[0102] In some alternative embodiments, in operation 1040 of method 1000, a second node connection structure extending in the X direction is formed in the lower conductive layer, and the second node connection structure conductively connects the third lower end conductor to the second lower gate conductor. In the exemplary embodiment shown in Figure 5A, a node connection structure 122A is formed in the back metal layer BMO, and the node connection structure 122A conductively connects the lower portion of the end conductor 136A to the lower portion of the gate conductor 154A.

[0103] Figure 11 is a block diagram of an electronic design automation (EDA) system 1100 according to some embodiments.

[0104] In some embodiments, EDA system 1100 includes an automatic placement and routing (APR) system. The design layout methods described herein represent wiring configurations according to one or more methods, and may be implemented using EDA system 1100, for example, according to some embodiments.

[0105] In some embodiments, the EDA system 1100 is a general-purpose computing element including a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. Among other things, the storage medium 1104 is also encoded (i.e., stored) with computer program code 1106, that is, a set of executable instructions. The hardware processor 1102 executes the instructions 1106 to represent (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0106] Processor 1102 is electrically coupled to computer-readable storage medium 1104 via bus 1108. Processor 1102 is also electrically coupled to I / O interface 1110 via bus 1108. Network interface 1112 is also electrically connected to processor 1102 via bus 1108. Network interface 1112 is connected to network 1114, enabling processor 1102 and computer-readable storage medium 1104 to be connected to external components via network 1114. Processor 1102 is used to execute computer program code 1106 encoded in computer-readable storage medium 1104 so that system 1100 can be used to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1102 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0107] In one or more embodiments, the computer-readable storage medium 1104 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1104 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1104 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0108] In one or more embodiments, storage medium 1104 stores computer program code 1106 that enables system 1100 (wherein the execution representative (at least partially) EDA tools) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1104 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1104 stores a standard cell library 1107 including standard cells of the type disclosed herein. In one or more embodiments, storage medium 1104 stores one or more layout figures 1109 corresponding to one or more layouts disclosed herein.

[0109] EDA system 1100 includes an I / O interface 1110. The I / O interface 1110 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 1102.

[0110] EDA system 1100 also includes a network interface 1112 coupled to processor 1102. Network interface 1112 allows system 1100 to communicate with a network 1114 to which one or more other computer systems are connected. Network interface 1112 includes wireless network interfaces such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 1100.

[0111] System 1100 receives information through I / O interface 1110. The information received through I / O interface 1110 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1102. This information is transmitted to processor 1102 via bus 1108. EDA system 1100 receives information related to the user interface (UI) through I / O interface 1110. This information is stored as UI 1142 on computer-readable media 1104.

[0112] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by EDA system 1100. In some embodiments, tools such as VIRTUOSO® or other suitable layout generation tools available from CADENCE DESIGN SYSTEMS, Inc. are used to generate layout diagrams including standard cells.

[0113] In some embodiments, such processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs), memory cards, and one or more of the like.

[0114] Figure 12 is a block diagram of an integrated circuit (IC) fabrication system 1200 and an associated IC fabrication process according to some embodiments. In some embodiments, based on a layout diagram, the fabrication system 1200 is used to fabricate at least one of (A) one or more semiconductor masks or (B) at least one element in a layer of semiconductor integrated circuits.

[0115] In Figure 12, the IC fabrication system 1200 includes entities such as design studio 1220, enclosure room 1230, and IC fabricator / manufacturer (wafer fab) 1250, which interact with each other in the design, development, and manufacturing cycle or in services related to the fabrication of IC components 1260. The entities in system 1200 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 1220, enclosure room 1230, and IC wafer fab 1250 are owned by a single larger company. In some embodiments, two or more of the design studio 1220, enclosure room 1230, and IC wafer fab 1250 coexist in a shared facility and use shared resources.

[0116] Design studio (or design team) 1220 generates IC design layout 1222. IC design layout 1222 includes various geometric patterns designed for IC component 1260. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC component 1260 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1222 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, vias for metal lines or interlayer interconnects, and openings in bonding pads, as well as various material layers disposed on the semiconductor substrate. Design studio 1220 performs appropriate design procedures to form IC design layout 1222. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1222 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1222 may be expressed in GDSII file format or DFII file format.

[0117] Mask room 1230 includes data preparation 1232 and mask fabrication 1244. Mask room 1230 uses an IC design layout 1222 to fabricate one or more masks 1245 for use in manufacturing various layers of IC components 1260 according to the IC design layout 1222. Mask room 1230 performs mask data preparation 1232, in which the IC design layout 1222 is converted into a representative data file (RDF). Mask data preparation 1232 provides the RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reduction mask) 1245 or a semiconductor wafer 1253. The design layout 1222 is manipulated by mask data preparation 1232 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1250. In Figure 12, the mask data preparation 1232 and the mask manufacturing 1244 are shown as separate components. In some embodiments, the mask data preparation 1232 and the mask manufacturing 1244 may be collectively referred to as mask data preparation.

[0118] In some embodiments, mask data preparation 1232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1222. In some embodiments, mask data preparation 1232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0119] In some embodiments, mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout 1222, which has already been processed in OPC, using a set of mask generation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for lithography effects during mask fabrication 1244, and can revert portions of the modifications performed by OPC to satisfy the mask generation rules.

[0120] In some embodiments, mask data preparation 1232 includes lithography process checking (LPC), a simulation of which is performed by IC wafer fab 1250 to manufacture IC device 1260. LPC simulates this process based on IC design layout 1222 to create simulated manufactured devices, such as IC device 1260. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after creating simulated manufactured devices using LPC, if the simulated devices are not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1222.

[0121] It should be understood that, for clarity, the above description of the mask data preparation 1232 has been simplified. In some embodiments, data preparation 1232 includes additional features such as logic operations (LOPs) to modify the IC design layout 1222 according to manufacturing rules. Furthermore, the procedures applied to the IC design layout 1222 during data preparation 1232 can be executed in various different sequences.

[0122] After mask data preparation 1232 and during mask manufacturing 1244, a mask 1245 or a set of masks 1245 is manufactured based on a modified IC design layout 1222. In some embodiments, mask manufacturing 1244 includes performing one or more lithography exposures based on the IC design layout 1222. In some embodiments, a pattern is formed on the mask (photomask or magnifying mask) 1245 using an electron beam or multiple electron beams based on the modified IC design layout 1222. The mask 1245 can be formed using various techniques. In some embodiments, the mask 1245 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas, with radiation beams (such as ultraviolet (UV) beams) blocked by the opaque areas and passing through the transparent areas to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer. In one embodiment, a binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in opaque areas of the binary mask. In another embodiment, mask 1245 is formed using a phase shift mask (PSM) technique. In a phase shift mask (PSM) version of mask 1245, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various embodiments, the phase shift mask may be a micro-attenuated PSM or an alternating PSM. One or more masks produced by mask fabrication 1244 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1253, in etching processes to form various etched regions in semiconductor wafer 1253, and / or in other suitable processes.

[0123] IC wafer fab 1250 is an IC manufacturing enterprise that includes one or more fabrication facilities for manufacturing various IC products. In some embodiments, IC wafer fab 1250 is a semiconductor foundry. For example, there may be one fabrication facility for front-end manufacturing (front-end-of-line, FEOL) of multiple IC products, a second fabrication facility for back-end manufacturing (back-end-of-line, BEOL) of interconnects and packaging for IC products, and a third fabrication facility for providing additional services for foundry operations.

[0124] IC wafer fab 1250 includes wafer fabrication tooling 1252 for performing various manufacturing operations on semiconductor wafers 1253 to fabricate IC devices 1260 according to one or more masks (e.g., mask 1245). In various embodiments, fabrication tooling 1252 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0125] IC wafer fab 1250 uses one or more masks 1245 manufactured by mask chamber 1230 to manufacture IC device 1260. Therefore, IC wafer fab 1250 uses IC design layout 1222 at least indirectly to manufacture IC device 1260. In some embodiments, semiconductor wafer 1253 is manufactured by IC wafer fab 1250 using mask 1245 to form IC device 1260. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1253 further includes one or more of various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent manufacturing steps).

[0126] This disclosure relates to an integrated circuit element having a complementary field-effect transistor (FET). The integrated circuit element includes: a first pair of stacked active region structures extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of first gate track, second gate track, third gate track, and fourth gate track; a first switching gate conductor aligned with the first gate track and serving as the gate of a first switching transistor intersecting with the first pair of stacked active region structures; a first complementary FET gate conductor aligned with the second gate track and serving as the connecting gate of the first complementary FET device intersecting with the first pair of stacked active region structures; a second complementary FET gate conductor aligned with the third gate track and serving as the connecting gate of the second complementary FET device intersecting with the first pair of stacked active region structures; and a second switching gate conductor aligned with the fourth gate track and serving as the gate of the second switching transistor intersecting with the first pair of stacked active region structures. The component also includes a first complementary field-effect transistor (FET) terminal conductor, which serves as the junction drain of the first complementary field-effect transistor element and intersects with a first pair of stacked active region structures between a first gate rail and a second gate rail. The first complementary field-effect transistor terminal conductor is conductively connected to a second complementary field-effect transistor gate conductor. The component also includes a second complementary field-effect transistor (FET) terminal conductor, which serves as the junction drain of the second complementary field-effect transistor element and intersects with a first pair of stacked active region structures between a third gate rail and a fourth gate rail. The second complementary field-effect transistor terminal conductor is conductively connected to the first complementary field-effect transistor gate conductor.

[0127] In some embodiments, the integrated circuit element further includes a first node connection structure and a second node connection structure. The first node connection structure extends in a first direction and connects the terminal conductor of a first complementary field-effect transistor (FET) to the gate conductor of a second FET, while not conducting electricity through the gate conductor of the first FET. The second node connection structure extends in the first direction and connects the terminal conductor of the second FET to the gate conductor of the first FET, while not conducting electricity through the gate conductor of the second FET.

[0128] In some embodiments, the integrated circuit element further includes a first switch selection conductor and a first word line. The first switch selection conductor extends in a first direction and electrically connects a first switch gate conductor to a second switch gate conductor. The first word line extends in a second direction and is electrically connected to the first switch selection conductor.

[0129] In some embodiments, the integrated circuit element further includes a first bit input-output conductor and a second bit input-output conductor. The first bit input-output conductor intersects with a first pair of stacked active regions at one end region of the first switching transistor, wherein a first switching gate conductor is located between the first bit input-output conductor and the first complementary field-effect transistor end conductor. The second bit input-output conductor intersects with the first pair of stacked active regions at one end region of the second switching transistor, wherein a second switching gate conductor is located between the second bit input-output conductor and the second complementary field-effect transistor end conductor.

[0130] In some embodiments, the first pair of stacked active region structures includes an upper active region structure and a lower active region structure stacked on top of each other along a normal direction of a substrate, wherein the lower active region structure is located between the upper active region structure and the substrate.

[0131] In some embodiments, the first switch gate conductor intersects with the upper active region structure or the lower active region structure at a channel region of the first switch transistor; and the second switch gate conductor intersects with the upper active region structure or the lower active region structure at a channel region of the second switch transistor.

[0132] In some embodiments, the integrated circuit element further includes a first power terminal conductor, a second power terminal conductor, and a first power line conductor. The first power terminal conductor intersects the lower active region structure between the second gate rail and the third gate rail. The second power terminal conductor intersects the upper active region structure between the second gate rail and the third gate rail. The first power line conductor extends in a first direction and is conductively connected to the first power terminal conductor or the second power terminal conductor.

[0133] In some embodiments, the integrated circuit element further includes a first bit input-output conductor, a first bit line conductor, a second bit input-output conductor, and a second bit line conductor. The first bit input-output conductor intersects with a first pair of stacked active regions at one end region of the first switching transistor, and is coupled to a first complementary field-effect transistor end conductor through a channel of the first switching transistor. The first bit line conductor extends in a first direction and is conductively connected to the first bit input-output conductor. The second bit input-output conductor intersects with the first pair of stacked active regions at one end region of the second switching transistor, and is coupled to a second complementary field-effect transistor end conductor through a channel of the second switching transistor. The second bit line conductor extends in a first direction and is conductively connected to the second bit input-output conductor, wherein the first electric field conductor extends parallel in the first direction between the first bit line conductor and the second bit line conductor in the same conductive layer.

[0134] In some embodiments, the integrated circuit element further includes a second power line conductor and a third power line conductor. The second power line conductor extends in a first direction and is conductively connected to the first power terminal conductor or the second power terminal conductor. The third power line conductor extends in a first direction and is conductively connected to the first power terminal conductor or the second power terminal conductor, wherein the first and second power line conductors extend parallel in the first direction between the second and third power line conductors in the same conductive layer.

[0135] In some embodiments, the gate conductor of the first complementary field-effect transistor includes a first upper gate conductor and a first lower gate conductor. The first upper gate conductor and the first lower gate conductor are electrically connected and stacked together along the normal direction of the substrate. The first upper gate conductor intersects with the upper active region structure, and the first lower gate conductor intersects with the lower active region structure. The gate conductor of the second complementary field-effect transistor includes a second upper gate conductor and a second lower gate conductor. The second upper gate conductor and the second lower gate conductor are electrically connected and stacked together along the normal direction of the substrate. The second upper gate conductor intersects with the upper active region structure, and the second lower gate conductor intersects with the lower active region structure. The terminal conductor of the first complementary field-effect transistor includes both a first upper terminal conductor and a first lower terminal conductor. The first upper terminal conductor and the first lower terminal conductor are electrically connected and stacked together along the normal direction of the substrate. The first upper terminal conductor intersects with the upper active region structure, and the first lower terminal conductor intersects with the lower active region structure. The second complementary field-effect transistor terminal conductor includes a second upper conductor and a second lower conductor. The second upper conductor and the second lower conductor are electrically connected and stacked to each other along the normal direction of the substrate. The second upper conductor intersects with the upper active region structure, and the second lower conductor intersects with the lower active region structure.

[0136] In some embodiments, the integrated circuit element further includes a first node connection structure and a second node connection structure. The first node connection structure is located in an upper conductive layer above the upper active region structure, and connects a first upper conductor to a second upper gate conductor through multiple via connection structures. The second node connection structure is located in a lower conductive layer below the lower active region structure, and connects a second lower conductor to a first lower gate conductor through multiple via connection structures.

[0137] In some embodiments, the integrated circuit element further includes a first node connection structure and a second node connection structure. The first node connection structure is located in a lower conductive layer below the lower active region structure, and the first node connection structure connects a first lower conductor to a second lower gate conductor through multiple via connection structures. The second node connection structure is located in a lower conductive layer below the lower active region structure, and the second node connection structure connects a second lower conductor to the first lower gate conductor through multiple via connection structures.

[0138] In some embodiments, the integrated circuit element further includes a first node connection structure and a second node connection structure. The first node connection structure is located in an upper conductive layer above the upper active region structure, and connects a first upper conductor to a second upper gate conductor through multiple via connection structures. The second node connection structure is located in an upper conductive layer above the upper active region structure, and connects a second upper conductor to the first upper gate conductor through multiple via connection structures.

[0139] Another aspect disclosed relates to an integrated circuit element having complementary field-effect transistor (FET) elements. The integrated circuit element includes: a first pair of stacked active region structures and a second pair of stacked active region structures, extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of first gate track, second gate track, third gate track, and fourth gate track; a first switching gate conductor, a first complementary FET gate conductor, a second complementary FET gate conductor, and a second switching gate conductor, all intersecting with the first pair of stacked active region structures; and a third switching gate conductor, a third complementary FET gate conductor, and a third complementary FET gate conductor. The first complementary field-effect transistor (FET) gate conductor, the fourth complementary FET gate conductor, and the fourth switching gate conductor all intersect with the second pair of stacked active region structures. Specifically, the first and third switching gate conductors are aligned with the first gate track, the first and third complementary FET gate conductors are aligned with the second gate track, the second and fourth complementary FET gate conductors are aligned with the third gate track, and the second and fourth switching gate conductors are aligned with the fourth gate track. The element also includes a first complementary FET terminal conductor, which serves as the junction drain of the first complementary FET element and intersects with the first pair of stacked active region structures between the first and second gate tracks. The first complementary FET terminal conductor is conductively connected to the second complementary FET gate conductor. The element also includes a second complementary field-effect transistor terminal conductor, which serves as the junction drain terminal of the second complementary field-effect transistor element and intersects with the first pair of stacked active region structures between the third gate track and the fourth gate track, wherein the second complementary field-effect transistor terminal conductor is electrically connected to the first complementary field-effect transistor gate conductor.

[0140] In some embodiments, the integrated circuit element further includes a third complementary field-effect transistor (FET) terminal conductor and a fourth complementary field-effect transistor (FET) terminal conductor. The third complementary field-effect transistor terminal conductor intersects with the second pair of stacked active region structures between the first gate rail and the second gate rail as a junction drain terminal of a third complementary field-effect transistor element, wherein the third complementary field-effect transistor terminal conductor is conductively connected to the fourth complementary field-effect transistor gate conductor. The fourth complementary field-effect transistor terminal conductor intersects with the second pair of stacked active region structures between the third gate rail and the fourth gate rail as a junction drain terminal of a fourth complementary field-effect transistor element, wherein the fourth complementary field-effect transistor terminal conductor is conductively connected to the third complementary field-effect transistor gate conductor.

[0141] In some embodiments, the integrated circuit element further includes a first switch selection conductor and a first word line, extending in a second direction and conductively connected to the first switch selection conductor, a second switch selection conductor, and a second word line. The first switch selection conductor extends in the first direction and is conductively connected between a first switch gate conductor and a second switch gate conductor. The first word line extends in the second direction and is conductively connected to the first switch selection conductor. The second switch selection conductor extends in the first direction and is conductively connected between each of a third switch gate conductor and a fourth switch gate conductor. The second word line extends in the second direction and is conductively connected to the second switch selection conductor.

[0142] In some embodiments, the integrated circuit element further includes a first bit input-output conductor, a second bit input-output conductor, and a first power conductor. The first bit input-output conductor and the second bit input-output conductor extend in a second direction, arranged such that a plurality of four gate rails are located between the first bit input-output conductor and the second bit input-output conductor, wherein each of the first bit input-output conductor and the second bit input-output conductor intersects with both the first pair of stacked active region structures and the second pair of stacked active region structures. The first power conductor extends in a second direction between the second gate rails and the third gate rails, wherein the first power conductor intersects with one or both of the first pair of stacked active region structures or the second pair of stacked active region structures.

[0143] In some embodiments, the integrated circuit element further includes a first bit line conductor, a second bit line conductor, and a first power line conductor. The first bit line conductor extends in a first direction and is conductively connected to a first bit input-output terminal conductor. The second bit line conductor extends in the first direction and is conductively connected to a second bit input-output terminal conductor. The first power line conductor extends parallel to the first bit line conductor and the second bit line conductor in the first direction, wherein the first power line conductor is conductively connected to a first power terminal conductor.

[0144] Another aspect disclosed herein relates to a method. The method includes fabricating a lower active region structure extending in a first direction on a substrate. The method also includes forming four lower gate conductors intersecting the lower active region structure, wherein the four lower gate conductors include a second lower gate conductor and a third gate conductor located between a first lower gate conductor and a fourth lower gate conductor. The method also includes forming three lower end conductors intersecting the lower active region structure, wherein the three lower end conductors include a first lower end conductor located between the first and second lower gate conductors, a second lower end conductor located between the second and third lower gate conductors, and a third lower end conductor located between the third and fourth lower gate conductors, wherein the second lower end conductor is located between the first and third lower end conductors. The method also includes fabricating an upper active region structure extending in the first direction and stacked with the lower active region structure. The method also includes forming four upper gate conductors intersecting the upper active region structure, wherein the four upper gate conductors include a second upper gate conductor and a third upper gate conductor located between a first upper gate conductor and a fourth upper gate conductor, and wherein the second upper gate conductor is stacked with a second lower gate conductor and electrically connected to the second lower gate conductor, and the third upper gate conductor is stacked with a third lower gate conductor and electrically connected to the third lower gate conductor. The method also includes forming three upper end conductors intersecting the upper active region structure, wherein the three upper end conductors include a first upper end conductor stacked with a first lower end conductor and electrically connected to the first lower end conductor, a second upper end conductor stacked with a second lower end conductor, and a third upper end conductor stacked with a third lower end conductor and electrically connected to the third lower end conductor. The method also includes forming a first node connection structure extending in a first direction, the first node connection structure electrically connecting one of the first upper end conductor and the first lower end conductor to one of the third upper gate conductor and the third lower gate conductor. The method also includes forming a second node connection structure extending in the first direction, the second node connection structure electrically connecting one of the third upper conductor and the third lower conductor to one of the second upper gate conductor and the second lower gate conductor.

[0145] In some embodiments, the method further includes forming a first switch selection conductor extending in a first direction, the first switch selection conductor being electrically connected between a first lower gate conductor and a fourth lower gate conductor or electrically connected between a first upper gate conductor and a fourth upper gate conductor.

[0146] Those skilled in the art will readily see that one or more of the disclosed embodiments satisfy one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to influence various variations, equivalent substitutions, and other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only to the definitions contained in the appended claims and their equivalents.

[0147] 30:Substrate 80A: First pair of stacked active region structures 80B: Second pair of stacked active region structures 82A, 82B: Upper active region structure 82A1, 82A2, 82A3, 84A1, 84A2, 84A3: Nanosheets 84A, 84B: Lower active region structure 100, 500, 700: Circuit Units 101, 102, 108, 109, 701, 702, 708, 709: Element boundaries 105: Dividing Boundary 122A, 122B, 124A, 124B, BCT1, BCT2: Node connection structure 132DA, 132DB, 132UA, 132UB, 134A, 134B, 135D, 135DA, 135DB, 135U, 135UA, 135UB, 136A, 136B, 138DA, 138DB, 138UA, 138UB: Terminal Conductors 152DA, 152DB, 152UA, 152UB, 154A, 154B, 156A, 156B, 158DA, 158DB, 158UA, 158UB: Gate conductors 162, 162A, 162B, 168, 168A, 168B: Bit line conductors 165A, 165B, WL: Switch selection conductor 182, 182A, 182B, 182C, 182L, 182R, 184, 184A, 184B: Electric power line conductors 362A, 368B: Bit lines 372, 378: Bit line interconnect extension 375A, 375B: Character lines 375A, 375B, 375Ab, 375Bb: Character lines 901, 902, 903, 904: Edge lines 910, 920, 930: Layout areas 1000: Method 1010, 1012, 1014, 1020, 1022, 1024, 1030, 1040, 1050: Operations 1100: EDA System 1102: Hardware Processor 1104: Non-transitory computer-readable storage media 1106: Computer program code 1107: Standard Unit Library 1108: Busbar 1109: Layout Diagram 1110:I / O interface 1112: Network Interface 1114: Internet 1142:UI 1200: Integrated Circuit Fabrication System 1220: Design Studio 1222: IC Design Layout Diagram 1230: Covered Room 1232: Data Preparation 1244: Curtain Manufacturing 1245: Curtain 1250: IC wafer fab 1252: Wafer Manufacturing Tools 1253: Semiconductor wafer 1260: IC Components A-A', B-B', C-C': Cutting planes / lines BL: First IO terminal conductor BLB: Second bit I / O terminal conductor BM0: First backside metal layer BM1: Second backside metal layer BV0, BVD, BVG, V0, V1, VD, VG: Through-hole connection structure CFET1: First CFET element CFET2: Second CFET element i101DA, i101DB, i101UA, i101UB, i109DA, i109DB, i109UA, i109UB: Border Segregation Zone ILD0, ILD1, ILD2: Interlayer dielectric M0: First metal layer M1: Second metal layer M2: Third metal layer MDLI: Terminal - Internal Connection Line Node1: First connection node Node2: Second connection node PG1, PG2: Switching transistors SRAM1, SRAM1b, SRAM2, SRAM2b: SRAM bit cell circuit TD1, TD2: Type II transistors TU1, TU2: Type I transistors VDD, VSS: Power supply voltage Vth1: First critical limit value Vth2: Second critical limit value

[0148]

[0149] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit element comprising: a first pair of stacked active region structures extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of a first gate track, a second gate track, a third gate track, and a fourth gate track; a first switching gate conductor aligned with the first gate track and intersecting the first pair of stacked active region structures as a gate of a first switching transistor; a first complementary field-effect transistor gate conductor aligned with the second gate track and intersecting the first pair of stacked active region structures as a connecting gate of a first complementary field-effect transistor device; a second complementary field-effect transistor gate conductor aligned with the third gate track and intersecting the first pair of stacked active region structures as a connecting gate of a second complementary field-effect transistor device; and a second switching gate conductor aligned with the fourth gate track and intersecting the first pair of stacked active region structures as a gate of a second switching transistor. A first complementary field-effect transistor (FET) terminal conductor, serving as a junction drain end of the first complementary field-effect transistor element, intersects with the first pair of stacked active region structures between the first gate track and the second gate track, wherein the first complementary field-effect transistor terminal conductor is electrically connected to the second complementary field-effect transistor gate conductor; and a second complementary field-effect transistor terminal conductor, serving as a junction drain end of the second complementary field-effect transistor element, intersects with the first pair of stacked active region structures between the third gate track and the fourth gate track, wherein the second complementary field-effect transistor terminal conductor is electrically connected to the first complementary field-effect transistor gate conductor.

2. The integrated circuit element as claimed in claim 1, further comprising: a first node connection structure extending in the first direction, the first node connection structure connecting the terminal conductor of the first complementary field-effect transistor to the gate conductor of the second complementary field-effect transistor, while not conducting electricity through the gate conductor of the first complementary field-effect transistor; and a second node connection structure extending in the first direction, the second node connection structure connecting the terminal conductor of the second complementary field-effect transistor to the gate conductor of the first complementary field-effect transistor, while not conducting electricity through the gate conductor of the second complementary field-effect transistor.

3. The integrated circuit element as claimed in claim 1 further comprises: a first switch selection conductor extending in the first direction, the first switch selection conductor electrically connecting the first switch gate conductor to the second switch gate conductor; and a first word line extending in the second direction and electrically connected to the first switch selection conductor.

4. The integrated circuit element as claimed in claim 1, further comprising: a first bit input-output conductor intersecting the first pair of stacked active regions at one end region of the first switching transistor, wherein the first switching gate conductor is located between the first bit input-output conductor and the first complementary field-effect transistor end conductor; and a second bit input-output conductor intersecting the first pair of stacked active regions at one end region of the second switching transistor, wherein the second switching gate conductor is located between the second bit input-output conductor and the second complementary field-effect transistor end conductor.

5. The integrated circuit element as described in claim 1, wherein: The first pair of stacked active region structures includes an upper active region structure and a lower active region structure stacked together along a normal direction of a substrate, and the lower active region structure is located between the upper active region structure and the substrate.

6. The integrated circuit element as claimed in claim 5 further comprises: a first power terminal conductor intersecting the upper active region structure between the second gate track and the third gate track; a second power terminal conductor intersecting the lower active region structure between the second gate track and the third gate track; and a first power line conductor extending in the first direction and conductively connected to the first power terminal conductor or the second power terminal conductor.

7. An integrated circuit element comprising: a first pair of stacked active region structures and a second pair of stacked active region structures extending in a first direction and passing through four gate tracks extending in a second direction, wherein the four gate tracks are uniformly distributed along the first direction in the order of a first gate track, a second gate track, a third gate track, and a fourth gate track; a first switching gate conductor, a first complementary field-effect transistor gate conductor, a second complementary field-effect transistor gate conductor, and a second switching gate conductor all intersecting with the first pair of stacked active region structures; A third switch gate conductor, a third complementary field-effect transistor gate conductor, a fourth complementary field-effect transistor gate conductor, and a fourth switch gate conductor all intersect with the second pair of stacked active region structures, wherein the first switch gate conductor and the third switch gate conductor are aligned with the first gate track, the first complementary field-effect transistor gate conductor and the third complementary field-effect transistor gate conductor are aligned with the second gate track, the second complementary field-effect transistor gate conductor and the fourth complementary field-effect transistor gate conductor are aligned with the third gate track, and the second switch gate conductor and the fourth switch gate conductor are aligned with the fourth gate track; A first complementary field-effect transistor (FET) terminal conductor, serving as a junction drain terminal of a first complementary field-effect transistor element, intersects the first pair of stacked active region structures between the first gate track and the second gate track, wherein the first complementary field-effect transistor terminal conductor is electrically connected to the second complementary field-effect transistor gate conductor; and a second complementary field-effect transistor terminal conductor, serving as a junction drain terminal of a second complementary field-effect transistor element, intersects the first pair of stacked active region structures between the third gate track and the fourth gate track, wherein the second complementary field-effect transistor terminal conductor is electrically connected to the first complementary field-effect transistor gate conductor.

8. The integrated circuit element as claimed in claim 7, further comprising: a third complementary field-effect transistor terminal conductor intersecting the second pair of stacked active region structures between the first gate rail and the second gate rail as a junction drain terminal of the third complementary field-effect transistor element; wherein the third complementary field-effect transistor terminal conductor is conductively connected to the fourth complementary field-effect transistor gate conductor; and a fourth complementary field-effect transistor terminal conductor intersecting the second pair of stacked active region structures between the third gate rail and the fourth gate rail as a junction drain terminal of the fourth complementary field-effect transistor element.

9. A method for forming an integrated circuit element, comprising the steps of: fabricating a lower active region structure extending in a first direction on a substrate; forming four lower gate conductors intersecting the lower active region structure, wherein the four lower gate conductors include a second lower gate conductor and a third lower gate conductor located between a first lower gate conductor and a fourth lower gate conductor; forming three lower end conductors intersecting the lower active region structure, wherein the three lower end conductors include a first lower end conductor located between the first lower gate conductor and the second lower gate conductor, a second lower end conductor located between the second lower gate conductor and the third lower gate conductor, and a third lower end conductor located between the third lower gate conductor and the fourth lower gate conductor, and wherein the second lower end conductor is located between the first lower end conductor and the third lower end conductor; and fabricating an upper active region structure extending in the first direction and stacked with the lower active region structure. Four upper gate conductors are formed intersecting the upper active region structure, wherein the four upper gate conductors include a second upper gate conductor and a third upper gate conductor located between a first upper gate conductor and a fourth upper gate conductor, wherein the second upper gate conductor is stacked with the second lower gate conductor and electrically connected to the second lower gate conductor, and the third upper gate conductor is stacked with the third lower gate conductor and electrically connected to the third lower gate conductor; Three upper end conductors are formed intersecting the upper active region structure, wherein the three upper end conductors include a first upper end conductor stacked with the first lower end conductor and electrically connected to the first lower end conductor, a second upper end conductor stacked with the second lower end conductor, and a third upper end conductor stacked with the third lower end conductor and electrically connected to the third lower end conductor; A first node connection structure extending in the first direction is formed, wherein the first node connection structure electrically connects one of the first upper conductor and the first lower conductor to one of the third upper gate conductor and the third lower gate conductor; and a second node connection structure extending in the first direction is formed, wherein the second node connection structure electrically connects one of the third upper conductor and the third lower conductor to one of the second upper gate conductor and the second lower gate conductor.

10. The method of claim 9 further comprises the step of: forming a first switch selection conductor extending in the first direction, the first switch selection conductor being electrically connected between the first lower gate conductor and the fourth lower gate conductor or being electrically connected between the first upper gate conductor and the fourth upper gate conductor.

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