Multiple wafers fabrication technique on large carrier with warpage control stiffener

Abstract

A method for manufacturing a semiconductor device is disclosed, comprising attaching a plurality of semiconductor substrates and a frame component to a support surface of a carrier substrate. The semiconductor substrates may be wafers dicable or slit into a plurality of dies. Thus, each wafer has a separate functional surface and at least one separate integrated circuit region. The method may further comprise encapsulating the frame component and the plurality of semiconductor substrates within an encapsulating agent. Subsequently, the carrier substrate is removed, and a redistribution layer (RDL) is formed on the semiconductor substrates and the frame component.

Description

Technical Field

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 631,305, entitled “Large Panel Wafer Level Packaging Process,” filed February 15, 2018, and U.S. Provisional Application No. 62 / 632,138, entitled “Large Panel Wafer Level Packaging with Stiffener,” filed February 19, 2018, both of which are incorporated herein by reference in their entirety.

[0003] This invention relates to semiconductor packaging technology. Prior Technology

[0004] Semiconductor devices are commonly found in modern electronic products. The number and density of electronic components in semiconductor devices vary. Discrete semiconductor devices typically contain one type of electronic component, such as light-emitting diodes (LEDs), small-signal transistors, resistors, capacitors, inductors, and power metal-oxide-semiconductor field-effect transistors (MOSFETs). Integrated semiconductor devices typically contain hundreds to millions of electronic components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

[0005] Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and creating visual projections for television displays. Semiconductor devices are found in entertainment, communications, power conversion, networking, computers, and consumer products. They are also used in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0006] Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of semiconductor materials allows their conductivity to be manipulated by applying an electric field or base current, or through a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

[0007] Semiconductor devices contain active and passive electrical structures. Active structures, including bipolar and field-effect transistors, control the flow of current. By varying the doping level and applying an electric field or base current, the transistor promotes or confines the current flow. Passive structures, including resistors, capacitors, and inductors, establish a relationship between the voltage and current required to perform various electrical functions. The passive and active structures are electrically connected to form circuits, enabling semiconductor devices to perform high-speed calculations and other useful functions.

[0008] Semiconductor devices are typically manufactured using two complex processes: front-end manufacturing and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuitry formed by electrically connecting active and passive components. Back-end manufacturing involves isolating semiconductor dies from the finished wafer and packaging the dies to provide structural support and environmental isolation.

[0009] In this specification, the terms "die," "semiconductor wafer," and "semiconductor die" are used interchangeably. The term wafer, as used herein, includes any structure having an exposed surface on which layers are deposited according to the invention, for example, to form a circuit structure.

[0010] Figures 1A to 1E show schematic cross-sectional views of a typical method for manufacturing wafer-level packages with redistribution layers (RDL).

[0011] As shown in Figure 1, wafer 100 is fabricated. Wafer 100 may contain a plurality of semiconductor device structures (not shown) formed according to a known process. An RDL layer is then formed on wafer 100 according to a known process. In Figures 1A to 1E, the RDL is denoted by the group of layers 102, 104, and 106. RDLs are typically defined by adding metal and dielectric layers to the wafer surface to redistribute the I / O layout into more loosely spaced occupancy areas. This redistribution typically involves thin-film polymers such as BCB, PI, or other organic polymers, and metallization such as Al or Cu, to redistribute peripheral pads to a region array configuration. Layers 102 and 106 represent dielectric layers, and layer 104 represents a metal feature. Layers 102, 104, and 106 together represent dielectric and metal layers formed to allow electrical connectivity from wafer 100 to the solder bumps or solder balls 108 shown in Figure 1E. Solder balls 108 are formed on the RDL for further interconnection. Also as shown in Figure 1E, a dicing or sawing process can be performed along the notch area of ​​the wafer to separate individual wafer-level dies from each other.

[0012] In wafer-level packaging, wafers and dies are prone to warping due to thermal expansion coefficient (CTE) mismatch. Wafer warping remains a well-known problem. Because the coupling between the die and wafer cannot be maintained, warping can hinder successful die-to-wafer stacking. Warping is particularly severe in large-size wafers and has posed a barrier to wafer-level semiconductor packaging processes requiring fine-pitch RDL (Reverse Density Linearization) processes.

[0013] This invention provides a novel and improved packaging method that results in reduced warpage or other defects. Summary of the Invention

[0014] The method of manufacturing a semiconductor device according to the present invention may include providing a plurality of semiconductor substrates, such as wafers, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region.

[0015] The method may also include attaching the plurality of semiconductor substrates to a support surface of a carrier substrate, and attaching a frame component to the support surface of the carrier substrate. The method may also include encapsulating the frame component and the plurality of semiconductor substrates within an encapsulating agent to obtain a polywafer encapsulation layer. Subsequently, the method may include removing the carrier substrate from the polywafer encapsulation layer and forming a redistribution layer (RDL) on the semiconductor substrates of the polywafer encapsulation layer to obtain a polywafer panel.

[0016] In some embodiments, the carrier substrate and / or the frame component may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of one of the plurality of semiconductor substrates.

[0017] In some embodiments, at least a portion of the frame member may extend along the support surface of the carrier substrate between at least two of the plurality of semiconductor substrates.

[0018] In some embodiments, the method may further include cutting a multilayer panel to obtain a separate semiconductor device.

[0019] In some embodiments, each of the plurality of semiconductor substrates may be a silicon wafer or any other type of semiconductor wafer.

[0020] In one embodiment, a method of manufacturing a semiconductor device includes: a plurality of semiconductor substrates, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region; attaching the plurality of semiconductor substrates to a support surface of a carrier substrate; attaching a frame component to the support surface of the carrier substrate; encapsulating the frame component and the plurality of semiconductor substrates in an encapsulating agent to obtain a polywafer encapsulation layer; removing the carrier substrate from the polywafer encapsulation layer; and forming a redistribution layer (RDL) on the semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel.

[0021] In one embodiment, the polycrystalline panel may be further subjected to a dicing step, thereby unifying the multilayer panel into a single semiconductor device. In some embodiments, the carrier substrate may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of one of the plurality of semiconductor substrates. In other embodiments, the frame component may also have a CTE that substantially matches the coefficient of thermal expansion (CTE) of one of the plurality of semiconductor substrates and / or the carrier substrate.

[0022] In one embodiment, at least a portion of the frame member may extend along the support surface of the carrier substrate between at least two of the plurality of semiconductor substrates. In some embodiments, each of the plurality of semiconductor substrates may contain silicon, and the frame member may have a CTE substantially matching the coefficient of thermal expansion (CTE) of silicon.

[0023] In another embodiment, the method of manufacturing a semiconductor device includes: providing a first semiconductor substrate and a second semiconductor substrate, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region; attaching the first semiconductor substrate and the second semiconductor substrate to a support surface of a carrier substrate; attaching a frame member to the support surface of the carrier substrate, wherein at least a portion of the frame member extends between the first semiconductor substrate and the second semiconductor substrate; encapsulating the frame member, the first semiconductor substrate, and the second semiconductor substrate in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame member and at least one of the first semiconductor substrate and the second semiconductor substrate; removing the carrier substrate from the polywafer encapsulation layer; and forming a redistribution layer (RDL) on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel.

[0024] In some embodiments, in the methods described above, the carrier substrate may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the first semiconductor substrate and the second semiconductor substrate. In other embodiments, the frame component has a coefficient of thermal expansion (CTE) that substantially matches the CTE of the first semiconductor substrate and the second semiconductor substrate and / or the CTE of the carrier substrate.

[0025] In one embodiment, at least a portion of the frame component extends along the support surface of the carrier between the first semiconductor substrate and the second semiconductor substrate. In some embodiments, each of the first semiconductor substrate and the second semiconductor substrate comprises silicon, and the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

[0026] In one embodiment, a method of manufacturing a semiconductor device includes: providing a frame component defining a first through-hole and a second through-hole thereunder; attaching the frame component to a support surface of a carrier substrate; attaching a first semiconductor substrate and a second semiconductor substrate to the support surface of the carrier substrate via the through-holes of the first frame component and the second frame component, respectively; encapsulating the frame component, the first semiconductor substrate, and the second semiconductor substrate in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame component and at least one of the first semiconductor substrate and the second semiconductor substrate; removing the carrier substrate from the polywafer encapsulation layer; and forming a redistribution layer (RDL) on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel.

[0027] In one embodiment, a method of manufacturing a semiconductor device begins with the following steps: providing a plurality of semiconductor substrates, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region, followed by the next step: attaching the plurality of semiconductor substrates to a support surface of a carrier substrate. The next step includes encapsulating the plurality of semiconductor substrates within an encapsulating agent, thereby obtaining a polywafer encapsulation layer. In this embodiment, there are no frame components. The process continues with the following steps: removing the carrier substrate from the polywafer encapsulation layer, followed by the next step: forming a redistribution layer (RDL) on the semiconductor substrates of the polywafer encapsulation layer, thereby obtaining a polywafer panel. In one embodiment, the polywafer panel may be further subjected to a dicing step, thereby unifying the multilayer panel to obtain a single semiconductor device. Simple Explanation of the Diagram

[0028] [Figures 1A to 1E] show schematic cross-sectional views of conventional methods for manufacturing wafer-level packages. [Figures 2A to 2E] show schematic cross-sectional views of an exemplary method for manufacturing wafer-level packages according to an embodiment of the present invention. [Figure 3] shows a plan view of an embodiment of the frame component according to an embodiment of the present invention. [Figure 4] is a process flow diagram illustrating an exemplary method for manufacturing wafer-level packages according to the present invention. Implementation

[0029] This invention relates to a wafer-level packaging process. For example, in a semiconductor wafer packaging process, a wafer can be a semiconductor wafer or device wafer having thousands of chips on it. Thin wafers, especially ultra-thin wafers (thickness less than 60 micrometers or even 30 micrometers), are very unstable and more susceptible to stress than conventional thick wafers. Thin wafers may easily crack and warp during processing. Therefore, temporary bonding to a rigid support carrier substrate can reduce the risk of wafer damage. The carrier substrate can be a square or rectangular panel made of glass, sapphire, metal, or other rigid materials to increase the chip volume. In one wafer packaging method, the wafer is temporarily placed on a carrier substrate coated with a temporary adhesive and encapsulated in an encapsulating agent material such as an epoxy molding compound. The encapsulated wafer is then processed with the desired semiconductor packaging operations, including RDL formation and dicing into individual chips.

[0030] In the following detailed description of the invention, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments in which the invention can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments and structural changes may be utilized without departing from the scope of the invention.

[0031] Therefore, the following detailed description should not be considered limiting, and the scope of the invention is defined only by the appended claims and the full scope of their equivalents.

[0032] One or more embodiments of the invention will now be described with reference to the accompanying drawings, wherein the same reference numerals are always used to denote the same elements, and the structures illustrated therein are not necessarily drawn to scale.

[0033] The schematic cross-sectional views shown in Figures 2A to 2E illustrate exemplary methods for manufacturing wafer-level packages according to the present invention.

[0034] As shown in Figure 2A, a carrier substrate 202 is fabricated. The carrier substrate 202 may comprise a releaseable substrate material. An adhesive layer 206 is disposed on the top surface of the carrier substrate 202. In one embodiment, the carrier substrate 202 may be a glass substrate, but alternatively, it may be any other material having a CTE matching that of the wafer 200 being processed. For example, the carrier substrate 202 may also be ceramic, sapphire, or quartz. The adhesive layer 206 may be an adhesive tape, or it may be an adhesive or epoxy resin applied to the carrier substrate 202 via a spin coating process or the like.

[0035] Subsequently, wafer 200 and frame component 204 can be mounted on the support surface of carrier substrate 202 via adhesive layer 206. A plan view of an exemplary frame component 204 is also shown in Figure 3. In some embodiments, no frame component 204 is required. In other words, wafer 200 is mounted on the support surface of carrier substrate 202 via adhesive layer 206 without any adjacent frame component 204. The carrier substrate can be formed of glass or other suitable material whose CTE at least substantially matches the CTE of wafer 200. For example, carrier substrate 202 can also be ceramic, sapphire, or quartz. Wafer 200 may contain semiconductor circuitry formed thereon, which is suitable for dicing or dicing into a plurality of dies. Frame component 204 may include a plurality of through-holes, the size and shape of which are designed to allow individual wafers 200 to be positioned therein, as shown in Figures 2A to 2E and Figure 3. Frame component 204 can also be referred to as a reinforcing material. In some embodiments, the frame component 204 may be formed of glass, ceramic, sapphire, quartz, or other suitable material whose CTE at least substantially matches the CTE of the wafer 200 and / or the carrier substrate 202.

[0036] The assembly order can be varied; in other words, the frame component 204 can be placed before, during, or after the placement of the wafer 200. Furthermore, although four wafers 200 and vias are shown, alternative embodiments may include any number of wafers 200 and vias. Moreover, although the frame component 204 is illustrated as square and the wafer 200 as circular, alternative embodiments of the frame component 204 may have any desired shape. For example, the frame component 204 may be circular or rectangular, and similarly, the wafer 200 may be square or rectangular. The wafer 200 and frame component 204 can be mounted on the carrier substrate 202 using any known surface mount technology, including, but not limited to, adhesives, glues, and / or temporary tapes.

[0037] As shown in Figure 2B, after the wafer 200 and the frame component 204 are mounted on the carrier substrate 202, an encapsulating agent, such as molding compound 208, is applied. Molding compound 208 covers the attached wafer 200 and frame component 204. In embodiments without frame component 204, molding compound 208 simply covers the attached wafer 200. Molding compound 208 may also fill any gaps that may exist between the wafer 200 and the frame component 204. A curing process can then be performed on the molding compound 208. In some embodiments where frame component 204 is absent, molding compound 208 simply fills the gaps between the wafers 200.

[0038] According to the illustrated embodiments, molding compound 208 can be formed using a thermosetting molding compound in, for example, a transfer molding machine. Other methods of applying the molding compound can be used. Epoxy resins, resins, and compounds that are liquid at high temperatures or at ambient temperatures can be used. Molding compound 208 can be an electrical insulator and a thermal conductor. Different fillers can be added to enhance the thermal conductivity, stiffness, or adhesive properties of molding compound 208.

[0039] Next, turning to Figures 2C through 2E, note that the illustrated structure has been flipped so that the top side shown in Figures 2A through 2B is the bottom side shown in Figures 2C through 2E. As shown in Figure 2C, after forming the molding compound 208, the carrier substrate 202 and the adhesive layer 206 are removed or peeled off to expose the wafer 200 and the frame component 204.

[0040] As shown in Figure 2D, RDL 210 can then be manufactured using known RDL forming techniques. Furthermore, to provide electrical connections between RDL 210 and other circuits, a plurality of bumps 212, such as microbumps or copper pillars, are formed. Optionally, heat treatment can be performed to resolder the bumps 212.

[0041] As shown in Figure 2E, a cutting or sawing process can be performed along the cut area to separate individual wafers 200 and their respective wafer-level packages from each other. It should be understood that the cross-sectional structures depicted in the figures are for illustrative purposes only.

[0042] Figure 4 is a process flow chart 400, illustrating an exemplary method for manufacturing wafer-level packages according to the present invention. In this embodiment, the method of manufacturing a semiconductor device begins at step 410: providing a plurality of semiconductor substrates, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region. In one embodiment, the next step 420 involves attaching the plurality of semiconductor substrates to a support surface of a carrier substrate, followed by step 430: attaching a frame component to the support surface of the carrier substrate. In an alternative embodiment, steps 420 and 430 may be performed in reverse order, for example, step 430 followed by step 420. The next step 440 involves encapsulating the frame component and the plurality of semiconductor substrates in an encapsulating agent to obtain a polywafer encapsulation layer, followed by processing step 450: removing the carrier substrate from the polywafer encapsulation layer. The next step 460 of this process includes forming a redistribution layer (RDL) on the semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel. In one embodiment, the multi-wafer panel may be further diced in a cutting step 470, thereby simplifying the multi-layer panel to obtain a single semiconductor device.

[0043] In some embodiments, in the methods described above, the carrier substrate may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of one of the plurality of semiconductor substrates. Similarly, the frame component may also have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the plurality of semiconductor substrates and / or the carrier substrate.

[0044] In one embodiment, at least a portion of the frame member may extend along the support surface of the carrier substrate between at least two of the plurality of semiconductor substrates. In these embodiments, each of the plurality of semiconductor substrates may contain silicon, and the frame member may have a CTE substantially matching the coefficient of thermal expansion (CTE) of silicon.

[0045] In another embodiment, the method of manufacturing a semiconductor device includes: providing a first semiconductor substrate and a second semiconductor substrate, each semiconductor substrate having a separate functional surface and at least one separate integrated circuit region; attaching the first semiconductor substrate and the second semiconductor substrate to a support surface of a carrier substrate; attaching a frame member to the support surface of the carrier substrate, wherein at least a portion of the frame member extends between the first semiconductor substrate and the second semiconductor substrate; encapsulating the frame member, the first semiconductor substrate, and the second semiconductor substrate in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame member and at least one of the first semiconductor substrate and the second semiconductor substrate; removing the carrier substrate from the polywafer encapsulation layer; and forming a redistribution layer (RDL) on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel.

[0046] In some embodiments, in the methods described above, the carrier substrate may have a coefficient of thermal expansion (CTE) that substantially matches that of the first semiconductor substrate and the second semiconductor substrate. Similarly, the frame component has a coefficient of thermal expansion (CTE) that substantially matches the CTE of the first semiconductor substrate and the second semiconductor substrate and / or the CTE of the carrier substrate.

[0047] In one embodiment, at least a portion of the frame component extends along the support surface of the carrier between the first semiconductor substrate and the second semiconductor substrate. In another embodiment, the method described above may further include dicing a polycrystalline panel to obtain individual semiconductor devices. In some embodiments, each of the first and second semiconductor substrates comprises silicon, and the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

[0048] In one embodiment, a method of manufacturing a semiconductor device includes: providing a frame component defining a first through-hole and a second through-hole thereunder; attaching the frame component to a support surface of a carrier substrate; attaching a first semiconductor substrate and a second semiconductor substrate to the support surface of the carrier substrate via the through-holes of the first frame component and the second frame component, respectively; encapsulating the frame component, the first semiconductor substrate, and the second semiconductor substrate in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame component and at least one of the first semiconductor substrate and the second semiconductor substrate; removing the carrier substrate from the polywafer encapsulation layer; and forming a redistribution layer (RDL) on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel.

[0049] In some embodiments, in the methods described above, the carrier substrate may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the first semiconductor substrate and the second semiconductor substrate. In other embodiments, the frame component may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the first semiconductor substrate and the second semiconductor substrate and / or the CTE of the carrier substrate.

[0050] In one embodiment, each of the first semiconductor substrate and the second semiconductor substrate comprises silicon. In another embodiment, the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

[0051] In one embodiment, the method described above also includes dicing a polycrystalline panel to obtain a separate semiconductor device.

[0052] In one embodiment, the method of manufacturing a semiconductor device does not require step 430. In other words, the method begins at step 410: providing a plurality of semiconductor substrates, each having a separate functional surface and at least one separate integrated circuit region, followed by step 420: attaching the plurality of semiconductor substrates to a support surface of a carrier substrate. Step 440 includes encapsulating the plurality of semiconductor substrates within an encapsulating agent, thereby obtaining a polywafer encapsulation layer. In this embodiment, there is no frame component 204. The process continues at step 450: removing the carrier substrate from the polywafer encapsulation layer, followed by step 460: forming a redistribution layer (RDL) on the semiconductor substrate of the polywafer encapsulation layer, thereby obtaining a polywafer panel. In one embodiment, the polywafer panel may be further diced in step 470, thereby simplifying the multilayer panel to obtain a single semiconductor device.

[0053] Those skilled in the art will readily observe that various modifications and alterations can be made to the apparatus and method while retaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

[0054] 100... wafers 102nd floor 104th floor 106th floor 108... Solder Balls 200... wafers 202‧‧‧Carrier substrate 204‧‧‧Framed Components 206... Adhesive layer 208‧‧‧Molded Compound 210‧‧‧RDL 212‧‧‧Bumps 400 Processing Flowchart 410...Steps 420... Steps 430... Steps 440... Steps 450... steps 460... Steps 470... Steps

Claims

1. A method for manufacturing a semiconductor device, comprising: A plurality of semiconductor substrates are provided, each semiconductor substrate having a separate functional surface and a plurality of separate integrated circuit regions; A plurality of semiconductor substrates are adhered to a support surface of a carrier substrate; a frame component is adhered to the support surface of the carrier substrate; the frame component and the plurality of semiconductor substrates are encapsulated in an encapsulating agent to obtain a polywafer encapsulation layer; the carrier substrate is removed from the polywafer encapsulation layer; a redistribution layer (RDL) is formed on the semiconductor substrates of the polywafer encapsulation layer to obtain a polywafer panel; And cutting the polycrystalline panel so that each of the semiconductor substrates is cut into separate multiple grains.

2. The method as described in claim 1, wherein the coefficient of thermal expansion (CTE) of one of the carrier substrates substantially matches the CTE of one of the plurality of semiconductor substrates.

3. The method as described in claim 1, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of one of the plurality of semiconductor substrates.

4. The method as described in claim 1, wherein at least a portion of the frame component extends along the support surface of the carrier substrate between at least two of the plurality of semiconductor substrates.

5. The method as described in claim 1, wherein each of the plurality of semiconductor substrates comprises silicon.

6. The method as described in claim 5, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

7. A method for manufacturing a semiconductor device, comprising: A first semiconductor substrate and a second semiconductor substrate are provided, each substrate having a separate functional surface and a plurality of separate integrated circuit regions; The first semiconductor substrate and the second semiconductor substrate are adhered to a support surface of a carrier substrate; a frame component is adhered to the support surface of the carrier substrate, wherein at least a portion of the frame component extends between the first semiconductor substrate and the second semiconductor substrate; the frame component, the first semiconductor substrate, and the second semiconductor substrate are encapsulated in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame component and at least one of the first semiconductor substrate and the second semiconductor substrate; the carrier substrate is removed from the polywafer encapsulation layer; a redistribution layer (RDL) is formed on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel; And to cut the polycrystalline panel so that both the first semiconductor substrate and the second semiconductor substrate are cut into separate plurality of grains.

8. The method as described in claim 7, wherein the coefficient of thermal expansion (CTE) of one of the carrier substrates substantially matches the CTE of one of the plurality of semiconductor substrates.

9. The method as described in claim 7, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of one of the first semiconductor substrate and the second semiconductor substrate.

10. The method as described in claim 7, wherein at least a portion of the frame member extends along the support surface of the carrier between the first semiconductor substrate and the second semiconductor substrate.

11. The method as described in claim 7, wherein each of the first semiconductor substrate and the second semiconductor substrate comprises silicon.

12. The method as described in claim 11, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

13. A method for manufacturing a semiconductor device, comprising: Provides a frame component that defines one of its first and second through holes; The frame component is attached to a support surface of a carrier substrate; a first semiconductor substrate and a second semiconductor substrate are attached to the support surface of the carrier substrate through the through-holes of the first frame component and the second frame component, respectively, wherein the first semiconductor substrate and the second semiconductor substrate each have a separate functional surface and a plurality of separate integrated circuit regions; the frame component, the first semiconductor substrate, and the second semiconductor substrate are encapsulated in an encapsulant to obtain a polywafer encapsulation layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the frame component and at least one of the first semiconductor substrate and the second semiconductor substrate; the carrier substrate is removed from the polywafer encapsulation layer; a redistribution layer (RDL) is formed on the first semiconductor substrate and the second semiconductor substrate of the polywafer encapsulation layer to obtain a polywafer panel; And to cut the polycrystalline panel so that both the first semiconductor substrate and the second semiconductor substrate are cut into separate plurality of grains.

14. The method as described in claim 13, wherein the coefficient of thermal expansion (CTE) of one of the carrier substrates substantially matches the CTE of one of the plurality of semiconductor substrates.

15. The method as described in claim 13, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of one of the first semiconductor substrate and the second semiconductor substrate.

16. The method as described in claim 13, wherein each of the first semiconductor substrate and the second semiconductor substrate comprises silicon.

17. The method as described in claim 16, wherein the coefficient of thermal expansion (CTE) of one of the frame components substantially matches the CTE of silicon.

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