Semiconductor devices

Abstract

A semiconductor device with small non-uniformity is provided. In this semiconductor device, the transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator disposed on the first and second insulators and wherein a first opening is formed in a manner overlapping the region between the first and second conductors; a fourth insulator on the oxide semiconductor and disposed between the first and second conductors; and a third conductor on the fourth insulator. The capacitor includes: a second conductor; a third insulator having a second opening extending to the second conductor; a fifth insulator disposed inside the second opening; and a fourth conductor on the fifth insulator. A plug passes through the first insulator, the third insulator, the first conductor, and the oxide semiconductor, and the plug is electrically connected to the first conductor. The first and second insulators are metal oxides having an amorphous structure.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment relates to a method for manufacturing a semiconductor device. Furthermore, another embodiment relates to a semiconductor wafer and a module.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing units, or memory devices are also embodiments of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting equipment, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Prior Technology

[0004] In recent years, semiconductor devices have been developed, mainly using LSI, CPU, and memory. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) that are fabricated on semiconductor wafers and have electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards such as printed circuit boards and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0007] Furthermore, it is known that the leakage current of oxide semiconductor transistors is extremely small in the non-conducting state. For example, low-power CPUs utilizing the low leakage current characteristic of oxide semiconductor transistors have been disclosed (see Patent Document 1). In addition, for example, memory devices that utilize the low leakage current characteristic of oxide semiconductor transistors to achieve long-term retention of stored content have been disclosed (see Patent Document 2).

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices incorporating integrated circuits.

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the Invention

[0010] One objective of one embodiment of the present invention is to provide a semiconductor device with minimal non-uniformity in transistor characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high reliability. Additionally, one objective of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Furthermore, one objective of one embodiment of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Additionally, one objective of one embodiment of the present invention is to provide a low-power semiconductor device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above are obvious from the description in the specification, drawings, claims, etc., and may be derived from said description.

[0012] One embodiment of the present invention is a semiconductor device including a transistor, a capacitor, and a plug. The transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator disposed on the first and second insulators and wherein a first opening is formed in a manner overlapping the region between the first and second conductors; a fourth insulator on the oxide semiconductor and disposed between the first and second conductors; and a third conductor on the fourth insulator. The capacitor includes: a second conductor; a third insulator having a second opening extending to the second conductor; a fifth insulator disposed inside the second opening; and a fourth conductor on the fifth insulator. The plug passes through the first insulator, the third insulator, the first conductor, and the oxide semiconductor, and is electrically connected to the first conductor. The first and second insulators are metal oxides having an amorphous structure.

[0013] One embodiment of the present invention is a semiconductor device including a transistor, a capacitor, and a plug. The transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator covering the first conductor and the second conductor and wherein a first opening is formed in a manner overlapping the region between the first conductor and the second conductor; a second insulator disposed on the first insulator and wherein a second opening is formed in a manner overlapping the region between the first conductor and the second conductor; a third insulator on the oxide semiconductor and disposed between the first conductor and the second conductor; and a third conductor on the third insulator. The capacitor includes: a second conductor; a first insulator and a second insulator having a third opening extending to the second conductor; a fourth insulator disposed inside the third opening; and a fourth conductor on the fourth insulator. The plug passes through the first insulator, the second insulator, the first conductor, and the oxide semiconductor, and the plug is electrically connected to the first conductor. The first insulator is a metal oxide having an amorphous structure.

[0014] One embodiment of the present invention is a semiconductor device including a transistor, a capacitor, and a plug. The transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator covering the first insulator and the second insulator and wherein a first opening is formed in a manner overlapping the region between the first conductor and the second conductor; a fourth insulator disposed on the third insulator and wherein a second opening is formed in a manner overlapping the region between the first conductor and the second conductor; a fifth insulator on the oxide semiconductor and disposed between the first conductor and the second conductor; and a third conductor on the fifth insulator. The capacitor includes: a second conductor; a second insulator, a third insulator, and a fourth insulator having a third opening extending to the second conductor; a sixth insulator disposed inside the third opening; and a fourth conductor on the sixth insulator. The plug passes through the first insulator, the third insulator, the fourth insulator, the first conductor, and the oxide semiconductor, and the plug is electrically connected to the first conductor. The first insulator, the second insulator, and the third insulator are metal oxides having an amorphous structure.

[0015] Furthermore, in the aforementioned semiconductor device, it is preferable that a seventh insulator and an eighth insulator are also included. The seventh insulator is disposed below the oxide semiconductor, and the eighth insulator is in contact with the top surface of the fourth insulator, the top surface of the third conductor, and the top surface of the fourth conductor. The seventh and eighth insulators are metal oxides having an amorphous structure.

[0016] In addition, in the above-mentioned semiconductor device, it is preferable to further include a ninth insulator, which covers the eighth insulator and contacts the top surface of the seventh insulator in a region that does not overlap with the fifth insulator, and the ninth insulator is a metal oxide having an amorphous structure.

[0017] In addition, the semiconductor device described above preferably includes a tenth insulator and an eleventh insulator, wherein the tenth insulator is in contact with the bottom surface of the seventh insulator and the eleventh insulator is in contact with the top surface of the eighth insulator, and the tenth and eleventh insulators are silicon nitride.

[0018] Furthermore, in the aforementioned semiconductor device, it is preferable that it also includes a first nitride insulator and a second nitride insulator, the first nitride insulator being disposed between a first insulator and a third insulator, and the second nitride insulator being disposed between a second insulator and a third insulator, wherein the first nitride insulator and the second nitride insulator are silicon nitride.

[0019] Furthermore, in the aforementioned semiconductor device, the top surfaces of the first insulator and the second insulator are preferably in contact with the third insulator.

[0020] Furthermore, in the aforementioned semiconductor device, the metal oxide is preferably AlOx (where x is any number greater than 0).

[0021] Additionally, one embodiment of the present invention provides a semiconductor device including a first insulating layer, a second insulating layer, a first memory cell, and a second memory cell. The first memory cell includes: a first transistor; a first capacitor; and a first plug. The first transistor includes: a first oxide semiconductor; a first conductor and a second conductor on the first oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator disposed on the first and second insulators and having a first opening formed therein overlapping the region between the first and second conductors; a fourth insulator on the first oxide semiconductor and disposed between the first and second conductors; and a third conductor on the fourth insulator. The first capacitor includes: a second conductor; a third insulator having a second opening reaching the second conductor; a fifth insulator disposed inside the second opening; and a fourth conductor on the fifth insulator. The first plug passes through the first insulator, the third insulator, the first conductor, and the first oxide semiconductor, and is electrically connected to the first conductor. The second memory cell includes: a second transistor; a second capacitor; and a second plug. The second transistor is packaged with... The second capacitor includes: a second oxide semiconductor; a fifth and a sixth conductor on the second oxide semiconductor; a sixth insulator on the fifth conductor; a seventh insulator on the sixth conductor; an eighth insulator disposed on the sixth and seventh insulators and wherein a third opening is formed in a manner overlapping the region between the fifth and sixth conductors; a ninth insulator on the second oxide semiconductor and disposed between the fifth and sixth conductors; and a seventh conductor on the ninth insulator. The second capacitor includes: a sixth conductor; an eighth insulator having a fourth opening reaching the sixth conductor; a tenth insulator disposed inside the fourth opening; and an eighth conductor on the tenth insulator. A second plug passes through the sixth insulator, the ninth insulator, the fifth conductor, and the second oxide semiconductor, and is electrically connected to the fifth conductor. A first memory cell is disposed on a first insulating layer, and a second memory cell is disposed on the first memory cell. The top surface of the first plug is electrically connected to the second plug. The second insulating layer covers the first memory cell and the second memory cell, and the second insulating layer contacts a portion of the top surface of the first insulating layer in a region that does not overlap with the first and second oxide semiconductors.

[0022] Furthermore, in the aforementioned semiconductor device, preferably, the first insulating layer includes an eleventh insulator and a twelfth insulator on the eleventh insulator, the second insulating layer includes a thirteenth insulator and a fourteenth insulator on the thirteenth insulator, the eleventh and thirteenth insulators contain silicon nitride, and the twelfth and fourteenth insulators are metal oxides having an amorphous structure.

[0023] Furthermore, in the aforementioned semiconductor device, the metal oxide is preferably AlOx (where x is any number greater than 0).

[0024] According to one embodiment of the present invention, a semiconductor device with small non-uniformity in transistor characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good reliability can be provided. Additionally, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Additionally, according to one embodiment of the present invention, a low-power semiconductor device can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the above-described effects to be achieved. Effects other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be derived from said description. Simple Explanation of the Diagram

[0026] [Fig. 1A] is a top view of a semiconductor device according to an embodiment of the present invention, and [Fig. 1B] to [Fig. 1D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 2] is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3A] is a top view of a semiconductor device according to an embodiment of the present invention, and [Figures 3B] to [Figures 3D] are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Figure 4A] is a diagram illustrating the classification of the crystal structure of IGZO, [Figure 4B] is a diagram illustrating the XRD pattern of the CAAC-IGZO film, and [Figure 4C] is a diagram illustrating the nano-beam electron diffraction pattern of the CAAC-IGZO film. [Fig. 5A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 5B] to [Fig. 5D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 6A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 6B] to [Fig. 6D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 7A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 7B] to [Fig. 7D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 8A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 8B] to [Fig. 8D] are cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 9A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 9B] to [Fig. 9D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 10A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 10B] to [Fig. 10D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 11A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 11B] to [Fig. 11D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 12A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 12B] to [Fig. 12D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 13A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 13B] to [Fig. 13D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 14A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 14B] to [Fig. 14D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 15A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 15B] to [Fig. 15D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 16A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 16B] to [Fig. 16D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 17A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 17B] to [Fig. 17D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 18A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 18B] to [Fig. 18D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 19A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 19B] to [Fig. 19D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 20A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 20B] to [Fig. 20D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 21A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 21B] to [Fig. 21D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Fig. 22A] is a top view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and [Fig. 22B] to [Fig. 22D] are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] is a top view illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 24] is a cross-sectional view illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 25] is a cross-sectional view illustrating a microwave processing apparatus according to an embodiment of the present invention. [Figure 26] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 27] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 28A] is a top view of a semiconductor device according to an embodiment of the present invention, and [Figure 28B] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 29] is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 30A] is a block diagram showing a structural example of a memory device according to an embodiment of the present invention, and [Figure 30B] is a perspective view showing a structural example of a memory device according to an embodiment of the present invention. Figures 31A to 31C are circuit diagrams illustrating a structural example of a memory device according to an embodiment of the present invention. [Figure 32] is a diagram showing the various memory devices in a hierarchical manner. [Figure 33A] is a block diagram of a semiconductor device according to an embodiment of the present invention, and [Figure 33B] is a perspective view of a semiconductor device according to an embodiment of the present invention. [Figure 34A] and [Figure 34B] are diagrams illustrating an example of an electronic component. Figures 35A to 35E are schematic diagrams of a memory device according to an embodiment of the present invention. Figures 36A to 36H are diagrams illustrating an electronic device according to one embodiment of the present invention. Implementation

[0027] The embodiments will now be described with reference to the drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0028] In the drawings, for obvious purposes, sizes, layer thicknesses, or areas are sometimes exaggerated. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples, and the invention is not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or photoresist masks are sometimes unintentionally etched due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, in the drawings, the same element symbols are sometimes used across different drawings to represent the same parts or parts with the same function, omitting repeated descriptions. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without specifically adding element symbols.

[0029] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some components are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0030] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the process sequence or stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0031] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration and to illustrate the positional relationships of components with reference to diagrams. Furthermore, the positional relationships of components may be appropriately changed depending on the orientation of each component being described. Therefore, the use of terms not limited to those described in the specification may be modified as appropriate.

[0032] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are disclosed in the drawings or text, not limited to those specified therein. Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0033] In this specification, etc., a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel-forming region (hereinafter also referred to as a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and drain. Note that in this specification, the channel-forming region refers to the region through which current primarily flows.

[0034] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0035] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the conducting state) and gate electrode in a top view of the transistor, or between the source (source region or source electrode) and drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, channel length refers to any value, maximum value, minimum value, or average value in the channel-forming region.

[0036] Channel width, for example, refers to the length of the channel-forming region perpendicular to the channel length direction in the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the conducting state) and gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value within the channel-forming region.

[0037] In this specification, depending on the transistor's structure, the actual channel width (hereinafter also referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the transistor's top view (hereinafter also referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, the effect cannot be ignored because the effective channel width is sometimes greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, the proportion of the channel formation region formed on the side of the semiconductor is sometimes increased. In this case, the effective channel width is greater than the apparent channel width.

[0038] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width based on design values, it is necessary to know the assumed shape of the semiconductor beforehand. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately measure the effective channel width.

[0039] In this specification, when simply described as "channel width," it sometimes refers to the visual channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, and visual channel width can be determined by analyzing cross-sectional TEM images, etc.

[0040] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also sometimes act as an impurity. Furthermore, the incorporation of impurities can sometimes lead to the formation of oxygen vacancies (also known as VO₂) in the oxide semiconductor.

[0041] Note that in this specification, silicon oxynitride refers to a substance in which the oxygen content is greater than the nitrogen content. Furthermore, silicon oxynitride refers to a substance in which the nitrogen content is greater than the oxygen content.

[0042] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0043] In this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°. Therefore, it also includes a state where the angle is between -5° and 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is between -30° and 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is between 80° and 100°. Therefore, it also includes a state where the angle is between 85° and 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is between 60° and 120°.

[0044] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0045] Note that in this specification, "normally off" means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor with a channel width of 1 μm is less than 1 × 10⁻²⁰ A at room temperature, less than 1 × 10⁻¹⁸ A at 85 °C, or less than 1 × 10⁻¹⁶ A at 125 °C.

[0046] Implementation Method 1 In this embodiment, an example of a semiconductor device including a transistor 200 and a capacitor 292 according to an embodiment of the present invention and a method thereof are described using Figures 1 to 22.

[0047] <Example 1 of semiconductor device structure> Figure 1 illustrates the structure of a semiconductor device including transistor 200 and capacitor 292. Figures 1A to 1D are top views and cross-sectional views of the semiconductor device including transistor 200 and capacitor 292. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Here, Figure 1B is a cross-sectional view along the dotted lines A1-A2 in Figure 1A, which corresponds to a cross-sectional view along the channel length direction of transistor 200. Figure 1C is a cross-sectional view along the dotted lines A3-A4 in Figure 1A, which corresponds to a cross-sectional view along the channel width direction of transistor 200. Figure 1D is a cross-sectional view of the portion indicated by dotted lines A5-A6 in Figure 1A, which corresponds to a cross-sectional view of capacitor 292. Note that in the top view of Figure 1A, some components are omitted for clarity.

[0048] A semiconductor device according to one embodiment of the present invention includes: an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 and a capacitor 292 on the insulator 214, an insulator 280 on the transistor 200 and the capacitor 292, an insulator 282 on the insulator 280, an insulator 284 on the insulator 282, an insulator 283 on the insulator 284, and an insulator 274 on the insulator 284. Insulators 212, 214, 280, 282, 283, 284, and 274 are used as interlayer films. Additionally, the semiconductor device includes a conductor 240a electrically connected to the transistor 200 and used as a plug, and a conductor 240b electrically connected to the capacitor and used as a plug. In addition, it includes an insulator 241a that contacts the side of the conductor 240a used as a plug, and an insulator 241b that contacts the side of the conductor 240b used as a plug. Furthermore, a conductor 246a, electrically connected to the conductor 240a and used as wiring, is provided on the insulator 274 and the conductor 240a; a conductor 246b, electrically connected to the conductor 240b and used as wiring, is provided on the insulator 274 and the conductor 240b. Furthermore, an insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 274.

[0049] An insulator 241a is disposed in contact with the inner wall of the openings of insulators 282, 284, 283, and 274. A first conductor 240a is disposed in contact with the side of insulator 241a, and a second conductor 240a is disposed inside the first conductor 240a. Similarly, an insulator 241b is disposed in contact with the inner wall of the openings of insulators 282, 284, 283, and 274. A first conductor 240b is disposed in contact with the side of insulator 241b, and a second conductor 240b is disposed inside the first conductor 240b. The height of the top surface of conductor 240a can be approximately the same as the height of the top surface of insulator 274 overlapping the area of ​​conductor 246a. Likewise, the height of the top surface of conductor 240b can be approximately the same as the height of the top surface of insulator 274 overlapping the area of ​​conductor 246b. Note that in transistor 200, a first conductor (conductor 240a and conductor 240b) and a second conductor of conductor 240 are stacked, but the present invention is not limited thereto. For example, conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In the case of a structure having a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for distinction.

[0050] [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, an insulator 273a on the insulator 271a, a conductor 242b on the oxide 243b, and an insulator on the conductor 242b. 271b, insulator 273b on insulator 271b, insulator 250 (insulator 250a and insulator 250b) on oxide 230b, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping a portion of oxide 230b, insulator 272a disposed on insulator 224, oxide 230a, oxide 230b, oxide 243a, conductor 242a, insulator 271a and insulator 273a, insulator 272b disposed on insulator 224, oxide 230a, oxide 230b, oxide 243b, conductor 242b, insulator 271b and insulator 273b, insulator 275a on insulator 272a and insulator 275b on insulator 272b. Here, as shown in Figure 1B, the height of the top surface of conductor 260 is approximately the same as the height of the top surfaces of insulator 250 and insulator 280. Furthermore, insulator 282 is in contact with the top surfaces of conductor 260, insulator 250, and insulator 280.

[0051] Hereinafter, oxides 230a and 230b are sometimes collectively referred to as oxide 230. Additionally, insulators 250a and 250b are sometimes collectively referred to as insulator 250. Additionally, insulators 271a and 271b are sometimes collectively referred to as insulator 271. Additionally, insulators 272a and 272b are sometimes collectively referred to as insulator 272. Additionally, insulators 273a and 273b are sometimes collectively referred to as insulator 273. Additionally, insulators 275a and 275b are sometimes collectively referred to as insulator 275.

[0052] An opening reaching the oxide 230b is formed in insulators 280, 272, and 275. An insulator 250 and a conductor 260 are disposed within this opening. Furthermore, along the channel length direction of the transistor 200, a conductor 260 and an insulator 250 are disposed between insulators 271a, 273a, 242a, and 243a and insulators 271b, 273b, 242b, and 243b. The insulator 250 has a region that contacts the side surface of the conductor 260 and a region that contacts the bottom surface of the conductor 260.

[0053] Oxide 230 preferably includes oxide 230a disposed on insulator 224 and oxide 230b disposed on oxide 230a. By disposing oxide 230a below oxide 230b, the diffusion of impurities from the structure formed below oxide 230a to oxide 230b can be suppressed.

[0054] Note that in transistor 200, oxide 230 has a two-layer stacked structure having oxide 230a and oxide 230b, but the present invention is not limited thereto. For example, oxide 230 may have a single-layer or three-layer stacked structure of oxide 230b, or it may have a structure in which both oxide 230a and oxide 230b have stacked structures.

[0055] Conductor 260 is used as the first gate electrode (also called the top gate electrode), and conductor 205 is used as the second gate electrode (also called the back gate electrode). Additionally, insulator 250 is used as the first gate insulator, and insulator 224 is used as the second gate insulator. Furthermore, conductor 242a is used as one of the source and drain electrodes, and conductor 242b is used as the other. Moreover, at least a portion of the region of oxide 230 overlapping with conductor 260 is used as a channel forming region.

[0056] Here, Figure 2 shows an enlarged view of the area near the channel formation region in Figure 1B. As shown in Figure 2, oxide 230b includes region 230bc, which serves as the channel formation region of transistor 200, and regions 230ba and 230bb, which are clamping regions 230bc and used as source or drain regions. At least a portion of region 230bc overlaps with conductor 260. In other words, region 230bc is disposed between conductor 242a and conductor 242b. Region 230ba overlaps with conductor 242a, and region 230bb overlaps with conductor 242b.

[0057] Compared to regions 230ba and 230bb, region 230bc, used as a channel forming region, is a high-resistivity region with low carrier concentration due to its fewer oxygen vacancies or lower impurity concentration. Conversely, regions 230ba and 230bb, used as source or drain regions, have increased carrier concentration due to their higher oxygen vacancies or higher concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in lower resistance. In other words, regions 230ba and 230bb are regions with higher carrier concentration and lower resistance than region 230bc.

[0058] Here, the carrier concentration in region 230bc, used as the channel forming region, is preferably below 1×10¹⁸ cm⁻³, more preferably below 1×10¹⁷ cm⁻³, further preferably below 1×10¹⁶ cm⁻³, more preferably below 1×10¹³ cm⁻³, and even more preferably below 1×10¹² cm⁻³. Note that there is no particular limitation on the lower limit of the carrier concentration in region 230bc, used as the channel forming region; for example, it can be set to 1×10⁻⁹ cm⁻³.

[0059] Additionally, a region can be formed between region 230bc and region 230ba or region 230bb where the carrier concentration is equal to or lower than that of region 230ba and region 230bb, but equal to or higher than that of region 230bc. In other words, this region is used as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region is sometimes equal to or lower than that of region 230ba and region 230bb, but equal to or higher than that of region 230bc. Furthermore, the oxygen vacancies in this junction region are sometimes equal to or less than those in region 230ba and region 230bb, but equal to or more than those in region 230bc.

[0060] Note that Figure 2 shows an example of regions 230ba, 230bb, and 230bc formed on oxide 230b, but the present invention is not limited thereto. For example, the above-mentioned regions can be formed not only on oxide 230b but also on oxide 230a.

[0061] Furthermore, in oxide 230, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metallic elements and impurity elements such as hydrogen and nitrogen detected in each region do not necessarily need to vary in stages for each region; they can vary gradually within each region. That is, the closer to the channel formation region, the lower the concentration of metallic elements and impurity elements such as hydrogen and nitrogen should be.

[0062] In transistor 200, the oxide 230 (oxide 230a and oxide 230b) that includes the channel forming region is preferably a metal oxide (hereinafter also referred to as oxide semiconductor) that can be used as a semiconductor.

[0063] Furthermore, the metal oxide used as the semiconductor is preferably a metal oxide with a band gap of 2 eV or more, and more preferably 2.5 eV or more. In this way, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced.

[0064] For example, oxide 230 is preferably an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). Alternatively, In-Ga oxide, In-Zn oxide, and indium oxide can also be used as oxide 230.

[0065] Preferably, the ratio of the number of In atoms to the number of element M in the metal oxide used for oxide 230b is greater than the ratio of the number of In atoms to the number of element M in the metal oxide used for oxide 230a.

[0066] Thus, by placing oxide 230a below oxide 230b, the diffusion of impurities and oxygen from the structure formed below oxide 230a to oxide 230b can be suppressed.

[0067] In addition, since the defect state density of each interface of oxides 230a and 230b can be reduced by including common elements (as main components) in addition to oxygen, the effect of interface scattering on carrier conduction is small, thereby obtaining a high on-state current.

[0068] Oxide 230b is preferably crystalline. In particular, it is preferred to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0069] CAAC-OS possesses a highly crystalline, dense structure and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating CAAC-OS after its formation at a temperature that prevents polymorphism (e.g., above 400°C and below 600°C), a more crystalline, dense structure can be achieved. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen within it can be further reduced.

[0070] On the other hand, distinct grain boundaries are not easily observed in CAAC-OS, thus reducing the likelihood of a decrease in electron mobility due to grain boundaries. Therefore, metal oxides containing CAAC-OS exhibit stable physical properties. Consequently, metal oxides with CAAC-OS demonstrate good heat resistance and reliability.

[0071] In transistors using oxide semiconductors, the electrical properties can easily change and sometimes reduce reliability if impurities or oxygen vacancies are present in the channel-forming region of the oxide semiconductor. Furthermore, hydrogen near oxygen vacancies can form defects (sometimes referred to as VOH) that allow hydrogen to enter the oxygen vacancy and potentially generate electrons that can become carriers. Therefore, when oxygen vacancies are present in the channel-forming region of the oxide semiconductor, the transistor exhibits always-on characteristics (the characteristic that current flows through the transistor even without a voltage applied to the gate electrode). Thus, it is preferable to minimize impurities, oxygen vacancies, and VOH in the channel-forming region of the oxide semiconductor. In other words, it is preferable to reduce the carrier concentration in the channel-forming region of the oxide semiconductor and to essentially or substantially reduce it to I-type.

[0072] In contrast, by performing heat treatment with an insulator containing oxygen that is removed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulator, thereby reducing oxygen vacancies and VOH. Note that when too much oxygen is supplied to the source or drain region, it may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, when the oxygen supplied to the source or drain region is non-uniform within the substrate surface, non-uniformity occurs in the semiconductor device characteristics, including the transistor.

[0073] Therefore, preferably, in the oxide semiconductor, the carrier concentration in region 230bc, which is used as the channel formation region, is reduced and is i-typened or substantially i-typened. On the other hand, preferably, the carrier concentration in regions 230ba and 230bb, which are used as source or drain regions, is high and is n-typened. In other words, it is preferable to reduce oxygen vacancies and VOH in region 230bc of the oxide semiconductor and not to supply excessive oxygen to regions 230ba and 230bb.

[0074] Therefore, in this embodiment, microwave treatment is performed in an oxygen-containing atmosphere with conductors 242a and 242b disposed on oxide 230b to reduce oxygen vacancies and VOH in region 230bc. Here, microwave treatment refers, for example, to treatment using a device including a power source that generates high-density plasma using microwaves.

[0075] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency radio waves (RF), thus enabling oxygen plasma activity. At this time, region 230bc can also be irradiated with microwaves or RF. Through the action of plasma and microwaves, the V OH in region 230bc can be separated, thereby removing hydrogen (H) from region 230bc and filling oxygen vacancies (VO) with oxygen. In other words, the reaction "V OH → H + VO" occurs in region 230bc, reducing the hydrogen concentration in region 230bc. Therefore, the oxygen vacancies and V OH in region 230bc can be reduced, thereby lowering the carrier concentration.

[0076] Furthermore, when microwave processing is performed in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not affect regions 230ba and 230bb. Moreover, the effects of oxygen plasma can be reduced by insulators 271, 273, 272, 275, and 280 covering oxide 230b and conductors 242 (conductors 242a and 242b). Therefore, since no reduction in VOH and excessive oxygen supply occur in regions 230ba and 230bb during microwave processing, a decrease in carrier concentration can be prevented.

[0077] As described above, region 230bc of the oxide semiconductor can be selectively degraded by removing oxygen vacancies and V OH groups, thereby making region 230bc i-type or substantially i-type. Furthermore, regions 230ba and 230bb, which are used as source or drain regions, can be kept n-type by suppressing excessive oxygen supply. Thus, variations in the electrical characteristics of the transistor 200 can be suppressed, thereby suppressing non-uniformity in the electrical characteristics of the transistor 200 within the substrate surface.

[0078] By employing the above structure, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, a semiconductor device with good reliability can be provided. In addition, a semiconductor device with excellent electrical characteristics can be provided.

[0079] Note that in Figure 1B, the side of the opening (including the groove of oxide 230b) into which the conductor 260 is embedded is approximately perpendicular to the surface on which oxide 230b is formed, but this embodiment is not limited to this. For example, the bottom of the opening may also be a U-shaped shape with a gently curved surface. In addition, for example, the side of the opening may also be inclined to the surface on which oxide 230b is formed.

[0080] Additionally, as shown in Figure 1C, when viewed in cross-section of the channel width of transistor 200, a curved surface may also be present between the side surface and the top surface of oxide 230b. That is, the ends of the side surface and the top surface may also be curved (hereinafter also referred to as circular).

[0081] The radius of curvature of the aforementioned curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the aforementioned curved surface. Specifically, the radius of curvature of the aforementioned curved surface is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the oxide 230b of the insulator 250 and the conductor 260 can be improved.

[0082] Oxide 230 is preferably a stacked structure having multiple oxide layers with different compositions. Specifically, the atomic ratio of element M, relative to the main metal element, in the metal oxide used for oxide 230a is preferably greater than the atomic ratio of element M, relative to the main metal element, in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 230a is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230b. Similarly, the atomic ratio of In to element M in the metal oxide used for oxide 230b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0083] Furthermore, oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Therefore, oxygen extraction from oxide 230b at the source electrode or drain electrode can be suppressed. Thus, even with heat treatment, oxygen extraction from oxide 230b can be reduced, and the transistor 200 is also stable at high temperatures (so-called thermal budget) during the process.

[0084] Here, the energy levels at the junction of oxides 230a and 230b will be explained. At the junction of oxides 230a and 230b, the conduction band bottom energy levels of oxides 230a and 230b change gradually. In other words, this can also be expressed as the conduction band bottom energy levels at the junction of oxides 230a and 230b changing continuously or continuously joining. Therefore, it is preferable to reduce the defect state density of the mixed layer formed at the interface of oxides 230a and 230b.

[0085] Specifically, by making oxides 230a and 230b contain a common element as a main component in addition to oxygen, a mixed layer with low defect state density can be formed. For example, when oxide 230b is an In-M-Zn oxide, oxides 230a can also be In-M-Zn oxides, M-Zn oxides, oxides of element M, In-Zn oxides, indium oxides, etc.

[0086] Specifically, for oxide 230a, a metal oxide with an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar, is acceptable. For oxide 230b, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, or an In:M:Zn ratio of 4:2:3 or similar, is acceptable. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, gallium is preferably used as element M.

[0087] Furthermore, when forming metal oxides by sputtering, the aforementioned atomic ratio is not limited to the atomic ratio of the formed metal oxide, but can also be the atomic ratio of the sputtering target used to form the metal oxide.

[0088] By equipping oxides 230a and 230b with the aforementioned structure, the defect state density at the interface between oxides 230a and 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, thereby enabling the transistor 200 to achieve high on-state current and high-frequency characteristics.

[0089] At least one of insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen from one side of the substrate or above the transistor 200 to the transistor 200. Therefore, at least one of insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286 is preferably an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, making it difficult for the aforementioned oxygen to permeate).

[0090] In addition, in this specification, "barrier insulating film" refers to an insulating film with barrier properties. Note that in this specification, barrier properties refer to the function of inhibiting the diffusion of the corresponding substance (or low permeability). Alternatively, it refers to the function of capturing and fixing the corresponding substance (also known as gettering).

[0091] As insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, silicon nitride, which has higher hydrogen blocking properties, is preferably used as insulators 212, 275, 283, and 286. Furthermore, for example, aluminum oxide or magnesium oxide, which have high hydrogen trapping and fixing performance, are preferably used as insulators 214, 271, 272, 282, and 284. Thus, the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through insulators 212 and 214 can be suppressed. Furthermore, the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed outside the insulator 286 to the transistor 200 side can be suppressed. Additionally, the diffusion of oxygen contained in insulator 224 through insulator 212 and insulator 214 to the substrate side can be suppressed. Alternatively, the diffusion of oxygen contained in insulator 280 through insulator 282 to the top of the transistor 200 can be suppressed. Therefore, it is preferable to employ a structure in which the transistor 200 is surrounded by insulators 212, 214, 271, 272, 275, 282, 283, 284, and 286, which have the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0092] Here, insulators 214, 271, 272, 282, and 284 are preferably insulators with an amorphous structure. For example, metal oxides such as AlOx (where x is any number greater than 0) or MgOy (where y is any number greater than 0) are preferred. These amorphous metal oxides have the property that oxygen atoms have dangling bonds, which sometimes trap or fix hydrogen. By using these amorphous metal oxides as components of the transistor 200 or placing them around the transistor 200, hydrogen contained in the transistor 200 or present around the transistor 200 can be trapped or fixed. In particular, it is preferable to trap or fix hydrogen contained in the channel-forming region of the transistor 200. By using amorphous metal oxides as components of the transistor 200 or placing them around the transistor 200, a highly reliable transistor 200 and semiconductor device with good characteristics can be manufactured.

[0093] Furthermore, insulators 214, 271, 272, 282, and 284 are preferably amorphous, but polycrystalline regions may also be formed therein. Additionally, insulators 214, 271, 272, 282, and 284 may have a multilayer structure with layers of amorphous and polycrystalline structures stacked on top of each other. For example, a stacked structure may also be formed with polycrystalline layers stacked on top of amorphous layers.

[0094] Films of insulators 214, 271, 272, 282, and 284 can be formed, for example, by sputtering. Sputtering does not require hydrogen as the deposition gas, thus reducing the hydrogen concentration in insulators 212, 214, 271, 272, 282, and 284. Besides sputtering, other suitable film formation methods include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0095] Additionally, it is sometimes preferable to reduce the resistivity of insulators 212, 275, 283, and 286. For example, by making the resistivity of insulators 212, 275, 283, and 286 approximately 1 × 10¹³ Ωcm, in semiconductor device manufacturing processes using plasma, etc., insulators 212, 275, 283, and 286 can sometimes mitigate charge buildup in conductors 205, 242, 260, or 246. The resistivity of insulators 212, 275, 283, and 286 is 1 × 10¹⁰ Ωcm or more and 1 × 10¹⁵ Ωcm or less.

[0096] Furthermore, the dielectric constants of insulators 216 and 280 are preferably lower than those of insulator 214. By using materials with low dielectric constants in the interlayer film, parasitic capacitances generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, fluorinated silicon oxide, carbon-containing silicon oxide, carbon and nitrogen-containing silicon oxide, or porous silicon oxide can be appropriately used as insulators 216 and 280.

[0097] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Preferably, the conductor 205 is disposed in an opening in the insulator 216.

[0098] Conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. Conductor 205a contacts the bottom surface and sidewalls of the opening. Conductor 205b is disposed in a recess formed in conductor 205a. Here, the top surface of conductor 205b is lower than the top surface of conductor 205a and the top surface of insulator 216. Conductor 205c contacts the top surface of conductor 205b and the side surface of conductor 205a. Here, the height of the top surface of conductor 205c is approximately the same as the height of the top surface of conductor 205a and the top surface of insulator 216. In other words, conductor 205b is surrounded by conductor 205a and conductor 205c.

[0099] Here, conductors 205a and 205c are preferably made of conductive materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), and copper atoms. Furthermore, it is preferable to use conductive materials that suppress the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0100] By using a conductive material that inhibits hydrogen diffusion as conductors 205a and 205c, impurities such as hydrogen contained in conductor 205b can be prevented from diffusing through insulator 224 to oxide 230. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductors 205a and 205c, oxidation of conductor 205b and subsequent decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, single-layer or multi-layered conductive materials can be used as conductors 205a and 205c. For example, titanium nitride can be used as conductors 205a and 205c.

[0101] Furthermore, conductor 205b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, conductor 205b can be made of tungsten.

[0102] Conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0103] Furthermore, the resistivity of the conductor 205 is designed based on the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to this resistivity. Additionally, the thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to reduce the thickness of both the conductor 205 and the insulator 216 within the design limits of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thus suppressing the diffusion of these impurities into the oxide 230.

[0104] Furthermore, as shown in FIG1A, the conductor 205 is preferably larger than the region in oxide 230 that does not overlap with conductors 242a and 242b. In particular, as shown in FIG1C, the conductor 205 is preferably a region extending to the outer side of the ends of oxides 230a and 230b in the channel width direction. That is, preferably, the conductor 205 and the conductor 260 overlap with an insulator on the outer side of the ends of oxide 230 in the channel width direction. With the above structure, a region can be formed around the channel of oxide 230 by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, the transistor structure in which the electric fields of the first gate and the second gate form a region around the channel is referred to as a Surrounded channel (S-channel) structure.

[0105] In this specification, an S-channel transistor refers to a transistor structure in which the electric fields of one and the other of a pair of gate electrodes form a region around the channel. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. By employing the S-channel structure, transistors with improved tolerance to short-channel effects can be realized; in other words, transistors less prone to short-channel effects can be achieved.

[0106] Furthermore, as shown in FIG1C, the conductor 205 is extended to be used as wiring. However, the present invention is not limited to this, and the conductor used as wiring may also be provided under the conductor 205. In addition, it is not necessary to provide a conductor 205 in each transistor. For example, the conductor 205 can be used in multiple transistors.

[0107] Note that the diagram shows a structure in which conductors 205a, 205b, and 205c are stacked in transistor 200, but the invention is not limited thereto. For example, conductor 205 may have a single-layer structure or a stacked structure with two or more layers.

[0108] Insulators 222 and 224 are used as gate insulators.

[0109] Insulator 222 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulator 222 preferably has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulator 224, insulator 222 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0110] The insulator 222 is preferably an oxide containing one or both of aluminum and hafnium, which is used as the insulating material. Preferably, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are used as the insulator. When this material is used to form the insulator 222, the insulator 222 serves to suppress the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the layer of the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inner side of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0111] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator 222. Alternatively, the insulator may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator 222.

[0112] Furthermore, as the insulator 222, high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used as single layers or in stacks. When miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thin-film nature of the gate insulator. By using high-k materials as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0113] Here, the insulator 224 in contact with the oxide 230 preferably contains excess oxygen (the oxygen is removed by heating). For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 224. By providing the above-mentioned oxygen-containing insulator in contact with the oxide 230, the oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0114] Specifically, the insulator 224 is preferably an oxide material that allows some oxygen to be removed by heating, i.e., an insulating material with an excess oxygen region. The oxide that allows oxygen to be removed by heating refers to an oxide film in which the amount of oxygen molecules removed in TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10¹⁸ molecules / cm³ or more, preferably 1.0 × 10¹⁹ molecules / cm³ or more, further preferably 2.0 × 10¹⁹ molecules / cm³ or more, or 3.0 × 10²⁰ molecules / cm³ or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0115] Furthermore, in the manufacturing process of transistor 200, heat treatment is preferably performed with the surface of oxide 230 exposed. This heat treatment is preferably performed at a temperature of 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxide 230, thereby reducing oxygen vacancies (VO). Heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in a nitrogen or inert gas atmosphere, followed by heat treatment in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to fill the detached oxygen. Alternatively, heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas, followed by continuous heat treatment in a nitrogen or inert gas atmosphere. Furthermore, the gas used in the above heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is less than 1 ppb, preferably less than 0.1 ppb, and more preferably less than 0.05 ppb. By using a highly purified gas for heat treatment, the absorption of moisture and other substances by the oxide 230 can be prevented as much as possible.

[0116] By oxidizing oxide 230, the supplied oxygen can fill the oxygen vacancies in oxide 230, in other words, the reaction "V O + O → null" can be promoted. Furthermore, the residual hydrogen in oxide 230 reacts with the supplied oxygen to remove the hydrogen as H₂O (dehydration). Therefore, the recombination of residual hydrogen with oxygen vacancies in oxide 230 to form V OH can be inhibited.

[0117] Furthermore, insulators 222 and 224 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material; it can also be a stacked structure made of different materials. Additionally, insulator 224 may be formed as an island and overlap with oxide 230a. In this case, insulator 272 contacts the side surface of insulator 224 and the top surface of insulator 222.

[0118] Oxides 243a and 243b are disposed on oxide 230b. Oxides 243a and 243b are separated by a conductor 260.

[0119] Oxide 243 (oxide 243a and oxide 243b) preferably has the function of suppressing oxygen permeation. By distributing oxide 243, which has the function of suppressing oxygen permeation, between the conductor 242, which is used as the source electrode or drain electrode, and oxide 230b, the resistance between the conductor 242 and oxide 230b is reduced, which is preferable. By adopting this structure, the electrical characteristics and reliability of transistor 200 can be improved. Alternatively, if the resistance between conductor 242 and oxide 230b can be sufficiently reduced, a structure without oxide 243 can also be used.

[0120] Metal oxides containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin are preferably used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as oxide 243. Additionally, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the number of atoms of element M relative to In in the metal oxide of oxide 243 is preferably greater than the ratio of the number of atoms of element M relative to In in the metal oxide of oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. Furthermore, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be appropriately suppressed. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen from oxide 230 can sometimes be suppressed.

[0121] Preferably, conductor 242a is in contact with the top surface of oxide 243a, and conductor 242b is in contact with the top surface of oxide 243b. Conductors 242a and 242b are used as the source electrode or drain electrode of transistor 200, respectively.

[0122] As the conductor 242, it is preferred to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the invention, a nitride containing tantalum is particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., may also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0123] Note that sometimes hydrogen contained in oxide 230b, etc., diffuses into conductor 242a or conductor 242b. In particular, by using a tantalum-containing nitride as conductor 242a and conductor 242b, sometimes hydrogen contained in oxide 230b, etc., readily diffuses into conductor 242a or conductor 242b, and this diffused hydrogen bonds with the nitrogen contained in conductor 242a or conductor 242b. That is, sometimes hydrogen contained in oxide 230b, etc., is absorbed by conductor 242a or conductor 242b.

[0124] Insulator 271a is in contact with the top surface of conductor 242a, and insulator 271b is in contact with the top surface of conductor 242b. Insulator 271 is preferably an insulating film having at least the function of blocking oxygen. Therefore, insulator 271 preferably has the function of suppressing oxygen diffusion. For example, compared with insulator 280, insulator 271 preferably has the function of further suppressing oxygen diffusion. As insulator 271, silicon-containing nitrides such as silicon nitride can be used, for example. Furthermore, insulator 271 preferably has the function of capturing impurities such as hydrogen. In this case, a metal oxide with an amorphous structure, such as aluminum oxide or magnesium oxide, can be used as insulator 271. In particular, by using aluminum oxide or aluminum oxide with an amorphous structure as insulator 271, hydrogen can sometimes be captured or fixed more effectively, so it is preferred. Thus, a transistor 200 and a semiconductor device with good characteristics and high reliability can be manufactured.

[0125] Insulator 273a is in contact with the top surface of insulator 271a, and insulator 273b is in contact with the top surface of insulator 271b. Preferably, the top surface of insulator 273a is in contact with insulator 272a, and the side surface of insulator 273a is in contact with insulator 250. Preferably, the top surface of insulator 273b is in contact with insulator 272b, and the side surface of insulator 273b is in contact with insulator 250. Insulator 273 is preferably an insulator that inhibits the diffusion of impurities such as water and hydrogen, as well as oxygen; for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, silicon nitride, which has higher hydrogen barrier properties, can be used as insulator 273.

[0126] Insulator 272a contacts the sides and top surface of oxides 230a, 230b, 243a, conductor 242a, insulator 271a, and 273a. Insulator 272b contacts the sides and top surface of oxides 230a, 230b, 243b, conductor 242b, insulator 271b, and 273b. Additionally, insulators 272a and 272b contact the top surface of insulator 224. Preferably, insulator 272 is used as a barrier insulating film to suppress oxygen permeation. Furthermore, insulator 272 is preferably used as a barrier insulating film to suppress the diffusion of impurities such as water and hydrogen from above towards insulator 224 or insulator 273, and also has the function of capturing impurities such as hydrogen. In this case, alumina with an amorphous structure or alumina with an amorphous structure is preferably used as insulator 272. Because metal oxides with amorphous structures, especially amorphous aluminum oxide and amorphous aluminum oxide, can sometimes capture or fix hydrogen present in the surrounding environment, it is possible to manufacture transistors 200 and semiconductor devices with good properties and high reliability.

[0127] The insulator 275 is provided in a manner that covers the insulator 272, and an opening is formed in the area where the insulator 250 and the conductor 260 will be disposed. Silicon nitride is preferably used as the insulator 275.

[0128] Insulators 280, 224, 222, and 275 are disposed in the region sandwiched between insulators 212 and 283. By providing insulator 272, which is in contact with insulator 275 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in insulators 280, 224, 275, and 273 can be captured, and the hydrogen content in that region can be set to a certain value. In this case, alumina or the like is preferably used as insulator 272.

[0129] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of oxide 230b. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride have good thermal stability and are therefore preferred.

[0130] Similar to insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in insulator 250 is reduced. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0131] Figures 1A and 1D show that the insulator 250 has a two-layer structure consisting of insulator 250a and insulator 250b. When the insulator 250 has a two-layer stacked structure, it is preferable that the lower insulator 250a is formed using an insulator that releases oxygen upon heating, and the upper insulator 250b is formed using an insulator that has the function of suppressing oxygen diffusion. By adopting this structure, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 caused by oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a can be made of a material suitable for the insulator 250 described above, and the upper layer of the insulator 250 can be made of the same material as the insulator 222. Note that the insulator 250 can be a single-layer structure or a stacked structure of three or more layers.

[0132] Note that while insulator 250a can be formed using silicon oxide or silicon oxynitride, insulator 250b can also be formed using a high-k insulating material with a high relative permittivity. By employing a stacked structure of insulator 250a and insulator 250b as the gate insulator, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0133] Specifically, as insulator 250b, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides suitable for oxide 230, can be used. In particular, it is preferred to use an insulator containing one or both of aluminum and hafnium oxides. For example, as insulator 250b, a multilayer structure containing silicon oxide and hafnium oxide on the silicon oxide can be adopted.

[0134] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide is preferably configured to suppress the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen contained in the insulator 250 can be suppressed.

[0135] Alternatively, the aforementioned metal oxide can also be used as part of the first gate electrode. For example, a metal oxide suitable for oxide 230 can be used as the aforementioned metal oxide. In this case, by forming the conductor 260a using a sputtering method, the resistance value of the aforementioned metal oxide can be reduced, making it a conductor. The aforementioned conductor can be referred to as an OC (Oxide Conductor) electrode.

[0136] By incorporating the aforementioned metal oxide, the on-state current of the transistor 200 can be increased without reducing the influence of the electric field from the conductor 260. Furthermore, by maintaining the distance between the conductor 260 and the oxide 230 using the physical thickness of the insulator 250 and the aforementioned metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. Additionally, by providing a stacked structure of the insulator 250 and the aforementioned metal oxide, the physical distance between the conductor 260 and the oxide 230, as well as the electric field strength applied from the conductor 260 to the oxide 230, can be easily adjusted.

[0137] Conductor 260 is used as the first gate electrode of transistor 200. Conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed such that it surrounds the bottom and side surfaces of conductor 260b. Furthermore, as shown in FIG1B, the top surface of conductor 260 is substantially aligned with the top surface of insulator 250. Moreover, although conductor 260 has a two-layer structure of conductor 260a and conductor 260b, it may also have a single-layer structure or a stacked structure of three or more layers.

[0138] Here, the conductor 260a is preferably a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0139] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. For example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be used as conductive materials with the function of inhibiting oxygen diffusion.

[0140] Furthermore, since conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main component. In addition, conductor 260b can have a multilayer structure, for example, it can have a multilayer of titanium or titanium nitride with the aforementioned conductive material.

[0141] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner by filling the openings formed in the insulator 280, etc. By forming the conductor 260 in this way, the conductor 260 can be accurately positioned in the region between the conductor 242a and the conductor 242b without alignment.

[0142] Furthermore, as shown in Figure 1C, in the channel width direction of the transistor 200, with the bottom surface of the insulator 222 as a reference, the height of the bottom surface of the region where the conductor 260 does not overlap with the oxide 230b is preferably lower than the height of the bottom surface of the oxide 230b. By employing a structure in which the conductor 260, used as a gate electrode, covers the side and top surfaces of the channel forming region of the oxide 230b via the insulator 250, it is easier for the electric field of the conductor 260 to act on the entire channel forming region of the oxide 230b. This improves the on-state current and frequency characteristics of the transistor 200. With the bottom surface of the insulator 222 as a reference, the difference between the height of the bottom surface of the conductor 260 and the bottom surface of the oxide 230b in the region where the oxides 230a and 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0143] <Capacitor 292> The capacitor 292 includes a conductor 242b, an insulator 293 disposed on the conductor 242b, and a conductor 294 disposed on the insulator 293. Here, the insulator 293 and conductor 294 are disposed in openings formed in insulators 280, 275b, 272b, 273b, and 271b. The insulator 293 is disposed in contact with the bottom surface and sidewalls of the opening. That is, the insulator 293 contacts the top surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 273b, the side surface of the insulator 272b, the side surface of the insulator 275b, and the side surface of the insulator 280. Furthermore, the insulator 293 is formed with a recess along the shape of the opening. The conductor 294 contacts the top surface and side surface of the insulator 293 by filling the recess. In addition, the height of the top surface of insulator 293 and conductor 294 is sometimes approximately the same as the height of the top surface of insulator 280, insulator 250 and conductor 260.

[0144] Here, conductor 242b is used as the lower electrode of capacitor 292, conductor 294 is used as the upper electrode of capacitor 292, and insulator 293 is used as the dielectric of capacitor 292. Thus, capacitor 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. Furthermore, since one of the electrodes in capacitor 292, namely conductor 242b, also serves as the source electrode of transistor, the area required for arranging transistors and capacitors can be reduced. Additionally, since a portion of the transistor manufacturing process can be incorporated into the manufacturing process of capacitor 292, highly productive semiconductor devices can be manufactured. Moreover, since insulator 293 can be provided separately from the structure of transistor 200, the structure and material of insulator 293 can be appropriately selected according to the required performance of capacitor 292.

[0145] The insulator 293 is preferably made of a high-k material. Examples of high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxynitride, hafnium oxynitride, hafnium nitride, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. Furthermore, the insulator 293 can also be a material in which films of these high-k materials are stacked. For example, the insulator 293 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked sequentially.

[0146] Alternatively, the conductor 294 can be made of a material suitable for conductor 260. Furthermore, similar to conductor 260, conductor 294 can also employ a multilayer structure.

[0147] An insulator 280 is disposed on an insulator 275, and an opening is formed in the region where the insulator 250 and the conductor 260 are disposed. Furthermore, the top surface of the insulator 280 may be planarized.

[0148] Preferably, the insulator 280 used as the interlayer film has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Especially, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen that has been released upon heating, which is also preferred.

[0149] Similar to insulator 224, insulator 280 preferably contains regions with excess oxygen or excess oxygen. Furthermore, the concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as insulator 280.

[0150] Insulator 282 is preferably a barrier insulating film used to suppress the diffusion of impurities such as water and hydrogen from above into insulator 280 and also has the function of capturing impurities such as hydrogen. Furthermore, insulator 282 is preferably a barrier insulating film used to suppress oxygen permeation. As insulator 282, a metal oxide with an amorphous structure, such as alumina, can be used. By providing insulator 282, which is in contact with insulator 280 and has the function of capturing impurities such as hydrogen, in the region sandwiched between insulator 212 and insulator 283, impurities such as hydrogen contained in insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, as insulator 282, using alumina with an amorphous structure or alumina with an amorphous structure can sometimes more effectively capture or fix hydrogen, so it is preferred. Thus, a transistor 200 and a semiconductor device with good characteristics and high reliability can be manufactured.

[0151] Insulator 283 can be used as a barrier insulating film to prevent impurities such as water and hydrogen from diffusing from above into insulator 280. Insulator 283 is disposed on insulator 282. As insulator 283, silicon-containing nitrides such as silicon nitride or silicon oxynitride are preferably used. For example, silicon nitride formed by sputtering is used as insulator 283. By forming insulator 283 by sputtering, a silicon nitride film with high density and low susceptibility to voids can be formed. Alternatively, as insulator 283, silicon nitride formed by CVD can also be laminated on silicon nitride formed by sputtering.

[0152] Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductors 240a and 240b may also have a laminated structure.

[0153] When the conductor 240 is constructed using a multilayer structure, the conductor in the lower layer of the conductor 240 is preferably a conductive material that suppresses the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc., are preferred. The conductive material that suppresses the permeation of impurities such as water and hydrogen can be used as a single layer or in multilayers. Furthermore, it prevents impurities such as water and hydrogen contained in the layer above the insulator 274 from permeating the conductor 240a and mixing into the oxide 230.

[0154] For example, silicon nitride, aluminum oxide, and silicon oxynitride can be used as insulators 241a and 241b. Because insulator 241a is disposed in contact with insulators 274, 283, 284, 282, 280, 275a, 272a, 273a, and 271a, impurities such as water and hydrogen contained in insulator 280 can be suppressed from mixing into oxide 230 via conductor 240a. Furthermore, because insulator 241b is disposed in contact with insulators 274, 283, 284, and 282, impurities such as water and hydrogen contained in insulator 274 can be suppressed from mixing into oxide 230 via conductors 240b and 294. Silicon nitride, in particular, has high hydrogen barrier properties, making it preferred. Additionally, it can prevent the oxygen contained in insulator 280 from being absorbed by conductor 240a. It can also prevent the oxygen contained in insulator 274 from being absorbed by conductor 240b.

[0155] Conductors 246 (conductors 246a and 246b) used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. Conductors 246 are preferably made of conductive materials primarily composed of tungsten, copper, or aluminum. Alternatively, the conductor can have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the aforementioned conductive materials. The conductor can also be formed by embedding it in an opening in an insulator. Alternatively, an insulator 286 can be disposed on conductors 246 and 274.

[0156] Materials Constituting Semiconductor Devices The following describes the constituent materials that can be used in semiconductor devices.

[0157] 《Substrate》 The substrate for forming the transistor 200 can be an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Additionally, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Alternatively, substrates with components mounted on them can be used. Examples of components mounted on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0158] Insulators As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0159] For example, when miniaturizing and hyper-integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using high-k materials as the gate insulator, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. On the other hand, by using materials with relatively low permittivity in the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0160] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0161] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide or resin.

[0162] Furthermore, by surrounding the transistor in which metal oxides are used to form the channel, an insulator that suppresses the permeation of impurities such as hydrogen and oxygen can stabilize the electrical properties of the transistor. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0163] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is removed by heating is contacted with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0164] Conductors As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicates can also be used.

[0165] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0166] Furthermore, when using oxides in the channel forming region of a transistor, it is preferable to employ a laminated structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material as the conductor used as the gate electrode. In this case, it is preferable to place the oxygen-containing conductive material on one side of the channel forming region. By placing the oxygen-containing conductive material on one side of the channel forming region, oxygen detached from the conductive material can be easily supplied to the channel forming region.

[0167] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Additionally, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide can also be used. By using the above materials, hydrogen contained in the metal oxide in which the channel is formed can sometimes be captured. Or, hydrogen mixed in from external insulators or the like can sometimes be captured.

[0168] Metal Oxides As oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that is used as a semiconductor. The metal oxides that can be used as oxide 230 will be described below.

[0169] The metal oxide preferably contains at least indium or zinc. It is particularly preferred that it contains both indium and zinc.

[0170] This section considers the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used with element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. Note that multiple of these elements can sometimes be combined as element M.

[0171] In addition, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0172] <Classification of Crystal Structures> First, the classification of crystal structures in oxide semiconductors will be explained with reference to Figure 4A. Figure 4A is a diagram illustrating the classification of crystal structures in oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0173] As shown in Figure 4A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." Completely amorphous is included within "Amorphous." "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). However, the "Crystalline" classification does not include single crystal, poly crystal, or completely amorphous. "Crystal" includes both single crystal and poly crystal.

[0174] Furthermore, the structure in the thickened portion of Figure 4A represents an intermediate state between "amorphous" and "crystal," belonging to a novel boundary region (New crystalline phase). In other words, this structure is entirely different from "crystal" or the energetically unstable "amorphous."

[0175] X-ray diffraction (XRD) spectroscopy can be used to evaluate the crystal structure of films or substrates. Here, Figure 4B shows the XRD spectrum of a CAAC-IGZO film classified as "Crystalline" obtained by GIXD (Grazing-Incidence XRD). GIXD is also known as the thin film method or the Seemann-Bohlin method. The XRD spectrum obtained by GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0176] As shown in Figure 4B, peaks indicating clear crystallinity were detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment was detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 4B, the peak near 2θ=31° is asymmetrical about the angle at which the peak intensity is detected.

[0177] Furthermore, the crystal structure of the film or substrate can be evaluated using the diffraction pattern observed by Nano Beam Electron Diffraction (NBED). Figure 4C shows the diffraction pattern of the CAAC-IGZO film. Figure 4C is the diffraction pattern observed by NBED with an electron beam incident in a direction parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Additionally, in the nanobeam electron diffraction, an electron diffraction method with a beam diameter of 1 nm was performed.

[0178] As shown in Figure 4C, multiple spots representing c-axis alignment were observed in the diffraction pattern of the CAAC-IGZO film.

[0179] Structure of Oxide Semiconductors Furthermore, when focusing on the crystal structure of oxide semiconductors, the classification of oxide semiconductors sometimes differs from that shown in Figure 4A. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include, for example, the aforementioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors, etc.

[0180] Here, we will explain the details of CAAC-OS, nc-OS, and a-like OS.

[0181] [CAAC-OS] CAAC-OS is an oxide semiconductor comprising multiple crystalline regions, whose c-axis is aligned in a specific direction. This specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. Furthermore, a crystalline region is a region exhibiting a periodic atomic arrangement. Note that when atomic arrangement is considered as lattice arrangement, a crystalline region is also a region with a consistent lattice arrangement. Moreover, CAAC-OS has regions where multiple crystalline regions are connected along the ab-plane direction, and sometimes these regions exhibit distortion. Distortion refers to the portion of the lattice arrangement direction that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor with c-axis alignment but no obvious alignment along the ab-plane direction.

[0182] Furthermore, each of the aforementioned multiple crystalline regions is composed of one or more microcrystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single microcrystal, the maximum diameter of that region is less than 10 nm. Conversely, when a crystalline region is composed of multiple microcrystals, the size of that region can sometimes be around tens of nm.

[0183] Furthermore, in In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, and titanium), CAAC-OS tends to have a layered crystal structure (also called a layered structure) comprising layers containing stacked indium (In) and oxygen (hereinafter, In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer). In addition, indium and element M can substitute for each other. Therefore, sometimes the (M,Zn) layer contains indium. Also, sometimes the In layer contains element M. Note that sometimes the In layer contains Zn. This layered structure is observed, for example, as a lattice image in high-resolution TEM images.

[0184] For example, when performing structural analysis on CAAC-OS films using an XRD apparatus, the peak value of the c-axis alignment is detected at or near 2θ = 31° in out-of-plane XRD measurements using θ / 2θ scanning. Note that the position (2θ value) representing the peak value of the c-axis alignment sometimes varies depending on the type and composition of the metallic elements constituting CAAC-OS.

[0185] Additionally, for example, multiple bright spots (spots) were observed in the electron diffraction pattern of the CAAC-OS film. Furthermore, when the spot of the incident electron beam passing through the sample (also known as the direct spot) is taken as the center of symmetry, one spot and other spots are observed at point-symmetrical positions.

[0186] When observing the crystalline region from the aforementioned specific directions, although the lattice arrangement within the region is primarily hexagonal, the unit lattice is not limited to a regular hexagon; there are also cases of non-regular hexagonal lattice arrangements. Furthermore, pentagonal, heptagonal, and other lattice arrangements are sometimes observed in the aforementioned distortions. Additionally, no distinct grain boundaries are observed near the distortions in CAAC-OS. In other words, the lattice arrangement distortion inhibits grain boundary formation. This may be because CAAC-OS can tolerate distortions caused by factors such as low oxygen atom density along the ab plane or changes in interatomic bonding distance due to metal atom substitution.

[0187] Furthermore, a crystalline structure with clearly defined grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially leading to a decrease in the transistor's on-state current and field-effect mobility. Therefore, CAAC-OS, which lacks clearly defined grain boundaries, is one of the crystalline oxides that provides an excellent crystalline structure for the semiconductor layer of the transistor. Note that a Zn-containing structure is preferred for constructing CAAC-OS. For example, In-Zn oxides and In-Ga-Zn oxides are preferred because they can further suppress grain boundary formation compared to In oxides.

[0188] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility due to grain boundaries is less likely to occur. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen defects). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Thus, oxide semiconductors containing CAAC-OS possess high heat resistance and good reliability. In addition, CAAC-OS is also stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, process flexibility can be increased.

[0189] [nc-OS] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. In other words, nc-OS possesses tiny crystallinity. Furthermore, for example, these tiny crystallinity sizes are between 1 nm and 10 nm, particularly between 1 nm and 3 nm; these tiny crystallinity sizes are referred to as nanocrystals. Additionally, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no alignment is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis on nc-OS films using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when performing electron diffraction (also known as selected area electron diffraction) on nc-OS films using an electron beam with a beam diameter larger than that of nanocrystals (e.g., larger than 50 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also known as nano-beam electron beam) is performed on nc-OS films using an electron beam whose beam diameter is close to or smaller than the size of nanocrystals (e.g., above 1 nm and below 30 nm), sometimes an electron diffraction pattern of multiple spots is observed in an annular region centered on a direct spot.

[0190] [a-like OS] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the hydrogen concentration in a-like OS films is higher than that in nc-OS and CAAC-OS films.

[0191] Structure of Oxide Semiconductors Next, the details of CAC-OS will be explained. Additionally, it will be explained that CAC-OS is related to material composition.

[0192] [CAC-OS] CAC-OS, for example, refers to a composition in which elements are non-uniformly distributed within a metal oxide, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to as mosaic or patch-like, wherein the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or approximately.

[0193] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region, forming a mosaic-like structure, with the first region distributed throughout the film (hereinafter also referred to as cloud-like). In other words, CAC-OS refers to a composite metal oxide having a structure that combines the first and second regions.

[0194] Here, each of the atomic ratios of In, Ga, and Zn, the metal elements constituting the CAC-OS in In-Ga-Zn oxide, is denoted as [In], [Ga], and [Zn]. For example, in the CAC-OS of In-Ga-Zn oxide, a first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. A second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. Alternatively, for example, a first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. A second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0195] Specifically, the first region mentioned above is a region whose main component is indium oxide or indium zinc oxide. Furthermore, the second region mentioned above is a region whose main component is gallium oxide or gallium zinc oxide. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0196] Note that sometimes the clear boundaries between the first region and the second region mentioned above are not observable.

[0197] For example, in CAC-OS of In-Ga-Zn oxide, based on the EDX surface analysis (mapping) image obtained by Energy Dispersive X-ray spectroscopy (EDX), a structure with an unevenly distributed and mixed structure of regions with In as the main component (first region) and regions with Ga as the main component (second region) can be identified.

[0198] When CAC-OS is used in transistors, the complementary effect of conductivity arising from the first region and insulation arising from the second region enables CAC-OS to possess switching functionality (the function of controlling conduction / turn-off). In other words, a part of the CAC-OS material has conductive functionality and another part has insulating functionality, while the entire material possesses semiconductor functionality. By separating the conductive and insulating functions, the individual functions can be maximized. Therefore, by using CAC-OS in transistors, high on-state current (Ion), high field-effect mobility (μ), and good switching operation can be achieved.

[0199] Oxide semiconductors possess various structures and properties. In one embodiment of the present invention, the oxide semiconductor may also include two or more of the following: amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0200] <Including oxide semiconductor transistors> Here, we will explain the case where the above-mentioned oxide semiconductor is used as a transistor.

[0201] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can be achieved.

[0202] Furthermore, it is preferable to use an oxide conductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10¹⁷ cm⁻³ or less, preferably 1×10¹⁵ cm⁻³ or less, more preferably 1×10¹³ cm⁻³ or less, further preferably 1×10¹¹ cm⁻³ or less, and even more preferably less than 1×10¹⁰ cm⁻³ and more than 1×10⁻⁹ cm⁻³. When the purpose is to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high purity nature" or "substantially high purity nature". In addition, oxide semiconductors with low carrier concentrations are sometimes referred to as "high purity nature" or "substantially high purity nature oxide semiconductors".

[0203] Because high-purity or essentially high-purity oxide semiconductor films have a low defect state density, they may also have a low trap state density.

[0204] Furthermore, the charge trapped in the trap state level of an oxide semiconductor takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical properties of transistors forming channel formation regions in oxide semiconductors with high trap state density are sometimes unstable.

[0205] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical properties of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0206] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0207] When an oxide semiconductor contains silicon or carbon, one of the elements in Group 14, a defect energy level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel forming region of the oxide semiconductor, and the concentration of silicon or carbon near the interface between the oxide semiconductor and the channel forming region (the concentration measured by secondary ion mass spectrometry) are set to 2 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁷ atoms / cm³ or less.

[0208] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, thus creating carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to have always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel-forming region of the oxide semiconductor, as measured by SIMS analysis, is set to 1 × 10¹⁸ atoms / cm³ or less, preferably 2 × 10¹⁶ atoms / cm³ or less.

[0209] When oxide semiconductors contain nitrogen, electrons are readily generated as carriers, increasing the carrier concentration and resulting in n-type characteristics. Consequently, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Alternatively, when oxide semiconductors contain nitrogen, trap levels can sometimes form. As a result, the electrical properties of the transistors can sometimes be unstable. Therefore, the nitrogen concentration in the channel-forming region of the oxide semiconductor, as measured by SIMS, is set to be below 5 × 10¹⁹ atoms / cm³, preferably below 5 × 10¹⁸ atoms / cm³, more preferably below 1 × 10¹⁸ atoms / cm³, and even more preferably below 5 × 10¹⁷ atoms / cm³.

[0210] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, thus sometimes creating oxygen vacancies. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to a metal atom, generating electrons as carriers. Therefore, transistors having an oxide semiconductor containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel-forming region of the oxide semiconductor. Specifically, in the channel-forming region of the oxide semiconductor, the hydrogen concentration measured using SIMS is set to be less than 1 × 10²⁰ atoms / cm³, preferably less than 5 × 10¹⁹ atoms / cm³, more preferably less than 1 × 10¹⁹ atoms / cm³, further preferably less than 5 × 10¹⁸ atoms / cm³, and even more preferably less than 1 × 10¹⁸ atoms / cm³.

[0211] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can be made to have stable electrical characteristics.

[0212] Other Semiconductor Materials The semiconductor materials that can be used for oxide 230 are not limited to the aforementioned metal oxides. As oxide 230, semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used. For example, it is preferable to use semiconductors of a single element such as silicon, compound semiconductors such as gallium arsenide, or layered materials used as semiconductors (also called atomic-layer materials, two-dimensional materials, etc.). In particular, it is preferable to use layered materials used as semiconductors as semiconductor materials.

[0213] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, intended for use as a semiconductor, in the channel-forming region, transistors with large on-state currents can be provided.

[0214] As layered materials, examples include graphene, silicon, and chalcogenides. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Additionally, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0215] As oxide 230, a transition metal chalcogenide, which is used as a semiconductor, is preferably used. Examples of transition metal chalcogenides that can be used as oxide 230 include molybdenum sulfide (typically MoS₂), molybdenum selenide (typically MoSe₂), molybdenum telluride (typically MoTe₂), tungsten sulfide (typically WS₂), tungsten selenide (typically WSe₂), tungsten telluride (typically WTe₂), hafnium sulfide (typically HfS₂), hafnium selenide (typically HfSe₂), zirconium sulfide (typically ZrS₂), and zirconium selenide (typically ZrSe₂).

[0216] <Structure Example of a Semiconductor Device 2> Figures 3A to 3D illustrate the structure of a semiconductor device, including a transistor 200 and a capacitor 292, which differs from the semiconductor device shown in <Structure Example 1 of Semiconductor Devices> described above. Figure 3A is a top view of this semiconductor device. Figures 3B to 3D are cross-sectional views of this semiconductor device. Here, Figure 3B is a cross-sectional view along the dashed lines A1-A2 in Figure 3A, corresponding to a cross-sectional view along the channel length direction of the transistor 200. Figure 3C is a cross-sectional view along the dashed lines A3-A4 in Figure 3A, corresponding to a cross-sectional view along the channel width direction of the transistor 200. Figure 3D is a cross-sectional view of the portion indicated by dashed lines A5-A6 in Figure 3A, corresponding to a cross-sectional view of the capacitor 292. In the top view of Figure 3A, some components are omitted for clarity.

[0217] Note that in the semiconductor devices shown in Figures 3A to 3D, components having the same function as those in the semiconductor device shown in <Structure Example 1 of Semiconductor Device> are given the same component symbols. Note that the materials constituting the semiconductor device in this section may be the materials described in detail in <Structure Example 1 of Semiconductor Device>.

[0218] In the semiconductor device shown in Figures 3A to 3D, insulators 214, 216, 222, 224, 272, 275, 280, and 282 are patterned. Furthermore, insulator 284 covers insulators 212, 214, 216, 222, 224, 272, 275, 280, and 282. In other words, insulator 284 is in contact with the top surface of insulator 282, the side surfaces of insulators 214, 216, 222, 224, 272, 275, and 280, and the top surface of insulator 214. Insulator 283 is disposed to cover insulator 284. Thus, the oxide 230, insulators 214, 216, 222, 224, 280, and 282 are separated from the outside by insulators 283, 284, 212, and 214. In other words, the transistor 200 is disposed within the area sealed by insulators 284 and 214.

[0219] For example, insulators 214, 271, 275, 282, and 284 can be formed using materials that capture and fix hydrogen. Furthermore, the same insulator as insulator 282 can be used as insulator 284. Additionally, insulators 212 and 283 can be formed using materials that suppress the diffusion of hydrogen and oxygen. Metal oxides with an amorphous structure, such as aluminum oxide, can be used as insulators 214, 271, 275, 282, and 284. Furthermore, silicon nitride can typically be used as insulators 212 and 283. In particular, using aluminum oxide or aluminum oxide with an amorphous structure as insulator 284 can sometimes more effectively capture or fix hydrogen, making it preferable. Thus, a semiconductor device including a transistor 200 with good characteristics and high reliability and a capacitor 292 can be manufactured.

[0220] With the above structure, hydrogen contained outside the sealed area can be prevented from mixing into the sealed area.

[0221] Furthermore, in Figures 3A to 3D, insulators 212 and 283 have a single-layer structure, but the present invention is not limited thereto. For example, insulators 212 and 283 may also have a stacked structure with two or more layers.

[0222] Insulator 274 covers insulator 283 and is used as an interlayer film. The dielectric constant of insulator 274 is preferably lower than that of insulator 214. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Insulator 274 is preferably formed, for example, using the same material as insulator 280.

[0223] <Methods for Manufacturing Semiconductor Devices> Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention shown in Figures 3A to 3D will be described using Figures 5A to 22D.

[0224] Figure A shows a top view. Figure B is a cross-sectional view along the dashed lines A1-A2 in Figure A, corresponding to a cross-sectional view along the channel length direction of transistor 200. Figure C is a cross-sectional view along the dashed lines A3-A4 in Figure A, corresponding to a cross-sectional view along the channel width direction of transistor 200. Figure D is a cross-sectional view along the dashed lines A5-A6 in Figure A, corresponding to a cross-sectional view of capacitor 292. Additionally, for clarity, some components are omitted in the top view of Figure A in each figure.

[0225] The insulating materials used to form insulators, the conductive materials used to form conductors, or the semiconductor materials used to form semiconductors can be appropriately deposited using sputtering, CVD, MBE, PLD, ALD, and other methods.

[0226] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used when forming insulating films, while DC sputtering is mainly used when forming conductive metallic films. Additionally, pulsed DC sputtering is mainly used when forming compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0227] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photoCVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0228] By utilizing plasma CVD, high-quality films can be obtained at lower temperatures. Furthermore, because plasma is not used in thermal CVD, damage to the workpiece is reduced. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage these components. On the other hand, since thermal CVD, which does not use plasma, does not produce this plasma damage, the yield of semiconductor devices can be improved. Additionally, since plasma damage during film formation is absent in thermal CVD, films with fewer defects can be obtained.

[0229] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to react the precursors and reactants, and PEALD (Plasma Enhanced ALD) methods that use reactants that have been excited by plasma.

[0230] Furthermore, the ALD method leverages the self-adjusting properties of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with fewer defects like pinholes, films with excellent coverage, and films formed at low temperatures. In the PEALD method, the use of plasma allows for film deposition at even lower temperatures, making it sometimes preferable. The precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. The quantitative determination of impurities can be achieved using X-ray photoelectron spectroscopy (XPS).

[0231] Unlike film deposition methods that use particles released from a target, CVD and ALD methods form films based on the reaction on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes better used in combination with other film deposition methods such as CVD, which have a faster deposition rate.

[0232] CVD or ALD methods allow control of the film composition by adjusting the source gas flow rate. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be formed by changing the source gas flow rate while forming the film. When forming a film while changing the source gas flow rate, the time required for pressure adjustment and transmission is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0233] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see Figures 5A to 5D). The insulator 212 is preferably formed using a sputtering method. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in the insulator 212 can be reduced. Note that the film formation of the insulator 212 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0234] In this embodiment, silicon nitride is formed using a silicon target as the insulator 212 in a nitrogen-containing gas atmosphere via pulsed DC sputtering. By using pulsed DC sputtering, particles generated due to arcing on the target surface can be suppressed, resulting in a more uniform thickness. Furthermore, by using pulsed voltage, the rise and fall during discharge can be more rapid compared to high-frequency voltage. This allows for more efficient power supply to the electrodes, thereby improving the sputtering rate and film quality.

[0235] By using an insulator such as silicon nitride, which does not easily allow impurities such as water and hydrogen to pass through, the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed. Furthermore, by using an insulator such as silicon nitride, which does not easily allow copper to pass through, even if a metal such as copper, which easily diffuses, is used as the conductor in the layer below the insulator 212 (not shown), the diffusion of that metal through the insulator 212 upwards can be suppressed.

[0236] Next, insulator 214 is formed on insulator 212 (see Figures 5A to 5D). Insulator 214 is preferably formed using a sputtering method. By using a sputtering method, which does not require hydrogen as the deposition gas, the hydrogen concentration in insulator 214 can be reduced. Note that the film formation of insulator 214 is not limited to sputtering; CVD, MBE, PLD, ALD, and other methods can also be appropriately used.

[0237] In this embodiment, aluminum oxide is formed using a silicon target in an oxygen-containing gas atmosphere as the insulator 214 via pulsed DC sputtering. By using pulsed DC sputtering, the thickness can be made more uniform, thereby increasing the sputtering rate and film quality.

[0238] A metal oxide with an amorphous structure, such as aluminum oxide, is preferably used as the insulator 214 because it has high hydrogen trapping and fixation performance. This allows hydrogen contained in the insulator 216 to be trapped or fixed, preventing it from diffusing into the oxide 230. In particular, using aluminum oxide or aluminum oxide with an amorphous structure as the insulator 214 can sometimes more effectively trap or fix hydrogen, making it preferable. This allows the manufacture of a transistor 200 and semiconductor devices with good properties and high reliability.

[0239] Next, insulator 216 is formed on insulator 214. Insulator 216 is preferably formed using a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in insulator 216 can be reduced. Note that the film formation of insulator 216 is not limited to sputtering; CVD, MBE, PLD, ALD, etc., can also be appropriately used.

[0240] In this embodiment, silicon oxide is formed using a silicon target in an oxygen-containing atmosphere via pulsed DC sputtering as the insulator 216. By using pulsed DC sputtering, the thickness can be made more uniform, thereby increasing the sputtering rate and film quality.

[0241] Insulators 212, 214, and 216 are preferably formed continuously without exposure to the atmosphere. For example, a multi-chamber film-forming apparatus can be used. This reduces the amount of hydrogen in the film while forming insulators 212, 214, and 216, and also reduces hydrogen ingress into the film between each film-forming process.

[0242] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or a slit. The area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. Furthermore, the insulator 214 is preferably an insulator that serves as an etch stop film when etching insulator 216 to form the groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as the insulator 214.

[0243] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus with a high-density plasma source can also be used. For example, as a dry etching apparatus with a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0244] After the opening is formed, a conductive film 205A is formed (see Figures 5A to 5D). The conductive film 205A preferably includes a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film 205A can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods.

[0245] In this embodiment, titanium nitride is formed as the conductive film 205A. By using the aforementioned metal nitride as the lower layer of the conductor 205b, oxidation of the conductor 205b, such as the insulator 216, can be suppressed. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, diffusion of that metal from the conductor 205a to the outside can be prevented.

[0246] Next, a conductive film 205B is formed (see Figures 5A to 5D). Tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used as the conductive film 205B. The conductive film can be formed using electroplating, sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, tungsten is formed as the conductive film 205B.

[0247] Next, a portion of conductive films 205A and 205B is removed by CMP (Chemical Mechanical Polishing) to expose insulator 216 (see Figures 6A to 6D). As a result, conductors 205a and 205b remain only at the opening. Alternatively, sometimes a portion of insulator 216 is removed by this CMP process.

[0248] Next, etching is performed to remove the top of the conductor 205b (see Figures 7A to 7D). As a result, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. Dry etching or wet etching can be used to etch the conductor 205b; from a microfabrication point of view, dry etching is preferable.

[0249] Next, a conductive film 205C is formed on the insulator 216, conductor 205a, and conductor 205b (see Figures 8A to 8D). Similar to the conductive film 205A, the conductive film 205C preferably includes a conductor that has the function of inhibiting oxygen permeation.

[0250] In this embodiment, titanium nitride is formed as the conductive film 205C. By using the aforementioned metal nitride as the upper layer of the conductor 205b, oxidation of the conductor 205b, such as the insulator 222, can be suppressed. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, diffusion of that metal from the conductor 205c to the outside can be prevented.

[0251] Next, a portion of the conductive film 205C is removed by CMP treatment, exposing the insulator 216 (see Figures 9A to 9D). As a result, only conductors 205a, 205b, and 205c remain at the opening. This allows the formation of a conductor 205 with a flat top surface. Furthermore, conductor 205b is surrounded by conductors 205a and 205c. Therefore, hydrogen diffusion from conductor 205b to the outside of conductors 205a and 205c is prevented, and oxygen ingress from the outside of conductors 205a and 205c, preventing oxidation of conductor 205b, is also prevented. Additionally, sometimes a portion of the insulator 216 is removed by this CMP treatment.

[0252] Next, an insulator 222 is formed on the insulator 216 and the conductor 205 (see Figures 10A to 10D). Preferably, the insulator 222 is an oxide containing one or both of aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferred as the insulator containing one or both of aluminum and hafnium. The insulator containing one or both of aluminum and hafnium provides barrier properties against oxygen, hydrogen, and water. When the insulator 222 provides barrier properties against hydrogen and water, the diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 through the insulator 222 into the inside of the transistor 200 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0253] Insulator 222 can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, hafnium oxide is formed as insulator 222 using sputtering. By using sputtering, which does not require hydrogen as the deposition gas, the hydrogen concentration in insulator 222 can be reduced.

[0254] Next, heat treatment is preferably performed. The heat treatment is carried out at a temperature of 250°C or higher and 650°C, preferably 300°C or higher and 500°C, and more preferably 320°C or higher and 450°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0255] Furthermore, the gas used in the above heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is less than 1 ppb, preferably less than 0.1 ppb, and more preferably less than 0.05 ppb. By using a highly purified gas for heat treatment, the absorption of moisture and the like by the insulator 222 can be prevented as much as possible.

[0256] In this embodiment, as a heat treatment, after the insulator 222 is formed, a treatment is performed at a temperature of 400°C for 1 hour with a nitrogen gas to oxygen gas flow ratio of 4 slm:1 slm. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. In addition, when a hafnium-containing oxide is used as the insulator 222, sometimes a portion of the insulator 222 is crystallized by performing this heat treatment. Furthermore, heat treatment can also be performed after the insulator 224 is formed, etc.

[0257] Next, insulator 224 is formed on insulator 222 (see Figures 10A to 10D). Insulator 224 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon oxide is formed as insulator 224 using sputtering. By using sputtering, which does not require hydrogen as the deposition gas, the hydrogen concentration in insulator 224 can be reduced. Since insulator 224 comes into contact with oxide 230a in subsequent processes, this reduction in hydrogen concentration is preferable.

[0258] To form an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, it may include a power supply that applies RF (Radio Frequency) to one side of the substrate. High-density plasma can generate high-density oxygen radicals, and applying RF to one side of the substrate allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heat treatment may not be necessary.

[0259] Here, an aluminum oxide film can be formed on the insulator 224, for example, by sputtering, and the aluminum oxide can be subjected to CMP treatment until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing CMP treatment, the endpoint of the CMP treatment can be easily detected. Furthermore, sometimes the thickness of the insulator 224 becomes thinner due to polishing of a portion of it during CMP treatment; however, this can be corrected by adjusting the thickness during the film formation process of the insulator 224. Planarizing and smoothing the surface of the insulator 224 can sometimes prevent a decrease in the coverage of the oxide film to be formed underneath and prevent a decrease in the yield of the semiconductor device. Moreover, it is preferable to form an aluminum oxide film on the insulator 224 by sputtering, as oxygen can be added to the insulator 224.

[0260] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see Figures 10A to 10D). Preferably, oxide films 230A and 230B are formed continuously without exposure to the atmospheric environment. By forming oxide films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide films 230A and 230B, thus keeping the area near the interface of oxide films 230A and 230B clean.

[0261] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0262] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the formed oxide film can be increased. Furthermore, when forming the above-mentioned oxide films using sputtering, a target material such as the aforementioned In-M-Zn oxide can be used, for example.

[0263] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0264] When forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor can be formed by forming the film under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Using an oxygen-excess oxide semiconductor as a transistor in the channel formation region can result in higher reliability. Note that one embodiment of the invention is not limited to this. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Using an oxygen-deficient oxide semiconductor as a transistor in the channel formation region can result in higher field-effect mobility. Furthermore, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0265] In this embodiment, an oxide film 230A is formed using an oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic number ratio) via sputtering. Additionally, an oxide film 230B is formed using an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic number ratio) via sputtering. The formation conditions and atomic number ratios of the oxide films can be appropriately selected based on the desired characteristics of oxides 230a and 230b.

[0266] Next, an oxide film 243A is formed on the oxide film 230B (see Figures 10A to 10D). The oxide film 243A can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. Preferably, the ratio of Ga atoms relative to In in the oxide film 243A is greater than the ratio of Ga atoms relative to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed using an oxide target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio] via sputtering.

[0267] Preferably, insulators 222, 224, oxide films 230A, 230B, and 243A are formed by sputtering in a manner that avoids exposure to the atmosphere. For example, a multi-chamber film deposition apparatus can be used. This reduces the amount of hydrogen in the film while forming insulators 222, 224, 230A, 230B, and 243A, and also reduces hydrogen ingress into the film between each film deposition process.

[0268] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range where polycrystalline formation does not occur in oxide films 230A, 230B, and 243A, preferably between 250°C and 650°C, and more preferably between 400°C and 600°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas. For example, when heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the proportion of oxygen gas can be set to approximately 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the released oxygen, heat treatment can be performed in an atmosphere containing 10 ppm, 1%, or 10% or more of an oxidizing gas.

[0269] Furthermore, the gas used in the above heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is less than 1 ppb, preferably less than 0.1 ppb, and more preferably less than 0.05 ppb. By using a highly purified gas for heat treatment, the absorption of moisture and other substances by oxide films 230A, 230B, and 243A can be prevented as much as possible.

[0270] In this embodiment, as a heat treatment, after treatment at 550°C for 1 hour in a nitrogen atmosphere, treatment is then continuously performed at 550°C for 1 hour in an oxygen atmosphere. This heat treatment removes impurities such as water and hydrogen from oxide films 230A, 230B, and 243A. Furthermore, this heat treatment improves the crystallinity of oxide film 230B, achieving a denser structure. This reduces the diffusion of oxygen or impurities from oxide film 230B.

[0271] Next, a conductive film 242A is formed on the oxide film 243A (see Figures 10A to 10D). The conductive film 242A can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. For example, tantalum nitride can be formed as the conductive film 242A using sputtering. Alternatively, heat treatment can be performed before forming the conductive film 242A. This heat treatment can also be performed under reduced pressure, wherein the conductive film 242A is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide films 230A, 230B, and 243A can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is set to 200°C.

[0272] Next, an insulating film 271A is formed on the conductive film 242A (see Figures 10A to 10D). The insulating film 271A can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Preferably, the insulating film 271A is an insulating film that inhibits oxygen permeation. For example, aluminum oxide or silicon nitride can be formed as the insulating film 271A by sputtering.

[0273] Next, an insulating film 273A is formed on the insulating film 271A (see Figures 10A to 10D). The insulating film 273A can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. For example, silicon nitride or silicon oxide can be formed as the insulating film 273A by sputtering.

[0274] Preferably, the conductive film 242A, insulating film 271A, and insulating film 273A are formed by sputtering in a manner that avoids exposure to the atmosphere. For example, a multi-chamber film deposition apparatus can be used. This reduces the amount of hydrogen in the films during formation and also reduces hydrogen ingress between film deposition processes. Furthermore, when a hard mask is formed on the insulating film 273A, the film serving as the hard mask can also be formed continuously in a manner that avoids exposure to the atmosphere.

[0275] Next, oxide films 230A, 230B, 243A, 242A, 271A, and 273A are processed into island shapes using photolithography to form oxides 230a, 230b, 243B, 242B, 271B, and 273B (see Figures 11A to 11D). This process can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, oxide films 230A, 230B, 243A, 242A, 271A, and 271B can be formed under different conditions. In this process, the thickness of the region of insulator 224 that does not overlap with oxide 230a may sometimes become thinner. Alternatively, in this process, insulator 224 can be processed into island shapes in a manner that overlaps with oxide 230a.

[0276] Note that in photolithography, the photoresist is first exposed using a mask. Next, a developing solution is used to remove or leave the exposed area, forming a photoresist mask. Then, the photoresist mask is etched to shape the conductor, semiconductor, or insulator into the desired form. For example, the photoresist mask can be formed by exposing the photoresist to KrF excimer laser, ArF excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where the space between the substrate and the projection lens is filled with liquid (e.g., water). Electron beams or ion beams can also be used instead of the aforementioned light. Note that when using electron beams or ion beams, a mask is not required. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0277] Furthermore, a hard mask made of an insulator or conductor can also be used under the photoresist mask. When using a hard mask, an insulating film or conductive film serving as the hard mask material can be formed on the conductive film 242A, and a photoresist mask can be formed thereon. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film 242A, etc., can be performed either after removing the photoresist mask or without removing the photoresist mask. In the latter case, the photoresist mask may disappear during etching. The hard mask can be removed by etching after etching the conductive film 242A, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask. In this embodiment, insulating layers 271B and 273B are used as hard masks. On the other hand, if insulating layer 271B is sufficiently used as a hard mask, it is not necessary to provide insulating layer 273B. In this case, insulating film 273A is not required. In addition, when the insulating layer 271B is used as a hard mask without setting the insulating layer 273B, it is preferable to appropriately adjust the film thickness of the insulating layer 271B to suppress the disappearance of the insulating layer 271B when etching the conductive film 242A, etc.

[0278] Here, insulating layers 271B and 273B are used as masks for forming the conductive layer 242B. As shown in Figures 11B to 11D, the conductive layer 242B does not have a curved surface between its side and top surfaces. Therefore, the ends where the side and top surfaces of conductors 242a and 242b intersect, as shown in Figure 3B, become angled. When the ends where the side and top surfaces of conductor 242 intersect are angled, the cross-sectional area of ​​conductor 242 increases compared to the case where the ends have curved surfaces. This reduces the resistance of conductor 242, thereby increasing the on-state current of transistor 200.

[0279] Furthermore, oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B are formed such that at least a portion of them overlaps with the conductor 205. Additionally, the side surfaces of oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B are preferably substantially perpendicular to the top surface of the insulator 222. By making the side surfaces of oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B substantially perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure can be adopted in which the side surfaces of oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B form a lower angle with the top surface of insulator 222. In this case, the angle formed by the side surfaces of oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B with the top surface of insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting this shape, the coverage of insulators 272, 275, etc., in the following process can be improved, and defects such as voids can be reduced.

[0280] Furthermore, byproducts generated during the aforementioned etching process sometimes form in layers on the sides of oxides 230a, 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B. In this case, the layered byproducts form between oxides 230a, 230b, 243, conductor 242, insulator 271, and insulator 273 and insulator 272. Similarly, sometimes the layered byproducts form on insulator 224. If insulator 272 is formed with these layered byproducts on insulator 224, these layered byproducts hinder the addition of oxygen to insulator 224. Therefore, it is preferable to remove the layered byproducts that contact the top surface of insulator 224.

[0281] Next, an insulating film 272A is formed on insulator 224, oxide 230a, oxide 230b, oxide layer 243B, conductive layer 242B, insulating layer 271B, and insulating layer 273B (see Figures 12A to 12D). The insulating film 272A can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. In this embodiment, aluminum oxide is formed as the insulating film 272A using sputtering.

[0282] The insulating film 272A is preferably formed using a sputtering method. By forming the insulating film 272A using a sputtering method, oxygen can be added to the insulator 224 and the insulating layer 273B. At this time, the insulating layer 271B is disposed in contact with the top surface of the conductive layer 242B, so the oxidation of the conductive layer 242B can be suppressed.

[0283] Next, an insulating film 275A is formed on the insulating film 272A (see Figures 12A to 12D). The insulating film 275A can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon nitride is formed as the insulating film 275A using sputtering.

[0284] Next, an insulating film, which becomes insulator 280, is formed on insulating film 275A. This insulating film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, silicon oxide can be formed as the insulating film by sputtering. By forming the insulating film into insulator 280 using sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require hydrogen as the deposition gas, the hydrogen concentration in insulator 280 can be reduced. Alternatively, heat treatment can be performed before forming the insulating film. This heat treatment can also be performed under reduced pressure, wherein the insulating film is continuously formed without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of insulating film 275A can be removed, and the moisture and hydrogen concentrations in oxide 230a, oxide 230b, oxide layer 243B, and insulator 224 can be reduced. The heat treatment can be performed under the conditions described above.

[0285] Next, by performing CMP treatment on the insulating film that becomes insulator 280, an insulator 280 with a flat top surface is formed (see Figures 12A to 12D). Alternatively, silicon nitride can be deposited on insulator 280, for example, by sputtering, and CMP treatment can be performed until the silicon nitride reaches insulator 280.

[0286] Next, a portion of insulator 280, a portion of insulating film 275A, a portion of insulating film 272A, a portion of insulating layer 273B, a portion of insulating layer 271B, a portion of conductive layer 242B, a portion of oxide layer 243B, and a portion of oxide 230b are processed to form an opening reaching oxide 230b. This opening is preferably formed in a manner that overlaps with conductor 205. By forming this opening, insulators 275a, 275b, 272a, 272b, 273a, 273b, 271a, 271b, conductors 242a, 242b, oxide 243a, and oxide 243b are formed (see Figures 13A to 13D).

[0287] Note that the top of oxide 230b is removed when forming the opening described above. By removing a portion of oxide 230b, a groove is formed within oxide 230b. Depending on the depth of the groove, it can be formed either during the opening formation process or in a different process.

[0288] Alternatively, a portion of insulator 280, a portion of insulating film 275A, a portion of insulating film 272A, a portion of insulating layer 273B, a portion of insulating layer 271B, a portion of conductive layer 242B, a portion of oxide layer 243B, and a portion of oxide 230b can be processed by dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, this processing can be performed under different conditions. For example, a portion of insulator 280 can be processed by dry etching, a portion of insulating film 275A, a portion of insulating film 272A, a portion of insulating layer 273B, and a portion of insulating layer 271B can be processed by wet etching, and a portion of oxide layer 243B, a portion of conductive layer 242B, and a portion of oxide 230b can be processed by dry etching. Note that the processing of a portion of oxide layer 243B and a portion of conductive layer 242B can be performed under different conditions than the processing of a portion of oxide 230b.

[0289] Here, it is preferable to remove impurities adhering to the surfaces of oxides 230a, oxides 230b, etc., or those diffused into their interiors. Furthermore, it is preferable to remove the damaged areas formed on the surface of oxide 230b by the aforementioned dry etching method. Examples of such impurities include those originating from the following components: components contained in insulator 280, a portion of insulating film 275A, a portion of insulating film 272A, a portion of insulating layer 273B, a portion of insulating layer 271B, and conductive layer 242B; components contained in the components of the device used to form the aforementioned opening; components contained in the gas or liquid used for etching; etc. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0290] In particular, impurities such as aluminum or silicon hinder the CAAC-OS formation of oxide 230b. Therefore, it is preferable to reduce or remove impurity elements such as aluminum or silicon that hinder CAAC-OS formation. For example, the concentration of aluminum atoms in and around oxide 230b can be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, further preferably 1.0 atomic% or less, and especially preferably less than 0.3 atomic%.

[0291] Sometimes, the regions of metal oxides that are hindered from CAAC-OS transformation by impurities such as aluminum or silicon, thus becoming a-like OS (amorphous-like oxide semiconductor), are called non-CAAC regions. In non-CAAC regions, the density of the crystal structure decreases, resulting in a large amount of V OH, and the transistor is prone to becoming normally on. Therefore, it is preferable to reduce or remove the non-CAAC regions in oxide 230b.

[0292] In contrast, oxide 230b preferably has a layered CAAC structure. In particular, it is preferable that the lower end of the drain of oxide 230b also has a CAAC structure. Here, in transistor 200, conductor 242a or conductor 242b and its vicinity are used as drains. In other words, oxide 230b near the lower end of conductor 242a (conductor 242b) preferably has a CAAC structure. Thus, by removing the damaged area of ​​oxide 230b in the drain end portion that significantly affects the drain withstand voltage and giving it a CAAC structure, variations in the electrical characteristics of transistor 200 can be further suppressed. Furthermore, the reliability of transistor 200 can be further improved.

[0293] To remove the aforementioned impurities, a washing process can be performed. Washing methods include wet washing using a washing liquid, plasma treatment using plasma, and heat treatment, and combinations thereof may also be appropriate. Note that this washing process may sometimes deepen the tank area.

[0294] As a wet cleaning method, washing can be performed using an aqueous solution prepared by diluting ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, or using pure water or carbonated water. Alternatively, ultrasonic cleaning can be performed using the aforementioned aqueous solution, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be used as appropriate.

[0295] Note that in this specification, etc., an aqueous solution of commercially available hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of commercially available ammonia diluted with pure water is sometimes referred to as dilute ammonia. Furthermore, the concentration, temperature, etc., of this aqueous solution can be appropriately adjusted according to the impurities to be removed and the structure of the semiconductor device being cleaned. The ammonia concentration of the dilute ammonia is set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. Similarly, the hydrogen fluoride concentration of the dilute hydrofluoric acid is set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0296] Furthermore, for ultrasonic cleaning, a frequency of 200kHz or higher, preferably 900kHz or higher, is preferred. By using this frequency, damage to oxides such as 230b can be reduced.

[0297] In addition, the above washing process can be performed multiple times, or the washing solution can be changed for each washing process. For example, the first washing process can be performed using dilute hydrofluoric acid or dilute ammonia, and the second washing process can be performed using pure water or carbonated water.

[0298] As a washing process described above, in this embodiment, a wet wash is performed using dilute hydrofluoric acid, followed by a wet wash with pure water or carbonated water. This washing process removes impurities adhering to the surface of oxides 230a, 230b, etc., or those diffused into their interior. Furthermore, it improves the crystallinity of oxide 230b.

[0299] By performing the above-mentioned dry etching process or the above-mentioned cleaning process, the thickness of the insulator 224 that overlaps the opening but does not overlap the region of oxide 230b is sometimes thinner than the thickness of the insulator 224 that overlaps the region of oxide 230b.

[0300] Heat treatment can be performed after the etching or washing described above. The heat treatment should be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment should be performed in a nitrogen atmosphere or an inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to oxides 230a and 230b, thereby reducing oxygen vacancies (VO). Furthermore, the crystallinity of oxide 230b can be improved by performing the above heat treatment. The heat treatment can also be performed under reduced pressure. Alternatively, heat treatment can be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0301] Next, an insulating film 250A (insulating film 250Aa and insulating film 250Ab) is formed (see Figures 14A to 14D). Heat treatment can be performed before forming the insulating film 250Aa, or the heat treatment can be performed under reduced pressure to continuously form the insulating film 250Aa without exposure to the atmosphere. Furthermore, the heat treatment is preferably performed in an oxygen-containing atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in oxides 230a and 230b can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0302] The insulating film 250Aa can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Preferably, the insulating film 250Aa is formed using a film-forming method that reduces or removes hydrogen atoms. This reduces the hydrogen concentration of the insulating film 250Aa. Since the insulating film 250Aa becomes the insulator 250a in contact with the oxide 230b in subsequent processes, this reduction in hydrogen concentration is preferable.

[0303] Furthermore, the insulating film 250Aa is preferably formed using the ALD method. The insulator 250, which serves as the gate insulating film of the miniaturized transistor 200, needs to be very thin (e.g., 5 nm or more and about 30 nm or less) and have minimal inhomogeneity. The ALD method is a film-forming method that alternately introduces precursors and reactants (oxidants). Since the film thickness can be adjusted according to the number of cycles, the ALD method allows for precise thickness control. Therefore, the necessary precision for the gate insulating film of the miniaturized transistor 200 can be achieved. Additionally, as shown in Figures 14B and 14C, the insulating film 250Aa needs to be formed with high coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Since each atomic layer can be deposited on the bottom and side surfaces of the opening, the insulating film 250Aa can be formed with high coverage over the opening.

[0304] Furthermore, for example, when forming the insulating film 250Aa using the PECVD method, the hydrogen-containing deposition gas is decomposed in the plasma, generating a large number of hydrogen free radicals. During the reduction reaction of these hydrogen free radicals, oxygen in the oxide 230b is extracted to form VOH, increasing the hydrogen concentration in the oxide 230b. However, when forming the insulating film 250Aa using the ALD method, the generation of hydrogen free radicals can be suppressed during both the introduction of the precursor and the introduction of the reactants. Therefore, by using the ALD method to form the insulating film 250Aa, the increase in the hydrogen concentration in the oxide 230b can be prevented.

[0305] Note that, preferably, the insulating film 250Aa is formed using an insulator that releases oxygen upon heating, and the insulating film 250Ab is formed using an insulator that inhibits oxygen diffusion. By employing this structure, the diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen contained in the insulator 250a can be suppressed.

[0306] Specifically, as the insulating film 250Ab, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or metal oxides suitable for use in oxide 230, can be used. In particular, it is preferred to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0307] In this embodiment, silicon oxide is formed using the PEALD method as the insulating film 250Aa, and hafnium oxide is formed using the thermal ALD method as the insulating film 250Ab.

[0308] Next, microwave treatment is performed in an oxygen-containing atmosphere (see Figures 14A to 14D). Here, the dashed lines in Figures 14B to 14D represent high-frequency oxygen plasmas or oxygen free radicals, such as microwaves or RF. Microwave treatment is preferably performed using a microwave processing apparatus that includes a power supply for generating high-density plasma using microwaves. Alternatively, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. By using high-density plasma, high-density oxygen free radicals can be generated. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230b. Preferably, the microwave treatment is performed under reduced pressure, with a pressure of 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O₂ / O₂+Ar) is 50% or less, preferably 10% to 30% or less. In addition, the processing temperature should be below 750°C, preferably below 500°C, for example, around 400°C. Alternatively, heat treatment can be performed continuously after oxygen plasma treatment without exposure to external air.

[0309] As shown in Figures 14B to 14D, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas plasma can be plasmaized using microwaves or high frequencies such as RF, and this oxygen plasma can act on the region between conductors 242a and 242b of oxide 230b. At this time, microwaves or high frequencies such as RF can also be used to irradiate region 230bc as shown in Figure 2. In other words, the high-frequency oxygen plasma can act in region 230bc. Through the action of plasma, microwaves, etc., the V OH in region 230bc can be separated, removing hydrogen H from region 230bc. In other words, the reaction "V OH→H+VO" occurs in region 230bc, reducing the hydrogen concentration contained in region 230bc. Therefore, oxygen vacancies and V OH in region 230bc can be reduced, thereby lowering the carrier concentration. Furthermore, by supplying oxygen free radicals generated in the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in region 230bc, the oxygen vacancies in region 230bc can be further reduced, thereby reducing the carrier concentration.

[0310] On the other hand, conductors 242a and 242b are provided in regions 230ba and 230bb as shown in Figure 2. As shown in Figures 14B, 14C, and 14D, conductors 242a and 242b shield regions 230ba and 230bb from the effects of microwaves or RF, high-frequency oxygen, plasma, etc., and therefore do not act on regions 230ba and 230bb. Thus, the decrease in VOH and excessive oxygen supply in regions 230ba and 230bb due to microwave treatment are prevented, thus preventing a decrease in carrier concentration.

[0311] As described above, region 230bc of the oxide semiconductor can be selectively degraded by removing oxygen vacancies and V OH groups, thereby making region 230bc i-type or substantially i-type. Furthermore, excessive oxygen supply to regions 230ba and 230bb, which are used as source or drain regions, can be suppressed, thus maintaining n-type characteristics. Therefore, variations in the electrical properties of the transistor 200 can be suppressed, thereby suppressing non-uniformity in the electrical properties of the transistor 200 within the substrate surface.

[0312] Therefore, a semiconductor device with small transistor characteristic non-uniformity can be provided. Furthermore, a semiconductor device with good reliability can be provided. In addition, a semiconductor device with good electrical characteristics can be provided.

[0313] In the process shown in Figures 14A to 14D, microwave processing is performed after the formation of the insulating film 250Ab, but the present invention is not limited thereto. For example, microwave processing can be performed either after the formation of the insulating film 250Aa, before the formation of the insulating film 250Aa, both before and after the formation of the insulating film 250Ab, or both after and after the formation of the insulating film 250Aa.

[0314] Furthermore, when the insulating film 250A has the above-mentioned two-layer structure, microwave treatment is performed first, followed by the formation of silicon oxide of the insulating film 250Aa by the PEALD method, and then the formation of hafnium oxide of the insulating film 250Ab by the thermal ALD method. Here, it is preferable that the microwave treatment, the PEALD film formation of silicon oxide, and the thermal ALD film formation of hafnium oxide are performed continuously without exposure to the atmosphere. For example, a multi-chamber processing apparatus can be used. Alternatively, plasma-excited reactant (oxidant) treatment using a PEALD apparatus can be used instead of the microwave treatment described above. Here, oxygen gas can be used as the reactant (oxidant).

[0315] Alternatively, heat treatment can be performed under reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the insulating film 250A, oxide 230b, and oxide 230a. Additionally, some hydrogen may be attracted by the conductors 242 (conductors 242a and 242b). Furthermore, the heat treatment step can be repeated under reduced pressure after microwave treatment. Repeated heat treatment further efficiently removes hydrogen from the insulating film 250A, oxide 230b, and oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0316] Furthermore, by altering the film quality of the insulating film 250A through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This suppresses the diffusion of hydrogen, water, impurities, etc., through the insulator 250 to oxides 230b, oxides 230a, etc., caused by post-processing such as film formation or heat treatment of the conductive film that becomes the conductor 260.

[0317] Next, a conductive film becoming conductor 260a and a conductive film becoming conductor 260b are formed sequentially. The conductive films becoming conductor 260a and conductor 260b can be formed by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, the conductive film becoming conductor 260a is formed using ALD, and the conductive film becoming conductor 260b is formed using CVD.

[0318] Next, the insulating film 250A, the conductive film that becomes conductor 260a, and the conductive film that becomes conductor 260b are polished using CMP processing until the insulator 280 is exposed, thereby forming the insulator 250 (insulator 250a and insulator 250b) and the conductor 260 (conductor 260a and conductor 260b) (see Figures 15A to 15D). Thus, the insulator 250 is arranged to cover the opening reaching the oxide 230b and the inner wall (side wall and bottom surface) of the groove portion of the oxide 230b. Furthermore, the conductor 260 is arranged across the insulator 250 to fill the aforementioned opening and groove portion.

[0319] Next, a portion of insulator 280, a portion of insulator 275b, a portion of insulator 272b, a portion of insulator 273b, and a portion of insulator 271b are processed to form an opening reaching conductor 242b (see Figures 16A to 16D). The portions of insulator 280, 275b, 272b, 273b, and 271b can be processed by dry etching or wet etching. Dry etching is suitable for micro-machining. Furthermore, the processing can be performed under different conditions. For example, a portion of insulator 280 can be processed by dry etching, and a portion of insulator 275b, 272b, 273b, and 271b can be processed by wet etching.

[0320] Next, an insulating film 293A is formed (see Figures 17A to 17D). The insulating film 293A can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. Examples of insulating films 293A include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxynitride, hafnium oxynitride, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. Furthermore, these films can be stacked as the insulating film 293A. In this embodiment, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked is used as the insulating film 293A.

[0321] Next, a conductive film 294A is formed (see Figures 17A to 17D). The conductive film 294A can be formed by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, the lower layer of the conductive film 294A is formed using the ALD method, and the upper layer of the conductive film 294A is formed using the CVD method.

[0322] Next, the insulating film 293A and the conductive film 294A are polished using CMP until the insulator 280 is exposed, thereby forming the insulator 293 and the conductor 294 (see Figures 18A to 18D). Thus, the insulator 293 is positioned to cover the inner wall (side wall and bottom surface) of the groove reaching the opening of the conductor 242. Furthermore, the conductor 294 is positioned across the insulator 293 to fill the opening and the groove.

[0323] Next, heat treatment can be performed under the same conditions as described above. In this embodiment, the treatment is carried out at 400°C for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250, 293, and 280. Furthermore, after the above heat treatment, insulator 282 can be continuously formed without exposure to the atmosphere.

[0324] Next, insulator 282 is formed on insulator 250, conductor 260, insulator 293, conductor 294, and insulator 280 (see Figures 19A to 19D). Insulator 282 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. Sputtering is preferred for forming insulator 282. By using sputtering, which does not require hydrogen as a deposition gas, the hydrogen concentration in insulator 282 can be reduced. Furthermore, by forming insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to insulator 280 during film formation. This allows insulator 280 to contain excess oxygen. Preferably, insulator 282 is formed while the substrate is heated.

[0325] In this embodiment, aluminum oxide is formed using an aluminum target in an oxygen-containing gas atmosphere via pulsed DC sputtering, serving as the insulator 282. By using pulsed DC sputtering, the thickness can be made more uniform, thereby improving the sputtering rate and film quality.

[0326] Next, a portion of insulator 282, a portion of insulator 280, a portion of insulator 275, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, and a portion of insulator 216 are processed to form an opening reaching insulator 214 (see Figures 20A to 20D). This opening is sometimes formed around transistor 200 and capacitor 292. Alternatively, this opening is sometimes formed around multiple transistors 200 and multiple capacitors 292. Therefore, in this opening, a portion of the side surface of insulator 282, a portion of the side surface of insulator 280, a portion of the side surface of insulator 275, a portion of the side surface of insulator 272, a portion of the side surface of insulator 224, a portion of the side surface of insulator 222, and a portion of the side surface of insulator 216 are exposed.

[0327] A portion of insulator 282, a portion of insulator 280, a portion of insulator 275, a portion of insulator 272, a portion of insulator 224, a portion of insulator 222, and a portion of insulator 216 can be processed using either dry etching or wet etching. Dry etching is suitable for micro-machining. Furthermore, this processing can be performed under different conditions. Additionally, during this process, the thickness of the region in insulator 214 that overlaps with the aforementioned opening may sometimes be reduced.

[0328] Next, insulator 284 is formed by covering insulators 282, 280, 275, 272, 224, 222, and 216 (see Figures 21B to 21D). Preferably, insulator 284 is formed under the same conditions as insulator 282. For example, insulator 284 can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods.

[0329] Specifically, the insulator 284 is preferably formed by sputtering, for example, by forming an aluminum oxide film. By forming the insulator 284 in an oxygen-containing atmosphere using sputtering, oxygen can be added to the insulator 280 during film formation. In this case, it is preferable to form the insulator 284 while heating the substrate. In addition, since the insulator 282 is formed in contact with the top surface of the conductor 260 and the top surface of the conductor 294, the absorption of oxygen contained in the insulator 280 by the conductors 260 and 294 can be suppressed during the film formation process of the insulator 284. As shown in Figures 21B to 21D, the insulator 284 is in contact with the insulator 214 at the bottom surface of the aforementioned opening. That is, the top and side surfaces of the transistor 200 and the capacitor 292 are surrounded by the insulator 284, while the bottom surface is surrounded by the insulator 214.

[0330] Next, insulator 283 is formed on insulator 284 (see Figures 21B to 21D). Insulator 283 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. Alternatively, insulator 283 can have a multilayer structure. For example, silicon nitride can be formed by sputtering, and then silicon nitride can be formed on top of that silicon nitride using CVD. As shown in Figures 21B to 21D, insulator 283 is a structure surrounding insulator 284. Thus, by surrounding transistor 200 and capacitor 292 with highly barrier insulators 283, 284, and 214, moisture and hydrogen can be prevented from entering from the outside.

[0331] Next, an insulating film, becoming insulator 274, is formed on insulator 284. This insulating film can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. For example, silicon oxide is preferably formed using CVD. Furthermore, the insulating film is preferably formed using the aforementioned film-forming method that uses a gas with reduced or removed hydrogen atoms. Thus, by using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulating film can be reduced.

[0332] Next, by performing CMP treatment on the insulating film that becomes insulator 274, an insulator 274 with a flat top surface is formed (see Figures 22B to 22D).

[0333] Next, heat treatment can be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. As shown in FIG2, this heat treatment allows the oxygen added during the formation of insulator 282 to diffuse into insulator 280 and insulator 250 and be selectively supplied to the channel formation region of oxide 230. In addition, this heat treatment is not limited to being performed after the formation of insulator 274, but can also be performed after the formation of insulator 282, after the formation of insulator 284, etc.

[0334] Next, openings leading to conductor 242 are formed in insulators 271a, 273a, 272a, 275a, 280, 282, 284, 283, and 274, and openings leading to conductor 294 are formed in insulators 282, 284, 283, and 274 (see Figures 22A, 22B, and 22D). Photolithography can be used to form these openings. Note that in Figure 22A, the opening is circular when viewed from above, but it is not limited to this. For example, when viewed from above, the opening may also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a shape with rounded corners.

[0335] Next, an insulating film is formed to become insulator 241, and the insulating film is anisotropically etched to form insulator 241 (see Figures 22A, 22B, and 22D). The insulating film to become insulator 241 can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods. As the insulating film to become insulator 241, it is preferable to use an insulating film that has the function of inhibiting oxygen permeation. For example, it is preferable to form aluminum oxide by ALD. Alternatively, it is preferable to form silicon nitride by PEALD. Silicon nitride has high hydrogen barrier properties, so it is preferable.

[0336] Furthermore, anisotropic etching of the insulating film, which serves as insulator 241, can be performed, for example, by dry etching. By providing insulator 241 on the sidewall of the opening, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed subsequently can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0337] Next, conductive films 240a and 240b are formed. Preferably, the conductive films 240a and 240b are multilayer structures containing conductive materials that suppress the permeation of impurities such as water and hydrogen. For example, multilayers of tantalum nitride, titanium nitride, etc., with tungsten, molybdenum, copper, etc., can be used. The conductive film 240a can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0338] Next, by performing a CMP process, a portion of the conductive film that forms conductors 240a and 240b is removed, exposing the top surface of insulator 274. As a result, the conductive film remains only in the opening, thereby forming conductors 240a and 240b with flat top surfaces (see Figures 22A, 22B, and 22D). Note that sometimes a portion of the top surface of insulator 274 is removed due to this CMP process.

[0339] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed using sputtering, CVD, MBE, PLD, ALD and other methods.

[0340] Next, the conductive film that becomes the conductor 246 is processed by photolithography to form conductor 246a, which is in contact with the top surface of conductor 240a, and conductor 246b, which is in contact with the top surface of conductor 240b. At this time, a portion of the insulator 274 in the area where conductor 246a and conductor 246b do not overlap with insulator 274 is sometimes removed (Figs. 3A, 3B, and 3D).

[0341] Next, an insulator 286 is formed on the conductor 246 and the insulator 274 (see Figures 3B to 3D). The insulator 286 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. Furthermore, the insulator 286 can also have a multilayer structure. For example, silicon nitride can be formed by sputtering, and then silicon nitride can be formed on that silicon nitride using CVD.

[0342] The above process can be used to manufacture a semiconductor device including the transistor 200 and capacitor 292 shown in Figures 3A to 3D.

[0343] Microwave Processing Device The following describes a microwave processing apparatus that can be used in the manufacturing method of the above-described semiconductor device.

[0344] First, the structure of a manufacturing apparatus with low impurity contamination during the manufacturing of semiconductor devices will be described with reference to Figures 23, 24 and 25.

[0345] Figure 23 schematically shows a top view of a monolithic mathematical multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes: an atmospheric-side substrate supply chamber 2701 having a cassette port 2761 for receiving substrates and an alignment port 2762 for aligning substrates; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a load locking chamber 2703a for loading substrates and switching the pressure inside the chamber from atmospheric pressure to depressurization or from depressurization to atmospheric pressure; an unloading locking chamber 2703b for unloading substrates and switching the pressure inside the chamber from depressurization to atmospheric pressure or from atmospheric pressure to depressurization; a transfer chamber 2704 for transferring substrates in a vacuum; and processing chambers 2706a, 2706b, 2706c, and 2706d.

[0346] In addition, the atmospheric side substrate transfer chamber 2702 is connected to the load locking chamber 2703a and the unloading locking chamber 2703b, the load locking chamber 2703a and the unloading locking chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the processing chambers 2706a, 2706b, 2706c and 2706d.

[0347] A gate valve GV is installed at the connection between the chambers, thereby allowing each chamber, except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transfer chamber 2702, to be independently maintained in a vacuum state. A transfer robot 2763a is installed in the atmospheric substrate transfer chamber 2702, and a transfer robot 2763b is installed in the transfer chamber 2704. The substrates can be transferred in the manufacturing apparatus 2700 using the transfer robots 2763a and 2763b.

[0348] The back pressure (total pressure) of the transfer chamber 2704 and each processing chamber is, for example, 1×10⁻⁴ Pa or less, preferably 3×10⁻⁵ Pa or less, and even more preferably 1×10⁻⁵ Pa or less. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with a mass charge ratio (m / z) of 18 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less. Furthermore, the partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with an m / z of 28 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and each processing chamber with an m / z of 44 is, for example, 3×10⁻⁵ Pa or less, preferably 1×10⁻⁵ Pa or less, and even more preferably 3×10⁻⁶ Pa or less.

[0349] The total and partial pressures in transfer chamber 2704 and each processing chamber can be measured using a mass analyzer. For example, a four-pole mass analyzer (also known as a Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0350] Furthermore, the transfer chamber 2704 and each processing chamber preferably have a structure with minimal external or internal leakage. For example, the leakage rate of the transfer chamber 2704 and each processing chamber is 3×10⁻⁶ Pa·m³ / s or less, preferably 1×10⁻⁶ Pa·m³ / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 18 is set to 1×10⁻⁷ Pa·m³ / s or less, preferably 3×10⁻⁸ Pa·m³ / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 28 is set to 1×10⁻⁵ Pa·m³ / s or less, preferably 1×10⁻⁶ Pa·m³ / s or less. Additionally, for example, the leakage rate of gas molecules (atoms) with m / z of 44 is set to 3×10⁻⁶ Pa·m³ / s or less, preferably 1×10⁻⁶ Pa·m³ / s or less.

[0351] The leakage rate can be calculated based on the total pressure and partial pressure measured using the aforementioned mass analyzer. The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system due to small holes or poor sealing. Internal leakage originates from leaks in valves or other baffles within the vacuum system, or from released gas from internal components. To keep the leakage rate below the aforementioned values, measures need to be taken to address both external and internal leakage.

[0352] For example, it is preferable to use metal gaskets to seal the opening and closing parts of the transfer chamber 2704 and each processing chamber. The metal gaskets are preferably made of metal coated with iron fluoride, alumina, or chromium oxide. Metal gaskets have a higher tightness than O-rings, thus reducing external leakage. By using passivated metals such as iron fluoride, alumina, or chromium oxide, the release of gases containing impurities from the metal gaskets can be suppressed, thereby reducing internal leakage.

[0353] As components constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few impurities and release gases, are used. Alternatively, the aforementioned components can be coated with alloys containing iron, chromium, and nickel. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the components through polishing or other methods to decrease the surface area, the release of gases can be reduced.

[0354] Alternatively, ferric fluoride, alumina, chromium oxide, etc., can be used to cover the components of the manufacturing apparatus 2700.

[0355] The components of the manufacturing apparatus 2700 are preferably made of metal as much as possible. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, the surface of the viewing window is preferably covered with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0356] Although the deposits present in the transfer chamber 2704 and each processing chamber adhere to the inner walls and do not affect the pressure of the transfer chamber 2704 and each processing chamber, these deposits become the cause of gas release during venting of the transfer chamber 2704 and each processing chamber. Therefore, although the leakage rate is not related to the venting rate, it is very important to use a pump with high venting capacity to remove the deposits present in the transfer chamber 2704 and each processing chamber as much as possible and to vent them in advance. To promote the removal of deposits, the transfer chamber 2704 and each processing chamber can also be baked. By baking, the removal rate of adsorbents can be increased by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by introducing inert gas into the transfer chamber 2704 and each processing chamber while removing deposits, the removal rate of substances such as water that are not easily removed by venting alone can be further increased. In addition, by heating the introduced inert gas at a temperature similar to the baking temperature, the removal rate of adsorbents can be further increased. Here, rare gas is preferred as the inert gas.

[0357] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each processing chamber by introducing heated rare gases or oxygen, and then exhaust the air from the transfer chamber 2704 and each processing chamber again after a certain period of time. The introduction of heated gas can cause deposits in the transfer chamber 2704 and each processing chamber to detach, thereby reducing impurities present in the transfer chamber 2704 and each processing chamber. Effectively, this process should be repeated more than twice and less than 30 times, preferably more than five times and less than 15 times. Specifically, the pressure in the transfer chamber 2704 and each processing chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, by introducing an inert gas or oxygen at a temperature of 40°C or higher and 400°C or less, preferably 50°C or higher and 200°C or less, and the pressure is maintained for a period of 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. Then, the transfer chamber 2704 and each processing chamber are vented for 5 minutes or more and 300 minutes or less, preferably 10 minutes or more and 120 minutes or less.

[0358] Next, processing chambers 2706b and 2706c will be described using the cross-sectional schematic diagram shown in Figure 24.

[0359] Processing chambers 2706b and 2706c are, for example, processing chambers capable of performing microwave processing on the object being processed. Note that the only difference between processing chambers 2706b and 2706c is the atmosphere during microwave processing. Since the other structures of processing chambers 2706b and 2706c are the same, they will be described together below.

[0360] Processing chambers 2706b and 2706c include a slotted antenna plate 2808, a dielectric plate 2809, a substrate support 2812, and an exhaust port 2819. Additionally, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided externally to processing chambers 2706b and 2706c.

[0361] A high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slotted antenna plate 2808 via a waveguide 2807. The slotted antenna plate 2808 is grounded in contact with a dielectric plate 2809. Furthermore, a gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is introduced into processing chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, waveguide 2807, and dielectric plate 2809. Additionally, a vacuum pump 2817 functions to discharge gas from processing chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. Finally, a high-frequency power supply 2816 is connected to a substrate support 2812 via a matching adapter 2815.

[0362] The substrate holder 2812 is capable of holding the substrate 2811. For example, the substrate holder 2812 has the function of electrostatic chuck or mechanical chuck for holding the substrate 2811. In addition, the substrate holder 2812 has the function of electrodes that are powered by a high-frequency power supply 2816. Furthermore, the substrate holder 2812 includes a heating mechanism 2813 inside and has the function of heating the substrate 2811.

[0363] As the vacuum pump 2817, various types of pumps can be used, such as drying pumps, mechanical booster pumps, ion pumps, titanium sublimation pumps, cryogenic pumps, or turbomolecular pumps. In addition to the vacuum pump 2817, a cryogenic cold trap can also be used. Using both a cryogenic pump and a cryogenic cold trap allows for efficient water removal, which is particularly advantageous.

[0364] As the heating mechanism 2813, a heating mechanism that uses a resistance heating element or the like for heating can be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a gas to be heated can also be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA uses a high-temperature gas for heat treatment. An inert gas is used as the gas.

[0365] Additionally, the gas supply source 2801 can be connected to the purifier via a mass flow controller. Preferably, the gas used has a dew point below -80°C, and more preferably below -100°C. For example, oxygen gas, nitrogen gas, and rare gases (such as argon) can be used.

[0366] For example, silicon oxide (quartz), aluminum oxide, or yttrium oxide can be used as the dielectric substrate 2809. Alternatively, other protective layers can be further formed on the surface of the dielectric substrate 2809. These protective layers can be made of materials such as magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric substrate 2809 is exposed to the particularly high-density region of the high-density plasma 2810 (described later), damage can be mitigated by providing a protective layer. As a result, the increase of particles during processing can be suppressed.

[0367] The high-frequency generator 2803 has the function of generating microwaves, for example, at frequencies above 0.3 GHz and below 3.0 GHz, above 0.7 GHz and below 1.1 GHz, or above 2.2 GHz and below 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. In the mode converter 2805, the transmitted TE-mode microwaves are converted to TEM-mode microwaves. Then, the microwaves are transmitted to a slotted antenna plate 2808 via a waveguide 2807. Multiple slots are provided in the slotted antenna plate 2808, through which microwaves pass and through a dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 includes ions and free radicals depending on the type of gas supplied from the gas supply source 2801. For example, the high-density plasma 2810 includes oxygen free radicals, etc.

[0368] At this time, the film quality on the substrate 2811 can be improved by utilizing the ions and free radicals generated in the high-density plasma 2810. Furthermore, it is sometimes preferable to apply a bias voltage to one side of the substrate 2811 using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with frequencies such as 13.56MHz or 27.12MHz can be used as the high-frequency power supply 2816. By applying a bias voltage to one side of the substrate, ions in the high-density plasma 2810 can efficiently reach the depth of the openings in the film on the substrate 2811.

[0369] For example, by introducing oxygen from gas supply source 2801, oxygen free radical treatment using high-density plasma 2810 can be carried out in treatment chamber 2706b or treatment chamber 2706c.

[0370] Next, the cross-sectional schematic diagram shown in Figure 25 will be used to describe the processing chambers 2706a and 2706d.

[0371] Processing chambers 2706a and 2706d are, for example, processing chambers capable of irradiating the object being processed with electromagnetic waves. Note that the only difference between processing chambers 2706a and 2706d is the type of electromagnetic wave. Since the other structures of processing chambers 2706a and 2706d are the same, they will be described together below.

[0372] Processing chambers 2706a and 2706d include one or more lamps 2820, a substrate support 2825, a gas inlet 2823, and an exhaust outlet 2830. Additionally, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the processing chambers 2706a and 2706d.

[0373] A gas supply source 2821 is connected to a gas inlet 2823 through a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 through a valve 2829. A lamp 2820 is disposed opposite to a substrate support 2825. The substrate support 2825 has the function of holding the substrate 2824. In addition, the substrate support 2825 includes a heating mechanism 2826 inside and has the function of heating the substrate 2824.

[0374] As for lamp 2820, for example, a light source that can emit electromagnetic waves such as infrared light, visible light, or ultraviolet light can be used. For example, a light source that can emit electromagnetic waves with peak values ​​in the wavelength regions of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm can be used.

[0375] For example, as lamp 2820, light sources such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps can be used.

[0376] For example, some or all of the electromagnetic waves emitted from the lamp 2820 are drawn into the substrate 2824, thereby improving the quality of films, etc., on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. In addition, when defects are generated or reduced, or impurities are removed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0377] Alternatively, for example, electromagnetic waves emitted from lamp 2820 can be used to heat the substrate support 2825, thereby heating the substrate 2824. In this case, it is not necessary to include a heating mechanism 2826 inside the substrate support 2825.

[0378] Vacuum pump 2828 can be found in the description of vacuum pump 2817. Heating mechanism 2826 can be found in the description of heating mechanism 2813. Gas supply source 2821 can be found in the description of gas supply source 2801.

[0379] By using the above-mentioned manufacturing apparatus, impurities can be prevented from entering the processed material and the membrane quality can be improved.

[0380] Implementation Method 2 In this embodiment, an embodiment of the semiconductor device will be described with reference to FIGS. 26 to 29.

[0381] [Memory Device 2] Figure 26 shows an example of a semiconductor device (memory device) according to one embodiment of the present invention.

[0382] <Examples of memory device structures> Figure 26 is a cross-sectional view of a semiconductor device including memory device 290. Figure 26 corresponds to a cross-sectional view along the channel length of transistor 200. The memory device 290 shown in Figure 26 differs from the semiconductor device including transistor 200 and capacitor 292 shown in Figures 3A to 3D described in <Structure Example 2 of Semiconductor Device> in the structure of conductor 240. In other words, conductor 240 is connected to conductor 242a and also to conductor 166 through conductor 242a, oxide 243a, oxide 230a, oxide 230b, insulator 224, and insulator 222.

[0383] Note that in the semiconductor device shown in FIG26, components having the same function as the components constituting the semiconductor device described in the above embodiments are given the same element symbols. In this section, materials described in detail in the above embodiments can be used as constituent materials of the semiconductor device.

[0384] A wiring layer may also be provided on the memory device 290. For example, in FIG26, insulators 160 and 162 are provided as interlayer films on transistor 200 and capacitor 292. In addition, conductors 166 electrically connected to transistor 200 are filled in insulators 160 and 162. Conductors 166 are used as plugs or wiring.

[0385] Wiring layers can also be provided on insulator 162 and conductor 166. For example, in FIG26, insulator 163 and insulator 164 are provided. In addition, conductor 168 is filled in insulator 163 and insulator 164. Conductor 168 is used as a plug or wiring.

[0386] Insulators 162 and 164 are preferably insulators with a relatively low permittivity. For example, insulators that can be used in insulators 280 and the like are preferably insulators 162 and 164.

[0387] Insulators 160 and 163 are preferably insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen. For example, insulators 160 and 163 are preferably insulators that can be used in insulators such as 283.

[0388] Alternatively, the memory device 290 described above can also have a stacked structure. Figure 27 is a cross-sectional view of the structure of a five-layer stacked memory device 290. As shown in Figure 27, the memory device 290 is electrically connected to different memory devices 290 through conductors 240 and 166.

[0389] Alternatively, as shown in Figure 27, insulators 284 and 214 can be used to seal multiple memory devices (memory devices 290_1 to 290_5). Sealing multiple memory devices simplifies the manufacturing process. Furthermore, by using sputtering to form part of the structure constituting the transistor 200 and part of the structure surrounding the transistor 200, the hydrogen concentration of the transistor 200 can be reduced. Therefore, when different transistors 200 are manufactured above the transistor 200, the hydrogen concentration of the transistor 200 located below can be kept low. Thus, when the memory device 290 has a stacked structure, sealing multiple memory devices instead of sealing each one individually also reduces the hydrogen concentration in the transistor 200.

[0390] In addition, when sealing multiple memory devices with insulators 284 and 214, sealing can be performed around all multiple memory devices or around each part of the memory devices.

[0391] Multiple memory devices 290 can be arranged in the channel length direction, the channel width direction, or in a matrix. Alternatively, they can be arranged irregularly according to the design.

[0392] Alternatively, when insulator 214 and insulator 282 are made of the same material, either insulator 214 or insulator 282 may be omitted. This reduces the number of manufacturing processes.

[0393] As shown in Figure 27, by stacking multiple memory devices (memory devices 290_1 to 290_5), memory devices can be integrated without increasing their footprint. In other words, 3D memory devices can be constructed.

[0394] Note that Figure 27 shows a structure where each layer includes one memory device, but it is not limited to this. Each layer may also include multiple memory devices, which can be arranged in the channel length direction, the channel width direction, or in a matrix. Alternatively, they can be arranged irregularly according to the design.

[0395] <Examples of variations of memory devices> Hereinafter, using Figures 28A, 28B, and 29, an example of a semiconductor device according to an embodiment of the present invention, including a transistor 200 and a capacitor 292, will be described, which differs from the semiconductor device shown in the above-described <Structure Example of a Memory Device>. Note that in the semiconductor devices shown in Figures 28A, 28B, and 29, components having the same function as the components constituting the semiconductor device shown in the above-described embodiment and Figure 26 are given the same element symbols. Furthermore, in this section, the materials constituting the transistor 200 and the capacitor 292 may be the materials described in detail in the above-described embodiment and the above-described <Structure Example of a Memory Device>.

[0396] Example 1 of a variation of a memory device Hereinafter, an example of a semiconductor device including a memory device 600 is described using Figures 28A and 28B. The memory device 600 includes transistors 200a and 200b, capacitors 292a and 292b.

[0397] Figure 28A is a top view of a semiconductor device including memory device 600. Figure 28B is a cross-sectional view along the dashed line A1-A2 in Figure 28A, and also a cross-sectional view along the channel length direction of transistors 200a and 200b. For clarity, some components are omitted in the top view of Figure 28A.

[0398] As shown in Figure 28B, the memory device 600 has an axially symmetric structure with the dotted line A3-A4 as the axis of symmetry. Conductor 242c serves as one of the source and drain electrodes of transistor 200a and one of the source and drain electrodes of transistor 200b. Furthermore, conductor 240c also serves as a conductor electrically connected to transistor 200a and used as a connector, and as a conductor electrically connected to transistor 200b and used as a connector. Thus, by employing the above structure as the connection relationship between two transistors, two capacitors, wiring, and a connector, a semiconductor device capable of miniaturization or hyper-integration can be provided.

[0399] The structures and effects of transistors 200a and 200b, capacitors 292a and 292b can be seen in the examples of semiconductor device structures shown in Figures 3A to 3D and Figure 26.

[0400] Example 2 of a variation of memory devices Figure 29 shows an example of a memory cell 470 having a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to memory device layers 415_4).

[0401] Each of memory device layers 415_1 to 415_4 includes a plurality of memory devices 420. As a memory device 420, for example, the memory device 290 shown in FIG. 26 or the memory device 600 shown in FIG. 28A and FIG. 28B can be used.

[0402] The memory device 420 is electrically connected to the memory device 420 and the transistor 200T of the transistor layer 413 included in the different memory device layers 415 via conductors 424 and 166.

[0403] The memory cell 470 is sealed by insulators 212, 214, 282, 284, and 283 (hereinafter referred to as the sealed structure for convenience). An insulator 274 is disposed around the insulator 283. Furthermore, conductors 440 are disposed on insulators 274, 212, and 214 and are electrically connected to the element layer 411.

[0404] Furthermore, insulators 212 and 283 are preferably made of materials with high hydrogen barrier properties. Additionally, insulators 214 and 282 are preferably made of materials that trap or fix hydrogen.

[0405] For example, silicon nitride and silicon oxynitride are examples of materials that have high hydrogen barrier properties. In addition, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are examples of materials that have the function of capturing or fixing hydrogen.

[0406] There are no particular restrictions on the crystal structure of the materials used in insulators 212, 214, 282, and 283; either amorphous or crystalline structures can be used. For example, amorphous alumina films are preferred as materials with hydrogen trapping or fixation capabilities. Amorphous alumina can sometimes trap or fix more hydrogen than highly crystalline alumina.

[0407] Additionally, an insulator 280 is provided inside the sealed structure. The insulator 280 has the function of releasing oxygen by heating. Alternatively, the insulator 280 has a region with excess oxygen.

[0408] Here, the following model can be considered as a model for the diffusion of excess oxygen in the insulator 280 relative to hydrogen in the oxide semiconductor in contact with the insulator 280.

[0409] Hydrogen in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. This hydrogen diffuses as OH bonds through the reaction of excess oxygen in the insulator 280 with the hydrogen in the oxide semiconductor. When hydrogen atoms with OH bonds reach a material that traps or fixes hydrogen (typically insulator 282), the hydrogen atoms react with oxygen atoms bonded to atoms (e.g., metal atoms) in insulator 282 and are trapped or fixed therein. On the other hand, the oxygen atoms of the excess oxygen with OH bonds are estimated to remain as excess oxygen in insulator 280. In other words, in this hydrogen diffusion, the excess oxygen in insulator 280 is highly likely to act as a mediator.

[0410] To meet the requirements of the above model, the manufacturing process of semiconductor devices is one of the important factors.

[0411] As an example, after forming an insulator 280 containing excess oxygen in the oxide semiconductor, an insulator 282 is formed. Subsequently, a heat treatment is preferably performed. Specifically, this heat treatment is carried out in an oxygen-containing atmosphere, a nitrogen-containing atmosphere, or a mixed atmosphere of oxygen and nitrogen, at a temperature of 350°C or higher, preferably 400°C or higher. The heat treatment time is 1 hour or more, preferably 4 hours or more, and even more preferably 8 hours or more.

[0412] By performing the above-described heat treatment, the diffusion of hydrogen from the oxide semiconductor through insulators 280 and 282 to the outside can be suppressed. In other words, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0413] After the above heat treatment, an insulator 284 is formed. Because the insulator 284 is a material with high hydrogen barrier properties, it can suppress hydrogen that diffuses to the outside or hydrogen present in the outside from penetrating into the interior, specifically, the oxide semiconductor or the insulator 280 side.

[0414] Note that the structure shown is formed after the heat treatment is performed on insulator 282, but it is not limited to this. For example, the heat treatment may also be performed after the formation of transistor layer 413 or after the formation of memory device layers 415_1 to 415_3. Furthermore, when hydrogen diffuses outward by the heat treatment, the hydrogen diffuses upward or laterally onto transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, hydrogen diffuses upward or laterally.

[0415] By using the above-described process to bond insulators 214 and 284 together, the above-described sealing structure can be obtained.

[0416] Thus, by employing the above structure and process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. For example, the oxide 230b included in the transistor 200T or memory device 420 has a region where the hydrogen concentration, as measured by SIMS, is less than 1×10 20 atoms / cm³, preferably less than 1×10 19 atoms / cm³.

[0417] Therefore, a semiconductor device with good reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0418] The structures and methods shown in this embodiment can be appropriately combined with the structures, configurations, and methods shown in other embodiments.

[0419] Implementation Method 3 In this embodiment, referring to FIGS. 30A, 30B, and 31A to 31C, a memory device (hereinafter sometimes referred to as an OS memory device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to an embodiment of the present invention will be described. An OS memory device is a memory device that includes at least a capacitor and an OS transistor for controlling the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS memory device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0420] <Structure examples of memory devices> Figure 30A shows an example of the structure of an OS memory device. The memory device 1400 includes peripheral circuitry 1411 and a memory cell array 1470. The peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0421] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 through the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0422] The memory device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). Furthermore, the memory device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0423] The control logic circuit 1460 processes externally input control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0424] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column arrangement and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0425] Furthermore, although FIG. 30A shows an example of the peripheral circuit 1411 and the memory cell array 1470 forming on the same plane, this embodiment is not limited thereto. For example, as shown in FIG. 30B, the memory cell array 1470 may also be arranged in a manner overlapping a portion of the peripheral circuit 1411. For example, a structure in which the sense amplifier is arranged overlapping the memory cell array 1470 may also be adopted.

[0426] Figures 31A to 31C illustrate examples of the structure of a memory cell that can be used in the memory cell MC described above.

[0427] [DOSRAM] Figures 31A to 31C show examples of the circuit structure of a DRAM memory cell. In this specification, DRAM using a 1OS transistor and 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 31A includes a transistor M1 and a capacitor CA. Furthermore, the transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0428] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0429] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, wiring LL can be either ground or a low-level potential. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying any potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0430] Here, the memory cell 1471 shown in FIG31A corresponds to the memory device shown in FIG26. That is, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 292.

[0431] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt a structure like memory cell 1472 shown in Figure 31B, where the back gate of transistor M1 is not connected to wiring BGL, but to wiring WOL. Alternatively, for example, the memory cell MC can also be a memory cell composed of a single-gate transistor, as shown in memory cell 1473 in Figure 31C, that is, a memory cell consisting of a transistor M1 without a back gate.

[0432] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200 can be used as transistor M1, and capacitor 292 can be used as capacitor CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be kept extremely low. In other words, since the written data can be retained by transistor M1 for a long time, the update frequency of the memory cell can be reduced. In addition, memory cell update operations can be eliminated. Furthermore, since the leakage current is extremely low, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0433] Furthermore, in DOSRAM, when the sense amplifier is arranged as described above, overlapping the memory cell array 1470, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0434] Note that the structure of the peripheral circuit 1411 and memory cell array 1470 shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed.

[0435] Generally, various memory devices (RAMs) are used in semiconductor devices such as computers, depending on their application. Figure 32 shows the various memory devices in a hierarchical manner. The higher the level of the memory device, the faster its access speed; the lower the level of the memory device, the larger its memory capacity and the higher its storage density. In Figure 32, from the top layer, the following are shown in sequence: RAM (Static Random Access Memory) installed as temporary storage in computing devices such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0436] Because they are used to temporarily store calculation results, memory installed as temporary storage in processing units such as CPUs is accessed frequently by the processing unit. Therefore, faster operating speed is required than memory capacity. In addition, temporary storage also has the function of holding settings data of the processing unit.

[0437] SRAM is used, for example, in cache memory. Cache memory has the function of copying and storing a portion of the data held in main memory. By copying frequently used data to cache memory, the speed of data access can be improved.

[0438] DRAM is used, for example, in main memory. Main memory has the function of holding programs or data read from storage. The storage density of DRAM is approximately 0.1 to 0.3 Gbit / mm².

[0439] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time or various programs used by computing devices. Therefore, storage requires large storage capacity and high storage density more than operating speed. The storage density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm².

[0440] A memory device according to one embodiment of the present invention can retain data for a long period of time and has a high operating speed. A memory device according to one embodiment of the present invention can be suitably used as a memory device located in the boundary region 901 between the hierarchy including cache memory and the hierarchy including main memory. Alternatively, a memory device according to one embodiment of the present invention can be suitably used as a memory device located in the boundary region 902 between the hierarchy including main memory and the hierarchy including storage.

[0441] The structure shown in this embodiment can be implemented by appropriately combining it with structures shown in other embodiments, etc.

[0442] Implementation Method 4 In this embodiment, an example of a wafer 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIGS. 33A and 33B. Multiple circuits (systems) are mounted on the wafer 1200. Thus, the technology of integrating multiple circuits (systems) on a single wafer is sometimes referred to as a System on Chip (SoC).

[0443] As shown in Figure 33A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0444] A bump (not shown) is provided on the chip 1200, which is connected to the first side of the printed circuit board (PCB) 1201 as shown in FIG33B. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0445] Alternatively, memory devices such as DRAM 1221 and flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to DRAM 1221. Alternatively, for example, the NOSRAM shown in the above embodiment can be applied to flash memory 1222.

[0446] CPU 1211 preferably has multiple CPU cores. Similarly, GPU 1212 preferably has multiple GPU cores. Furthermore, CPU 1211 and GPU 1212 may each have memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned DOSRAM can be applied to this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0447] Furthermore, since the CPU1211 and GPU1212 are mounted on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation results from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0448] The analog operation unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog operation unit 1213.

[0449] The memory controller 1214 has circuitry that serves as a controller for DRAM 1221 and circuitry that serves as an interface for flash memory 1222.

[0450] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, video recording devices, and controllers. Controllers include mice, keyboards, game console controllers, etc. As the aforementioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc., can be used.

[0451] The network circuit 1216 includes network circuits such as LAN (Local Area Network). Additionally, it may include network security circuits.

[0452] The aforementioned circuits (systems) can be formed on the chip 1200 using the same process. Therefore, even if the number of circuits required for the chip 1200 increases, no additional process is needed, and the chip 1200 can be manufactured at a low cost.

[0453] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0454] The GPU module 1204 can reduce its size due to the presence of a chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product operation circuitry of the GPU 1212, methods such as Deep Neural Networks (DNN), Convolutional Neural Networks (CNN), Recursive Neural Networks (RNN), autoencoders, Deep Boltzmann Machines (DBM), and Deep Belief Networks (DBN) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0455] The structure shown in this embodiment can be implemented by appropriately combining it with structures shown in other embodiments, etc.

[0456] Implementation Method 5 This embodiment shows an example of an electronic component and electronic device in which a memory device or the like described in the above embodiment is installed.

[0457] <Electronic Components> First, an example of an electronic component assembled with a memory device 720 will be described with reference to Figures 34A and 34B.

[0458] Figure 34A shows a perspective view of electronic component 700 and a substrate (circuit board 704) on which electronic component 700 is mounted. The electronic component 700 shown in Figure 34A includes a memory device 720 within a mold 711. In Figure 34A, a portion of the electronic component 700 is omitted to show its interior. The electronic component 700 includes a connection land 712 on the outside of the mold 711. The connection land 712 is electrically connected to electrode pads 713, which are electrically connected to the memory device 720 via leads 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Circuit board 704 is completed by assembling multiple electronic components and electrically connecting them respectively on the printed circuit board 702.

[0459] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722.

[0460] Figure 34B shows a perspective view of electronic component 730. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 are provided on the interposer 731.

[0461] Electronic component 730 illustrates an example where memory device 720 is used as high-bandwidth memory (HBM). Alternatively, semiconductor device 735 can utilize integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs.

[0462] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0463] The through-hole board 731 has the function of providing multiple wirings and electrically connecting multiple integrated circuits with different terminal spacings. These wirings can be composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuits are electrically connected to the packaging substrate 732. Furthermore, when using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through electrode.

[0464] Silicon interposers are preferred for the 731. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Wiring formation on silicon interposers can be performed during semiconductor manufacturing processes, making it easy to create fine wiring that is difficult to achieve with resin interposers.

[0465] In HBM, achieving wide memory bandwidth requires connecting numerous traces. Therefore, the board on which HBM is mounted needs to be able to form fine traces at high density. Thus, silicon boards are preferred for mounting HBM.

[0466] Furthermore, in SiP or MCM applications using silicon through-hole boards, reliability degradation due to differences in the coefficients of thermal expansion between integrated circuits and the through-hole board is less likely to occur. Additionally, due to the high surface flatness of silicon through-hole boards, poor connections between the integrated circuits mounted on the board and the board itself are less likely to occur. It is particularly preferable to use silicon through-hole boards in 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the through-hole board.

[0467] Alternatively, a heat sink (heat plate) may be disposed overlapping with the electronic component 730. When a heat sink is disposed, it is preferable that the height of the integrated circuit disposed on the insert 731 is the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the height of the memory device 720 and the semiconductor device 735 are the same.

[0468] To mount the electronic component 730 onto other substrates, electrodes 733 can be disposed on the bottom of the package substrate 732. Figure 34B shows an example of forming the electrodes 733 using solder balls. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0469] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0470] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0471] Implementation Method 6 In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to memory devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, laptops, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 35A to 35E schematically illustrate several structural examples of removable storage devices. For example, the semiconductor device described in the above embodiments is processed into a packaged memory chip and used in various memory devices or removable memories.

[0472] Figure 35A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1105, etc.

[0473] Figure 35B is a schematic diagram of the external appearance of the SD card, and Figure 35C is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, through wireless communication between the host device and the SD card 1110, data can be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be assembled onto the memory chip 1114, etc.

[0474] Figure 35D is a schematic diagram of the external appearance of the SSD, and Figure 35E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor devices shown in the above embodiments can be assembled onto the memory chip 1154, etc.

[0475] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0476] Implementation Method 7 A semiconductor device according to one embodiment of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 36A to 36H show specific examples of electronic devices having processors or chips such as CPUs and GPUs according to one embodiment of the present invention.

[0477] Electronic Devices and Systems The GPU or chip according to one embodiment of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to large-screen electronic devices such as televisions, displays for desktop or laptop information terminals, digital signage, and large game consoles such as pinball machines, digital cameras, digital camcorders, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and audio playback devices. Furthermore, by incorporating the GPU or chip according to one embodiment of the present invention into an electronic device, the electronic device can be endowed with artificial intelligence.

[0478] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on the display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0479] An electronic device according to one embodiment of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0480] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have the following functions: displaying various information (still images, moving pictures, text images, etc.) on a display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); performing wireless communication function; reading programs or data stored in a storage medium; etc. Figures 36A to 36H show examples of electronic devices.

[0481] [Information Terminal] Figure 36A shows a mobile phone (smartphone), one of the information terminals. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0482] By applying the chip of one embodiment of the present invention to the information terminal 5100, an application utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5102, applications that recognize text or graphics input by the user to the touch panel of the display unit 5102 and display those text or graphics on the display unit 5102, and applications that perform biometric identification such as fingerprints or voiceprints.

[0483] Figure 36B shows a notebook-type information terminal 5200. The notebook-type information terminal 5200 includes an information terminal body 5201, a display unit 5202, and a keyboard 5203.

[0484] Similar to the aforementioned information terminal 5100, by applying the chip of one embodiment of the present invention to the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and menu automatic generation software. Furthermore, by using the notebook information terminal 5200, novel artificial intelligence technologies can be developed.

[0485] Note that in the examples above, Figures 36A and 36B respectively show smartphones and laptops as examples of electronic devices, but they can also be applied to information terminals other than smartphones and laptops. Examples of information terminals other than smartphones and laptops include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0486] [Game console] Figure 36C shows a portable game console 5300 as an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connector 5305, and operation keys 5306. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connector 5305 provided in housing 5301 to another housing (not shown), the image output to the display unit 5304 can be output to another video display device (not shown). At this time, housings 5302 and 5303 can each be used as operation units. Thus, multiple gamers can play the game simultaneously. Chips, etc., as shown in the above embodiment, can be embedded in the substrates provided in housings 5301, 5302, and 5303.

[0487] Additionally, Figure 36D shows a stationary game console 5400, one of the game consoles. The stationary game console 5400 is connected to a controller 5402 wirelessly or via a wired connection.

[0488] By applying the GPU or chip of one embodiment of the present invention to game consoles such as portable game console 5300 and stationary game console 5400, low-power game consoles can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0489] Furthermore, by applying the GPU or chip of one embodiment of the present invention to a portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0490] The progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are all normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time, and changes in the behavior of characters appearing in the game.

[0491] Furthermore, when playing games that require multiple players using the portable game console 5300, artificial intelligence can be used to create anthropomorphic game players, thus allowing one person to play a game that can be played by multiple people.

[0492] Although Figures 36C and 36D show portable and stationary game consoles as examples of game consoles, game consoles using GPUs or chips according to one embodiment of the present invention are not limited thereto. Examples of game consoles using GPUs or chips according to one embodiment of the present invention include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0493] [Main Computer] The GPU or chip of one embodiment of the present invention can be applied to large computers.

[0494] Figure 36E shows the supercomputer 5500 as an example of a mainframe computer. Figure 36F shows the rack-mount computer 5502 included in the supercomputer 5500.

[0495] The supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that the multiple computers 5502 are housed in the rack 5501. In addition, each computer 5502 has multiple substrates 5504 on which the GPU or chip described in the above embodiments can be mounted.

[0496] The Supercomputer 5500 is primarily a large-scale computer suitable for scientific computing. Scientific computing requires massive calculations at high speeds, resulting in high power consumption and significant heat generation from the chips. By applying the GPU or chip of one embodiment of this invention to the Supercomputer 5500, a low-power supercomputer can be achieved. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat on the circuitry itself, peripheral circuits, and modules.

[0497] Figures 36E and 36F show a supercomputer as an example of a mainframe computer; however, the mainframe computer using a GPU or chip according to one embodiment of the present invention is not limited to this. Examples of mainframe computers using a GPU or chip according to one embodiment of the present invention include service-providing computers (servers), mainframe computers (hosts), etc.

[0498] [Moving Object] The GPU or chip of one embodiment of the present invention can be applied to a car as a moving body and the area around the driver's seat of the car.

[0499] Figure 36G is a diagram of the perimeter of the windshield inside a car interior, illustrating an example of a moving body. Figure 36G shows display panels 5701, 5702, and 5703 mounted on the dashboard, and display panel 5704 mounted on the pillar.

[0500] Display panels 5701 to 5703 can provide various other information by displaying speedometer, tachometer, distance traveled, fuel gauge, gear shift status, and air conditioning settings. Furthermore, users can customize the display content and layout according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting equipment.

[0501] By displaying images captured by a camera (not shown) installed in the vehicle on the display panel 5704, blind spots (obstructions to the view) can be filled in. In other words, by displaying images captured by a camera installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that supplement areas that are not visible, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0502] Because the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system for automobiles. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0503] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies. The chip of one embodiment of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0504] [Electrical Products] Figure 36H shows an example of an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes an outer casing 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0505] By applying the chip of one embodiment of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a function table based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and the function of automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0506] Electric refrigerators and freezers are one example of electrical appliances, but other electrical appliances that can be cited include vacuum cleaners, microwave ovens, electric ovens, electric rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners), washing machines, dryers, and audio-visual equipment.

[0507] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and its effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0508] This embodiment can be implemented by appropriately combining it with the structures described in other embodiments, etc.

[0509] 160: Insulator 162: Insulator 163: Insulator 164: Insulator 166: Conductor 168: Conductor 200: Transistor 200a: Transistor 200b: Transistor 200T: Transistor 205: Conductor 205a: Conductor 205A: Conductive film 205b: Conductor 205B: Conductive film 205c: Conductor 205C: Conductive film 212: Insulator 214: Insulator 216: Insulator 222: Insulator 224: Insulator 230: Oxides 230a: Oxide 230A: Oxide film 230b: Oxide 230B: Oxide film 230ba: Area 230bb: Area 230bc: Area 240: Conductor 240a: Conductor 240b: Conductor 240C: Conductor 241: Insulator 241a: Insulator 241b: Insulator 242: Conductor 242a: Conductor 242A: Conductive film 242b: Conductor 242B: Conductive layer 242c: Conductor 243: Oxides 243a: Oxide 243A: Oxide film 243b: Oxide 243B: Oxide layer 246: Conductor 246a: Conductor 246b: Conductor 250: Insulator 250a: Insulator 250A: Insulating film 250Aa: Insulating film 250Ab: Insulating film 250b: Insulator 260: Conductor 260a: Conductor 260b: Conductor 271: Insulator 271a: Insulator 271A: Insulating film 271b: Insulator 271B: Insulation layer 272: Insulator 272a: Insulator 272A: Insulating film 272b: Insulator 273: Insulator 273a: Insulator 273A: Insulating film 273b: Insulator 273B: Insulation layer 274: Insulator 275: Insulator 275a: Insulator 275A: Insulating film 275b: Insulator 280: Insulator 282: Insulator 283: Insulator 284: Insulator 286: Insulator 290: Memory devices 290_1: Memory Devices 290_5: Memory Devices 292: Capacitor 292a: Capacitor 292b: Capacitor 293: Insulator 293A: Insulating film 294: Conductor 294A: Conductive film 411: Component Layer 413: Transistor layer 415: Memory Device Layer 415_1: Memory Device Layer 415_3: Memory Device Layer 415_4: Memory Device Layer 420: Memory devices 424: Conductor 440: Conductor 470: Memory Unit 600: Memory Devices 700: Electronic Components 702: Printed Circuit Board 704: Circuit Board 711: Mold 712: Connector 713: Electrode pads 714: Lead wire 720: Memory Device 721: Driver Circuit Layer 722: Memory Circuit Layer 730: Electronic Components 731: Insert Board 732: Packaging substrate 733: Electrode 735: Semiconductor Device 901: Boundary Area 902: Boundary Area

Claims

1. A semiconductor device comprising a transistor, a capacitor, and a plug, wherein, The transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator disposed on the first insulator and the second insulator, wherein a first opening is formed overlapping the region between the first conductor and the second conductor, and a second opening is formed overlapping the second conductor; a fourth insulator embedded in the first opening; and a third conductor disposed on the fourth insulator and embedded in the first opening. The capacitor includes: the second conductor; a fifth insulator embedded in the second opening; and a fourth conductor on the fifth insulator. The height of the top surface of the third conductor and the height of the top surface of the fourth conductor are substantially the same as the height of the top surface of the third insulator. The plug passes through the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are metal oxides having an amorphous structure.

2. A semiconductor device comprising a transistor, a capacitor, and a plug, wherein, The transistor includes: an oxide semiconductor; a first conductor and a second conductor on the oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator covering the first insulator and the second insulator, wherein a first opening is formed overlapping the region between the first conductor and the second conductor, and a second opening is formed overlapping the second conductor; a fourth insulator disposed on the third insulator, wherein a third opening is formed overlapping the first opening, and a fourth opening is formed overlapping the second opening; a fifth insulator embedded in the first opening and the third opening; and a third conductor disposed on the fifth insulator and embedded in the first opening and the third opening. The capacitor includes: the second conductor; a sixth insulator embedded in the second opening and the fourth opening; and a fourth conductor on the sixth insulator. The plug passes through the first insulator, the third insulator, the fourth insulator, the first conductor, and the oxide semiconductor, and the plug is electrically connected to the first conductor. Furthermore, the first insulator, the second insulator, and the third insulator are metal oxides with an amorphous structure.

3. The semiconductor device of claim 2 further includes a seventh insulator and an eighth insulator, wherein the seventh insulator is disposed below the oxide semiconductor, the eighth insulator is in contact with the top surface of the fourth insulator, the top surface of the third conductor and the top surface of the fourth conductor, and the seventh insulator and the eighth insulator are metal oxides having an amorphous structure.

4. The semiconductor device of claim 3 further includes a ninth insulator, wherein the ninth insulator covers the eighth insulator and contacts the top surface of the seventh insulator in a region that does not overlap with the fifth insulator, and the ninth insulator is a metal oxide having an amorphous structure.

5. The semiconductor device of claim 4 further includes a tenth insulator and an eleventh insulator, wherein the tenth insulator is in contact with the bottom surface of the seventh insulator, the eleventh insulator is in contact with the top surface of the ninth insulator, and the tenth insulator and the eleventh insulator are silicon nitride.

6. The semiconductor device of claim 1 or 2 further includes a first nitride insulator and a second nitride insulator, wherein the first nitride insulator is disposed between the first insulator and the third insulator, the second nitride insulator is disposed between the second insulator and the third insulator, and the first nitride insulator and the second nitride insulator are silicon nitride.

7. A semiconductor device as claimed in claim 1 or 2, wherein the metal oxide is AlO x, where x is any number greater than 0.

8. A semiconductor device, comprising: The system comprises a first insulating layer, a second insulating layer, a first memory cell, and a second memory cell, wherein the first memory cell includes a first transistor, a first capacitor, and a first connector. The first transistor includes: a first oxide semiconductor; a first conductor and a second conductor on the first oxide semiconductor; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator disposed on the first and second insulators, wherein a first opening is formed overlapping the region between the first and second conductors, and a second opening is formed overlapping the second conductor; a fourth insulator on the first oxide semiconductor and disposed between the first and second conductors; and a third conductor on the fourth insulator. The first capacitor includes: the second conductor; a fifth insulator disposed inside the second opening; and a fourth conductor on the fifth insulator. The first connector passes through the first insulator, the third insulator, the first conductor, and the first oxide semiconductor, and is electrically connected to the first conductor. The second memory cell includes: a second transistor, a second capacitor, and a second connector. The second transistor includes: The second oxide semiconductor includes: a second oxide semiconductor; a fifth and a sixth conductor on the second oxide semiconductor; a sixth insulator on the fifth conductor; a seventh insulator on the sixth conductor; an eighth insulator disposed on the sixth and seventh insulators, wherein a third opening is formed overlapping the region between the fifth and sixth conductors, and a fourth opening is formed overlapping the sixth conductor; a ninth insulator on the second oxide semiconductor and disposed between the fifth and sixth conductors; and a seventh conductor on the ninth insulator. The second capacitor includes: the sixth conductor; a tenth insulator disposed inside the fourth opening; and an eighth conductor on the tenth insulator. A second plug passes through the sixth insulator, the ninth insulator, the fifth conductor, and the second oxide semiconductor. The second plug is electrically connected to the fifth conductor. A first memory cell is disposed on the first insulating layer. A second memory cell is disposed on the first memory cell. The top surface of the first plug is electrically connected to the second plug. The second insulating layer covers the first memory cell and the second memory cell. Furthermore, the second insulating layer contacts a portion of the top surface of the first insulating layer in a region that does not overlap with the first oxide semiconductor and the second oxide semiconductor.

9. The semiconductor device of claim 8, wherein the first insulating layer includes an eleventh insulator and a twelfth insulator on the eleventh insulator, the second insulating layer includes a thirteenth insulator and a fourteenth insulator on the thirteenth insulator, the eleventh insulator and the thirteenth insulator comprising silicon nitride, and the twelfth insulator and the fourteenth insulator are metal oxides having an amorphous structure.

10. The semiconductor device of claim 9, wherein the metal oxide is AlO x, where x is any number greater than 0.

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