Bonded structure and method forming the same

Abstract

A wafer-on-wafer (WoW) structure, such as a bonded wafer element structure, includes an array of contact pads formed in an interconnect layer of at least one wafer of the bonded wafer element structure. The contact pad array formed in the at least one wafer interconnect layer may have an array pattern corresponding to a contact pad array pattern subsequently formed on the surface of the bonded wafer structure. Testing of the contact pad array formed in the interconnect layer of at least one wafer of the bonded wafer element structure for improvements on individual wafers includes circuit probe testing prior to stacking and bonding the wafers to one or more additional wafers to form the bonded wafer structure.

Description

Technical Field

[0001] This disclosure relates to a joint structure and its manufacturing method. Prior Technology

[0002] The semiconductor industry is growing due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the successive reduction in the smallest feature size, which allows more components to be integrated into a given area.

[0003] Higher density electronic components can also be achieved by fabricating three-dimensional (3D) integrated circuit (IC) device structures. Some 3D device structures, such as wafer-on-wafer structures, involve stacking and bonding multiple IC devices (i.e., chips) on a semiconductor wafer layer. Such 3D-bonded wafer device structures offer improved integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced length of interconnects between the stacked chips. However, there are many challenges associated with 3D devices. Summary of the Invention

[0004] One embodiment of this disclosure provides a bonding structure comprising a first semiconductor structure having a first substrate, a first element structure, and a first interconnection structure, and a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure located on a first surface of the second substrate, wherein the second interconnection structure includes an array of top metal contact pads, and the bonding structure includes a bonding layer between the top metal contact pad array and the first surface of the first substrate and a contact pad array on the second surface of the first substrate, wherein the top metal contact pad array includes an array pattern corresponding to the array pattern of contact pads of the contact pad array formed on the second surface of the first substrate, wherein the spatial coordinates of the geometric center point of each contact pad in the contact pad array formed on the second surface of the first substrate are within 5µm of the spatial coordinates of the geometric center point of each top metal contact pad of the top metal contact pad array in a common reference architecture.

[0005] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure having a first substrate, a first element structure, and a first interconnection; a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure; wherein the second interconnection structure includes a top metal layer, the top metal layer including a plurality of metal features, each metal feature having a contact pad region and a second region adjacent to the contact pad region; wherein the contact pad region has length and width dimensions configured for circuit probe testing of the second semiconductor structure; a bonding layer between the top metal layer of the second interconnection structure and a first surface of the first substrate; and an array of contact pads on the first substrate above the second surface of the first substrate.

[0006] Another embodiment of this disclosure provides a method for fabricating a bonding structure, comprising providing a first semiconductor structure, a component structure and an interconnect structure included on a first substrate, forming a top metal feature array in a top metal layer of the interconnect structure of the first semiconductor structure, forming a bonding layer on the top metal feature array, bonding the first semiconductor structure to a second semiconductor structure to form a bonding structure, and forming a contact pad array on the surface of the bonding structure. The top metal layer includes contact pad regions and a second region adjacent to the contact pad regions, and the length and width dimensions of the contact pad regions are configured for circuit probe testing of the first semiconductor structure, wherein the second region of the top metal feature array contacts electrically connecting the second region of the top metal feature array to a plurality of bonding connection portions of the bonding layer. The pattern of the contact pad array formed on the surface of the bonding structure corresponds to the pattern of the top metal contact pad array formed in the top metal layer of the interconnect structure of the first semiconductor structure.

[0007] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure comprising a first substrate, a first element structure, and a first interconnection structure, and a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure on a first surface of the second substrate. The second interconnection structure includes a top metal layer comprising a plurality of metal features, wherein at least some of the metal features include contact pad regions and second regions adjacent to the contact pad regions. The bonding structure includes a bonding layer between an array of top metal contact pads and the first surface of the first substrate, a bonding connection portion contacting the second regions of the metal features and electrically connecting the metal features to the bonding layer, and a contact pad array on the second surface of the first substrate, wherein the connecting pad regions of the metal features form an array pattern corresponding to the array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

[0008] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure comprising a first substrate, a first element structure, and a first interconnection structure, and a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure. The second interconnection structure includes a top metal layer comprising a plurality of metal features, each of which has a contact pad region and a second region adjacent to the contact pad region. The upper surface of the contact pad region and the upper surface of the second region are coplanar. The contact pad region has a length and width dimension between 40 μm and 100 μm, and the second region has a length and / or width dimension less than 40 μm. The bonding structure includes a bonding layer between the top metal layer of the second interconnection structure and a first surface of the first substrate, and a contact pad array on the second surface of the first substrate. The contact pad regions of the metal features form an array pattern corresponding to the array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

[0009] Another embodiment of this disclosure provides a method for fabricating a bonding structure, comprising providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and interconnection structures on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure, each of the plurality of top metal features in the top metal feature array including a contact pad region and a second region adjacent to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar, the contact pad region includes a length and width dimension between 40 μm and 100 μm, and the second region includes a length and / or width dimension less than 40 μm; forming a bonding layer on the top metal feature array; bonding the first semiconductor structure to a second semiconductor structure to form a bonding structure; and forming a contact pad array on the surface of the bonding structure, wherein the pattern formed by the contact pad regions in the top metal features corresponds to the pattern of the contact pad array formed on the surface of the bonding structure.

[0010] Another embodiment of this disclosure provides a method for fabricating a bonding structure, comprising the following steps: providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and interconnection structures on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure; forming a bonding layer on the top metal feature array; bonding the first semiconductor structure to a second semiconductor structure including a second substrate to form a bonding structure; and forming a plurality of contact pads on the surface of the second substrate, wherein the spatial coordinates of the geometric center point of each of the contact pads are within 5µm of the spatial coordinates of the geometric center points of each of the plurality of top metal features of the top metal feature array.

[0011] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure. The second semiconductor structure includes a second substrate, a plurality of second elements on a first surface of the second substrate, and a second interconnection structure, wherein the second interconnection structure includes a top metal feature array. The bonding structure includes a bonding layer between the top metal feature array and the first surface of the first substrate, and a contact pad array on the second surface of the first substrate, wherein the spatial coordinates of the geometric center points of the plurality of contact pads in the contact pad array are within 5 µm of the spatial coordinates of the geometric center points of the plurality of top metal features in the top metal feature array of the second interconnection structure of the second semiconductor structure.

[0012] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure. The second semiconductor structure includes a second substrate, a plurality of second elements, and a second interconnection structure, wherein the second interconnection structure includes a top metal feature array. Each of the top metal features includes a contact pad region and a second region adjacent to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar. The bonding structure includes a bonding layer between the top metal features of the second interconnection structure and a first surface of the first substrate, and a contact pad array on the second surface of the first substrate, wherein the contact pad regions of the top metal features form an array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate. Simple Explanation of the Diagram

[0013] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in this industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation. Figure 1A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer including elements and interconnection structures formed on a semiconductor material substrate. Figure 1B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer including elements and interconnection structures formed on a semiconductor material substrate. Figure 2A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer including a dielectric material layer deposited on an interconnect structure and a patterned mask formed on the dielectric material layer. Figure 2B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer comprising a dielectric material layer deposited on an interconnect structure and a patterned mask formed on the dielectric material layer. Figure 3A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, illustrating via openings formed through a dielectric material layer and a patterned mask deposited on the first dielectric material layer. Figure 3B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, illustrating via openings formed through a dielectric material layer and a patterned mask deposited on the dielectric material layer. Figure 4A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer containing a plurality of trench openings formed in a dielectric material layer. Figure 4B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer containing a plurality of trench openings formed in a dielectric material layer. Figure 5A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer comprising a metal material layer deposited on and filled with a plurality of trenches and via openings in the dielectric material layer. Figure 5B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer comprising a metal material layer deposited on and filled with a plurality of trenches and via openings in the dielectric material layer. Figure 6A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer comprising a plurality of metallic features and via structures embedded in a dielectric material layer. Figure 6B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer comprising a plurality of metallic features and via structures embedded in a dielectric material layer. Figure 7A is a top view of a portion of the top metal layer of a first wafer according to an embodiment of the present disclosure, illustrating an array of metal features embedded in a dielectric material layer. Figure 7B is a top view of a portion of the top metal layer of a second wafer according to an embodiment of the present disclosure, illustrating an array of metal features embedded in a dielectric material layer. Figure 8A is a top view of a portion of a bonded wafer structure according to an embodiment of the present disclosure, illustrating an array of contact pads of the bonded wafer structure. Figure 8B is a top view of a portion of the top metal layer of a wafer for bonding according to an embodiment of the present disclosure, illustrating a plurality of metal features including an array of contact pads. Figure 8C is a vertical cross-sectional view of the contact pads of the bonded wafer structure and the top metal contact pads of the wafer in the bonded wafer structure, according to an embodiment of the present disclosure. Figure 9 is a top view of a portion of a wafer according to an embodiment of the present disclosure, illustrating a top metal feature with a contact pad region. Figure 10A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer comprising a dielectric material layer deposited on a top metal layer and a patterned mask formed on the dielectric material layer. Figure 10B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer comprising a dielectric material layer deposited on a top metal layer and a patterned mask formed on the dielectric material layer. Figure 11A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer including an opening formed through a dielectric material layer to expose a portion of a top metal layer. Figure 11B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer including an opening formed through a dielectric material layer to expose a portion of a top metal layer. Figure 12A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer containing trenches formed in a dielectric material layer. Figure 12B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer containing trenches formed in a dielectric material layer. Figure 13A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer comprising a metal material layer deposited on and filled with a plurality of trenches and via openings in the dielectric material layer. Figure 13B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer comprising a metal material layer deposited on and filled with a plurality of trenches and via openings in the dielectric material layer. Figure 14A is a vertical cross-sectional view of a portion of a first wafer according to an embodiment of the present disclosure, the first wafer including a plurality of bonding pads and bonding connections embedded in a dielectric material layer. Figure 14B is a vertical cross-sectional view of a portion of a second wafer according to an embodiment of the present disclosure, the second wafer including a plurality of bonding pads and bonding connections embedded in a dielectric material layer. Figure 15 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, wherein the bonded wafer includes a first wafer bonded to a second wafer. Figure 16 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, wherein the bonded wafer includes a patterned mask formed on the back side of a substrate of a first wafer. Figure 17 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure including a plurality of openings formed through a substrate and a dielectric material of a first wafer to expose metallic features of an interconnect structure. Figure 18 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure. The bonded wafer structure includes a lining material layer on the sidewalls of a plurality of openings, the openings being formed through the substrate and the dielectric material of the first wafer. Figure 19 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a layer of conductive material deposited on the back side of a substrate of a first wafer and within a plurality of openings in the first wafer. Figure 20 is a vertical cross-sectional view of a wafer structure comprising a plurality of conductive vias formed in a first wafer and joined through a substrate, according to an embodiment of the present disclosure. Figure 21 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a dielectric material layer deposited on the back side of a substrate of a first wafer and a plurality of conductive vias through the substrate. Figure 22 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the vertical cross-sectional view of the bonded wafer structure including a patterned mask formed on a dielectric material layer on the back side of the substrate of the first wafer. Figure 23 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure including a plurality of openings formed through a dielectric material layer to expose conductive vias through a substrate. Figure 24 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a layer of conductive material deposited on a dielectric material layer and within a plurality of openings through the dielectric material layer. Figure 25 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a patterned mask on a conductive material layer. Figure 26 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure including an array of contact pads of the bonded wafer structure located on the rear side of the substrate of the first wafer. Figure 27 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a dielectric material layer of a contact pad array deposited on the back side of a substrate of a first wafer. Figure 28 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure comprising a patterned mask formed on a dielectric material layer. Figure 29 is a vertical cross-sectional view of a bonded wafer structure according to an embodiment of the present disclosure, the bonded wafer structure including openings through a dielectric material layer to expose corresponding contact surfaces of the contact pad array of the bonded wafer structure. Figure 30 is a flowchart illustrating the steps of a method for fabricating a bonded wafer element structure according to various embodiments of the present disclosure. Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, in various examples, element symbols and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity, and the repetition itself does not govern the relationships between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "higher," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(e). In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptions used herein may be interpreted accordingly. Unless otherwise explicitly stated, it is assumed that each element having the same element symbol has the same material composition and a thickness within the same thickness range.

[0016] This disclosure relates to bonded wafer device structures, such as wafer-on-wafer (WoW) structures, and methods for fabricating bonded wafer device structures, including contact pad arrays formed in interconnect layers of at least one wafer of the bonded wafer device structure. In various embodiments, the contact pad array enables improved testing of individual wafers, including circuit probe testing, prior to stacking and bonding wafers to one or more additional wafers to form the bonded wafer structure.

[0017] In conventional processes used to fabricate bonded wafer structures such as WoW structures, the functional characteristics of individual wafers are typically unknown before the wafers are stacked and bonded. For example, circuit probe testing can only be performed after the wafers have been stacked and bonded to form a bonded wafer structure, and contact pads have been formed on the bonded wafer structure. However, if one of the wafers used to form the bonded wafer structure is defective, the entire bonded wafer structure may also be defective and may need to be discarded. This can significantly reduce productivity and increase the costs associated with fabricating the bonded wafer structure.

[0018] Accordingly, a method for fabricating a bonded wafer structure is required, which enables improved testing of individual wafers prior to wafer stacking and bonding to form a bonded wafer structure. Various embodiments disclosed herein include forming an array of contact pads in the interconnect layers of the wafers before stacking and bonding wafers to one or more additional wafers to form a bonded wafer structure. In some embodiments, the contact pad array may have an array pattern corresponding to a contact pad array pattern subsequently formed on the bonded wafer structure. This allows for more comprehensive testing of individual wafers prior to forming the bonded wafer structure, including circuit probe testing, which enables earlier identification of defective wafers, improved yield, and lower cost of fabricating the bonded wafer structure.

[0019] Figures 1A to 6B and Figures 10A to 30 are sequential vertical cross-sectional views of exemplary structures during the fabrication process of forming a bonded wafer device structure, such as a WoW structure, according to various embodiments of the present disclosure. The bonded wafer device structure may comprise a plurality of wafers, each wafer comprising device structures and interconnection structures formed on a substrate. Wafers may be vertically stacked and bonded together to form an integrated bonded wafer device structure. In some embodiments, a plurality of contact pads may be formed on at least one substrate of the bonded wafer device structure. In some embodiments, the bonded wafer device structure may be monolithized (e.g., diced) to provide a plurality of integrated circuit (IC) wafers. Although the exemplary embodiments illustrated in Figures 1A to 6B and Figures 10A to 30 illustrate a process for forming a bonded wafer device structure having two wafers, various bonded wafer device structures comprising more than two wafers and methods for forming such structures are also within the scope of the disclosure considered.

[0020] Figure 1A is a vertical cross-sectional view of a portion of a first wafer 100 according to various embodiments of the present disclosure, and Figure 1B is a vertical cross-sectional view of a portion of a second wafer 200. Referring to Figures 1A and 1B, the first wafer 100 and the second wafer 200 may each include substrates 110 and 210, a plurality of element structures 112 and 212, and a plurality of interconnection structures located on or above a first surface 30 of the substrates 110 and 210, including elements 111, 211, 113, 213, 115, 215, 117, and 217.

[0021] Each of the first substrate 110 and the second substrate 210 may be a semiconductor material substrate, which may include elemental semiconductors such as silicon or germanium and / or compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide, or combinations thereof. Other semiconductor substrate materials are within the scope of the disclosure considered. In some embodiments, the first substrate 110 and / or the second substrate 210 may be a semiconductor-on-insulator (SOI) substrate. In some embodiments, at least one of the first substrate 110 and the second substrate 210 may be a support substrate made of quartz, glass, or the like. In various embodiments, the first substrate 110 and the second substrate 210 may contain the same material or may contain different materials.

[0022] In various embodiments, the first substrate 110 and / or the second substrate 210 may take the form of a planar substrate, a substrate having multiple fin structures, a nanowire substrate, or other forms known to those skilled in the art. Depending on design requirements, the first substrate 110 and / or the second substrate 210 may be a P-type semiconductor substrate or an N-type semiconductor material substrate, and may have doped regions therein. The doped regions may be configured for N-type devices or P-type devices.

[0023] The first substrate 110 and the second substrate 210 may each include a first main surface (i.e., front side 30) and a second main surface (i.e., back side 40). In some embodiments, the first substrate 110 and / or the second substrate 210 may include an isolation structure defining at least one active region on the front side 30 of the substrates 110 and 210, and a first device level (DL) DL may be disposed on / in the active region. The first device level DL may include various types of components 112 and 212. In some embodiments, components 112 and 212 may include active components, passive components, or combinations thereof. In some embodiments, components 112 and 212 may include integrated circuit elements. Components 112 and 212 may be, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse elements, or other similar elements. In some embodiments, the first device level DL may include gate electrodes, source / drain regions, spacers, and the like.

[0024] The first substrate 110 and the second substrate 210 may each further include interconnect structures located on the front side 30 of the substrates 110 and 210. Each interconnect structure may include dielectric materials 111 and 211 and metal features 115, 215, 117, and 217. The dielectric materials may include at least one inter-layer dielectric (ILD) layer and / or at least one inter-metal dielectric (IMD) layer. The metal features 115, 215, 117, and 217 may be at least partially located in the dielectric materials 111 and 211. The dielectric materials 111 and 211 may be formed of dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), or similar dielectric materials. Other dielectric materials are within the scope of the disclosure considered. The dielectric materials 111 and 211 may be deposited using any suitable deposition process. In this article, "suitable deposition process" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, or similar processes.

[0025] The metallic features of the interconnect structure may include any of various via structures 117, 217 and metallic lines 115, 215. The metallic features may be formed of any suitable conductive material, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, combinations thereof, or the like. Other conductive materials are within the scope of the disclosure considered. In some embodiments, a barrier layer (not shown) may be disposed between the metallic features and the dielectric material 111 to prevent material from diffusing from the metallic features 115, 215, 117, 217 to surrounding features. The barrier layer, for example, may comprise Ta, TaN, Ti, TiN, CoW, or combinations thereof. Other barrier layer materials are within the scope of the disclosure considered.

[0026] Metal features 115, 215, 117, 217 can be configured to deliver electrical signals to and / or between various elements 112, 212, and / or between wafers 100, 200, some or all of which may be located on a first element layer DL. In various embodiments, the interconnect structure of each wafer 100, 200 may include a plurality of interconnect layer structures, wherein each interconnect layer structure may include dielectric material layers 111, 211, and a plurality of metal lines 115, 117 formed in the dielectric material layers 111, 211. As illustrated in Figures 1A and 1B, for example, the interconnect structure of each wafer 100, 200 may include a plurality of metal layers (such as metal layers M1, M2, M3, etc.), wherein each metal layer may include a plurality of metal lines 115 embedded in the dielectric material 111. The first metal layer M1 may be located above the first element layer DL. Multiple component contact via structures 113, 213 can electrically connect components 112, 212 of the first component layer DL to metal lines 115, 215 of the first metal layer M1. Additional metal layers M2, M3, etc., can be located above the first metal layer M1. Each metal layer can be separated by dielectric material layers 111, 211. Via structures 117, 217 can extend through the dielectric material layers 111, 211 to electrically connect metal lines 115, 215 of different metal layers. Although the wafers 100, 200 illustrated in Figures 1A and 1B include an interconnection structure with three metal layers M1, M2, M3, it should be understood that the interconnection structure according to various embodiments may have more or fewer metal layers. Furthermore, although the first wafer 100 and the second wafer 200 include interconnect structures having the same number of metal layers in the various exemplary embodiments illustrated herein, it will be understood that the interconnect structures of the first wafer 100 and the second wafer 200 may have different numbers of metal layers.

[0027] Figures 2A to 6B are sequential side cross-sectional views illustrating the processes of forming a top metal level (TM) on a first wafer 100 and a second wafer 200, respectively. In various embodiments, the top metal level TM of at least one of the first wafer 100 and the second wafer 200 may be formed to include an array of top metal contact pads. In embodiments, the top metal contact pads may have an array pattern corresponding to a contact pad array pattern subsequently formed on a wafer device structure comprising the first wafer 100 and the second wafer 200. The top metal contact pad array enables improved wafer testing processes, including circuit probe testing of individual wafers before bonding them to form a bonded wafer device structure. This provides early detection of defects or other non-conforming wafers and reduces the risks and costs associated with the fabrication of the bonded wafer devices.

[0028] Referring to Figures 2A and 2B, dielectric material layers 121 and 221 can be deposited on each upper surface of the respective wafers 100 and 200. Dielectric material layers 121 and 221 can be deposited on the uppermost metal layer (e.g., M3) of the interconnect structure of each wafer 100 and 200, including the upper surfaces of dielectric materials 111 and 211 and the exposed upper surfaces of the metal lines 115 of the uppermost metal layer M3. Each dielectric material layer 121 and 221 can contain a suitable dielectric material, such as silicon oxide, silicon nitride, etc., and can be deposited using the suitable deposition process described above.

[0029] Referring again to Figures 2A and 2B, additional patterned masks 122 and 222 can be formed on the upper surfaces of the respective dielectric material layers 121 and 221 on each of the first wafer 100 and the second wafer 200. Each patterned mask 122 and 222 can be photolithographically patterned to form openings through the mask 122 and 222. The openings may correspond to patterns of via openings that may subsequently be formed through the respective dielectric material layers 121 and 221. In some embodiments, the mask 122 formed on the dielectric material layer 121 on the first wafer 100 may have an opening pattern consistent with the pattern of the openings of the mask 222 formed on the dielectric material layer 221 on the second wafer 200. Alternatively, the mask 122 formed on the dielectric material layer 121 on the first wafer 100 may have a different opening pattern than the mask 222 formed on the dielectric material layer 221 on the second wafer 200.

[0030] Figure 3A is a vertical cross-sectional view of a portion of the first wafer 100, illustrating a via structure formed in the dielectric material layer 121, and Figure 3B is a vertical cross-sectional view of a portion of the second wafer 200, illustrating a via structure 217 formed in the dielectric material layer 221. Referring to Figures 3A and 3B, an anisotropic etching process can be performed on each patterned mask 122, 222 to remove portions of the dielectric material layers 121, 221 and form via openings 116, 216 through the dielectric material layers 121, 221. The via openings 116, 216 can expose the surface of metal features (e.g., metal lines 115, 215) in the underlying metal layer (e.g., M3). The patterned masks 122, 222 can then be removed by a suitable process, such as by ashing or by solvent dissolution (see Figures 2A and 2B).

[0031] Referring again to Figures 3A and 3B, additional patterned masks 123 and 223 may be formed on the upper surfaces of the respective dielectric material layers 121 and 221 on each of the first wafer 100 and the second wafer 200. Each patterned mask 123 and 223 may be photolithographically patterned to form openings through the mask 123 and 223. The openings may correspond to patterns of trench openings that may subsequently be formed within the respective dielectric material layers 121 and 221. The trench openings may correspond to the locations of metal features subsequently formed in the top metal layer TM of each of the respective wafers 100 and 200. As further discussed later, the top metal layer TM of at least one of the first wafer 100 and the second wafer 200 may include a top metal contact pad array. In an embodiment, the top metal contact pads may have an array pattern corresponding to a contact pad array pattern that is subsequently formed on a wafer element structure comprising the bonding of the first wafer 100 and the second wafer 200.

[0032] In some embodiments, the mask 123 formed over the dielectric material layer 121 on the first wafer 100 may have an opening pattern consistent with the pattern of the openings in the mask 223 formed over the dielectric material layer 221 on the second wafer 200. Alternatively, the mask 123 formed over the dielectric material layer 121 on the first wafer 100 may have a different opening pattern than the mask 223 formed over the dielectric material layer 221 on the second wafer 200.

[0033] Figure 4A is a vertical cross-sectional view of a portion of a first wafer 100, which includes a plurality of trench openings 126 formed in a dielectric material layer 121, and Figure 4B is a vertical cross-sectional view of a portion of a second wafer 200, which includes a plurality of trench openings 226 formed in a dielectric material layer 221. Referring to Figures 4A and 4B, an anisotropic etching process can be performed on each patterned mask 123, 223 to remove a portion of the dielectric material layers 121, 221 and form trench openings 126, 226 within the dielectric material layers 121, 221. In an embodiment, each trench opening 126, 226 may be located above one or more via openings 116, 216. The patterned masks 123, 223 can then be removed by a suitable process, such as by ashing or by solvent dissolution.

[0034] Figure 5A is a vertical cross-sectional view of a portion of a first wafer 100, which includes a metal layer 125 deposited and filled with a plurality of trench openings 126 and via openings 116 on the upper surface of a dielectric material layer 121. Figure 5B is a vertical cross-sectional view of a portion of a second wafer 200, which includes a metal layer 225 deposited and filled with a plurality of trench openings 226 and via openings 216 on the upper surface of a dielectric material layer 221. Referring to Figures 5A and 5B, layers 125 and 225 of suitable conductive materials such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, combinations thereof, or the like can be used to deposit the first metal layer on the upper surface of the dielectric material layers 121 and 221 and within the trench openings 126 and 226 and the via openings 116 and 216. Other suitable metal materials are within the scope of the disclosure considered. In some embodiments, a barrier layer (not shown) composed of a suitable barrier material as described above may first be deposited on the upper surface of the dielectric material layers 121, 221 and within the trench openings 126, 226 and via openings 116, 216, and a metal material layer 125, 225 may be deposited on the barrier layer. The metal material layers 125, 225 and the barrier layer (if present) may be deposited using a suitable deposition process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or one or more of the like. Other suitable deposition processes are within the scope of the disclosure considered.

[0035] Figure 6A is a vertical cross-sectional view of a portion of the first wafer 100, illustrating a plurality of metal features 119 and via structures 117 embedded in the dielectric material layer 121, and Figure 6B is a vertical cross-sectional view of a portion of the second wafer 200, illustrating a plurality of metal features 219 and via structures 217 embedded in the dielectric material layer 221. Referring to Figures 6A and 6B, each of the first and second wafers 100 and 200 may undergo a planarization process, such as a chemical mechanical planarization (CMP) process, to remove metal material layers 125 and 225 and barrier material (if present) from above the upper surfaces of the dielectric material layers 121 and 221. The remaining metal material layers 125 and 225 located within the trench openings 126 and 226 and the via openings 116 and 216 may form metal features 119 and 219 and via structures 117 and 217 embedded in the respective dielectric material layers 121 and 221. Metal features 119 and 219 may form the top metal layer TM of the interconnection structure of the first wafer 100 and the second wafer 200. Each metal feature 119 and 219 may have an exposed upper surface and may be connected to the metal features of the lower metal layer (e.g., M3) via one or more via structures 117 and 219.

[0036] As mentioned above, the metal features 119, 219 of the top metal layer TM of at least one of the first wafer 100 and the second wafer 200 may include an array of contact pads. This array of contact pads enables circuit probe testing of the first and second wafers 100, 200 prior to the bonding of the first and second wafers 100, 200 to form a bonded wafer structure, as further described below. Figures 7A and 7B are top views of portions of the first wafer 100 and the second wafer 200, respectively, schematically illustrating the top metal layer TM of the first and second wafers 100, 200 according to an embodiment. As illustrated in Figures 7A and 7B, at least a portion of the metal features 119, 219 of the top metal layer TM of the first and second wafers 100, 200 is in the form of an array of contact pads 127, 227. The contact pads 127, 227 may have a size sufficient to enable circuit probe testing of the first and second wafers 100, 200. In embodiments, an automated wafer prober system can be used to perform circuit probe testing on first and second wafers 100, 200. The wafer prober system can align the first and second wafers 100, 200 on a probe system (e.g., using optical pattern recognition) and electrically contact a plurality of contact elements with contact pads 127, 227 of the first and second wafers 100, 200. In various embodiments, the contact elements may be located on probe cards mounted to the wafer prober system. In various embodiments, each contact pad 127, 227 may have a length and width dimension of at least about 40 μm (i.e., along the x-axis and y-axis directions in Figures 7A and 7B), such as between about 40 μm and about 100 μm. Circuit probe testing may include applying an electrical signal test pattern to first and second wafers 100 and 200 via contact pads 127 and 227, detecting the electrical responses from the first and second wafers 100 and 200, and determining whether the first and second wafers 100 and 200 contain functional defects based on the detected responses to the test pattern. Based on circuit probe testing, the first and second wafers 100 and 200 can be classified so that wafers without defects can be used to form a bonded wafer structure.

[0037] In various embodiments, at least some wafers with top metal contact pads may be formed, these top metal contact pads comprising an array pattern corresponding to a contact pad array pattern subsequently formed on a bonded wafer element structure comprising multiple stacked and bonded wafers. This allows the same circuit probe test elements (e.g., probe cards) used for testing assembled bonded wafer elements to also be used to identify defective or other non-conforming wafers at an earlier stage of the fabrication process. FIG8A is a top view of a portion of a bonded wafer structure 300 according to an embodiment of the present disclosure, schematically illustrating the contact pad array 19 of the bonded wafer structure 300, and FIG8B is a top view of a portion of the top metal layer TM of a second wafer 200, schematically illustrating an array of top metal contact pads 227. Referring to FIG8A and 8B, the pattern of the contact pad array 19 of the bonded wafer structure 300 may correspond to the array pattern of the top metal contact pads 227 of the second wafer 200. In various embodiments, when the spatial coordinates of the geometric center point C of each contact pad 19 of the contact pad array pattern of the bonded wafer structure 300 (e.g., contact pads 19-1 to 19-8 in FIG. 8A) and the geometric center point C of the top metal contact pad 227 array pattern of the wafer 200 (e.g., contact pads 227-1 to 227-8 in FIG. 8B) spatially coincide, the contact pad array of the bonded wafer structure 300 can be considered to correspond to the top metal contact pad 227 array of the wafer 200. The spatial coordinates of the corresponding center point C can be relative to a common reference architecture. In the illustrative embodiments shown in FIG. 8A and 8B, for example, when viewed from above, the spatial coordinates are relative to the origin O(x,y) located at the upper left corner of both the depicted portion of the bonded wafer structure 300 and the depicted portion of the second wafer 200. As used in this paper, two contact pads can be considered to coincide when the difference between their geometric center points in the spatial coordinates of the two contact pads does not exceed 5 μm in the spatial coordinates along the x-axis or y-axis within the common reference architecture.

[0038] In various embodiments, the top metal contact pads 227 of the second wafer 200 may have the same size and shape as the corresponding contact pads 19 of the bonded wafer structure 300, or at least some of the top metal contact pads 227 of the second wafer 200 may have a different size and / or shape than the corresponding contact pads 19 of the bonded wafer structure 300. As illustrated in Figures 8A and 8B, for example, top metal contact pads 227-4 have the same size and shape as the corresponding contact pads 19-4 of the bonded wafer structure 300 in the horizontal xy plane. Top metal contact pads 227-8 have a different size than the corresponding contact pads 19-8 of the bonded wafer structure 300. In particular, top metal contact pads 227-8 have a length dimension L2 smaller than the length dimension L1 of contact pads 19-8. In various embodiments, the length dimension L of each top metal contact pad 227 of the second wafer 200 in the horizontal xy plane may be at least about 40 μm, such as between about 40 μm and about 100 μm.

[0039] Figure 8C illustrates a vertical cross-sectional view of the contact pads 19-4 and 19-8 of the bonded wafer structure 300 and the top metal contact pads 227-4 and 227-8 of the second wafer 200. Referring to Figures 8A to 8C, regardless of whether the contact pads 19-4 and 19-8 and the top metal contact pads 227-4 and 227-8 have the same size and shape, the geometric center points C4 and C8 of the corresponding pairs of contact pads 19-4 and 19-8 and the top metal contact pads 227-4 and 227-8 can coincide (±5 μm). Furthermore, although the contact pads 19-4 and 19-8 and the top metal contact pads 227-4 and 227-8 illustrated in this embodiment have the same thickness, it should be understood that the thicknesses of the pads 19-4 and 19-8 and the top metal contact pads 227-4 and 227-8 can be different.

[0040] Referring again to Figure 8B, the top metal contact pad 227 may comprise a solid contact pad without internal openings, as illustrated in contact pads 227-2 to 227-8. Alternatively, at least a portion of the top metal contact pad 227 may be a slotted contact pad having openings through it, such as the contact pad illustrated in top metal contact pad 227-1. In various embodiments, the slotted contact pad design, as illustrated in contact pad 227-1, can reduce stress on the contact pad and surrounding features of the wafer.

[0041] Figure 9 is a top view of a portion of the second wafer 200, illustrating a top metal feature 219 with contact pad regions 127 according to an embodiment of the present disclosure. Referring to Figure 9, in various embodiments, top metal features 119, 219 of the top metal layers TM of the first and second wafers 100, 200 may include contact pad regions 127 and one or more second regions 129. Contact pad regions 127 and one or more second regions 129 may be adjacent, non-overlapping portions of the top metal feature 219 and may be laterally surrounded by a dielectric material layer 221 as illustrated in Figure 9. The contact pad regions 127 of the top metal feature 219 may have length and width dimensions suitable for circuit probe testing of the top metal feature 219. In embodiments, the length and width dimensions of the contact pad regions 127 may be at least about 40 μm, such as between 40 μm and 100 μm. Typically, the contact pad region 127 is large enough to enable effective electrical contact between the contact pad region 127 and contact elements (e.g., probe marks) of the wafer probe system. In embodiments, the contact pad region 127 may not be large enough to trigger an antenna effect that could damage components on the first and second wafers 100, 200. The length and width dimensions of one or more second regions 129 may differ from the dimensions of the contact pad region 127. For example, one or more second regions 129 may have at least one dimension less than about 40 μm and at least one dimension greater than about 100 μm. In the embodiment illustrated in FIG9, each metal feature 219 of the top metal layer TM includes a contact pad region 127 and a second region 129 that can be elongated similarly to conventional metal wires.

[0042] In various embodiments, as illustrated in FIG9, a top metal feature 219 comprising contact pad regions 127 and one or more second regions 129 can be used to deliver electrical signals from lower layers (e.g., M1 to M3) of the interconnect structure to a bonding layer that may subsequently be formed on a top metal layer TM of a second wafer 200, and ultimately to an adjacent wafer (e.g., a first wafer 100) in the bonded wafer structure. Since circuit probe testing in the contact pad regions 127 of the metal feature 219 may result in a change in the topology of the conductive material in the contact pad regions 127, in various embodiments, electrical connections between the metal feature 219 and the subsequently formed bonding layer can be made in one or more second regions 129. This helps ensure the establishment of effective electrical connections. FIG9 schematically illustrates a contact region 231 in the second region 129 of the top metal feature 219. In an embodiment, contact region 231 may be the location of a subsequently formed conductive material (e.g., a hybrid bonding material) to electrically connect the top metal feature 219 to an upper layer of wafer 200, such as bonding layer BL, which is further described below.

[0043] Figures 10A to 15 are sequential side cross-sectional views illustrating the process of forming a bonding layer BL on each of the first and second wafers 100 and 200, and bonding the first and second wafers 100 and 200 to form a bonded wafer structure 300. Referring to Figures 10A and 10B, dielectric material layers 133 and 233 can be deposited on the upper surface of each wafer 100 and 200. Dielectric material layers 133 and 233 can be deposited on the top metal layer TM of the interconnection structure of each wafer 100 and 200, including the upper surface of dielectric material layers 121 and 221 and the exposed upper surface of the metal features 119 and 219 of the top metal layer TM. Each dielectric material layer 133 and 233 can contain a suitable dielectric material, such as silicon oxide, silicon nitride, etc., and can be deposited using the suitable deposition process described above. In various embodiments, dielectric layers 133, 233 may comprise silicon oxynitride (SiOxNy). Other suitable dielectric materials are within the scope of the disclosure considered.

[0044] Referring again to Figures 10A and 10B, additional patterned masks 137 and 237 may be formed on the upper surfaces of the respective dielectric material layers 133 and 233 on each of the first wafer 100 and the second wafer 200. Each patterned mask 137 and 237 may be photolithographically patterned to form openings through the mask 137 and 237. The openings may correspond to patterns that may subsequently be formed through the respective dielectric material layers 133 and 233. In various embodiments, the openings through the masks 137 and 237 may correspond to the positions of metal features 119 and 219 in the top metal layer TM of the first and second wafers 100 and 200.

[0045] Figure 11A is a vertical cross-sectional view of a portion of a first wafer 100, which includes an opening 138 formed through a dielectric material layer 133 to expose a portion of the top metal layer TM. Figure 11B is a vertical cross-sectional view of a portion of a second wafer 200, which includes an opening 238 formed through a dielectric material layer 233 to expose a portion of the top metal layer TM. Referring to Figures 11A and 11B, an anisotropic etching process can be performed through each patterned mask 137, 237 to remove a portion of the dielectric material layers 133, 233 and form openings 138, 238 through the dielectric material layers 133, 233. The openings 138, 238 can expose the surfaces of the metal features 119, 219 in the underlying top metal layer TM. The patterned masks 137, 237 can then be removed by a suitable process, such as by ashing or by solvent dissolution (see Figures 10A and 10B).

[0046] Referring again to Figures 11A and 11B, additional patterned masks 140 and 240 may be formed on the upper surfaces of the respective dielectric material layers 133 and 233 on each of the first wafer 100 and the second wafer 100. Each patterned mask 140 and 240 may be photolithographically patterned to form an opening through the mask 140 and 240. The opening may correspond to a pattern of trench openings that may subsequently be formed within the respective dielectric material layers 133 and 233. The trench openings may then be filled with bonding material that can be used to bond the first wafer 100 and the second wafer 200 to form a bonded wafer structure 300.

[0047] Figure 12A is a vertical cross-sectional view of a portion of a first wafer 100, which includes a plurality of trench openings 142 formed in a dielectric material layer 133, and Figure 12B is a vertical cross-sectional view of a portion of a second wafer 200, which includes a plurality of trench openings 242 formed in a dielectric material layer 233. Referring to Figures 12A and 12B, an anisotropic etching process can be performed on each patterned mask 140, 240 to remove a portion of the dielectric material layers 121, 221 and form trench openings 142, 242 within the dielectric material layers 133, 233. In an embodiment, at least some of the trench openings 142, 242 may be located above one or more openings 138, 238. The patterned masks 140, 240 can then be removed by a suitable process, such as by ashing or by solvent dissolution.

[0048] Figure 13A is a vertical cross-sectional view of a portion of a first wafer 100, which includes a bonding material layer 139 deposited and filled with a plurality of trench openings 142 and 138 on the upper surface of a dielectric material layer 133. Figure 13B is a vertical cross-sectional view of a portion of a second wafer 200, which includes a bonding material layer 239 deposited and filled with a plurality of trench openings 242 and 238 on the upper surface of a dielectric material layer 233. Referring to Figures 13A and 13B, the bonding material layers 139 and 239 may comprise a conductive material, which can serve as a bonding medium to mechanically bond the first wafer 100 to the second wafer 200 and also allow electrical signals to be delivered between the first wafer 100 and the second wafer 200. In various embodiments, the bonding material layers 139 and 239 may be metallic materials, such as copper, copper alloys, tungsten (W), aluminum (Al), aluminum alloys, combinations thereof, or the like. Other suitable bonding materials are within the scope of the disclosure considered. In some embodiments, a barrier layer (not shown) consisting of a suitable barrier material as described above may first be deposited on the upper surface of the dielectric material layers 133, 233 and within the trench openings 142, 242 and the via openings 138, 238, and bonding material layers 139, 239 may be deposited on the barrier layer. The bonding material layers 139, 239 and the barrier layer (if present) may be deposited using suitable deposition processes, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or one or more of the like. Other suitable deposition processes are within the scope of the disclosure considered.

[0049] Figure 14A is a vertical cross-sectional view of a portion of a first wafer 100 according to an embodiment of the present disclosure. The first wafer 100 includes a plurality of bonding pads 141 and bonding connection portions 143 embedded within a dielectric material layer 133. Figure 14B is a vertical cross-sectional view of a portion of a second wafer 200, which includes a plurality of bonding pads 241 and bonding connection portions 243 embedded within a dielectric material layer 233. Referring to Figures 14A and 14B, each of the first wafer 100 and the second wafer 200 may undergo a planarization process, such as a chemical mechanical planarization (CMP) process, to remove bonding material layers 139 and 239 and barrier material (if present) from above the upper surfaces of the dielectric material layers 133 and 233. The remaining portions of the bonding materials 139, 239 located within the trench openings 142, 242 and openings 138, 238 may form bonding pads 141, 241 and bonding connection portions 143, 243 embedded in the respective dielectric material layers 133, 233. Bonding pads 141, 241 may form a bonding layer BL on each of the first wafer 100 and the second wafer 200. Each bonding pad 141, 241 may have an exposed upper surface and may be laterally surrounded by the respective dielectric material layers 133, 233. At least a portion of the bonding pads 141, 241 may be connected to the metal features 119, 219 of the upper metal layer TM of the lower layer by one or more bonding connection portions 143, 243.

[0050] Figure 15 is a vertical cross-sectional view of a wafer structure 300 including a first wafer 100 bonded to a second wafer 200, according to an embodiment of the present disclosure. In various embodiments, a hybrid bonding technique can be used to bond the first wafer 100 to the second wafer 200. Referring to Figure 15, in various embodiments, the surface energy of the first and second wafers 100, 200 is pretreated to promote surface activation (e.g., using a plasma processing process). The first wafer 100 can be flipped (e.g., inverted) and stacked on the second wafer 200 such that the bonding layer BL of the first wafer 100 faces the bonding layer BL of the second wafer 200. The first wafer 100 and the second wafer 200 can be aligned such that the bonding pad 141 of the first wafer 100 contacts the corresponding bonding pad 241 of the second wafer 200. The stack of the first and second wafers 100, 200 can then be annealed at an elevated temperature. The bonding process can cause a diffusion bond to be formed between the bonding pad 141 of the first wafer 100 and the corresponding bonding pad 241 of the second wafer 200.

[0051] Figures 16 to 29 are sequential side cross-sectional views illustrating, according to an embodiment of the present disclosure, the process of forming a contact pad array 19 on a bonded wafer structure 300. Referring to Figure 16, the back side 40 of the first substrate 110 of the first wafer 100 can be processed using suitable processes, such as mechanical polishing, chemical mechanical planarization (CMP), or thinning by etching. A patterned mask 301 can be formed on the back side 40 of the first substrate 100. The patterned mask 301 can be photolithographically patterned to form openings through the mask 301. The openings can correspond to patterns of through-substrate vias subsequently formed on the first substrate 110.

[0052] Figure 17 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure. The bonded wafer structure 300 includes a plurality of via openings 302 formed through a first substrate 110 and a dielectric material 111 of a first wafer 100 to expose a portion of a metal feature 115. Referring to Figure 17, an anisotropic etching process can be performed using a patterned mask 301 to remove a portion of the first substrate 110 and the dielectric material 111 of the first wafer 100 and to form via openings 302 through the back side of the first wafer 100. Each via opening 302 can expose the surface of a metal feature, such as the metal lines 115 of the interconnect structure of the first wafer 100. After the etching process, the patterned mask 301 can be removed by a suitable process, such as by ashing or by solvent dissolution.

[0053] Figure 18 is a vertical cross-sectional view of a joined wafer structure 300 according to an embodiment of the present disclosure. The wafer structure 300 includes a liner material layer 303 on the sidewalls of a plurality of openings 302 formed by dielectric material 111 of a first substrate 110 and a first wafer 100. The plurality of openings 302 are formed by dielectric material 111 of the first substrate 110 and the first wafer 100. Referring to Figure 18, the liner material layer 303 can be deposited shaped on the back side 40 of the first substrate 110 and along the sidewalls and bottom surface of each opening 302. In an embodiment, an anisotropic etching process can remove the horizontally extended portion of the liner material layer 303 while retaining the liner material layer 303 on the sidewalls of the openings 302. The liner material layer 303 may contain a suitable dielectric material, such as an oxide material (e.g., SiO2) deposited using a suitable deposition process. Other suitable dielectric materials for the liner material layer 303 are within the scope of the disclosure considered. The lining material layer 303 helps maintain the voltage bias between the via structure formed subsequently within the opening 302 through the substrate and the surrounding semiconductor material of the first substrate 110.

[0054] Figure 19 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure. The bonded wafer structure includes a conductive material layer 305 deposited on the back side 40 of a first substrate 110 of a first wafer 100 and within a plurality of openings 302 in the first wafer 100. Referring to Figure 19, the conductive material layer 305 may comprise a metallic material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, tungsten (W), combinations thereof, or the like, which may be deposited on the back side 40 of the first substrate 110 of the first wafer 100 and within the openings 302 in the first wafer 100. Other suitable conductive materials are within the scope of the disclosure considered. The conductive material layer 305 may be deposited using suitable deposition processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or one or more of the like. Other suitable deposition processes are within the scope of the disclosure considered.

[0055] Figure 20 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, including a plurality of conductive vias 307 through the substrate formed in a first wafer 100. Referring to Figure 20, the bonded wafer structure 300 may undergo a planarization process, such as chemical mechanical planarization (CMP), to remove a conductive material layer 305 from the back side 40 of the first substrate 110. The remaining conductive material within openings 302 in the first wafer 100 may form conductive vias 307 through the substrate. Each conductive via 307 through the substrate may have an exposed upper surface and may be electrically connected to a metal feature (e.g., metal line 115) in a metal layer (e.g., M1) of the interconnection structure of the first wafer 100.

[0056] Figure 21 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including dielectric material layers 308 and 309 deposited on the back side 40 of a first substrate 110 of a first wafer 100. Referring to Figure 21, dielectric material layer 308 can be deposited on the back side 40 of the first substrate 110 and on the exposed surface through the conductive vias 307 of the substrate using a suitable deposition method. Dielectric material layer 309 can then be deposited on the upper surface of dielectric material layer 308 using a suitable deposition method. In an embodiment, dielectric material layers 308 and 309 may be passivation films for stress and / or moisture protection. In one embodiment, dielectric material layer 308 may comprise a nitride material such as silicon nitride, and dielectric material layer 309 may comprise an oxide material such as silicon oxide. Other suitable dielectric materials are within the scope of the disclosure considered.

[0057] Figure 22 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure. The bonded wafer structure 300 includes a patterned mask 313 formed on the upper surface of a dielectric material layer 309 on the back side 40 of a first substrate 110 of a first wafer 100. Referring to Figure 22, the patterned mask 313 can be photolithographically patterned to form openings through the mask 313. The openings may correspond to the locations of conductive vias 307 through the substrate beneath the dielectric material layers 308 and 309.

[0058] Figure 23 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure. The bonded wafer structure 300 includes a plurality of openings 312 formed through dielectric material layers 308 and 309 to expose the upper surface of conductive vias 307 through the substrate. Referring to Figure 23, an anisotropic etching process can be performed using a patterned mask 313 to remove portions of the dielectric material layers 308 and 309 and form openings 312 through the dielectric material layers 308 and 309. Each of the openings 312 exposes the upper surface of a corresponding contact via 307 through the substrate. After the etching process, the patterned mask 313 can be removed by a suitable process, such as by ashing or by solvent dissolution.

[0059] Figure 24 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including a conductive material layer 315 deposited on the upper surface of a dielectric material layer 309 and through openings 312 in dielectric material layers 308 and 309. Referring to Figure 24, the conductive material layer 315 is deposited on the upper surface of the dielectric material layer 309 and on the sidewalls and bottom surfaces of the openings 312 in dielectric material layers 308 and 309. The conductive material layer 315 may contact the exposed surface of a conductive via 307 through the substrate at the bottom of each opening 312. In various embodiments, the conductive material layer 315 may comprise a metallic material, such as copper (Cu), copper alloys, aluminum (Al), aluminum alloys, tungsten (W), and combinations thereof. Other conductive materials are within the scope of the disclosure considered. A conductive material layer 315 may be deposited using a suitable deposition process, which may include one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or the like. Other suitable deposition processes are within the scope of the disclosure considered.

[0060] Figure 25 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including a patterned mask 317 on a conductive material layer 315. Referring to Figure 25, the patterned mask 317 may be photolithographically patterned to form openings through the mask 317. The mask 317 may cover portions of the conductive material layer 315 corresponding to locations on which contact pads may subsequently be formed.

[0061] Figure 26 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure including an array of contact pads 19 of the bonded wafer structure 300 located on the back side 40 of a first substrate 110 of a first wafer 100. Referring to Figure 26, an anisotropic etching process can be performed by a patterned mask 313 to remove a portion of the conductive material layer 315 from above the dielectric material layer 309. The remaining portion of the conductive material layer 315 can be formed into discrete contact pads 19 on the back side 40 of the first substrate 110. After the etching process, the patterned mask 313 can be removed by a suitable process, such as by ashing or by solvent dissolution.

[0062] Figure 27 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including dielectric material layers 310 and 311 deposited on the back side 40 of the first substrate 110 of the first wafer structure 100 and on the contact pad array 19 of the bonded wafer structure 300. Referring to Figure 27, dielectric material layer 310 may be deposited morphologically on dielectric material layer 309 and on contact pad array 19, including on the side and top surfaces of each contact pad 19. Dielectric material layer 311 is then deposited on the top surface of dielectric material layer 310. In embodiments, dielectric material layers 310 and 311 may be additional passivation films for stress and / or moisture protection. In one embodiment, dielectric material layer 310 may comprise an oxide material such as silicon nitride, and dielectric material layer 311 may comprise a nitride material such as silicon oxide. Other suitable dielectric materials are within the scope of the disclosure considered.

[0063] Figure 28 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including a patterned mask 321 formed over dielectric material layers 309 and 310. Referring to Figure 28, the patterned mask 321 may be photolithographically patterned to form openings through the mask 321. The openings may expose portions of the dielectric material layer 309 located above the central region of each contact pad 19. The mask 321 may cover portions of the dielectric material layer 309 located above the peripheral region of the contact pad 19.

[0064] Figure 29 is a vertical cross-sectional view of a bonded wafer structure 300 according to an embodiment of the present disclosure, the bonded wafer structure 300 including openings in the form of dielectric material layers 310 and 311 to expose corresponding contact surfaces of the contact pad array 19 of the bonded wafer structure 300. Referring to Figure 29, an anisotropic etching process can be performed using a patterned mask 321 to remove portions of the dielectric material layers 310 and 311 from above the upper surface of the contact pads 19 to expose the contact surfaces of the contact pads 19. The dielectric material layers 310 and 311 may remain on the side surfaces and peripheral regions of the upper surface of the contact pads 19, as illustrated in Figure 29. After the etching process, the patterned mask 321 may be removed by a suitable process, such as by ashing or by solvent dissolution. As discussed above, in various embodiments, the contact pad array 19 pattern of the bonded wafer structure 300 may correspond to the top metal contact pad array pattern 127, 227 in the interconnection structure of at least one of the first and second wafers 100, 200 in the bonded wafer structure 300 (see Figures 7A and 7B).

[0065] Figure 30 is a flowchart illustrating the steps of a method 400 for forming a bonded wafer structure 300 according to various embodiments of the present disclosure. Referring to Figures 1A, 1B, and 30, in step 402 of method 400, a first wafer (100, 200) may be provided, the first wafer (100, 200) including component structures (112, 212) and interconnect structures (111, 211, 113, 213, 115, 215, 117, 217) on the substrate (110, 210). Referring to Figures 2A to 9, in step 404 of method 400, an array of top metal contact pads (127, 227) may be formed in the top metal layer (TM) of the interconnect structure of the first wafer (100, 200). In an alternative step 406 of method 400, the array of top metal contact pads (127, 227) may be used for circuit probe testing of the first wafer (100, 200).

[0066] Referring to Figures 10A to 14B, in step 408 of method 400, a bonding layer (BL) may be formed over the array of top metal contact pads (127, 227) on the first wafer (100, 200). Referring to Figures 15 and 30, in step 410 of method 400, the first wafer (100, 200) may be bonded to the second wafer (100, 200) to form a bonded wafer structure (300). Referring to Figures 16 to 30, in step 412 of method 400, a contact pad array (19) may be formed over the surface (40) of the bonded wafer structure (300), wherein the pattern of the contact pad array (19) formed over the surface (40) of the bonded wafer structure (300) corresponds to the array pattern of the top metal contact pads (127, 227) formed in the top metal layer (TM) of the interconnection structure of the first wafer (100, 200).

[0067] Referring to all the accompanying drawings and various embodiments according to the present disclosure, the bonded wafer structure 300 includes a first wafer 100 having a first substrate 110, a first element structure 112, and a first interconnection structure (111, 113, 115, 117, 119), a second wafer 200 having a second substrate 210, a second element structure 212, and a second interconnection structure (211, 213, 215, 217, 219) located on a first surface 30 of the second substrate 210, wherein the second interconnection structure includes an array of top metal contact pads 227, a bonding layer BL between the array of top metal contact pads 227 and the first surface 30 of the first substrate 110, and a contact pad array 19 on a second surface 40 of the first substrate 110, wherein the array of top metal contact pads 227 has an array pattern corresponding to the pattern of the contact pad array 19 formed on the second surface 40 of the first substrate 110.

[0068] In an embodiment, each of the top metal contact pads includes length and width dimensions ranging from about 40 μm to about 100 μm.

[0069] In another embodiment, the spatial coordinates of the geometric center point (C) of each contact pad 19 of the top metal contact pad array 19 formed on the second surface 40 of the first substrate 110 are within 5µm of the spatial coordinates of the geometric center point (C) of each top metal contact pad 227 of the top metal contact pad array 227 in the common reference architecture.

[0070] In another embodiment, at least some of the top metal contact pads 227 in the array of top metal contact pads 227 comprise slotted pads.

[0071] In another embodiment, each top metal contact pad 227 in the array of contact pads 227 is electrically connected to the lower metal feature 215 of the second interconnection structure via a through-hole structure 217.

[0072] In another embodiment, the second interconnection structure includes a top metal layer TM comprising a plurality of metal features 219, wherein at least some of the metal features 219 include a contact pad region 127 and a second region 129 adjacent to the contact pad region 127.

[0073] In another embodiment, the contact pad area 127 has length and width dimensions configured to enable circuit probe testing of a plurality of metal features 219.

[0074] In another embodiment, the second region 129 contacts of the plurality of metal features 219 electrically connect the metal features 219 to the bonding connection portion 243 of the bonding layer BL.

[0075] In another embodiment, the bonded wafer structure 300 further includes a plurality of conductive vias 307 through the substrate, extending through the first substrate 110 and contacting the metal features 115 of the first interconnect structure of the first wafer 100, wherein each contact pad 19 in the contact pad array 19 above the second surface 40 of the first substrate 110 is electrically connected to the corresponding conductive via 307 through the substrate.

[0076] In another embodiment, the bonding layer BL includes a plurality of bonding pads (141, 241) laterally surrounded by dielectric materials (133, 233), and a plurality of bonding connection portions (143, 243) electrically connecting the plurality of bonding pads to a plurality of metal features (119, 219) of the first interconnection structure and the second interconnection structure.

[0077] In another embodiment, the bonding pads (141, 241) and the bonding connection portions (143, 243) comprise copper.

[0078] In another embodiment, the joined wafer structure 300 includes an additional array of top metal contact pads 127 in the first interconnection structure of the first wafer 100.

[0079] Another embodiment relates to a bonded wafer structure (300) comprising a first wafer 100 having a first substrate 110, a first element structure 112, and a first interconnect structure (111, 113, 115, 117, 119), and a second wafer 200 having a second substrate 210, a second element structure 212, and a second interconnect structure (211, 213, 215, 217, 219), wherein the second interconnect structure includes a top metal layer TM having contact pad regions 227 and a plurality of metal features 219 of a second region 129 adjacent to the contact pad regions 227, wherein the contact pad regions 227 have length and width dimensions configured for circuit probe testing of the second wafer 200, a bonding layer BL between the top metal layer of the second interconnect structure and a first surface 30 of the first substrate 100, and an array of contact pads 19 on the first substrate above the second surface 40 of the first substrate 100.

[0080] In the embodiment, the contact pad area 227 of the metal feature 219 has a length and width dimension in the range of about 40 μm to about 100 μm, and the second area 129 of each metal feature 219 has a length and / or width dimension of less than 40 μm.

[0081] In another embodiment, the second region 129 of each metal feature 219 contacts electrically connecting the metal feature 219 to the bonding connection portion 243 of the bonding layer BL.

[0082] In another embodiment, the pattern of the array of contact pad regions 227 corresponds to the pattern of the contact pad array 19 on the second surface 40 of the first substrate 100.

[0083] Another embodiment relates to a method of fabricating a bonded wafer structure 300, comprising providing a first wafer (100, 200) including a component structure (112, 212) and an interconnect structure (111, 211, 113, 213, 115, 215, 117, 217, 119, 219) on a first substrate 100, forming a top metal contact pad array (127, 227) in a top metal layer TM of the interconnect structure of the first wafer (100, 200), and forming a top metal contact pad array (127, 227) in the top metal contact pad array (127, 227). A bonding layer BL is formed on top of the first wafer (100, 200) and the second wafer (100, 200) is bonded to form a bonded wafer structure 300. A contact pad array 19 is formed on the surface of the bonded wafer structure (300), wherein the pattern of the contact pad array 19 formed on the surface of the bonded wafer structure 300 corresponds to the pattern of the top metal contact pad array (127, 227) formed in the top metal layer TM of the interconnection structure of the first wafer (100, 200).

[0084] In an embodiment, this method further includes performing circuit probe testing on the first wafer (100, 200) using the top metal contact pad array (127, 227) before forming the bonding layer BL on top of the top metal contact pad array (127, 227).

[0085] In another embodiment, the bonding layer BL includes a first bonding layer, and the second wafer (100, 200) is contained on the second substrate (110, 210) of the second bonding layer BL. Bonding the first wafer (100, 200) to the second wafer (100, 200) includes stacking the first wafer (100, 200) and the second wafer (100, 200) such that the bonding pads (141, 241) of the first bonding layer BL contact the contact pads (141, 241) of the second bonding layer BL and diffuse bonding pads (141, 242) to bond the first wafer (100, 200) to the second wafer (100, 200).

[0086] In another embodiment, the step of forming a contact pad array 19 on the surface of the bonded wafer structure 300 includes forming conductive vias 307 through the second substrate (110, 210) and forming contact pads 19 on the back side 40 of the second substrate (110, 210), wherein each contact pad 19 contacts a corresponding conductive via 307 through the substrate.

[0087] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure comprising a first substrate, a first element structure, and a first interconnection structure, and a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure on a first surface of the second substrate. The second interconnection structure includes a top metal layer comprising a plurality of metal features, wherein at least some of the metal features include contact pad regions and second regions adjacent to the contact pad regions. The bonding structure includes a bonding layer between an array of top metal contact pads and the first surface of the first substrate, a bonding connection portion contacting the second regions of the metal features and electrically connecting the metal features to the bonding layer, and a contact pad array on the second surface of the first substrate, wherein the connecting pad regions of the metal features form an array pattern corresponding to the array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

[0088] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure comprising a first substrate, a first element structure, and a first interconnection structure, and a second semiconductor structure having a second substrate, a second element structure, and a second interconnection structure. The second interconnection structure includes a top metal layer comprising a plurality of metal features, each of which has a contact pad region and a second region adjacent to the contact pad region. The upper surface of the contact pad region and the upper surface of the second region are coplanar. The contact pad region has a length and width dimension between 40 μm and 100 μm, and the second region has a length and / or width dimension less than 40 μm. The bonding structure includes a bonding layer between the top metal layer of the second interconnection structure and a first surface of the first substrate, and a contact pad array on the second surface of the first substrate. The contact pad regions of the metal features form an array pattern corresponding to the array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

[0089] Another embodiment of this disclosure provides a method for fabricating a bonding structure, comprising providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and interconnection structures on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure, each of the plurality of top metal features in the top metal feature array including a contact pad region and a second region adjacent to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar, the contact pad region includes a length and width dimension between 40 μm and 100 μm, and the second region includes a length and / or width dimension less than 40 μm; forming a bonding layer on the top metal feature array; bonding the first semiconductor structure to a second semiconductor structure to form a bonding structure; and forming a contact pad array on the surface of the bonding structure, wherein the pattern formed by the contact pad regions in the top metal features corresponds to the pattern of the contact pad array formed on the surface of the bonding structure.

[0090] Another embodiment of this disclosure provides a method for fabricating a bonding structure, comprising the following steps: providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and interconnection structures on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure; forming a bonding layer on the top metal feature array; bonding the first semiconductor structure to a second semiconductor structure including a second substrate to form a bonding structure; and forming a plurality of contact pads on the surface of the second substrate, wherein the spatial coordinates of the geometric center point of each of the contact pads are within 5µm of the spatial coordinates of the geometric center points of each of the plurality of top metal features of the top metal feature array.

[0091] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure. The second semiconductor structure includes a second substrate, a plurality of second elements on a first surface of the second substrate, and a second interconnection structure, wherein the second interconnection structure includes a top metal feature array. The bonding structure includes a bonding layer between the top metal feature array and the first surface of the first substrate, and a contact pad array on the second surface of the first substrate, wherein the spatial coordinates of the geometric center points of the plurality of contact pads in the contact pad array are within 5 µm of the spatial coordinates of the geometric center points of the plurality of top metal features in the top metal feature array of the second interconnection structure of the second semiconductor structure.

[0092] Another embodiment of this disclosure provides a bonding structure including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure. The second semiconductor structure includes a second substrate, a plurality of second elements, and a second interconnection structure, wherein the second interconnection structure includes a top metal feature array. Each of the top metal features includes a contact pad region and a second region adjacent to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar. The bonding structure includes a bonding layer between the top metal features of the second interconnection structure and a first surface of the first substrate, and a contact pad array on the second surface of the first substrate, wherein the contact pad regions of the top metal features form an array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

[0093] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0094] C, C4, C8: Geometric center points DL: First Component Level M1~M3: Metallic Layer TM: Top Metal Layer 19: Contact pad array / contact pad 19-1~19-8: Contact pads 30: First surface / front side 40: Second surface / back side 100, 200: Wafers 110, 210: Substrate 111,211,311: Dielectric material / dielectric material layer 112,212: Components / Component Structures 113,213: Component contact through-hole structure 115, 117, 215, 217: Metallic lines / metallic features / through-hole structures 116, 216: Through-hole opening 119,219: Metallic characteristics 121,133,221,233,308,309,310,311: Dielectric material layers 122,123,137,140,​​222,223,237,240,301,313,317,321: Patterned mask / mask 125, 225: Metallic material layer 126,226,142,242: Trench opening 127,227-1~227-9: Contact pad / Contact pad area 227: Top metal contact pad / Top metal contact pad array 129: Second District 138,238,302,312: Through-hole opening / opening 139,239: Bonding material layer 141,241: Joint pad 143,243: Joint connection part 231: Contact Area 300: Joined wafer structure 303: Lining material layer 305, 315: Conductive material layer 307: Conductive via 400: Method 402~412: Steps

Claims

1. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first element structures, and a first interconnection structure; A second semiconductor structure includes a second substrate, a plurality of second element structures, and a second interconnection structure on a first surface of the second substrate, wherein the second interconnection structure includes a top metal contact pad array, the top metal contact pad array includes a plurality of top metal features, each of the top metal features having a contact pad region and a second region directly connected to the contact pad region, wherein the contact pad regions are configured for circuit probe testing of the second semiconductor structure, and the second regions are configured with a plurality of contact areas; A bonding layer, between the top metal contact pad array and a first surface of the first substrate, the bonding layer being electrically connected to the contact areas of the second regions; and a contact pad array, on a second surface of the first substrate, wherein the top metal contact pad array includes an array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate, wherein the spatial coordinates of a geometric center point of each contact pad in the contact pad array formed on the second surface of the first substrate are within 5µm of the spatial coordinates of a geometric center point of each top metal feature of the top metal contact pad array in a common reference architecture.

2. The engagement structure as described in claim 1, wherein at least some of the top metal features in the array of top metal contact pads include slotted pads.

3. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first element structures, and a first interconnect structure; a second semiconductor structure includes a second substrate, a plurality of second element structures, and a second interconnect structure, wherein the second interconnect structure includes a top metal layer, the top metal layer includes a plurality of metal features, each of the metal features having a contact pad region and a second region directly connected to the contact pad region, wherein the contact pad regions are configured for circuit probe testing of the second semiconductor structure, and the second regions are configured with a plurality of contact areas; a bonding layer is disposed between the top metal layer of the second interconnect structure and a first surface of the first substrate, the bonding layer being electrically connected to the contact areas of the second regions; and a contact pad array is disposed on a second surface of the first substrate, wherein the metal features of the top metal layer include an array pattern, the array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array.

4. A method of fabricating a bonding structure, comprising the steps of: providing a first semiconductor structure on a first substrate, the first semiconductor structure including a plurality of element structures and an interconnection structure; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure, the top metal layer including a plurality of metal features, each of the metal features including a contact pad region and a second region directly connected to the contact pad region, wherein the length and width dimensions of the contact pad regions are configured for circuit probe testing of the first semiconductor structure, and the second regions are configured with a plurality of contact areas; performing a circuit probe test of the first semiconductor structure on the contact pad regions; and after performing the circuit probe test, forming a bonding layer on the top metal feature array, wherein the contact areas of the second regions of the top metal feature array contact a plurality of bonding connection portions electrically connecting the second regions of the top metal feature array to the bonding layer; The first semiconductor structure is bonded to a second semiconductor structure to form a bonding structure; and a contact pad array is formed on a surface of the bonding structure, wherein a pattern of the contact pad array formed on the surface of the bonding structure corresponds to a pattern of the contact pad region in the top metal feature array formed in the top metal layer of the interconnection structure of the first semiconductor structure.

5. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure; A second semiconductor structure includes a second substrate, a plurality of second elements, and a second interconnection structure on a first surface of the second substrate, wherein the second interconnection structure includes a top metal layer comprising a plurality of metal features, wherein at least some of the metal features include a contact pad region and a second region directly connected to the contact pad region, the contact pad regions being configured for circuit probe testing of the second semiconductor structure, and the second regions being configured with a plurality of contact areas; a bonding layer between an array of the metal features and a first surface of the first substrate; a plurality of bonding connection portions contacting the contact areas of the second regions of the metal features and electrically connecting the metal features to the bonding layer; and a contact pad array on a second surface of the first substrate, wherein the contact pad regions of the metal features form an array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

6. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure; a second semiconductor structure includes a second substrate, a plurality of second elements, and a second interconnection structure, wherein the second interconnection structure includes a top metal layer, the top metal layer includes a plurality of metal features, each of the metal features having a contact pad region and a second region directly connected to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar, the contact pad region includes a length and width dimension between 40 μm and 100 μm, the contact pad region is configured for circuit probe testing of the second semiconductor structure, the second region includes a length and / or width dimension less than 40 μm, and the second region is configured with a plurality of contact areas; A bonding layer, between the top metal layer of the second interconnection structure and a first surface of the first substrate, the bonding layer being electrically connected to the contact areas of the second regions; and a contact pad array, on a second surface of the first substrate, wherein the contact pad areas of the metal features form an array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

7. A method of fabricating a bonding structure, comprising the steps of: providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and an interconnection structure on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure, each of the plurality of top metal features in the top metal feature array including a contact pad region and a second region directly connected to the contact pad region, wherein the upper surfaces of the contact pad regions are coplanar with the upper surfaces of the second regions, the contact pad regions having length and width dimensions between 40 μm and 100 μm, the second regions having length and / or width dimensions less than 40 μm, and the second regions being configured with a plurality of contact areas; performing a circuit probe test of the first semiconductor structure on the contact pad regions; after performing the circuit probe test, forming a bonding layer on the top metal feature array, the bonding layer being electrically connected to the contact areas of the second regions; The first semiconductor structure is bonded to a second semiconductor structure to form a bonding structure; and a contact pad array is formed on a surface of the bonding structure, wherein a pattern formed by the contact pad regions in the top metal features corresponds to a pattern of the contact pad array formed on the surface of the bonding structure.

8. A method of fabricating a bonding structure, comprising the steps of: providing a first semiconductor structure, the first semiconductor structure including a plurality of elements and an interconnection structure on a first substrate; forming a top metal feature array in a top metal layer of the interconnection structure of the first semiconductor structure, the top metal feature array including a plurality of top metal features, each of the top metal features having a contact pad region and a second region directly connected to the contact pad region, the second region being configured with a plurality of contact areas; performing a circuit probe test on the contact pad regions of the first semiconductor structure; after performing the circuit probe test, forming a bonding layer on the top metal feature array; bonding the first semiconductor structure to a second semiconductor structure including a second substrate to form a bonding structure; and forming a plurality of contact pads on a surface of the second substrate, wherein the spatial coordinates of a geometric center point of each of the contact pads are within 5µm of the spatial coordinates of a geometric center point of each of the plurality of top metal features of the top metal feature array, wherein an array pattern of the top metal features of the top metal feature array corresponds to an array pattern of the contact pads.

9. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure; a second semiconductor structure includes a second substrate, a plurality of second elements on a first surface of the second substrate, and a second interconnection structure, wherein the second interconnection structure includes a top metal feature array, the top metal feature array including a plurality of top metal features, each of the top metal features having a contact pad region and a second region directly connected to the contact pad region, wherein the contact pad regions are configured for circuit probe testing of the second semiconductor structure, and the second regions are configured with a plurality of contact areas; A bonding layer, between the top metal feature array and a first surface of the first substrate, the bonding layer being electrically connected to the contact areas of the second regions; and a contact pad array, on a second surface of the first substrate, wherein the spatial coordinates of the geometric center point of each of the plurality of contact pads in the contact pad array are within 5µm of the spatial coordinates of the geometric center point of each of the plurality of top metal features of the top metal feature array in the second interconnection structure of the second semiconductor structure, wherein an array pattern of the top metal features of the top metal feature array corresponds to an array pattern of the contact pads.

10. A joining structure, comprising: A first semiconductor structure includes a first substrate, a plurality of first elements, and a first interconnection structure; a second semiconductor structure includes a second substrate, a plurality of second elements, and a second interconnection structure, wherein the second interconnection structure includes a plurality of top metal features, each of the top metal features including a contact pad region and a second region directly connected to the contact pad region, wherein the upper surface of the contact pad region and the upper surface of the second region are coplanar, and the second regions are configured with a plurality of contact areas; a bonding layer between the top metal features of the second interconnection structure and a first surface of the first substrate, the bonding layer being electrically connected to the contact areas of the second regions; and a contact pad array on a second surface of the first substrate, wherein the contact pad regions of the top metal features form an array pattern, the array pattern corresponding to an array pattern of a plurality of contact pads of the contact pad array formed on the second surface of the first substrate.

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