INTEGRATED CIRCUITS (ICs) EMPLOYING FRONT SIDE (FS) BACK END-OF-LINE (BEOL) (FS-BEOL) INPUT / OUTPUT (I / O) ROUTING AND BACK SIDE (BS) BEOL (BS-BEOL) POWER ROUTING FOR CURRENT FLOW ORGANIZATION, AND RELATED METHODS

Abstract

This paper discloses an integrated circuit (IC) employing front-side (FS) back-end process (BEOL) (FS-BEOL) input / output (I / O) routing and back-side (BS) BEOL (BS-BEOL) power routing for current organization, as well as related IC packaging and manufacturing methods. The IC includes an FS-BEOL metallization structure disposed on the first side of the semiconductor layer and a BS-BEOL metallization structure disposed on the second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I / O signals to the semiconductor device. The IC's FS-BEOL metallization structure is also configured to receive power signals, which are routed to the semiconductor device. However, to avoid the need to route power signals through the FS-BEOL metallization structure to the semiconductor device (increasing the wiring density and complexity of the FS-BEOL metallization structure), the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and the semiconductor device for power supply.

Description

Technical Field

[0001] The field of this case relates to integrated circuits (ICs) comprising one or more semiconductor dies and related IC packages, wherein the semiconductor dies are attached to a package structure to provide electrical interfaces to the semiconductor dies. Prior Technology

[0002] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as "semiconductor packages" or "chip packages." An IC package includes one or more semiconductor dies as ICs(s), which are mounted on and electrically coupled to the package substrate to provide physical support and electrical interfaces to the semiconductor dies(s). The package substrate can be an embedded trace substrate (ETS), for example, an ETS including embedded electrical traces in one or more dielectric layers and vertical interconnect channels (vias) coupling the electrical traces together to provide electrical interfaces between the semiconductor dies(s). The semiconductor dies(s) are mounted to and electrically connected to interconnects exposed in the top layer of the package substrate to electrically couple the semiconductor dies(s) to the electrical traces of the package substrate for interconnection. The semiconductor dies(s) and the package substrate are encapsulated in a packaging material such as molding compound to form an IC package. IC packages may also include external solder balls in a ball grid array (BGA) that are electrically coupled to interconnects exposed in the underlying layer of the package substrate to electrically couple the solder balls to electrical traces in the package substrate. The solder balls provide external electrical interfaces to the semiconductor die(s)(s) within the IC package. When the IC package is mounted to a printed circuit board (PCB), the solder balls are electrically coupled to metal contacts on the PCB to provide electrical interfaces between electrical traces in the PCB to the IC die via the package substrate within the IC package. Summary of the Invention

[0003] The forms disclosed herein include integrated circuits (ICs) employing front-side (FS) back-end process online (BEOL) (FS-BEOL) input / output (I / O) routing and back-side (BS) BEOL (BS-BEOL) power routing for current organization. Related IC packaging and methods for manufacturing ICs and IC packages are also disclosed. ICs can be provided as IC dies. An IC comprises an active or semiconductor layer of semiconductor material, which includes semiconductor devices, such as field-effect transistors (FETs), fabricated in a front-side process online (FEOL) process. An IC can be coupled to a package metallization structure (e.g., a package substrate or redistribution layer (RDL)) as part of an IC package. The package metallization structure can provide electrical connections between the IC and other devices electrically coupled to the package metallization structure. For example, another IC can be electrically coupled to both the package metallization structure and the IC via conductive bumps that electrically couple another IC to the package metallization structure.

[0004] In the exemplary configurations disclosed herein, to reduce wiring complexity and / or shorten I / O routing connections between the IC and the package metallization structure to provide lower I / O signal resistance, the IC includes an FS-BEOL metallization structure and a BS-BEOL metallization structure. The FS-BEOL metallization structure is a metallization structure disposed on a first, front side of the semiconductor layer of the IC. The BS-BEOL is another metallization structure disposed on a second, back side of the semiconductor layer of the IC, opposite the front side of the IC. The FS-BEOL metallization structure includes one or more front metal layers comprising front metal lines configured to route I / O signals received from the package metallization structure to the semiconductor layer of the IC. The FS-BEOL metallization structure of the IC is also configured to receive power signals, which are routed in power routing lines to the semiconductor device to provide power to the semiconductor device within the IC. However, to avoid the need to reroute power signals to the semiconductor device via power routing lines through the FS-BEOL metallization structure (which could increase the wiring density and complexity of the FS-BEOL metallization structure), power signals are routed from the FS-BEOL metallization structure to power routing in the BS-BEOL metallization structure. In this regard, the BS-BEOL metallization structure includes one or more back metal layers that include one or more back metal lines as power routing lines, which are electrically coupled to the semiconductor device to route power signals on the back of the semiconductor layer to the semiconductor device for power supply. In this way, additional power signal routing in the FS-BEOL metallization structure is avoided, thus not increasing the wiring density in the FS-BEOL metallization structure. For example, reducing the wiring density in the FS-BEOL metallization structure can reduce the wiring complexity of IC placement and routing (referred to as "PNR"), which can enable shorter I / O signal connections to reduce I / O signal resistance.

[0005] In the exemplary embodiment, note that the power signals routed between the FS-BEOL metallization structure and the BS-BEOL metallization structure may include power signals for the positive power rail and / or ground rail. In other exemplary embodiments, to route power signals from the FS-BEOL metallization structure to power wiring in the BS-BEOL metallization structure, one or more vertical interconnect channels (vias) are provided and extend from the front side of the semiconductor layer and through the semiconductor layer to the back side of the semiconductor layer. For example, the via may be a through-silicon via (TSV). The metal lines in the FS-BEOL metallization structure that route the power signals to the BS-BEOL metallization structure are electrically coupled to the vias. One or more back metal lines, which are power routing lines in one or more back metal layers in the BS-BEOL metallization structure, are also coupled to the vias to receive power signals from the power wiring in the FS-BEOL. The back metal lines are electrically coupled to the semiconductor device to route the power signals to the semiconductor device to provide power to the semiconductor device. In another exemplary embodiment, a power head switch is formed in a semiconductor layer and coupled between the front metal lines in the FS-BEOL metallization structure and the back metal lines in the BS-BEOL metallization structure to control the routing of power signals from the FS-BEOL metallization structure to the BS-BEOL metallization structure.

[0006] In this regard, as an example, an IC is provided. The IC includes a semiconductor layer comprising a front side and a back side opposite the front side, the semiconductor layer including a semiconductor device. The IC also includes a FS-BEOL metallization structure disposed adjacent to the front side of the semiconductor layer. The FS-BEOL metallization structure includes front metal lines and front interconnects coupled to the front metal lines. The IC also includes a BS-BEOL metallization structure disposed adjacent to the back side of the semiconductor layer, the BS-BEOL metallization structure including back metal lines. The IC also includes a front-back connection structure coupled to the front metal lines and the back metal lines. The IC also includes a back metal line coupled to the semiconductor device.

[0007] In another exemplary embodiment, an IC package is provided. The IC package includes a substrate. The IC package also includes an IC die coupled to the substrate, the IC die including an active side and a passive side. The IC die also includes a semiconductor layer including a front side and a back side opposite to the front side, the semiconductor layer including a semiconductor device. The IC die also includes an FS-BEOL metallization structure disposed between the active side and the front side of the semiconductor layer. The FS-BEOL metallization structure includes front metal lines and front interconnects exposed from the active side and coupled to the front metal lines. The IC die also includes a BS-BEOL metallization structure disposed between the back side and the passive side of the semiconductor layer. The BS-BEOL metallization structure includes back metal lines. The IC die also includes a front-back connection structure coupled to the front metal lines and the back metal lines, and a back metal line coupled to the semiconductor device. The IC package also includes a power IC coupled to the substrate.

[0008] In another exemplary embodiment, a method for manufacturing an IC is provided. A semiconductor layer is disposed on a substrate, the semiconductor layer including a front side and a back side opposite the front side. The method also includes forming a semiconductor device in the semiconductor layer. The method further includes: forming a front-side metallization structure adjacent to the front side of the semiconductor layer, the FS-BEOL metallization structure including front-side metal lines and front-side interconnects coupled to the front-side metal lines. The method also includes: forming a back-side metallization structure adjacent to the back side of the semiconductor layer, the BS-BEOL metallization structure including back-side metal lines coupled to the semiconductor device. The method also includes forming a front-side to back-side connection structure coupled to the front-side and back-side metal lines. Simple Explanation of the Diagram

[0009] Figure 1 is a side view of an integrated circuit (IC) package comprising an IC in an exemplary form, the IC die including a front (FS) back-end process (BEOL) (FS-BEOL) metallization structure providing front input / output (I / O) signal routing to (multiple) semiconductor devices and a back (BS) BEOL (BS-BEOL) metallization structure providing back-end power routing to (multiple) semiconductor devices.

[0010] Figure 2A is a more detailed side view of the IC in the IC package shown in Figure 1;

[0011] Figure 2B is a top view of the IC in the IC package shown in Figure 1;

[0012] Figures 3A and 3B are side views of an IC package and an IC within the IC package, respectively, where the IC includes an FS-BEOL metallization structure for routing I / O signals and power signals to the IC die;

[0013] Figures 4A and 4B are respectively cross-sectional side and bottom views of an exemplary IC in an exemplary form of an IC die, which includes a field-effect transistor (FET), a front routing of I / O signals to the FET in an FS-BEOL metallization structure, and a back routing of power signals to the FET in a BS-BEOL metallization structure;

[0014] Figure 5 is a flowchart illustrating an exemplary process for manufacturing an IC, which includes an FS-BEOL metallization structure that provides front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure that provides back-side power routing to (multiple) semiconductor devices, such as the ICs in Figures 1 to 2B and Figures 4A to 4B;

[0015] Figures 6A to 6C are flowcharts illustrating another exemplary process for manufacturing an IC, which includes an FS-BEOL metallization structure that provides front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure that provides back-side power routing to (multiple) semiconductor devices, such as the ICs in Figures 1 to 2B and Figures 4A to 4B;

[0016] Figures 7A to 7G are exemplary manufacturing stages of an IC manufactured according to the procedures in Figures 6A to 6C;

[0017] Figures 8A and 8B are flowcharts illustrating another exemplary process for manufacturing an IC, which includes an FS-BEOL metallization structure that provides front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure that provides back-side power routing to (multiple) semiconductor devices, such as the ICs in Figures 1 to 2B and Figures 4A to 4B;

[0018] Figures 9A to 9E are exemplary manufacturing stages of an IC manufactured according to the procedures in Figures 8A and 8B;

[0019] Figure 10 is a block diagram of an exemplary processor-based system that may include one or more ICs, each IC including an FS-BEOL metallization structure providing front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing back-side power routing to (multiple) semiconductor devices, including but not limited to the ICs in Figures 1 to 2B, 4A to 4B, 7A to 7G, and 9A to 9E; and

[0020] Figure 11 is a block diagram of an exemplary wireless communication device, which includes a radio frequency (RF) component formed by one or more ICs. Each IC includes an FS-BEOL metallization structure that provides front I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure that provides back power routing to (multiple) semiconductor devices, including but not limited to the ICs in Figures 1 to 2B, Figures 4A to 4B, Figures 7A to 7G, and Figures 9A to 9E. Implementation

[0021] Several exemplary embodiments of this case are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, illustration, or description." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0022] The forms disclosed herein include integrated circuits (ICs) employing front-side (FS) back-end process online (BEOL) (FS-BEOL) input / output (I / O) routing and back-side (BS) BEOL (BS-BEOL) power routing for current organization. Related IC packaging and methods for manufacturing ICs and IC packages are also disclosed. ICs can be provided as IC dies. An IC comprises an active or semiconductor layer of semiconductor material, which includes semiconductor devices, such as field-effect transistors (FETs), fabricated in a front-side process online (FEOL) process. An IC can be coupled to a package metallization structure (e.g., a package substrate or redistribution layer (RDL)) as part of an IC package. The package metallization structure can provide electrical connections between the IC and other devices electrically coupled to the package metallization structure. For example, another IC can be electrically coupled to both the package metallization structure and the IC via conductive bumps that electrically couple another IC to the package metallization structure.

[0023] In the exemplary configurations disclosed herein, to reduce wiring complexity and / or shorten I / O routing connections between the IC and the package metallization structure to provide lower I / O signal resistance, the IC includes an FS-BEOL metallization structure and a BS-BEOL metallization structure. The FS-BEOL metallization structure is a metallization structure disposed on a first, front side of the semiconductor layer of the IC. The BS-BEOL is another metallization structure disposed on a second, back side of the semiconductor layer of the IC, opposite the front side of the IC. The FS-BEOL metallization structure includes one or more front metal layers comprising front metal lines configured to route I / O signals received from the package metallization structure to the semiconductor layer of the IC. The FS-BEOL metallization structure of the IC is also configured to receive power signals, which are routed in power routing lines to the semiconductor device to provide power to the semiconductor device within the IC. However, to avoid the need to reroute power signals to the semiconductor device via power routing lines through the FS-BEOL metallization structure (which could increase the wiring density and complexity of the FS-BEOL metallization structure), power signals are routed from the FS-BEOL metallization structure to power routing in the BS-BEOL metallization structure. In this regard, the BS-BEOL metallization structure includes one or more back metal layers, which include one or more back metal lines as power routing lines electrically coupled to the semiconductor device to route power signals on the back of the semiconductor layer to the semiconductor device for power supply. In this way, additional power signal routing in the FS-BEOL metallization structure is avoided, thus not increasing the wiring density in the FS-BEOL metallization structure. For example, reducing the wiring density in the FS-BEOL metallization structure can reduce the wiring complexity of IC placement and routing (referred to as "PNR"), which can achieve shorter I / O signal connections to reduce I / O signal resistance.

[0024] In this regard, Figure 1 is a side view of an IC package 100, which includes an IC 102 in an exemplary form as an IC die 104. For example, the IC 102 may be a processor circuit, a memory circuit, a logic circuit, or any combination thereof. For example, the IC 102 can be used in electronic device applications such as computing devices. As discussed in more detail below, the IC die 104 includes an FS-BEOL metallization structure 106 and a BS-BEOL metallization structure 108. The FS-BEOL metallization structure 106 is a metallization structure including one or more metal layers comprising metal lines for transmitting I / O signals, providing front-side I / O signal routing between one or more die interconnects 110 (e.g., solder bumps, ball grid arrays (BGAs)) and one or more semiconductor devices 112 formed in the semiconductor layer 114. The die interconnects 110 are on the active surface 115 of the IC die 104. An FS-BEOL metallization structure 106 is disposed on the first surface of the semiconductor layer 114 of IC 102 to form an interconnect with semiconductor device 112 after being formed in the semiconductor layer 114 during a front-end process (FEOL) process. For example, semiconductor device 112 may be a field-effect transistor (FET) configured to operate based on the state of I / O signals coupled to its gate, source, and / or drain. The FET may be part of a complementary metal-oxide-semiconductor (CMOS) circuit formed in semiconductor layer 114 as a positive (P)-type FET (PFET) and a negative (N)-type FET (NFET). Another circuit may be electrically connected to communicate I / O signals with semiconductor device 112 in IC die 104 of IC package 100 via package substrate 116. For example, package substrate 116 may be a laminated substrate or a redistribution layer (RDL) substrate. The package substrate 116 is mounted to the printed circuit board (PCB) 117 via external conductive bumps 118 (e.g., solder bumps, ball grid array (BGA)). The external conductive bumps 118 are electrically coupled to metal lines in the package substrate 116, which are also coupled to die interconnects 110 (e.g., solder bumps, ball grid array (BGA)) to provide a conductive routing path between the external conductive bumps 118 and the semiconductor device 112 in the IC die 104.

[0025] The "front side" (also referred to as "FS" herein) of the FS-BEOL metallization structure 106 indicates that the FS-BEOL metallization structure 106 is positioned adjacent to the front side 120F of the semiconductor layer 114. In FIG. 1, the FS-BEOL metallization structure 106 is positioned adjacent to the front side 120F of the semiconductor layer 114 in the Z-axis direction. In this example, the IC die 104 in FIG. 1 has been flipped so that the FS-BEOL metallization structure 106 is positioned below and adjacent to the front side 120F of the semiconductor layer 114 in the Z-axis direction, and the FS-BEOL metallization structure 106 is located on the front side 122F of the IC die 104. In this example, the BS-BEOL metallization structure 108 is positioned above and adjacent to the semiconductor layer 114 in the Z-axis direction, and the BS-BEOL metallization structure 108 is located on the back side 122B of the IC die 104.

[0026] In the example of IC package 100 in Figure 1, a separate memory chip 124 (i.e., memory IC) is interface-connected to IC die 104 to communicate I / O signals with IC die 104 for memory access (i.e., read and write operations). Memory chip 124 is coupled to second package substrate 126 and package substrate 116 via external conductive bumps 128 coupled to vertical interconnect channels (vias) 130; for example, external conductive bumps 128 may be conductive pillars. A BS-BEOL metallization structure 108 is positioned adjacent to the second package substrate 126. The passive surface 127 of IC die 104 is positioned adjacent to the second package substrate 126. In this example, the FS-BEOL metallization structure 106 of the IC die 104 supports forward routing of I / O signals from the memory chip 124 (via conductive bumps 128, second package substrate 126, vias 130, package substrate 116, and die interconnects 110) to the semiconductor device 112 within the IC die 104. In this example, the FS-BEOL metallization structure 106 is designed to provide sufficient conductive paths in the metal lines within its metal layers to provide I / O signal routing between the memory chip 124 and the IC die 104.

[0027] Referring again to Figure 1, as previously mentioned, the IC die 104 also includes a BS-BEOL metallization structure 108. The BS-BEOL metallization structure 108 is a metallization structure comprising one or more metal layers disposed on a second surface of the second semiconductor layer 114 opposite to the surface on which the FS-BEOL metallization structure 106 is disposed. Each metal layer of the BS-BEOL metallization structure 108 has a metal line for interconnection with the semiconductor device 112. The BS-BEOL metallization structure is positioned adjacent to the back surface 120B of the semiconductor layer 114. The term "back surface" (also referred to herein as "BS") indicates that the BS-BEOL metallization structure 108 is positioned adjacent to the back surface 120B of the semiconductor layer 114. In Figure 1, the BS-BEOL metallization structure 108 is positioned adjacent to the back surface 120B of the semiconductor layer 114 in the Z-axis direction. In this example, a substrate 132 on which a semiconductor layer 114 is formed is disposed between the BS-BEOL metallization structure 108 and the semiconductor layer 114. In this example, the IC die 104 in FIG1 has been flipped so that the BS-BEOL metallization structure 108 is disposed above the semiconductor layer 114 in the X-axis direction, and the semiconductor layer 114 is considered to be adjacent to the back surface 122B of the IC die 104.

[0028] As discussed in more detail below, the BS-BEOL metallization structure 108 includes one or more metal layers including metal lines for transmitting power signals (e.g., positive and / or negative voltage signals and / or ground signals) to provide back-side power routing between one or more die interconnects 110 (e.g., solder bumps) and one or more semiconductor devices 112 formed in the semiconductor layer 114. Power routing involves metal lines configured to transmit power signals. For example, semiconductor device 112 may require power to operate. In the example of a FET as semiconductor device 112, power signals may need to be coupled to the gate, source, and / or drain of the FET to achieve its desired function and operation. As shown in Figure 1, a power management IC (PMIC) chip 125 (i.e., a power IC) can be coupled to a PCB 117 via conductive bumps 129. The power signal from the PMIC chip 125 can be routed via the PCB 117 and the package substrate 116 and via the conductive bumps 118 to the IC die 104 and the FS-BEOL metallization structure 106, and then to the BS-BEOL metallization structure 108.

[0029] In this example, as will be discussed in more detail below, the FS-BEOL metallization structure 106 includes conductive routing paths to provide power signals received via external conductive bumps 118 and the package substrate 116 to the BS-BEOL metallization structure 108. The power signals can then be routed via metal lines within the metal layer of the BS-BEOL metallization structure 108 on the back side 120B of the semiconductor layer 114, such that the power signals can be coupled from the back side 122B of the IC die 104 to the semiconductor device 112 in the semiconductor layer 114. Therefore, the power signals are routed directly to the semiconductor device 112 from the BS-BEOL metallization structure 108 rather than from the FS-BEOL metallization structure 106. The power signals can be routed via a backside power distribution network of metal lines in the BS-BEOL metallization structure 108 coupled to the semiconductor device 112 to provide power to the multiple semiconductor devices 112 in the IC die 104 for operation. For example, in CMOS circuits, a positive power supply signal is typically provided to the source of a PFET by pulling it up, and a ground signal is typically provided to an NFET by pulling it down to provide logic operation. Therefore, by providing power signals via a back-side routing in the BS-BEOL metallization structure 108, the complex routing of power signals in the FS-BEOL metallization structure 106 can be avoided, thus not increasing the wiring density in the FS-BEOL metallization structure 106. For example, the reduced wiring density in the FS-BEOL metallization structure 106 allows for reduced layout and routing complexity, which can allow for shorter I / O connections to reduce I / O signal resistance. For example, the reduced wiring complexity in the FS-BEOL metallization structure 106 allows for shorter I / O routing connections between the semiconductor device 112 and the package substrate 116 due to the lower I / O signal resistance provided to the IC die 104.

[0030] Because IC die 104 can have different power domains for powering semiconductor device 112, BS-BEOL metallization structure 108 can include multiple power distribution networks for routing power to different power domains. For example, IC die 104 can include CPU and memory circuitry. The CPU can be configured to operate at a first power domain, which can be reduced to a voltage level lower than a second power domain powering the memory circuitry. For example, the memory circuitry may require a minimum power level to maintain data storage. To save power, it is desirable to reduce or disconnect the power to the CPU in idle or power-off modes without affecting the power supplied to the memory circuitry. Providing multiple separate power domains to the CPU and memory circuitry can achieve this functionality.

[0031] Referring again to FIG1, another circuit may be electrically connected to communicate power signals to the semiconductor device 112 in the IC die 104 of the IC package 100 via the package substrate 116. For example, the power signal may be routed to the IC die 104 via external conductive bumps 118 (e.g., solder bumps, ball grid array (BGA)) electrically coupled to metal lines in the package substrate 116. The external conductive bumps 118 are coupled to die interconnects 110 (e.g., solder bumps) to provide a conductive path between the external conductive bumps 118 and the semiconductor device 112 in the IC die 104. For example, the IC package 100 may be mounted in a printed circuit board having another power management IC (PMIC) such that the PMIC is electrically coupled to the IC die 104 via the conductive bumps 118 to provide power signals to the IC die 104 and to the BS-BEOL metallization structure 108, which is coupled to the semiconductor device 112. PMIC or other circuits can also be integrated into IC package 100 and coupled to IC die 104, such as mounted on second package substrate 126 like memory chip 124.

[0032] Figures 2A and 2B are respectively more detailed side and top views of IC 102 in IC package 100 of Figure 1 to illustrate further exemplary details of IC die 104 and FS-BEOL metallization structure 106 and BS-BEOL metallization structure 108. As mentioned above, FS-BEOL metallization structure 106 supports front I / O signal routing for IC die 104, and BS-BEOL metallization structure 108 supports rear power routing for IC die 104.

[0033] Referring to Figure 2A, the FS-BEOL metallization structure 106 is shown as comprising eight (8) front metal layers FS-ML1 to FS-ML8, but note that this is not limiting. Each front metal layer FS-ML1 to FS-ML8 includes one or more front metal lines 200 (1) to 200 (8) fabricated in the FS-BEOL metallization structure 106 to provide a conductive routing path for signals via the FS-BEOL metallization structure 106. The front metal line 200 (8) in the uppermost or topmost front metal layer FS-ML8 is coupled to a front interconnect 202 in a front interconnect layer 204, which is coupled to a die interconnect 110 to provide a conductive routing path between the die interconnect 110 and the front metal line 200 (8) in the front metal layer FS-ML8. The front interconnect 202 in the front interconnect layer 204 is exposed from the active surface 115 of the IC die 104 and coupled to the die interconnect 110. For example, as described above, the front interconnect 202 is configured to receive I / O signals that are routed in the FS-BEOL metallization structure 106 to the semiconductor device 112 in the semiconductor layer 114. The front interconnect 202 is also configured to receive power signals that are routed in the FS-BEOL metallization structure 106 to the BS-BEOL metallization structure 108 on the back side 122B of the IC die 104, which is coupled to the semiconductor device 112 in the semiconductor layer 114. Vias 206 are provided in the front metallization layers FS-ML1 to FS-ML8 between adjacent front metal lines 200(1) to 200(8) to electrically couple certain front metal lines 200(1) to 200(8) together to establish signal routing paths in the FS-BEOL metallization structure 106 according to the layout and routing design of the IC 102.

[0034] Referring again to Figure 2A, the BS-BEOL metallization structure 108 is shown as comprising two (2) back metal layers BS-ML1 and BS-ML2, but note that this is not limiting. Each back metal layer BS-ML1 and BS-ML2 includes one or more back metal lines 208(1) and 208(2) fabricated in the BS-BEOL metallization structure 108 to provide a conductive routing path for power signals transmitted through the BS-BEOL metallization structure 108. The back metal lines 208(1) and 208(2) provide a power distribution network for transmitting power signals distributed to semiconductor devices 112 in the semiconductor layer 114 of the IC die 104. The back metal line 208(2) is coupled to the back metal line 208(1) via a back via 210. In this example, the back metal line 208(1) is coupled to the back side of the semiconductor device 112 formed in the semiconductor device layer 114 via a back via 212. For example, the back via 212 can be a through-silicon via (TSV) because the back via 212 extends through the semiconductor layer 114. In another example, the back via 212 can extend through the front 120F of the semiconductor layer 114 into the front 122F of the IC die 104 and couple to front metal lines 200(1) to 200(8), which are then used to route power signals. In addition, one back metal line 208(1) can be used to route a positive power signal, and another back metal line 208(2) can be used to route a negative power signal or a ground signal.

[0035] For example, as described above, the front interconnect 202 is configured to receive I / O signals that are routed in the FS-BEOL metallization structure 106 to the semiconductor device 112 in the semiconductor layer 114. The front interconnect 202 is also configured to receive power signals that are routed in the FS-BEOL metallization structure 106 to the BS-BEOL metallization structure 108 on the back side 122B of the IC die 104, which is coupled to the semiconductor device 112 in the semiconductor layer 114. Vias 206 are provided in the front metallization layers FS-ML1 to FS-ML8 between adjacent front metal lines 200(1) to 200(8) to electrically couple certain front metal lines 200(1) to 200(8) together to establish signal routing paths in the FS-BEOL metallization structure 106 according to the layout and routing design of the IC 102.

[0036] Figure 2B illustrates a top view of the IC die 104 in Figure 2A. As shown in Figure 2A, power signals received from the die interconnect 110 and entering the FS-BEOL metallization structure 106 are routed to the BS-BEOL metallization structure 108 for further distribution. At this point, the IC die 104 includes a front-to-back connection structure 214 to couple the front metal lines 200P, 200N in the FS-BEOL metallization structure 106 to the back metal line 208 (1) in the BS-BEOL metallization structure 108. As shown in Figure 2B, a top view of the front metal lines 200P, 200N in the FS-BEOL metallization structure 106 extends down to the front-to-back connection structure 214 to route power signals to the front-to-back connection structure 214. In one example, the front-to-back connection structure 214 is a head switch in the form of a FET 216. In this example, the FET 216 includes a drain (D) and a source (S). In this example, the front metal line 200P located above FET 216 in the Z-axis direction effectively routes the positive power supply signal to the source S and / or drain D of FET 216. Furthermore, as shown in Figure 2B, a front metal line 200N is provided to route the ground or negative power supply signal in the FS-BEOL metallization structure 106 to the ground network in the BS-BEOL metallization structure 108.

[0037] Referring again to Figure 2A, in this example, the source S of FET 216 is coupled to front metal line 200P, and the drain D of FET 216 is coupled to back metal line 208(1). Front metal line 200P is coupled to other front metal lines 200(2) to 200(8), which are coupled to the die interconnect 110 for transmitting power signals via via 206 in the FS-BEOL metallization structure 106, such that the source S of FET 216 is configured to receive power signals. The drain D of FET 216 is coupled to the back metal line 208(1) via via 212. In this way, the power signal received from the die interconnect 110 is routed from the FS-BEOL metallization structure 106 to the BS-BEOL metallization structure 108 for distribution. Subsequently, by coupling the back metal line 208(1) to the FET 216 on the back side 122B of the IC die 104, the power signal can be routed to other semiconductor devices 112 via the BS-BEOL metallization structure 108.

[0038] Note that by providing power routing in the BS-BEOL metallization structure 108 of the IC package 100 on the back side of the IC die 104, side-channel attacks on the IC package 100 can be reduced and / or avoided. A side-channel attack involves coupling a separate device to the IC package to attempt to monitor the power consumption and / or electromagnetic (EM) emissions of the IC die 104 during operation. For example, a side-channel attack can be used to attempt to collect data and other confidential information processed by the IC die 104. To perform a side-channel attack on the IC package 100 in FIG. 1, a monitoring probe can be coupled to an externally accessible conductive bump 118 of the IC package 100 mounted to the PCB 117 to attempt to determine information regarding signal processing within the IC die 104. Because a power routing network is provided for the IC die 104 located in the BS-BEOL metallization structure 108 between the second package substrate 126 and the package substrate 116, bypass attacks on the power distribution network via the conductive bumps 118 exposed from the IC package 100 on the PCB 117 are more difficult (if not impossible). The main power signal is routed to the FS-BEOL metallization structure 106 via the conductive bumps 118. The BS-BEOL metallization structure 108 can then further process the power signal routed in the FS-BEOL metallization structure 106 into multiple power domain signals to route to different power domains in the IC die 104. These multiple power domains cannot be directly accessed via the conductive bumps 118 and the FS-BEOL metallization structure 106.

[0039] Figures 3A and 3B are side views of the IC package 300, memory chip 324, and IC die 304, without showing the back-side power routing, for comparison with the IC package 100 in Figures 1 through 2B. As shown in Figures 3A and 3B, the IC package 300 includes an IC die 304 mounted on a package substrate 316 via conductive bumps 310. The IC die 304 can be interconnected to another circuit via conductive bumps 318. As shown in Figure 3B, the IC die 304 includes an FS-BEOL metallization structure 306 electrically coupled to the conductive bumps 310 and a semiconductor layer 314 mounted on a substrate 332. A semiconductor device 312 is formed in the semiconductor layer 314. Because the IC die 304 includes only one metallization structure (FS-BEOL metallization structure 306), power and I / O signals are routed to the semiconductor layer 314 via the FS-BEOL metallization structure 306. Therefore, the signal routing in the FS-BEOL metallization structure 306 may be more complex than the signal routing in the FS-BEOL metallization structure 106 in the IC die 104 in Figures 1 to 2B, because power wiring is coupled to each of the semiconductor devices 312, which require power via the FS-BEOL metallization structure 306 that routes I / O signals in the same way.

[0040] As discussed above with respect to Figures 1 to 2A, the back metal line 208(1) in the BS-BEOL metallization structure 108 of the IC die 104 is coupled to the semiconductor device 112 in the semiconductor layer 114 to route power to the semiconductor device 112. In this regard, for example, Figures 4A and 4B are additional cross-sectional side and bottom views of the IC die 104 in Figures 1A to 2A, which includes a field-effect transistor (FET) as the semiconductor device 112. Figure 4A is a cross-sectional side view of the IC die 104 in Figure 4A along the A1-A1' section line. Figures 4A and 4B illustrate an example of how the front I / O signal routing from the FS-BEOL metallization structure 106 and the back power routing from the BS-BEOL metallization structure 108 are coupled to the semiconductor device 112.

[0041] Referring to Figures 4A and 4B, IC die 104 includes FET 400. In this example, FET 400 is a gate-all-around (GAA) FET, but note that, as other non-limiting examples, FET 400 can be a planar FET or a FinFET. A GAA FET, also known as a gate-around transistor (SGT), is conceptually similar to a FinFET, except that the gate material surrounds the channel region on all sides. A FinFET is a multi-gate MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate, wherein the gate is placed on two, three, or four sides of the channel or surrounds the channel to form a dual-gate structure. A planar FET includes a conductive channel formed in a substrate, wherein the gate is placed above the conductive channel with an insulating material in between. FET 400 includes a conductive channel 402 disposed above a substrate 132 in the Z-axis direction, the substrate 132 being a bulk substrate in this example. A plurality of nanostructures 404(1) to 404(3) (e.g., nanowires or nanoplates) are provided, which may be formed from substrate 132 and have a semiconductor material capable of conducting current in response to an electric field. The bulk substrate is a self-supporting substrate. FET 400 includes a source S disposed in a first end 406(1) of conductive channel 402. In this example, back metal contact 408 is also below conductive channel 402. In this example, since back metal contact 408 is below substrate 132 on the Z-axis, back metal contact 408 is also below conductive channel 402 because FET 400 is a GAA FET in this example, where conductive channel 402 is disposed above substrate 132. For example, if FET 400 is a planar FET, where conductive channel 402 is disposed below the gate and in the substrate, the back metal wire may be below the conductive channel 402 of the planar FET, but may not be completely below the substrate.

[0042] The FET 400 also includes a drain D disposed in the X-axis direction on a second end 406(2) of the conductive channel 402 opposite to the first end 406(1). The gate G of the FET 400 is disposed above at least a portion of the conductive channel 402 between the first end 406(1) and the second end 406(2). In this example, the gate G is composed of a gate material of each of the nanostructures 404(1) to 404(3) surrounding the conductive channel 402. In this way, the voltage applied between the gate G and the source S of the FET 400 can generate an electric field in the conductive channel 402 sufficient to conduct current between the source S and the drain D in the nanostructures 404(1) to 404(3) of the conductive channel 402.

[0043] Referring again to Figure 4A, in this example, the source S has an active top surface 410T and a source bottom surface 410B, and the drain D has a drain top surface 412T and a drain bottom surface 412B. For example, the source S and drain D may have been epitaxially grown on the substrate 132 or formed as implants into the substrate 132. In this example, the front metal contact 414 contacts the drain top surface 412T of the drain D of the FET 400 to provide a connection between the drain D and the front metal line 200(1) in the FS-BEOL metallization structure 106. For example, the front metal contact 414 may be a conductive post or via that connects the front metal contact 414 to the front metal line 200(1). For example, the front metal contact 414 may be a via (TSV) or other via with a sufficiently small diameter to connect the front metal contact 414 to the front metal line 200(1) without interfering with adjacent routing areas. Similarly, in this example, the back metal contact 408 contacts the source bottom surface 410B of the source S of the FET 400 to provide a connection between the source S and the back metal line 208(1). For example, the back metal contact 408 may be a conductive post or via that connects the back metal contact 408 to the back metal line 208(1) in the BS-BEOL metallization structure 108. For example, the back metal contact 408 may be of a sufficiently small diameter to connect the back metal contact 408 to the back metal line 208(1) without interfering with TSVs or other vias in adjacent routing areas.

[0044] Note that although the FET 400 in Figures 4A and 4B illustrates a source S connected to the back metal line 208(1) for back-side routing of power signals to the source S, and a drain D connected to the front metal line 200(1) for front-side routing of I / O signals to the drain D, this is not limiting. As another example, the drain D of the FET 400 may be connected to the back metal line 208(1) for back-side routing of power signals to the drain D, and the source S may be connected to the front metal line 200(1) for front-side routing of I / O signals to the source S of the FET 400. Furthermore, if desired, the source S and / or drain D of the FET 400 may be connected via both front and back routes for I / O signal and / or power routing. Additionally, the gate G of the FET 400 may be connected to the front metal contact and / or the back metal contact to provide gate connectivity to the front and / or back metal lines for I / O signal and / or power routing. The gate G of the FET 400 includes a gate top surface 418T that can be connected to a front metal contact and a gate bottom surface 418B that can be connected to a back metal contact to provide top and / or back routing to the gate G.

[0045] Figure 5 is a flowchart illustrating an exemplary process 500 for manufacturing an IC (e.g., IC 102 in Figures 1-2B and 4A-4B), which includes an FS-BEOL metallization structure providing front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing back-side power routing to (multiple) semiconductor devices. For example, the process 500 in Figure 5 will be discussed below with respect to IC 102 in Figures 1-2B and 4A-4B.

[0046] Process 500 includes forming a semiconductor layer 114 on a substrate 132, the semiconductor layer 114 including a front side 120F and a back side 120B opposite to the front side 120F (block 502 in FIG. 5). Process 500 also includes forming a semiconductor device 112 in the semiconductor layer 114 (block 504 in FIG. 5). Process 500 also includes forming an FS-BEOL metallization structure 106 adjacent to the front side 120F of the semiconductor layer 114, the FS-BEOL metallization structure 106 including a front metal line 200 and a front interconnect 202 coupled to the front metal line 200 (block 506 in FIG. 5). Process 500 also includes forming a BS-BEOL metallization structure 108 adjacent to the back side 120B of the semiconductor layer 114, the BS-BEOL metallization structure 108 including a back metal line 208 coupled to the semiconductor device 112 (block 508 in FIG. 5). The procedure also includes forming a front-back connection structure 214 (block 510 in FIG5) that is coupled to the front metal line 200 and the back metal line 208.

[0047] Figures 6A to 6C are flowcharts illustrating another exemplary process 600 for manufacturing an IC, which includes an FS-BEOL metallization structure providing front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing back-side power routing to (multiple) semiconductor devices. Process 600 in Figures 6A to 6C can be used to manufacture an IC (e.g., IC 102 in Figures 1 to 2A and 4A to 4B). Figures 7A to 7G are exemplary manufacturing stages of an IC manufactured according to the processes in Figures 6A to 6C. As shown below, in manufacturing process 600 of Figures 6A to 6C, the FS-BEOL metallization structure is formed before the BS-BEOL metallization structure is formed. This involves forming two carrier wafers in the IC formation process such that the FS-BEOL metallization structure and the BS-BEOL metallization structure disposed on opposite surfaces of the semiconductor layer to be processed have sufficient mechanical stability.

[0048] The exemplary manufacturing stages of process 600 in Figures 6A to 6C and the ICs manufactured in Figures 7A to 7G are described below with reference to each other. References to components in the manufacturing stages of Figures 7A to 7G for process 600 in Figures 6A to 6C and the ICs manufactured according to process 600 in Figures 6A to 6C use the same or similar component names as those in IC packages 100 and their ICs 102 in Figures 1 to 2B and Figures 4A to 4B. The discussion of examples of these components in Figures 1 to 2B and Figures 4A to 4B also applies to the manufacturing stages of the ICs in Figures 7A to 7G.

[0049] In this configuration, process 600 includes forming a semiconductor layer 714 on a substrate 732, as shown in manufacturing stage 700A of FIG. 7A. The semiconductor layer 714 includes a front side 720F and a back side 720B opposite to the front side 720F (block 602 in FIG. 6A). A semiconductor device 712 is formed in the semiconductor layer 714. Process 600 also includes forming an FS-BEOL metallization structure 706 on the front side 720F of the semiconductor layer 714 before forming a BS-BEOL metallization structure adjacent to the back side 720F of the semiconductor layer 714, as shown in manufacturing stage 700A of FIG. 7A (block 602 in FIG. 6A). The FS-BEOL metallization structure 706 facilitates I / O routing and power routing to the subsequent BS-BEOL metallization structure to route power signals. The next step in process 600 is to form a carrier wafer 734 on the front side 736F of the FS-BEOL metallization structure 706, as shown in fabrication stage 700B in Figure 7B (block 604 in Figure 6A). This allows fabrication stage 600B to be manipulated to allow grinding of the back side 738B of the substrate 732 to fabricate the IC, as shown in fabrication stage 700C in Figure 7C (block 606 in Figure 6C).

[0050] Referring to FIG6B, the next step of process 600 is to form a BS-BEOL metallization structure of the IC to facilitate power routing. In this manner, process 600 includes forming a BS-BEOL metallization structure 708 adjacent to the back side 736B of the semiconductor layer 714, as shown in manufacturing stage 700D in FIG7D (block 608 in FIG6B). Process 600 then involves forming a second carrier wafer 742 on the back side 740B of the BS-BEOL metallization structure 708, as shown in manufacturing stage 700E in FIG7E (block 610 in FIG6B). This allows for the mechanically stable handling of the BS-BEOL metallization structure 708. Furthermore, the second carrier wafer 742 allows manufacturing stage 700E to be manipulated to have the stability required for removing the first carrier wafer 734 for fabricating the IC to form an IC die 704, as shown in manufacturing stage 700F in FIG7F (block 612 in FIG6C). The carrier wafer 734 is removed to allow access to the FS-BEOL metallization structure 706, forming conductive bumps coupled to the FS-BEOL metallization structure 706 to provide signal access to the semiconductor device 712 formed in the semiconductor layer 714. Subsequently, process 600 includes forming a plurality of conductive bumps 710 on the front side 736F of the FS-BEOL metallization structure 706, wherein at least one conductive bump 710 is coupled to the front side interconnect 702 of the FS-BEOL metallization structure 706 to provide an IC die 704, as shown in manufacturing stage 700G in FIG7G (block 614 in FIG6C).

[0051] Figures 8A and 8B are flowcharts illustrating another exemplary process 800 for manufacturing an IC, which includes an FS-BEOL metallization structure providing front-side I / O signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing back-side power routing to (multiple) semiconductor devices. Process 800 in Figures 8A and 8B can be used to manufacture an IC (e.g., IC 102 in Figures 1-2A and 4A-4B). Figures 9A-9E are exemplary manufacturing stages of an IC manufactured according to the process in Figures 8A and 8B. As described below, in manufacturing process 800 in Figures 8A and 8B, the BS-BEOL metallization structure is formed prior to the formation of the FS-BEOL metallization structure. This involves forming a single carrier wafer on the BS-BEOL metallization structure during the IC formation process, because the single carrier wafer can be held in place after processing the BS-BEOL metallization structure and during subsequent formation and processing of the FS-BEOL metallization structure. Since access to the IC is performed via metal lines in the FS-BEOL metallization structure, conductive bumps can be formed using a carrier wafer coupled to the BS-BEOL metallization structure and coupled to the FS-BEOL metallization structure.

[0052] The exemplary manufacturing stages of process 800 in Figures 8A and 8B and the ICs manufactured in Figures 9A through 9E are described below with reference to each other. References to components in process 800 in Figures 8A and 8B and in the manufacturing stages of the ICs manufactured according to process 800 in Figures 8A and 8B in Figures 9A through 9E use the same or similar component names as those in IC packages 100 and their ICs 102 in Figures 1 through 2B and Figures 4A through 4B. The discussion of examples of these components in Figures 1 through 2B and Figures 4A through 4B also applies to the manufacturing stages of the ICs in Figures 9A through 9E.

[0053] In this process, procedure 800 includes first forming a BS-BEOL metallization structure 908 on the back side 938B of substrate 932, as shown in fabrication stage 900A in FIG9A (block 802 in FIG8A). In this example, the BS-BEOL metallization structure 908 is formed before the semiconductor layer and the FS-BEOL metallization structure are formed. The next step of procedure 800 is to form a carrier wafer 934 on the back side 940B of the BS-BEOL metallization structure 908, as shown in fabrication stage 900B in FIG9B (block 804 in FIG8A). This is used to provide mechanical stability for the layers that will form the IC. The next step of procedure 800 is to polish the front side 938F of substrate 932, as shown in fabrication stage 900B in FIG9B, to provide a polished substrate 932 as shown in fabrication stage 900C in FIG9C (block 806 in FIG8A).

[0054] The next step in process 800 is to form a semiconductor layer 914 on the front side 938F of the substrate 932, as shown in manufacturing stage 900D in FIG9D (block 808 in FIG8B). The semiconductor layer 914 includes a front side 920F and a back side 920B opposite to the front side 920F. A semiconductor device 912 is formed in the semiconductor layer 914. Process 800 also includes forming an FS-BEOL metallization structure 906 on the front side 920F of the semiconductor layer 914 before forming a BS-BEOL metallization structure 908 adjacent to the back side 920B of the semiconductor layer 914 to form an IC die 904, as shown in manufacturing stage 900D in FIG9D (block 808 in FIG8B). The previously formed carrier wafer 934 is retained to provide mechanical structures to support the formation and processing of the FS-BEOL metallization structure 906. The FS-BEOL metallization structure 906 facilitates I / O signal routing and routes power signals to the BS-BEOL metallization structure 908 for power signal routing. Procedure 800 then includes forming a plurality of conductive bumps 910 on the front side 936F of the FS-BEOL metallization structure 906, wherein at least one conductive bump 910 is coupled to the front side interconnect 902 of the FS-BEOL metallization structure 906 of the IC die 904, as shown in manufacturing stage 900E of FIG9E (block 810 in FIG8B).

[0055] Note that the term "couple" and its derivatives (such as "couples" and "coupled") do not necessarily require a direct connection. For example, coupling can include electrical coupling. It should also be noted that the terms "front," "front side," "back," and "back side" as used herein are relative terms. For example, these terms are not intended to restrict or imply a strict orientation of "front" or "front side" relative to the ground above "back" or "back side," but only a relative orientation to another stated orientation. For example, the "front side" of a component is a side on the generally opposite side of the "back side" of the component.

[0056] Each IC (including, but not limited to, the ICs in Figures 1 to 2B, 4A to 4B, 7A to 7G and 9A to 9E) of any of the forms disclosed herein, including FS-BEOL metallization structures that provide front input / output (I / O) signal routing to (multiple) semiconductor devices and BS-BEOL metallization structures that provide rear power routing to (multiple) semiconductor devices, can be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite broadcasting, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0057] In this context, Figure 10 illustrates an example of a processor-based system 1000 according to any of the embodiments disclosed herein. The processor-based system 1000 includes an IC comprising an FS-BEOL metallization structure providing front input / output (I / O) signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing back-side power routing to (multiple) semiconductor devices, including but not limited to the ICs in Figures 1-2B, 4A-4B, 7A-7G, and 9A-9E. For example, the IC may be a FET used in CMOS circuitry. In this example, the processor-based system 1000 may be configured as IC 1004 as a system-on-a-chip (SoC) 1006. The processor-based system 1000 includes a CPU 1008, which includes one or more processors 1010, which may also be referred to as a CPU core or processor core. CPU 1008 may have a cache memory 1012 coupled to CPU 1008 for fast access to temporarily stored data. CPU 1008 is coupled to system bus 1014 and can couple master and slave devices included in the processor-based system 1000 to each other. As is known, CPU 1008 communicates with these other devices by exchanging address, control, and data information on system bus 1014. For example, CPU 1008 can convey bus transaction requests to memory controller 1016, which is an instance of a slave device. Although not shown in FIG. 10, multiple system buses 1014 may be provided, each of which may have a different configuration.

[0058] Other master and slave devices can be connected to system bus 1014. As shown in FIG10, for example, these devices may include: a memory system 1020 including a memory controller 1016 and multiple memory arrays 1018, one or more input devices 1022, one or more output devices 1024, one or more network peripheral devices 1026, and one or more display controllers 1028. Each of the memory system 1020, the one or more input devices 1022, the one or more output devices 1024, the one or more network peripheral devices 1026, and the one or more display controllers 1028 may include an IC. The multiple input devices 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The multiple output devices 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The multiple network peripheral devices 1026 may be any device configured to allow data exchange with network 1030. Network 1030 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Multiple network peripheral devices 1026 can be configured to support any desired type of communication protocol.

[0059] CPU 1008 can also be configured to access multiple display controllers 1028 on system bus 1014 to control information sent to one or more displays 1032. The multiple display controllers 1028 send information to be displayed to the multiple displays 1032 via one or more video processors 1034, which process the information to be displayed into a format suitable for the multiple displays 1032. The multiple displays 1032 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0060] Figure 11 illustrates an exemplary wireless communication device 1100 comprising radio frequency (RF) components formed of one or more ICs according to any of the forms disclosed herein, wherein the ICs include an FS-BEOL metallization structure providing front input / output (I / O) signal routing to (multiple) semiconductor devices and a BS-BEOL metallization structure providing rear power routing to (multiple) semiconductor devices, including but not limited to the ICs in Figures 1-2B, 4A-4B, 7A-7G, and 9A-9E. For example, the wireless communication device 1100 may include or be incorporated in any of the devices in the aforementioned reference devices. As shown in Figure 11, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include memory for storing data and code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. Typically, wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of transceiver 1104 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0061] Transmitter 1108 or receiver 1110 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, for receiver 1110, it is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 1100 of Figure 11, transmitter 1108 and receiver 1110 are implemented using a direct conversion architecture.

[0062] In the transmission path, data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1108. In the exemplary wireless communication device 1100, data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) for converting digital signals generated by data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0063] Within transmitter 1108, low-pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers AMP 1116(1) and 1116(2) amplify the signals from low-pass filters 1114(1) and 1114(2), respectively, and provide I and Q baseband signals. Upconverter 1118 uses the I and Q transmit (TX) local oscillator (LO) signals from mixers 1120(1) and 1120(2) from TX LO signal generator 1122 to upconvert the I and Q baseband signals to provide upconverted signal 1124. Filter 1126 filters the upconverted signal 1124 to remove unwanted signals caused by frequency upconversion and noise in the receive band. Power amplifier (PA) 1128 amplifies the up-converted signal 1124 from filter 1126 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed via duplexer or switch 1130 and transmitted via antenna 1132.

[0064] In the receiving path, antenna 1132 receives the signal transmitted by the base station and provides the received RF signal, which is routed via duplexer or switch 1130 and provided to low-noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate at a specific receive (RX) to TX ((RX)-to-TX) duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Down-conversion mixers 1138(1) and 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by amplifiers (AMPs) 1142(1) and 1142(2) and further filtered by low-pass filters 1144(1) and 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes ADCs 1146(1) and 1146(2) to convert the analog input signals into digital signals, which are further processed by data processor 1106.

[0065] In the wireless communication device 1100 of Figure 11, the TX LO signal generator 1122 generates I and Q TX LO signals for frequency up-conversion, while the RX LO signal generator 1140 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, the RX PLL circuit 1150 receives timing information from the data processor 1106 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0066] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described herein in conjunction with the various forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. For example, the master and slave devices described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in functional forms. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as leading out of the scope of this invention.

[0067] The various illustrative logic blocks, modules, and circuits described in connection with the various states disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, individual gate or transistor logic, individual hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any general processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors integrated with a DSP core, or any other such configuration).

[0068] The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor, allowing the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as separate components in a remote station, base station, or server.

[0069] It should also be noted that the operational steps described in any of the exemplary embodiments herein are for the purpose of providing examples and discussion. The described operations can be performed in many different orders besides the order shown. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art to which this invention pertains. Those skilled in the art to which this invention pertains will also understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0070] The preceding description of this invention is provided to enable those skilled in the art to make or use it. Various modifications to this invention will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this invention is not intended to be limited to the examples and designs described herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0071] 100: IC package 102:IC 104: IC die 106:FS-BEOL metallized structure 108:BS-BEOL metallized structure 110: Die-to-die interconnect 112: Semiconductor device 114: Semiconductor layer 115: Proactive Side 116: Packaging substrate 117: Printed Circuit Board (PCB) 118: External conductive bump 120B: Back 120F: Front 122B: Back 122F: Front 124: Memory Chip 125: Power Management IC (PMIC) Chip 126: Second packaging substrate 127: Passive Side 128: External conductive bump 129: Conductive bump 130: Via 132: Substrate 200(1): Front metal line 200(2): Front metal line 200(6): Front metal line 200(7): Front metal line 200(8): Front metal line 200N: Front metal wire 200P: Front metal wire 202: Frontal Interconnect 204: Interconnection Layer 206: Via 208(1): Back metal wire 208(2): Back metal wire 210: Backside via 212: Backside via 214: Front-back connection structure 216:FET 300: IC package 304: IC die 306:FS-BEOL metallized structure 310: Conductive bump 312: Semiconductor device 314: Semiconductor layer 316: Packaging substrate 318: Conductive bump 324: Memory chip 332: Substrate 400:FET 402: Conductive Channel 404(1): Nanostructure 404(2): Nanostructure 404(3): Nanostructure 406(1): First end 406(2): Second end 408: Metal contact on the back 410B: Source bottom surface 410T: Active Top Surface 412B: Drain bottom surface 412T: Top surface of the drain pole 414: Front metal contact 418B: Gate bottom surface 418T: Gate top surface 500: Program 502: Square 504: Square 506: Square 508: Square 510: Square 600: Program 602: Square 604: Square 606: Square 608: Square 610: Square 612: Square 614: Square 700A: Manufacturing Stage 700B: Manufacturing Stage 700C: Manufacturing Stage 700D: Manufacturing Stage 700E: Manufacturing Stage 700F: Manufacturing Stage 700G: Manufacturing Stage 702: Front-side interconnect 704: IC die 706:FS-BEOL metallized structure 708:BS-BEOL metallized structure 710: Conductive bump 712: Semiconductor Device 714: Semiconductor layer 720B: Back 720F: Front 732: Substrate 734: First carrier chip 736B: Back 736F: Front 738B: Back 740B: Back 742: Second carrier chip 800: Program 802: Square 804: Square 806: Square 808: Square 810: Square 900A: Manufacturing Stage 900B: Manufacturing Stage 900C: Manufacturing Stage 900D: Manufacturing Stage 900E: Manufacturing Stage 936F: Front 902: Front Interconnect 904: IC die 906:FS-BEOL metallized structure 908:BS-BEOL metallized structure 910: Conductive bump 912: Semiconductor device 914: Semiconductor layer 932: Substrate 934: Carrier wafer 936F: Front 938B: Back 938F: Front 940B: Back 1000: System 1004:IC 1006: System-on-a-Chip (SoC) 1008: CPU 1010: Processor 1012: Cache memory 1014: System Bus 1016: Memory Controller 1018: Memory Array 1020: Memory System 1022: Input devices 1024: Output device 1026: Network peripheral equipment 1028: Display Controller 1030: Internet 1032: Monitor 1034: Video Processor 1100: Wireless communication equipment 1104: Transceiver 1106: Data Processor 1108: Transmitter 1110: Receiver 1112(1): Digital-to-Analog Converter 1112(2): Digital-to-Analog Converter 1114(1): Low-pass filter 1114(2): Low-pass filter 1116(1): Amplifier AMP 1116(2): Amplifier AMP 1118: Up converter 1120(1): Mixer 1120(2): Mixer 1122: TX LO signal generator 1124: Signal 1126: Filter 1128: Power Amplifier (PA) 1130: Duplexer or switch 1132: Antenna 1134: Low-noise amplifier (LNA) 1136: Filter 1138(1): Down-conversion mixer 1138(2): Down-conversion mixer 1140:RX LO signal generator 1142(1): Amplifier 1142(2): Amplifier 1144(1): Low-pass filter 1144(2): Low-pass filter 1146(1):ADC 1146(2):ADC 1148: TX Phase-Locked Loop (PLL) Circuit 1150:RX PLL circuit A1-A1': Cross-section line BS-ML1: Backside metal layer BS-ML2: Backside Metal Layer FS-ML1: Front metal layer FS-ML2: Front Metallic Layer FS-ML3: Front Metallic Layer FS-ML4: Front Metallic Layer FS-ML5: Front Metallic Layer FS-ML6: Front Metallic Layer FS-ML7: Front Metallic Layer FS-ML8: Front Metallic Layer D: Jiji G: Grounding S: Source X: axis Y: axis Z: Axis

Claims

1. An integrated circuit (IC), comprising: A semiconductor layer includes a front side and a back side opposite to the front side, the semiconductor layer including a semiconductor device; A front-side (FS) back-end process (BEOL) metallization structure is configured adjacent to the front side of the semiconductor layer. The FS-BEOL metallization structure includes: a front-side metal line; a front-side interconnect coupled to the front-side metal line; a second front-side metal line; and a second front-side interconnect coupled to the second front-side metal line; the second front-side metal line is coupled to the semiconductor device. A back-side (BS) BEOL metallization structure is configured adjacent to the back side of the semiconductor layer. The BS-BEOL metallization structure includes: a back-side metal line; a front-side to back-side interconnect coupled to the front-side metal line and the back-side metal line; and the back-side metal line coupled to the semiconductor device.

2. According to the IC in request item 1, where: The front interconnect is configured to receive a power signal; and the back metal line is configured to transmit the power signal to the semiconductor device.

3. According to the IC in request item 1, where: The front interconnect is configured to receive a ground signal; and the back metal line is configured to transmit the ground signal to the semiconductor device.

4. According to the IC in request item 1, where: The second front interconnect is configured to receive input / output (I / O) signals; The second front-side metal line is configured to transmit the I / O signal to the semiconductor device.

5. The IC according to request item 1 also includes: A front-side metal contact is coupled to the semiconductor device and the second front-side metal line; And a back metal contact, coupled to the semiconductor device and the back metal line.

6. The IC according to claim 5 also includes: A front-side vertical interconnect channel (via) is coupled to the front-side metal contact and the second front-side metal line; And a back via, coupled to the back metal contact and the back metal line.

7. The IC according to claim 1, wherein the front-back connection structure includes a switch.

8. The IC according to claim 7, wherein the head switch includes a field-effect transistor (FET).

9. The IC according to claim 8, wherein the FET includes a drain and a source, one of the drain and the source being coupled to the front metal line, and one of the source and the drain not coupled to the front metal line being coupled to the back metal line.

10. The IC according to claim 1 also includes a vertical interconnect channel (via) coupled to the front-to-back connection structure and the back metal line.

11. The IC according to claim 10, wherein the via includes a through-silicon via (TSV) configured to penetrate the semiconductor layer and be coupled to the front-back connection structure and the back metal line.

12. The IC according to claim 1, wherein the BS-BEOL metallization structure also includes a back metal layer, the back metal layer including the back metal line.

13. The IC according to claim 12, wherein the BS-BEOL metallization structure also includes a second back metal layer, the second back metal layer being configured adjacent to the back metal layer, the second back metal layer including a second back metal line coupled to the back metal line.

14. The IC according to claim 13 also includes a back vertical interconnect channel (via) that couples the second back metal line to the back metal line.

15. The IC according to claim 1 also includes a conductive bump coupled to the front interconnect.

16. According to the IC in request item 1, where: The semiconductor layer also includes a plurality of second semiconductor devices; and the back metal line is coupled to the plurality of second semiconductor devices.

17. According to the IC in request item 1, where: The semiconductor layer also includes a plurality of second semiconductor devices; The FS-BEOL metallization structure also includes: a plurality of second front-side metal lines; a plurality of second front-side interconnects, each second front-side interconnect being coupled to a corresponding second front-side metal line among the plurality of second front-side metal lines; and the BS-BEOL metallization structure also includes: a plurality of second back-side metal lines; and the front-back connection structure includes a plurality of second front-back connection structures, each second front-back connection structure being coupled to a corresponding second front-side metal line among the plurality of second front-side metal lines and a corresponding second back-side metal line among the plurality of second back-side metal lines; the plurality of second back-side metal lines being coupled to a corresponding second semiconductor device among the plurality of second semiconductor devices.

18. A method of manufacturing an integrated circuit (IC), comprising the steps of: forming a semiconductor layer on a substrate, the semiconductor layer including a front side and a back side opposite to the front side; forming a semiconductor device in the semiconductor layer; and forming a front-side (FS) back-to-office (BEOL) (FS-BEOL) metallization structure adjacent to the front side of the semiconductor layer, the FS-BEOL metallization structure comprising: A front-facing metal line; A front-side interconnect is coupled to the front-side metal line; A second front metal line; A second front-side interconnect is coupled to the second front-side metal line; the second front-side metal line is coupled to the semiconductor device; a back-side (BS) BEOL (BS-BEOL) metallization structure is formed adjacent to the back-side of the semiconductor layer, the BS-BEOL metallization structure including: a back-side metal line coupled to the semiconductor device; And form a front-back connection structure, which is coupled to the front metal line and the back metal line.

19. The method according to claim 18 includes the following steps: forming the FS-BEOL metallization structure adjacent to the front side of the semiconductor layer before forming the BS-BEOL metallization structure adjacent to the back side of the semiconductor layer.

20. The method according to claim 19 also includes the following steps: before forming the BS-BEOL metallization structure on the back side adjacent to the semiconductor layer: forming a carrier wafer on a front side of the FS-BEOL metallization structure; and grinding a back side of the substrate.

21. The method according to claim 20 also includes the following steps: forming a second carrier wafer on the back side of the BS-BEOL metallized structure; removing the carrier wafer on the front side of the FS-BEOL metallized structure; and forming a plurality of conductive bumps on the front side of the FS-BEOL metallized structure, one of the conductive bumps being coupled to the front interconnect.

22. The method according to claim 18 includes the following steps: forming the BS-BEOL metallization structure adjacent to the back side of the semiconductor layer before forming the FS-BEOL metallization structure adjacent to the front side of the semiconductor layer.

23. The method according to claim 22 also includes the following steps: forming a carrier wafer on a back side of the BS-BEOL metallization structure; and grinding a front side of the substrate.

24. The method according to claim 23 also includes the following steps: forming a plurality of conductive bumps on a front side of the FS-BEOL metallized structure, one of the conductive bumps being coupled to the front interconnect; and removing the carrier wafer from the back side of the BS-BEOL metallized structure.

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