Level shifter including dummy circuit and method of manufacturing the same

Abstract

This invention provides a level shifter including dummy circuitry and a method for manufacturing the same. This disclosure provides a technique for level shifters that allows selection of a single-stage or two-stage level shifter by simple changes to the wiring. When a single-stage level shifter is selected, some circuitry can be retained as dummy circuitry.

Description

Technical Field

[0001] This disclosure relates to a level shifter. Prior Technology

[0002] Various electrical devices, such as displays, may include level shifters for converting voltage signals from one voltage level to a desired voltage level.

[0003] A level shifter can convert a low-voltage level input signal into a high-voltage level output signal, or vice versa.

[0004] Level shifters can take various forms, and these forms are primarily determined by the operating environment of the electrical installations using the level shifters. Based on an understanding of these environments, level shifter designers create level shifters that are adaptable to different operating conditions.

[0005] With the diversification of electrical installations and their widespread application in recent years, diverse demands have arisen for the design of level shifters. However, this diversity can increase the workload for designers and lead to higher manufacturing costs. Summary of the Invention

[0006] One aspect of this disclosure provides a level shifter technique that is easy to modify in design. Another aspect of this disclosure provides a technique for manufacturing level shifters that allows selection of single-stage or two-stage level shifters simply by changing the wiring.

[0007] In one aspect, this disclosure provides a level shifter, comprising: a level shifter circuit including a first transistor and a second transistor, the first transistor being turned on and off by an input voltage to generate a voltage having a waveform opposite to the input voltage at an inverting node, and the second transistor being turned on and off by an inverted voltage having a waveform opposite to the input voltage to generate a voltage having the same waveform as the input voltage at an output node; and a dummy circuit including a first dummy transistor and a second dummy transistor, the gate and source terminals of the first dummy transistor being short-circuited by a first short circuit, and the gate and source terminals of the second dummy transistor being short-circuited by a second short circuit, wherein the dummy circuit operates as a two-stage level shifter circuit when the first and second short circuits are removed.

[0008] When the dummy circuit operates as the two-stage level shifter circuit, the output voltage can be determined using the voltage at the drain terminal of the second dummy transistor, and the inverted output voltage can be determined using the voltage at the drain terminal of the first dummy transistor.

[0009] The first transistor and the first dummy transistor can be different types of transistors, and the second transistor and the second dummy transistor can be different types of transistors.

[0010] In another aspect, this disclosure provides a level shifter, comprising: a first path circuit in which a first transistor and a third transistor are connected in series between a high driving voltage and a low driving voltage; a second path circuit in which a second transistor and a fourth transistor are connected in series between the high driving voltage and the low driving voltage; a third path circuit in which a first dummy transistor and a third dummy transistor are connected in series between the high driving voltage and the low driving voltage; and a fourth path circuit in which a second dummy transistor and a fourth dummy transistor are connected in series between the high driving voltage and the low driving voltage. Between the dynamic voltage and the low drive voltage, wherein an input voltage is supplied to the gate terminal of the first transistor, an inverted voltage having a waveform opposite to the input voltage is supplied to the gate terminal of the second transistor, the drain terminal of the first transistor is electrically connected to the inverting node, the drain terminal of the second transistor is electrically connected to the output node, the output node is electrically connected to the gate terminal of the third transistor, and the inverting node is electrically connected to the gate terminal of the fourth transistor, wherein the gate terminal and source terminal of the first dummy transistor are short-circuited by a first short circuit, and the gate terminal and source terminal of the second dummy transistor are short-circuited by a second short circuit.

[0011] The drain terminal of the first dummy transistor can be electrically connected to the gate terminal of the fourth dummy transistor, and the drain terminal of the second dummy transistor can be electrically connected to the gate terminal of the third dummy transistor.

[0012] In another aspect, this disclosure provides a method for manufacturing a level shifter, the method comprising: placing a transistor shield; forming a first transistor, a second transistor, a first dummy transistor, and a second dummy transistor in accordance with the transistor shield; placing a metal shield; and using the metal shield to mount wiring in such a manner that: the first transistor is turned on and off using an input voltage to generate a voltage having a waveform opposite to the input voltage at an inverting node; the second transistor is turned on and off using an inverting voltage having a waveform opposite to the input voltage to generate a voltage having a waveform identical to the input voltage at an output node; the gate and source terminals of the first dummy transistor are short-circuited; and the gate and source terminals of the second dummy transistor are short-circuited.

[0013] The manufacturing method may further include forming a passivation layer after wiring is installed, and exposing the output node and the inverting node through the passivation layer.

[0014] The first dummy transistor and the second dummy transistor can form a two-stage level shifter circuit by changing the metal shield.

[0015] When forming the transistor, a first dummy limiting transistor for limiting the amount of current flowing to the first dummy transistor and a second dummy limiting transistor for limiting the amount of current flowing to the second dummy transistor can also be formed. When installing wiring, the wiring can be installed in such a way that the gate and source terminals of the first dummy limiting transistor and the gate and source terminals of the second dummy limiting transistor are short-circuited.

[0016] Another exemplary embodiment of this disclosure provides a level shifter, comprising: a level shifter circuit including a first transistor and a second transistor, the first transistor being turned on and off using an input voltage to generate a voltage having a waveform opposite to the input voltage at an inverting node, and the second transistor being turned on and off using an inverted voltage having a waveform opposite to the input voltage to generate a voltage having the same waveform as the input voltage at an output node; and a dummy circuit including transistors configured in the form of a two-stage level shifter circuit, the transistors including a first dummy transistor and a second dummy transistor with their gate terminals and source terminals short-circuited.

[0017] As described above, according to embodiments of this disclosure, the design of the level shifter can be changed more easily, and a single-stage shifter or a two-stage level shifter can be selected simply by changing the wiring in the manufacturing process. Simple Explanation of the Diagram

[0018] Figure 1 is a circuit diagram of a single-stage level shifter.

[0019] Figure 2 is a circuit diagram of a two-stage level shifter.

[0020] Figure 3 is a circuit diagram of a level shifter including a dummy circuit.

[0021] Figure 4 is a flowchart of a method for manufacturing a level shifter including a dummy circuit.

[0022] Figure 5 is a diagram showing the pattern used to form the transistor.

[0023] Figure 6A is a diagram showing the metal layer pattern used to form a two-stage level shifter.

[0024] Figure 6B is a diagram showing the metal layer pattern used to form a single-level level shifter. Implementation

[0025] Figure 1 is a circuit diagram of a single-stage level shifter.

[0026] Referring to Figure 1, the level shifter 100 may include a first path circuit PT1 and a second path circuit PT2 formed between a first high drive voltage VDD1 and a first low drive voltage VSS1.

[0027] The first high driving voltage VDD1 can be electrically connected to one side of the first path circuit PT1, and the first low driving voltage VSS1 can be electrically connected to the other side, and current can flow from the first high driving voltage VDD1 to the first low driving voltage VSS1 via the first path circuit PT1.

[0028] The first path circuit PT1 may include a first transistor TR1, a third transistor TR3, and a fifth transistor TR5. Furthermore, the first transistor TR1, the third transistor TR3, and the fifth transistor TR5 may be connected in series with each other.

[0029] Although for ease of explanation, Figure 1 shows the first transistor TR1 as an N-type transistor and the third transistor TR3 and the fifth transistor TR5 as P-type transistors, this disclosure is not limited thereto.

[0030] The input voltage VI can be supplied to the gate terminal of the first transistor TR1. Furthermore, the first transistor TR1 can be turned on and off according to the voltage level of the input voltage VI.

[0031] The source terminal of the first transistor TR1 can be connected to a first low drive voltage VSS1, and its drain terminal can be connected to the inverting node NDOB. Using this structure, when a high-level input voltage VI is supplied to the gate terminal of the first transistor TR1, a low-level inverted output voltage VOB can be generated at the inverting node NDOB.

[0032] The gate terminal of the third transistor TR3 can be connected to the output node NDO. Furthermore, the source terminal of the third transistor TR3 can be electrically connected to the first high drive voltage VDD1, and its drain terminal can be connected to the inverting node NDOB. As described below, an output voltage VO with the same waveform as the input voltage VI can be generated at the output node NDO. The third transistor TR3 can be turned on and off using the output voltage VO. Using this structure, when a low-level input voltage VI is supplied, a high-level inverted output voltage VOB can be generated at the inverting node NDOB.

[0033] The fifth transistor TR5 can limit the amount of current flowing to the first path circuit PT1.

[0034] The gate terminal of the fifth transistor TR5 can be supplied with a first bias voltage VBIA1. Furthermore, the source terminal of the fifth transistor TR5 can be connected to a first high drive voltage VDD1, and its drain terminal can be connected to the source terminal of the third transistor TR3.

[0035] The first high driving voltage VDD1 can be electrically connected to one side of the second path circuit PT2, and the first low driving voltage VSS1 can be electrically connected to the other side, and current can flow from the first high driving voltage VDD1 to the first low driving voltage VSS1 via the second path circuit PT2.

[0036] The second path circuit PT2 may include a second transistor TR2, a fourth transistor TR4, and a sixth transistor TR6. Furthermore, the second transistor TR2, the fourth transistor TR4, and the sixth transistor TR6 may be connected in series with each other.

[0037] Although for ease of explanation, FIG1 shows the second transistor TR2 as an N-type transistor and the fourth transistor TR4 and the sixth transistor TR6 as P-type transistors, this disclosure is not limited thereto.

[0038] An inverting voltage VIB can be supplied to the gate terminals of the second transistor TR2. Furthermore, the second transistor TR2 can be turned on and off according to the voltage level of the inverting voltage VIB.

[0039] The source terminal of the second transistor TR2 can be connected to the first low drive voltage VSS1, and its drain terminal can be connected to the output node NDO. Using this structure, when a high-level inverted voltage VIB is supplied to the gate terminal of the second transistor TR2, a low-level output voltage VO can be generated at the output node NDO. Because the inverted voltage VIB has a waveform that is inversely phase to the input voltage VI, the output voltage VO can have the same waveform as the input voltage VI.

[0040] The gate terminal of the fourth transistor TR4 can be connected to the inverting node NDOB. Furthermore, the source terminal of the fourth transistor TR4 can be electrically connected to the first high drive voltage VDD1, and its drain terminal can be connected to the output node NDO.

[0041] As described above, an inverted output voltage VOB with the same waveform as the inverted voltage VIB can be generated at the inverting node NDOB. The fourth transistor TR4 can be turned on and off using the inverted output voltage VOB. With this structure, a high-level inverted output voltage VOB can be generated at the output node NDO when a low-level inverted voltage VIB is supplied.

[0042] The sixth transistor TR6 can limit the amount of current flowing to the second path circuit PT2.

[0043] The gate terminal of the sixth transistor TR6 can be supplied with a first bias voltage VBIA1.

[0044] Furthermore, the source terminal of the sixth transistor TR6 can be connected to the first high drive voltage VDD1, and its drain terminal can be connected to the source terminal of the fourth transistor TR4.

[0045] Figure 2 is a circuit diagram of a two-stage level shifter.

[0046] Referring to Figure 2, the level shifter 200 may include a single-stage circuit 210 and a two-stage circuit 220.

[0047] The single-stage circuit 210 may include a first path circuit PT1 and a second path circuit PT2. The single-stage circuit 210 may have the same circuit configuration as the single-stage level shifter explained with reference to FIG1 (see 100 in FIG1). Therefore, a detailed description of the single-stage circuit 210 will be omitted.

[0048] The difference between the single-stage level shifter depicted in Figure 1 (see 100 in Figure 1) and the single-stage circuit 210 is that: a second high drive voltage VDD2 is supplied as a high drive voltage, a second low drive voltage VSS2 is supplied as a low drive voltage, and a second bias voltage VBIA2 is supplied to the fifth transistor TR5 and the sixth transistor TR6.

[0049] Furthermore, another difference between the single-stage circuit 210 and the single-stage level shifter depicted in FIG1 (see 100 in FIG1) is that the output of the single-stage circuit 210 is connected to the input of the two-stage circuit 220. To illustrate this difference, the output node of the single-stage level shifter depicted in FIG1 (see 100 in FIG1) is referred to as the first output node NDO1, and its inverting node is referred to as the first inverting node NDOB1.

[0050] The two-stage circuit 220 may include a third-path circuit PT3 and a fourth-path circuit PT4.

[0051] The second high drive voltage VDD2 can be electrically connected to one side of the third path circuit PT3, and the second low drive voltage VSS2 can be electrically connected to the other side, and current can flow from the second high drive voltage VDD2 to the second low drive voltage VSS2 via the third path circuit PT3.

[0052] The third path circuit PT3 may include a seventh transistor TR7, a ninth transistor TR9, and an eleventh transistor TR11. Furthermore, the seventh transistor TR7, the ninth transistor TR9, and the eleventh transistor TR11 may be connected in series with each other.

[0053] Although for ease of explanation, Figure 2 shows the seventh transistor TR7 as a P-type transistor and the ninth transistor TR9 and the eleventh transistor TR11 as N-type transistors, this disclosure is not limited thereto.

[0054] The gate terminal of the seventh transistor TR7 can be connected to the first output node NDO1 of the single-stage circuit 210. Furthermore, the seventh transistor TR7 can be turned on and off according to the voltage level at the first output node NDO1.

[0055] The source terminal of the seventh transistor TR7 can be connected to the second high drive voltage VDD2, and its drain terminal can be connected to the second inverting node NDOB2. Using this structure, when a low-level input voltage VI is supplied to the gate terminal of the seventh transistor TR7, a high-level inverted output voltage VOB can be generated at the second inverting node NDOB2.

[0056] The gate terminal of the ninth transistor TR9 can be connected to the second output node NDO2. Furthermore, the source terminal of the ninth transistor TR9 can be electrically connected to the second low drive voltage VSS2, and its drain terminal can be connected to the second inverting node NDOB2. As described below, an output voltage VO with the same waveform as the input voltage VI can be generated at the second output node NDO2. The ninth transistor TR9 can be turned on and off using the output voltage VO. With this structure, when a high-level input voltage VI is supplied, a low-level inverted output voltage VOB can be generated at the second inverting node NDOB2.

[0057] The eleventh transistor, TR11, can limit the amount of current flowing to the third-path circuit, PT3.

[0058] The gate terminal of the eleventh transistor TR11 can be supplied with a third bias voltage VBIA3. In addition, the source terminal of the eleventh transistor TR11 can be connected to a second low drive voltage VSS2, and its drain terminal can be connected to the source terminal of the ninth transistor TR9.

[0059] The second high drive voltage VDD2 can be electrically connected to one side of the fourth path circuit PT4, and the second low drive voltage VSS2 can be electrically connected to the other side, and current can flow from the second high drive voltage VDD2 to the second low drive voltage VSS2 via the fourth path circuit PT4.

[0060] The fourth path circuit PT4 may include an eighth transistor TR8, a tenth transistor TR10, and a twelfth transistor TR12. Furthermore, the eighth transistor TR8, the tenth transistor TR10, and the twelfth transistor TR12 may be connected in series with each other.

[0061] Although for ease of explanation, Figure 2 shows the eighth transistor TR8 as a P-type transistor and the tenth transistor TR10 and the twelfth transistor TR12 as N-type transistors, this disclosure is not limited thereto.

[0062] The gate terminal of the eighth transistor TR8 can be connected to the first inverting node NDOB1 of the single-stage circuit 210. Furthermore, the eighth transistor TR8 can be turned on and off according to the voltage level at the first inverting node NDOB1.

[0063] The source terminal of the eighth transistor TR8 can be connected to the second high drive voltage VDD2, and its drain terminal can be connected to the second output node NDO2. Using this structure, when a low-level input voltage VI is supplied to the gate terminal of the eighth transistor TR8, a high-level output voltage VO can be generated at the second output node NDO2.

[0064] The gate terminal of the tenth transistor TR10 can be connected to the second inverting node NDOB2. Furthermore, the source terminal of the tenth transistor TR10 can be electrically connected to the second low drive voltage VSS2, and its drain terminal can be connected to the second output node NDO2.

[0065] As described above, an inverted output voltage VOB with the same waveform as the inverted voltage VIB can be generated at the second inverting node NDOB2. The tenth transistor TR10 can be turned on and off using the inverted output voltage VOB. With this structure, when a high-voltage level inverted voltage VIB is supplied, a low-voltage level inverted output voltage VOB can be generated at the second output node NDO2.

[0066] The twelfth transistor TR12 can limit the amount of current flowing to the fourth path circuit PT4.

[0067] The gate terminal of the twelfth transistor TR12 can be supplied with a third bias voltage VBIA3.

[0068] Furthermore, the source terminal of the twelfth transistor TR12 can be connected to the second low drive voltage VSS2, and its drain terminal can be connected to the source terminal of the tenth transistor TR10.

[0069] Figure 3 is a circuit diagram of a level shifter including a dummy circuit.

[0070] Referring to Figure 3, the level shifter 300 may include a level shifter circuit 310 and a dummy circuit 320.

[0071] The level shifter circuit 310 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 is turned on and off using an input voltage VI to generate a voltage with a waveform opposite to the input voltage VI at the inverting node NDOB. The second transistor TR2 is turned on and off using an inverting voltage VIB with a waveform opposite to the input voltage VI to generate a voltage with the same waveform as the input voltage VI at the output node NDO.

[0072] The level shifter circuit 310 can have the same circuit configuration as the level shifter depicted in FIG1 (see 100 in FIG1).

[0073] Therefore, a detailed description of the level shifter circuit 310 will be omitted.

[0074] The dummy circuit 320 may include a first dummy transistor DTR1 and a second dummy transistor DTR2. The gate and source terminals of the first dummy transistor DTR1 are short-circuited by a first shorting line LN1, and the gate and source terminals of the second dummy transistor DTR2 are short-circuited by a second shorting line LN2. When the first shorting line LN1 and the second shorting line LN2 are removed, the dummy circuit 320 can operate as a two-stage level shifter circuit (the two-stage circuit in FIG2).

[0075] The virtual circuit 320 may include the third path circuit PT3 and the fourth path circuit PT4.

[0076] The third path circuit PT3 may include a first dummy transistor DTR1, a third dummy transistor DTR3, and a fifth dummy transistor DTR5, which are connected in series between the first high drive voltage VDD1 and the first low drive voltage VSS1.

[0077] In addition, the fourth path circuit PT4 may include a second dummy transistor DTR2, a fourth dummy transistor DTR4 and a sixth dummy transistor DTR6 arranged in series between the first high drive voltage VDD1 and the first low drive voltage VSS1.

[0078] The drain terminal of the first dummy transistor DTR1 can be electrically connected to the gate terminal of the fourth dummy transistor DTR4, and the drain terminal of the second dummy transistor DTR2 can be electrically connected to the gate terminal of the third dummy transistor DTR3.

[0079] Furthermore, the fifth dummy transistor DTR5 can be configured to limit the amount of current flowing to the first dummy transistor DTR1 and the third dummy transistor DTR3.

[0080] Furthermore, the sixth dummy transistor DTR6 can be configured to limit the amount of current flowing to the second dummy transistor DTR2 and the fourth dummy transistor DTR4.

[0081] The dummy circuit 320 may include the same transistors as the two-stage circuit depicted in FIG2 (see 220 in FIG2), but there may be wiring differences between the dummy circuit 320 and the two-stage circuit 220.

[0082] In the comparison between Figures 2 and 3, the first dummy transistor DTR1 can correspond to the seventh transistor TR7, the second dummy transistor DTR2 can correspond to the eighth transistor TR8, the third dummy transistor DTR3 can correspond to the ninth transistor TR9, the fourth dummy transistor DTR4 can correspond to the tenth transistor TR10, the fifth dummy transistor DTR5 can correspond to the eleventh transistor TR11, and the sixth dummy transistor DTR6 can correspond to the twelfth transistor TR12.

[0083] When the level shifter 300 operates as a single-stage level shifter, the dummy circuit 320 can be wired to prevent current from flowing into it. For example, the gate and source terminals of the first dummy transistor DTR1 can be short-circuited by the first shorting line LN1. Furthermore, the gate and source terminals of the second dummy transistor DTR2 can be short-circuited by the second shorting line LN2. Additionally, the gate and source terminals of the fifth dummy transistor DTR5 and the sixth dummy transistor DTR6 can be short-circuited by the third shorting line LN3.

[0084] The design of level shifter 300 can be changed to a two-stage level shifter. To change the design of level shifter 300 to a two-stage level shifter, the wiring needs to be changed as shown in Figure 2.

[0085] For example, when the dummy circuit 320 operates as a two-stage level shifter circuit, the output node NDO of the level shifter circuit 310 can be electrically connected to the gate terminal of the first dummy transistor DTR1, and its inverting node NDOB can be electrically connected to the gate terminal of the second dummy transistor DTR2.

[0086] In addition, the first shortest route LN1, the second shortest route LN2, and the third shortest route LN3 can be removed.

[0087] Figure 4 is a flowchart of a method for manufacturing a level shifter including a dummy circuit.

[0088] Referring to Figure 4, a wafer fabrication process (S400) can be performed to provide a substrate to the level shifter.

[0089] Next, a transistor mask can be placed (S402), and the transistor can be formed in accordance with the transistor mask (S404). In this case, the transistor mask may include multiple masks, and some components of the transistor can be formed in accordance with each mask.

[0090] Next, a metal mask can be placed (S406), and a metal layer can be formed consistent with the metal mask (S408).

[0091] The metal layer may include wiring. Manufacturers or designers can form wiring in different ways by changing the metal mask. Furthermore, manufacturers or designers can manufacture single-level or two-level level shifters by using two types of metal masks.

[0092] In manufacturing a single-stage level shifter, in the metal layer formation step S408, wiring can be installed as follows: a first transistor is turned on and off using an input voltage to generate a voltage with a waveform opposite to the input voltage at the inverting node; a second transistor is turned on and off using an inverting voltage with a waveform opposite to the input voltage to generate a voltage with the same waveform as the input voltage at the output node; the gate and source terminals of the first dummy transistor are short-circuited; and the gate and source terminals of the second dummy transistor are short-circuited.

[0093] In addition, wiring can be installed by short-circuiting the gate and source terminals of the fifth dummy transistor and the gate and source terminals of the sixth dummy transistor.

[0094] A passivation layer can be formed on the metal layer to isolate the metal layer (S410). In addition, the output node and the inverting node can be exposed by the passivation layer.

[0095] Figure 5 is a diagram showing the pattern used to form a transistor. Figure 6A is a diagram showing the metal layer pattern used to form a two-stage level shifter. Figure 6B is a diagram showing the metal layer pattern used to form a single-stage level shifter.

[0096] Referring to Figures 5, 6A, and 6B, transistors TR1 to TR6 and DTR1 to DTR6, as shown in Figure 5, can be formed for both single-stage level shifters and two-stage level shifters.

[0097] Subsequently, in the case of forming a two-stage level shifter, the manufacturer can have a metal layer pattern as shown in Figure 6A. The level shifter manufactured in this way can be a two-stage level shifter.

[0098] When a single-stage level shifter is formed after forming transistors TR1 to TR6 and DTR1 to DTR6 as shown in Figure 5, the manufacturer can form the metal layer pattern shown in Figure 6B. The level shifter manufactured in this way can be a single-stage level shifter.

[0099] As described above, according to embodiments of the present disclosure, the design of the level shifter can be changed more easily, and a single-stage shifter or a two-stage level shifter can be selected simply by changing the wiring in the manufacturing process.

[0100] Cross-reference of related applications

[0101] This application claims priority to Korean Patent Application No. 10-2020-0178855, filed on December 18, 2020, which is incorporated herein by reference for all purposes as fully set forth herein.

[0102] 100: Level shifter 200: Level shifter 210: Single-stage circuit 220: Two-stage circuit 300: Level Shifter 310: Level shifter circuit 320: Dummy Circuit DTR1: First Dummy Transistor DTR2: Second Dummy Transistor DTR3: Third Dummy Transistor DTR4: Fourth Dummy Transistor DTR5: Fifth Dummy Transistor DTR6: Sixth Dummy Transistor LN1: First Shortest Route LN2: Second Shortest Route LN3: Third Shortest Route NDO: Output Node NDO1: First output node NDO2: Second Output Node NDOB: Inverse Node NDOB1: First inverted node NDOB2: Second Inverted Node PT1: First Path Circuit PT2: Second Path Circuit PT3: Third Path Circuit PT4: Fourth Path Circuit S400: Steps S402: Steps S404: Steps S406: Steps S408: Steps S410: Steps TR1: First transistor TR2: Second transistor TR3: Third transistor TR4: Fourth Transistor TR5: Fifth Transistor TR6: Sixth Transistor TR7: Seventh Transistor TR8: Eighth Transistor TR9: Ninth Transistor TR10: Tenth Transistor TR11: Eleventh Transistor TR12: Twelfth Transistor VBIA1: First bias voltage VBIA2: Second bias voltage VBIA3: Third bias voltage VDD1: First high drive voltage VDD2: Second highest drive voltage VI: Input Voltage VIB: Reverse voltage VO: Output voltage VOB: Inverting output voltage VSS1: First low drive voltage VSS2: Second Low Drive Voltage

Claims

1. A level shifter, comprising: A first path circuit, wherein a first transistor and a third transistor are connected in series between a high driving voltage and a low driving voltage. The second path circuit, in which a second transistor and a fourth transistor are connected in series between the high driving voltage and the low driving voltage; the third path circuit, in which a first dummy transistor and a third dummy transistor are connected in series between the high driving voltage and the low driving voltage. And a fourth path circuit, in which a second dummy transistor and a fourth dummy transistor are arranged in series between the high drive voltage and the low drive voltage, wherein an input voltage is supplied to the gate terminal of the first transistor, and an inverted voltage having a waveform opposite to the input voltage is supplied to the gate terminal of the second transistor, the drain terminal of the first transistor is electrically connected to an inverting node, the drain terminal of the second transistor is electrically connected to an output node, the output node is electrically connected to the gate terminal of the third transistor, and the inverting node is electrically connected to the gate terminal of the fourth transistor, and wherein the gate terminal and the source terminal of the first dummy transistor are short-circuited by a first short circuit, and the gate terminal and the source terminal of the second dummy transistor are short-circuited by a second short circuit.

2. The level shifter according to claim 1, wherein, The first path circuit further includes a fifth transistor for limiting the amount of current flowing to the first transistor and the third transistor, and the second path circuit further includes a sixth transistor for limiting the amount of current flowing to the second transistor and the fourth transistor.

3. The level shifter according to claim 1, wherein, The drain terminal of the first dummy transistor is electrically connected to the gate terminal of the fourth dummy transistor, and the drain terminal of the second dummy transistor is electrically connected to the gate terminal of the third dummy transistor.

4. The level shifter according to claim 3, wherein, The third path circuit further includes a fifth dummy transistor for limiting the amount of current flowing to the first dummy transistor and the third dummy transistor, and the fourth path circuit further includes a sixth dummy transistor for limiting the amount of current flowing to the second dummy transistor and the fourth dummy transistor.

5. The level shifter according to claim 4, wherein, The gate and source terminals of the fifth and sixth dummy transistors are short-circuited.

6. A method for manufacturing a level shifter, the method comprising: Place a transistor shield; A first transistor, a second transistor, a first dummy transistor, and a second dummy transistor are formed in accordance with the transistor shield; A metal shield is placed; and the wiring is installed using the metal shield in the following manner: a first transistor is turned on and off according to an input voltage to generate a voltage at an inverting node having a waveform opposite to the waveform of the input voltage; a second transistor is turned on and off according to an inverting voltage having a waveform opposite to the waveform of the input voltage to generate a voltage at an output node having a waveform identical to the waveform of the input voltage; the gate and source terminals of the first dummy transistor are short-circuited; And the gate and source terminals of the second dummy transistor are short-circuited.

7. The method according to claim 6 further includes: After the wiring is installed, a passivation layer is formed, and the output node and the inverting node are exposed through the passivation layer.

8. The method according to claim 6, wherein, The first dummy transistor and the second dummy transistor form a two-stage level shifter circuit by changing the metal shield.

9. The method according to claim 6, wherein, When forming the transistor, a first dummy limiting transistor for limiting the amount of current flowing to the first dummy transistor and a second dummy limiting transistor for limiting the amount of current flowing to the second dummy transistor are also formed. During wiring installation, the wiring is installed in such a way that the gate and source terminals of the first dummy limiting transistor and the gate and source terminals of the second dummy limiting transistor are short-circuited.

10. A level shifter, comprising: A level shifter circuit includes a first transistor and a second transistor, the first transistor being turned on and off according to an input voltage to generate a voltage at an inverting node having a waveform opposite to the waveform of the input voltage, and the second transistor being turned on and off according to an inverting voltage having a waveform opposite to the waveform of the input voltage to generate a voltage at an output node having a waveform identical to the waveform of the input voltage. And a dummy circuit comprising a transistor arranged in the form of a two-stage level shifter circuit, wherein the gate and source terminals of the first and second dummy transistors are short-circuited.

11. The level shifter according to claim 10, wherein, When the dummy circuit operates as the two-stage level shifter circuit, the output node is electrically connected to the gate terminal of the first dummy transistor, and the inverting node is electrically connected to the gate terminal of the second dummy transistor.

12. The level shifter according to claim 11, wherein, When the dummy circuit operates as the two-stage level shifter circuit, the output voltage is determined based on the voltage at the drain terminal of the second dummy transistor, and the inverted output voltage is determined based on the voltage at the drain terminal of the first dummy transistor.

13. The level shifter according to claim 10, wherein, The dummy circuit further includes a first dummy limiting transistor for limiting the current flowing to the first dummy transistor and a second dummy limiting transistor for limiting the current flowing to the second dummy transistor.

14. The level shifter according to claim 13, wherein, The gate and source terminals of the first dummy limiting transistor and the gate and source terminals of the second dummy limiting transistor are short-circuited by a third short circuit.

15. The level shifter according to claim 10, wherein, The first transistor and the first dummy transistor are different types of transistors, and the second transistor and the second dummy transistor are different types of transistors.

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