Display device

Abstract

A display device includes: a substrate including a plurality of pixels; a first embankment defining an emitting region for the plurality of pixels; a first electrode and a second electrode spaced apart from each other in the emitting regions; a first insulating layer disposed on the first electrode and the second electrode; a plurality of light-emitting elements disposed on the first insulating layer between the first electrode and the second electrode; a second insulating layer disposed on the first embankment; a first opening penetrating through the first insulating layer; and a second opening penetrating through the second insulating layer. The first opening and the second opening may overlap with the first embankment.

Description

Technical Field

[0001] Cross-referencing of related applications

[0002] This case asserts priority to Korean Patent Application No. 10-2020-0182613, filed with the Korean Intellectual Property Office (KIPO) on December 23, 2020, the entire contents of which are incorporated herein by reference.

[0003] The various embodiments disclosed herein relate to a display device. Prior Technology

[0004] In recent years, with the increasing interest in information display, research and development of display devices have been ongoing. Summary of the Invention

[0005] The various embodiments disclosed herein are directed to a display device capable of reducing or minimizing defects attributable to outgassing.

[0006] The purpose of this disclosure is not limited to the above-mentioned purposes, and those skilled in the art will clearly understand other unmentioned purposes from the appended claims.

[0007] One embodiment of this disclosure provides a display device comprising: a substrate including a plurality of pixels; a first embankment defining an emitting region for the plurality of pixels; a first electrode and a second electrode separated from each other in the emitting region; a first insulating layer disposed on the first electrode and the second electrode; a plurality of light-emitting elements disposed on the first insulating layer between the first electrode and the second electrode; a second insulating layer disposed on the first embankment; a first opening penetrating the first insulating layer; and a second opening penetrating the second insulating layer. The first opening and the second opening may overlap with the first embankment.

[0008] In one embodiment, the second opening may expose the first embankment.

[0009] In one embodiment, the first opening may overlap with the second opening.

[0010] In one embodiment, the surface area of ​​the first opening may be greater than the surface area of ​​the second opening.

[0011] In one embodiment, the surface area of ​​the first opening may be smaller than the surface area of ​​the second opening.

[0012] In one embodiment, the first opening and the second opening may extend in a first direction.

[0013] In one embodiment, the first dam wall may be disposed between the first insulating layer and the second insulating layer.

[0014] In one embodiment, the display device may further include a second dam wall disposed between the substrate and the first dam wall.

[0015] In one embodiment, the first opening may expose the second embankment.

[0016] In one embodiment, the first embankment wall can contact the second embankment wall through a first opening.

[0017] In one embodiment, the display device may further include: a third insulating layer disposed on the second insulating layer; and a third opening penetrating through the second and third insulating layers.

[0018] In one embodiment, the third insulating layer may overlap with the first embankment.

[0019] In one embodiment, the third opening can expose the first embankment.

[0020] In one embodiment, the third insulating layer can contact the first embankment through the second opening.

[0021] In one embodiment, the second opening and the third opening may be alternately arranged in the first direction.

[0022] In one embodiment, the second opening and the third opening may extend in the first direction.

[0023] In one embodiment, the second opening and the third opening may be separated from each other in a second direction intersecting the first direction.

[0024] In one embodiment, the display device may further include: a first connecting electrode disposed on a third insulating layer; and a second connecting electrode disposed between the second insulating layer and the third insulating layer.

[0025] In one embodiment, a first connecting electrode may electrically contact one end of each of a plurality of light-emitting elements, and a second connecting electrode may electrically contact the other end of each of a plurality of light-emitting elements.

[0026] In one embodiment, at least one of the first insulating layer, the second insulating layer, and the third insulating layer may contain an inorganic material.

[0027] Details of the various embodiments are included in the detailed description and drawings. Simple Explanation of the Diagram

[0028] Figures 1 and 2 illustrate, illustratively, a perspective view and a cross-sectional view of a light-emitting element according to an embodiment of the present disclosure. Figure 3 illustrates a plan view of a display device according to an embodiment of the present disclosure. Figure 4 illustrates a circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 5 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 6 is a schematic cross-sectional view taken along line A-A' in Figure 5. Figure 7 is a schematic cross-sectional view taken along line B-B' in Figure 5. Figure 8 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 9 is a schematic cross-sectional view taken along line C-C' in Figure 8. Figure 10 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 11 is a schematic cross-sectional view taken along line D-D' in Figure 10. Figure 12 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 13 is a schematic cross-sectional view taken along line E-E' in Figure 12. Figure 14 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 15 is a schematic cross-sectional view taken along line F-F' in Figure 14. Figure 16 illustrates a plan view of pixels according to an embodiment of the present disclosure. Figure 17 is a schematic cross-sectional view taken along line G-G' in Figure 16. Implementation

[0029] The advantages, features, and implementation methods of this disclosure will be described in detail with reference to the accompanying drawings and embodiments. This disclosure is not limited to the following embodiments and can have various modifications. These embodiments are provided to make this disclosure more thorough and complete, and to fully convey the disclosed concepts to those skilled in the art.

[0030] The terminology used herein is for illustrative purposes only and is not intended to limit the embodiments. In this specification, singular terms may include plural forms unless specifically stated otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, and / or components.

[0031] Furthermore, the terms "coupling" or "connection" can refer to physical and / or electrical coupling or connection in general. Additionally, the terms "coupling" or "connection" can refer to direct or indirect coupling or connection, as well as integral or non-integral coupling or connection.

[0032] It is understood that when a component or layer is referred to as being "on" another component or layer, it may be directly on the other component or layer, directly connected to or coupled to the other component or layer, or one or more intermediate components may be present. Throughout the specification, the same component symbol denotes the same component.

[0033] It is understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0034] For the purposes of its meaning and interpretation, the term "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood as meaning "A, B or A and B".

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as understood by one of ordinary skill in the field to which this disclosure pertains. It will be further understood that, unless explicitly defined otherwise, terms, such as those defined in a common dictionary, shall be interpreted as having a meaning consistent with their meaning in their relevant field and in the context of this disclosure, and shall not be idealized or overly formalized unless explicitly defined herein.

[0036] The embodiments disclosed herein will be described in detail below with reference to the accompanying drawings.

[0037] Figures 1 and 2 are schematic perspective views and schematic cross-sectional views illustrating a light-emitting element according to an embodiment of the present disclosure. Although Figures 1 and 2 illustrate a columnar (or columnar) light-emitting element LD, the type and / or shape of the light-emitting element LD are not limited thereto.

[0038] Referring to Figures 1 and 2, the light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, if the direction in which the light-emitting element (LD) extends is along a reference longitudinal axis (L), the light-emitting element (LD) may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 stacked sequentially or successively along the longitudinal axis (L).

[0039] The light-emitting element (LD) can be configured as a pillar extending in one direction. The LD may include a first end EP1 and a second end EP2. A first semiconductor layer 11 may be disposed on the first end EP1 of the LD, and a second semiconductor layer 13 may be disposed on the second end EP2 of the LD, but this disclosure is not limited thereto.

[0040] In one embodiment, the light-emitting element (LD) can be a columnar light-emitting element manufactured by etching or similar methods. In this specification, the terms "column-type" or "columnar shape" can refer to rod-like shapes and bar-like shapes, such as cylindrical and prismatic shapes extending along the longitudinal axis (i.e., having an aspect ratio greater than 1), and the shape of its cross-section is not limited to a specific shape. For example, the length L of the light-emitting element LD can be greater than its diameter D (or the width of its cross-section).

[0041] Light-emitting elements (LDs) can have small dimensions corresponding to the nanometer to micrometer scale. For example, each LD can have a diameter D (or width) and / or length L ranging from the nanometer to the micrometer scale. However, the size of the LD is not limited thereto, and can be varied in various ways depending on the design conditions of various devices that use a light-emitting device with LDs as a light source, such as display devices.

[0042] The first semiconductor layer 11 may be a first conductive semiconductor layer. For example, the first semiconductor layer 11 may include a p-type semiconductor layer. For example, the first semiconductor layer 11 may include a p-type semiconductor layer comprising semiconductor materials such as indium gallium aluminum nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is doped with a first conductive dopant such as magnesium (Mg). However, the materials used to form the first semiconductor layer 11 are not limited thereto, and the first semiconductor layer 11 may be formed from various other materials.

[0043] The active layer 12 may be disposed below the first semiconductor layer 11 and may have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be varied in various ways depending on the type of light-emitting element (LD). A cladding layer (not shown) doped with conductive dopant may be selectively formed above and / or below the active layer 12. For example, the cladding layer may be formed of aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (InAlGaN). In one embodiment, materials such as aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (InAlGaN) may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0044] The second semiconductor layer 13 may be disposed below the active layer 12 and may include a semiconductor layer having a different type of semiconductor layer than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include an n-type semiconductor layer. The n-type semiconductor layer may include semiconductor materials such as indium gallium aluminum nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and is doped with a second conductive dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the materials used to form the second semiconductor layer 13 are not limited thereto, and the second semiconductor layer 13 may be formed from various other materials.

[0045] If a voltage equal to or greater than the threshold voltage is applied to each of the opposite terminals of the light-emitting element (LD), the LD can emit light through the coupling of electron-hole pairs in the active layer 12. Since the light emission of the LD is controlled based on the aforementioned principle, the LD can be used as a light source for various light-emitting devices and as a pixel for display devices.

[0046] The light-emitting element (LD) may further include an insulating film INF disposed on the surface of the light-emitting element (LD). The insulating film INF may be formed on the surface of the light-emitting element (LD) to at least surround the active layer 12, and may further surround the region of each of the first semiconductor layer 11 and the second semiconductor layer 13.

[0047] The insulating film INF can expose the opposite ends of light-emitting elements (LDs) with different polarities to the outside. For example, the insulating film INF can expose the ends of each of the first semiconductor layer 11 and the second semiconductor layer 13 respectively disposed on the first end EP1 and the second end EP2 of the light-emitting element LD. In one embodiment, the insulating film INF can expose the sides of each of the first semiconductor layer 11 and the second semiconductor layer 13 respectively adjacent to the first end EP1 and the second end EP2 of the light-emitting element LD with different polarities.

[0048] The insulating film INF can have a single-layer structure or a multi-layer structure (e.g., a bilayer structure formed of aluminum oxide (AlOx) and silicon oxide (SiOx)), comprising at least one insulating material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and titanium oxide (TiOx). However, this disclosure is not limited thereto. In one embodiment, the insulating film INF may be omitted.

[0049] If the insulating film INF covers the surface of the light-emitting element LD, especially the outer peripheral surface of the active layer 12, undesirable short circuits can be prevented even when the light-emitting elements LD are arranged adjacent to each other. Furthermore, surface defects of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD.

[0050] In one embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF surrounding the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include additional components. For example, the light-emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed on one end (or the first end) of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. For example, the electrode layer may be disposed on each of the first end EP1 and the second end EP2 of the light-emitting element LD.

[0051] Although Figures 1 and 2 depict columnar light-emitting elements (LDs), the type, structure, and / or shape of LDs can be varied in various ways. For example, an LD can be formed as a core-shell structure with a multi-conical shape.

[0052] The light-emitting device including the aforementioned light-emitting element (LD) can be used not only in display devices but also in various devices that require a light source. For example, the light-emitting element (LD) can be disposed in each pixel of a display panel, so that the light-emitting element (LD) can serve as a light source for the pixel. However, the application scope of the light-emitting element (LD) is not limited to the above examples. For example, the light-emitting element (LD) can also be used in other types of devices that require a light source, such as light-emitting devices.

[0053] Figure 3 is a schematic plan view illustrating a display device according to one embodiment.

[0054] Figure 3 illustrates a display device, specifically a display panel PNL disposed in the display device, which serves as an example of an electronic device that can use the light-emitting element LD described in Figures 1 and 2 as a light source.

[0055] Each pixel unit PXU of the display panel PNL and each pixel used to form the pixel unit PXU may include at least one light-emitting element LD. For ease of illustration, Figure 3 simply illustrates the structure of the display panel PNL according to one embodiment, which is focused on the display area DA. In some embodiments, although not shown, at least one of the following may be further disposed on the display panel PNL: driving circuitry (e.g., at least one of a scan driver and a data driver), wires, and / or pads.

[0056] Referring to Figure 3, the display panel PNL may include a substrate SUB and pixel units PXU disposed on the substrate SUB. Pixel unit PXU may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. In the following embodiments, the term "pixel PXL" or "pixels PXL" will be used to arbitrarily specify at least one pixel among the first pixel PXL1, the second pixel PXL2, and / or the third pixel PXL3, or to jointly specify two or more of these pixels.

[0057] The substrate SUB can be formed as the base of the display panel PNL and can be a rigid or flexible substrate or film. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate (or film) made of plastic or metal, and there are no particular limitations on the material and / or properties of the substrate SUB.

[0058] The display panel PNL and the substrate SUB used to form the display panel PNL may include a display area DA for displaying images and a non-display area NDA formed in a predetermined area outside the display area DA. Pixels PXL are disposed in the display area DA. Various wires and / or pads electrically connected to the pixels PXL may be disposed in the non-display area NDA. Pixels PXL may be regularly arranged according to a stripe arrangement structure or a PenTile® arrangement structure. The arrangement structure of the pixels PXL is not limited to this, and various structures and / or methods may be used to arrange the pixels PXL in the display area DA.

[0059] In one embodiment, two or more pixels PXL emitting different colors of light can be arranged in the display area DA. For example, a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color, and a third pixel PXL3 configured to emit light of a third color can be arranged in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 arranged adjacent to each other can form a pixel unit PXU, which can emit light of different colors. For example, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be a sub-pixel configured to emit light of a predetermined color. In one embodiment, the first pixel PXL1 can be a red pixel emitting red light, the second pixel PXL2 can be a green pixel emitting green light, and the third pixel PXL3 can be a blue pixel emitting blue light. However, this disclosure is not limited thereto.

[0060] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements of a first color, a second color, and a third color, respectively, serving as a light source, such that the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may each include a light-emitting element configured to emit light of the same color and a color filter, and color conversion layers of different colors may be disposed on each of the respective light-emitting elements, such that the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can emit light of the first color, the second color, and the third color, respectively. However, there are no particular limitations on the color, type, and / or number of pixels PXL forming each pixel unit PXU. In other words, the color of the light emitted from each pixel PXL can be changed in various ways.

[0061] The pixel PXL may include at least one light source driven by a control signal (e.g., a scan signal and a data signal) or a power source (e.g., a first power source and a second power source). In one embodiment, the light source may include at least one light-emitting element (LD) according to one embodiment of Figures 1 and 2, such as an ultra-miniature cylindrical light-emitting element (LD) having a small size corresponding to the nanometer to micrometer scale. However, this disclosure is not limited thereto, and different types of light-emitting elements (LDs) may be used as the light source for the pixel PXL.

[0062] Figure 4 is a schematic equivalent circuit diagram illustrating a pixel according to one embodiment.

[0063] In one embodiment, the pixel PXL shown in Figure 4 can be one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 disposed on the display panel PNL in Figure 3. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can have substantially the same or similar structures.

[0064] Referring to Figure 4, a pixel PXL may include an emitting circuit LSU for generating light with a brightness corresponding to the data signal, and a pixel circuit PXC for driving the emitting circuit LSU.

[0065] The emitting circuit LSU may include at least one light-emitting element LD electrically connected between a first power supply VDD and a second power supply VSS. For example, the emitting circuit LSU may include a first electrode ELT1 (also referred to as a "first pixel electrode" or "first alignment electrode") electrically connected to the first power supply VDD through a pixel circuit PXC and a first power line PL1, a second electrode ELT2 (also referred to as a "second pixel electrode" or "second alignment electrode") electrically connected to the second power supply VSS through a second power line PL2, and a light-emitting element LD electrically connected between the first electrode ELT1 and the second electrode ELT2. In one embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0066] Each light-emitting element (LD) may include a first terminal electrically connected to a first power supply VDD via a first electrode ELT1 and / or pixel circuit PXC, and a second terminal electrically connected to a second power supply VSS via a second electrode ELT2. In other words, the light-emitting elements (LDs) may be electrically connected in the forward direction between the first electrode ELT1 and the second electrode ELT2. Each light-emitting element (LD) electrically connected in the forward direction between the first power supply VDD and the second power supply VSS can form an effective light source. The effective light source can form the emission circuit LSU of the pixel PXL.

[0067] The first power supply VDD and the second power supply VSS can have different potentials to make the light-emitting element LD emit light. For example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. Here, at least during the emission cycle of pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS can be set to the threshold voltage of the light-emitting element LD or higher.

[0068] The first terminal of the light-emitting element LD forming each emission circuit LSU can be electrically connected to the pixel circuit PXC through the electrodes of the emission circuit LSU (e.g., the first electrode ELT1 of each pixel PXL), and electrically connected to the first power supply VDD through the pixel circuit PXC and the first power supply line PL1. The second terminal of the light-emitting element LD can be electrically connected to the second power supply VSS through the other electrode of the emission circuit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power supply line PL2.

[0069] The light-emitting element (LD) can emit light with a driving current corresponding to that provided to it through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can provide a driving current to the emitting circuit (LSU) corresponding to the grayscale value to be represented in the corresponding frame. The driving current provided to the emitting circuit (LSU) can be distributed to the light-emitting elements (LDs) electrically connected in the conduction direction. Therefore, each light-emitting element (LD) can emit light with a brightness corresponding to the current applied to it, such that the emitting circuit (LSU) can emit light with a brightness corresponding to the driving current.

[0070] The pixel circuit PXC can be electrically connected between the first power supply VDD and the first electrode ELT1. The pixel circuit PXC can also be electrically connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, if pixel PXL is located in the i-th horizontal line (row) (where i is a natural number) and the j-th vertical line (column) (where j is a natural number) of display area DA, the pixel circuit PXC can be electrically connected to the i-th scan line Si and the j-th data line Dj of display area DA.

[0071] In one embodiment, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and at least one storage capacitor Cst.

[0072] The first transistor T1 can be electrically connected between the first power supply VDD and the transmitting circuit LSU. For example, the first electrode (e.g., the source electrode) of the first transistor T1 can be electrically connected to the first power supply VDD, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be electrically connected to the first electrode ELT1. The gate electrode of the first transistor T1 can be electrically connected to the first node N1. The first transistor T1 can respond to the voltage of the first node N1 to control the drive current supplied to the transmitting circuit LSU. In other words, the first transistor T1 can be a driving transistor that controls the drive current of the pixel PXL.

[0073] The second transistor T2 can be electrically connected between the data line Dj and the first node N1. For example, the first electrode (e.g., the source electrode) of the second transistor T2 can be electrically connected to the data line Dj, and the second electrode (e.g., the drain electrode) of the second transistor T2 can be electrically connected to the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the scan line Si. When a scan signal with a gate turn-on voltage (e.g., a low-level voltage) is provided from the scan line Si to the second transistor T2, the second transistor T2 can be turned on to electrically connect the first node N1 to the data line Dj.

[0074] During each frame period, the data signal DSj corresponding to the frame is provided to the data line Dj, and the data signal DSj is transmitted to the first node N1 through the second transistor T2. The second transistor T2 is turned on during the period when the scan signal SSi with gate turn-on voltage is provided to it. That is, the second transistor T2 can be configured to transmit each data signal DSj to the switching transistor inside the pixel PXL.

[0075] The third transistor T3 can be electrically connected between the first transistor T1 and the sensing line SLj. For example, the first electrode of the third transistor T3 can be electrically connected to an electrode (e.g., the source electrode) of the first transistor T1, which is electrically connected to the first electrode ELT1, and the second electrode of the third transistor T3 can be electrically connected to the sensing line SLj. If the sensing line SLj is omitted, the second electrode of the third transistor T3 can be electrically connected to the data line Dj.

[0076] The gate electrode of the third transistor T3 can be electrically connected to the sensing control line SCLi. If the sensing control line SCLi is omitted, the gate electrode of the third transistor T3 can be electrically connected to the scan line Si. The third transistor T3 can be turned on by providing a sensing control signal SCSi with a gate on-state voltage (e.g., a high-level voltage) to the sensing control line SCLi during the sensing cycle, thereby electrically connecting the sensing line SLj to the first transistor T1.

[0077] In one embodiment, the sensing period can be a time period for extracting the characteristics (e.g., the threshold voltage of the first transistor T1) of each pixel PXL disposed in the display area DA. During the sensing period, the first transistor T1 can be turned on by providing a predetermined reference voltage to the first node N1 using data line Dj and the second transistor T2, or each pixel PXL can be electrically connected to a current source or the like. Further, the third transistor T3 can be turned on by providing a sensing control signal SCSi with a gate turn-on voltage to the third transistor T3, so that the first transistor T1 can be coupled to the sensing line SLj. Thereafter, a sensing signal SENj can be obtained through the sensing line SLj, and the sensing signal SENj can be used to detect the characteristics of each pixel PXL including the threshold voltage of the first transistor T1 or the like. Information about the characteristics of each pixel PXL can be used to convert image data, thereby compensating for characteristic deviations between pixels PXL disposed in the display area DA.

[0078] The first electrode of the storage capacitor Cst can be electrically connected to the first power supply VDD, and its second electrode can be electrically connected to the first node N1. The storage capacitor Cst can be charged by a voltage corresponding to the data signal DSj that will be provided to the first node N1 in each frame cycle.

[0079] Although Figure 4 illustrates an embodiment where the first transistor T1, the second transistor T2, and the third transistor T3 are all n-type transistors, this disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a p-type transistor.

[0080] Furthermore, although Figure 4 illustrates an embodiment in which all effective light sources, such as light-emitting elements (LDs), used to form each emission circuit LSU are electrically connected in parallel with each other, this disclosure is not limited thereto. For example, the emission circuit LSU of each pixel PXL may comprise at least two series-connected structures. The light-emitting elements forming each series stage may be electrically connected in series with each other through at least one intermediate electrode.

[0081] Assuming that light-emitting elements (LDs) with identical characteristics (e.g., identical size and / or quantity) are used as effective light sources to configure or form an emission circuit LSU, power efficiency can be improved if the LDs are electrically connected to each other in series or in a series / parallel combination. For example, in an emission circuit LSU where LDs are coupled in series or in a series / parallel combination, the brightness exhibited (or displayed) based on the same current can be higher than the brightness of LDs electrically connected only to each other. Furthermore, in a pixel PXL where LDs are electrically connected in series or in a series / parallel combination, even if short-circuit defects or similar conditions occur in some series stages, the brightness can still be represented by the LDs in other series stages, thereby reducing the probability of black spot defects in the pixel PXL.

[0082] Figure 5 is a schematic plan view illustrating pixels according to one embodiment. Figure 6 is a schematic cross-sectional view taken along line A-A' of Figure 5. Figure 7 is a schematic cross-sectional view taken along line B-B' of Figure 5.

[0083] For example, the pixel PXL in Figure 5 can be one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 that form the pixel unit PXU in Figure 3, and the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can have substantially the same or similar structures.

[0084] Referring to Figure 5, pixel PXL can contain a first dam wall BNK1, which defines each emission region EMA. In other words, the first dam wall BNK1 can surround the emission region EMA.

[0085] Pixel PXL may include a first opening OP1, a second opening OP2, and a third opening OP3 disposed around the emission region EMA. Each of the first opening OP1, the second opening OP2, and the third opening OP3 may overlap with the first embankment BNK1.

[0086] The first openings OP1 can be separated from each other. For example, as shown in Figure 5, the first openings OP1 can be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the first openings OP1 can be changed in various ways as long as the first openings OP1 overlap with the first embankment BNK1. For example, the first openings OP1 can be separated from each other not only in the first direction DR1, but also in various directions.

[0087] The second openings OP2 can be separated from each other. For example, as shown in Figure 5, the second openings OP2 can be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the second openings OP2 can be changed in various ways as long as the second openings OP2 overlap with the first embankment BNK1. For example, the second openings OP2 can be separated from each other not only in the first direction DR1, but also in various directions.

[0088] The second opening OP2 may overlap with the first opening OP1. Although Figure 5 illustrates the case where each second opening OP2 completely overlaps with its corresponding first opening OP1, this disclosure is not limited thereto. In other words, each second opening OP2 may partially overlap with its corresponding first opening OP1, or may not overlap with it at all. The surface area of ​​the second opening OP2 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the second opening OP2 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0089] The third opening OP3 can be separated from each other. For example, as shown in Figure 5, the third opening OP3 can be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the third opening OP3 can be changed in various ways as long as the third opening OP3 overlaps with the first embankment BNK1. For example, the third opening OP3 can be separated from each other not only in the first direction DR1, but also in various directions.

[0090] The third opening OP3 may overlap with the first opening OP1. Although Figure 5 illustrates the case where each third opening OP3 overlaps entirely with its corresponding first opening OP1, this disclosure is not limited thereto. In other words, each third opening OP3 may partially overlap with its corresponding first opening OP1, or may not overlap with its first opening OP1. The surface area of ​​the third opening OP3 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the third opening OP3 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto. Furthermore, the surface areas of the third opening OP3 and the second opening OP2 may be substantially the same as the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0091] The second opening OP2 and the third opening OP3 can be arranged alternately. In other words, each second opening OP2 can be arranged between adjacent third openings OP3, and each third opening OP3 can be arranged between adjacent second openings OP2. For example, as illustrated in Figure 5, the second openings OP2 and the third openings OP3 can be arranged alternately in the first direction DR1. However, this disclosure is not limited to this, and the arrangement of the second openings OP2 and the third openings OP3 can be varied in various ways. For example, the second openings OP2 and the third openings OP3 can be arranged alternately not only in the first direction DR1, but also in various directions. As another example, the second openings OP2 can be arranged successively, and the third openings OP3 can be arranged successively.

[0092] As described above, when the first opening OP1, the second opening OP2, and the third opening OP3 are formed around the emission region EMA of each pixel PXL, the outgas generated during the manufacturing process of the display device can be discharged outward through the first opening OP1, the second opening OP2, and the third opening OP3, thereby preventing defects attributable to the outgas. This will be explained in detail with reference to Figure 7.

[0093] The first electrode ELT1, the second electrode ELT2, the third electrode ELT3, the first light-emitting element LD1, the second light-emitting element LD2, the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be disposed in the emission area EMA of the pixel PXL.

[0094] Each of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2. The first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may be arranged consecutively in the second direction DR2. However, this disclosure is not limited thereto, and the shape and / or relative positional relationship of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may be changed in various ways.

[0095] In the alignment step of the light-emitting element (LD), alignment signals (or alignment voltages) can be provided to the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3. Therefore, an electric field can be formed between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3, allowing the LD supplied to the emitting region EMA to be aligned between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3. After the alignment of the LD is completed, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 are electrically disconnected from each other at the boundaries between pixels PXL, thereby allowing pixels PXL to be driven independently.

[0096] The first electrode ELT1 may be electrically connected to the first transistor T1 or its similar as illustrated in Figure 4. The second electrode ELT2 may be electrically connected to the second power supply VSS (or the second power line PL2) or its similar as illustrated in Figure 4. The first electrode ELT1, the second electrode ELT2, and / or the third electrode ELT3 may partially overlap with the first embankment BNK1. In one embodiment, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may partially extend to the periphery of the emission region EMA. In other words, before the light-emitting element LD is provided to the emission region EMA, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may extend to the adjacent pixel PXL. After the light-emitting element LD is provided to the emission region EMA and aligned in the emission region EMA, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may be cut off (or partially removed) around the first embankment BNK1.

[0097] A light-emitting element (LD) can be disposed between a first electrode ELT1, a second electrode ELT2, and a third electrode ELT3. A first light-emitting element LD1 can be disposed between the first electrode ELT1 and the second electrode ELT2. A second light-emitting element LD2 can be disposed between the second electrode ELT2 and the third electrode ELT3. The light-emitting elements LD can be aligned between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 to have directionality. For example, each first end EP1 of the first light-emitting element LD1 can face the first electrode ELT1. Each second end EP2 of the first light-emitting element LD1 can face the second electrode ELT2. Further, each first end EP1 of the second light-emitting element LD2 can face the second electrode ELT2. Each second end EP2 of the second light-emitting element LD2 can face the third electrode ELT3.

[0098] In one embodiment, the light-emitting element (LD) can be prepared by diffusion in a predetermined solution and provided to the emitting region EMA via inkjet printing, slot coating, or similar methods. For example, the LD can be mixed with a volatile solvent and provided to the emitting region EMA. Here, if a predetermined voltage is applied between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3, an electric field can be formed between them, allowing the LD to be aligned. After the LD is aligned, the solvent can be removed by evaporation or other methods. This allows the LD to be reliably disposed between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3.

[0099] The light-emitting element (LD) can be electrically connected to the first electrode ELT1 and the second electrode ELT2 through the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3. The first connecting electrode CNE1 can be disposed on each of the first terminals EP1 of the first electrode ELT1 and the first light-emitting element LD1. The first connecting electrode CNE1 can electrically contact the first electrode ELT1 and each of the first terminals EP1 of the first light-emitting element LD1. In other words, the first connecting electrode CNE1 can electrically contact the first electrode ELT1 and the first light-emitting element LD1. The first connecting electrode CNE1 can extend to the periphery of the first embankment BNK1 and be electrically connected to the first electrode ELT1. For example, the first connecting electrode CNE1 can extend to the periphery of the first embankment BNK1 and electrically contact the first electrode ELT1 through the first contact hole CH1. In one embodiment, the first connecting electrode CNE1 can extend in the first direction DR1. The shape and / or arrangement of the first connecting electrode CNE1 can be varied in various ways.

[0100] The second connecting electrode CNE2 can be disposed on the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. The second connecting electrode CNE2 can electrically contact the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. The second connecting electrode CNE2 can electrically connect the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. In one embodiment, the second connecting electrode CNE2 can overlap with the second electrode ELT2 and / or the third electrode ELT3, but this disclosure is not limited thereto. In one embodiment, the second connecting electrode CNE2 can be separated from the first connecting electrode CNE1 and the third connecting electrode CNE3. For example, the second connecting electrode CNE2 can extend from the second end EP2 of the first light-emitting element LD1, bypass the third connecting electrode CNE3, and extend to the first end EP1 of the second light-emitting element LD2. In other words, the second connecting electrode CNE2 can have a shape that partially surrounds the third connecting electrode CNE3. The second connecting electrode CNE2 can have an overall closed-loop shape and a shape in which a portion is cut off or opened. Here, the shape and / or arrangement of the second connecting electrode CNE2 can be changed in various ways.

[0101] The third connecting electrode CNE3 can be disposed on the second end EP2 of the second light-emitting element LD2 and the second electrode ELT2. The third connecting electrode CNE3 can electrically contact the second end EP2 of the second light-emitting element LD2 and the second electrode ELT2. The third connecting electrode CNE3 can electrically connect the second end EP2 of the second light-emitting element LD2 and the second electrode ELT2. The third connecting electrode CNE3 can extend around the first embankment BNK1 and be electrically connected to the second electrode ELT2. For example, the third connecting electrode CNE3 can extend around the first embankment BNK1 and electrically contact the second electrode ELT2 through the second contact hole CH2. In one embodiment, the third connecting electrode CNE3 can extend in the first direction DR1. Here, the shape and / or arrangement of the third connecting electrode CNE3 can be varied in various ways.

[0102] Therefore, the first light-emitting element LD1 and the second light-emitting element LD2 can be electrically connected in series between the first electrode ELT1 and the second electrode ELT2 via the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3. However, this disclosure is not limited to this. The light-emitting element LD can be directly electrically connected to the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3, thereby eliminating the need for additional (separate) connecting electrodes.

[0103] In one embodiment, pixel PXL may include a second dam wall BNK2 that overlaps with the first electrode ELT1, the second electrode ELT2, or the third electrode ELT3. The second dam walls BNK2 may be positioned at spaced-apart locations within the emission region EMA, and each second dam wall BNK2 may protrude such that the region corresponding to one of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may protrude upwards, for example, on the third-direction DR3. Although Figure 5 illustrates a case where the second dam walls BNK2 are located not only within the emission region EMA but also on the boundary of pixel PXL, this disclosure is not limited thereto. In one embodiment, each second dam wall BNK2 may be only partially located within the emission region EMA.

[0104] In the following description, the cross-sectional structure of each pixel PXL will be detailed based on the light-emitting element (LD) with reference to Figures 6 and 7. Figure 6 illustrates a transistor T (e.g., the first transistor T1 of Figure 4 or a similar thereof), electrically connected to a first electrode ELT1 in the various circuit elements forming the pixel circuit PXC. In the following description, the term "transistor T" may be used generally to refer to the first transistor T1 unless it is not required to specify it individually. The structure of the transistor T and / or its position in layers is not limited to the embodiments illustrated in Figure 6 and can be varied in various ways depending on the embodiment. The transistors T forming each pixel circuit PXC may have substantially the same or similar structures, but this disclosure is not limited thereto. For example, in an embodiment, at least one of the transistors T forming the pixel circuit PXC may have a cross-sectional structure different from that of other transistors T, and / or be disposed on a different layer than other transistors T.

[0105] Referring to Figures 6 and 7, the pixel PXL and the display device containing the pixel PXL may include a substrate SUB, a transistor T, a first electrode ELT1, a second electrode ELT2, a third electrode ELT3, a light-emitting element LD, a first connecting electrode CNE1, a second connecting electrode CNE2, and a third connecting electrode CNE3.

[0106] The substrate SUB can form a base and is formed from a rigid or flexible substrate or film. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least an insulating layer. There are no particular limitations on the material and / or properties of the substrate SUB. In one embodiment, the substrate SUB can be substantially transparent. Here, the term "substantially transparent" can mean that light can pass through the substrate SUB at a predetermined or higher transmittance. In one embodiment, the substrate SUB can be translucent or opaque. Further, in some embodiments, the substrate SUB may include a reflective material.

[0107] Each transistor T may include a lower conductive layer BML, a semiconductor pattern SCL, a gate electrode GE, a first transistor electrode TE1, and a second transistor electrode TE2. Although Figure 6 illustrates an embodiment in which the transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed independently of the semiconductor pattern SCL, this disclosure is not limited thereto. For example, in one embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 disposed on at least one transistor T may be integrated with the corresponding semiconductor pattern SCL.

[0108] The lower conductive layer (BML) can be disposed on the substrate (SUB). The lower conductive layer (BML) can have a single-layer or multi-layer structure formed of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0109] A buffer layer (BFL) can be disposed on the underlying conductive layer (BML). The buffer layer (BFL) prevents impurities from diffusing into the circuit components. The buffer layer (BFL) can be formed as a single layer or as multiple layers having at least two or more layers. In the case of a multilayer structure, the layers can be formed of the same material or different materials.

[0110] The semiconductor pattern SCL can be disposed on the buffer layer BFL. For example, the semiconductor pattern SCL can include a first region contacting each first transistor electrode TE1, a second region contacting each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In one embodiment, one of the first region and the second region can be a source region, and the other can be a drain region.

[0111] In one embodiment, the semiconductor pattern SCL can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, or the like. The channel regions of the semiconductor pattern SCL can be intrinsically semiconductors, which are undoped semiconductor patterns. Each of the first and second regions of the semiconductor pattern SCL can be a semiconductor doped with a predetermined impurity.

[0112] The gate insulating layer GI can be disposed on the semiconductor pattern SCL. For example, the gate insulating layer GI can be disposed between the semiconductor pattern SCL and the gate electrode GE. The gate insulating layer GI can be formed of a single layer or multiple layers and contains various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0113] The gate electrode GE and / or the lower power line PL2_1 can be disposed on the gate insulating layer GI. The gate electrode GE can be disposed on the gate insulating layer GI to overlap with the semiconductor pattern SCL on the third-direction DR3. The lower power line PL2_1 can be formed as a second power line PL2 as described in Figure 4, etc. The gate electrode GE and the lower power line PL2_1 can be formed from the same conductive layer. In other words, the gate electrode GE and the lower power line PL2_1 can be formed simultaneously through the same process, but this disclosure is not limited thereto.

[0114] The interlayer insulating layer (ILD) can be disposed on the gate electrode GE and / or the lower power line PL2_1. For example, the ILD can be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The ILD can be formed of a single layer or multiple layers and contains various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0115] The first transistor electrode TE1, the second transistor electrode TE2, and / or the upper power line PL2_2 can be disposed on the interlayer insulating layer ILD. The first transistor electrode TE1 and the second transistor electrode TE2 can overlap with the semiconductor pattern SCL on the third-direction DR3. The first transistor electrode TE1 and the second transistor electrode TE2 can be electrically connected to the semiconductor pattern SCL. For example, the first transistor electrode TE1 can be electrically connected to a first region of the semiconductor pattern SCL through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. The first transistor electrode TE1 can be electrically connected to the lower half-conductive layer BML through a contact hole penetrating the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. The second transistor electrode TE2 can be electrically connected to a second region of the semiconductor pattern SCL through a contact hole penetrating the interlayer insulating layer ILD and the gate insulating layer GI. In one embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 can be a source electrode, and the other can be a drain electrode.

[0116] The upper power line PL2_2 and the lower power line PL2_1 may overlap each other on the third-direction DR3. The upper power line PL2_2 may be electrically connected to the lower power line PL2_1 through a contact hole that penetrates the interlayer insulation layer (ILD). The upper power line PL2_2 and the lower power line PL2_1 may form a second power line PL2 or similar thereof as described in Figure 4.

[0117] The first transistor electrode TE1, the second transistor electrode TE2, and the upper power line PL2_2 can be formed from the same conductive layer. In other words, the first transistor electrode TE1, the second transistor electrode TE2, and the upper power line PL2_2 can be formed simultaneously through the same process, but this disclosure is not limited to this.

[0118] A passivation layer PSV can be disposed on a circuit element containing a transistor T. The passivation layer PSV can be formed of an organic material, which is used to planarize the stepped structure disposed beneath it. For example, the passivation layer PSV can contain organic insulating materials such as acrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimides resins, unsaturated polyester resins, polyphenylene sulfides resins, or benzocyclobutene (BCB). However, this disclosure is not limited to these. The passivation layer PSV can contain various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0119] The second dam wall BNK2 can be disposed on the passivation layer PSV. The second dam wall BNK2 can be formed by individual or integral patterns. The second dam wall BNK2 can have various shapes depending on the embodiment. In one embodiment, the second dam wall BNK2 can have a shape that protrudes from the substrate SUB along a third direction DR3. Further, the second dam wall BNK2 can have an inclined surface that is tilted relative to the substrate SUB at a predetermined angle. However, this disclosure is not limited thereto. The second dam wall BNK2 can have sidewalls with curved or stepped shapes. For example, the second dam wall BNK2 can have a semi-circular or semi-elliptical cross-section.

[0120] The electrodes and insulating layer disposed on the second embankment BNK2 can have shapes corresponding to the shape of the second embankment BNK2. For example, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 disposed on the second embankment BNK2 can each have inclined or curved surfaces with shapes corresponding to the shape of the second embankment BNK2. Therefore, the second embankment BNK2 and the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 disposed thereon can be used as reflectors to guide the light emitted by the photosensitive element LD in the front direction of the pixel PXL, for example, on the third-direction DR3, thereby improving the light output efficiency.

[0121] The second dam wall BNK2 may contain at least one organic material and / or inorganic material. For example, the second dam wall BNK2 may contain organic materials such as acrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfides resin, or benzocyclobutene (BCB). However, this disclosure is not limited thereto. The second dam wall BNK2 may contain various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0122] The first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 can be disposed on the second embankment BNK2. The first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 can be separated from each other. An alignment signal (or alignment voltage) can be provided to the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 during the alignment of the light-emitting element LD. Therefore, an electric field can be formed between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3, allowing the light-emitting element LD supplied to the emission region EMA to be aligned between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3.

[0123] The first electrode ELT1 can be electrically connected to the first transistor electrode TE1 through a contact hole that penetrates the passivation layer PSV. The second electrode ELT2 can be electrically connected to the upper power line PL2_2 and the lower power line PL2_1 through a contact hole that penetrates the passivation layer PSV.

[0124] Each of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may contain at least one conductive material. For example, the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may contain at least one conductive material selected from at least one of various metallic materials, including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), and similar materials or alloys thereof; conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or fluorine tin oxide (FTO); and conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT), but this disclosure is not limited thereto.

[0125] The first insulating layer INS1 can be disposed on the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3. The first insulating layer INS1 can be formed as a single layer or multiple layers and contains various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0126] The first opening OP1 can penetrate the first insulating layer INS1. The first opening OP1 can penetrate the first insulating layer INS1 and expose the second dam wall BNK2 disposed therebelow. Even during the manufacturing process of the display device, the passivation layer PSV and / or the second dam wall BNK2 formed of organic material generate venting, which can be discharged outward through the first opening OP1 formed in the first insulating layer INS1. Therefore, defects attributable to venting can be minimized.

[0127] A first conductive layer BNK1 may be disposed on a first insulating layer INS1. A first dam wall BNK1 may be disposed around the periphery of pixel PXL to define an emission region EMA. The first dam wall BNK1 may overlap with a first opening OP1 on a third-direction DR3. The first dam wall BNK1 may contact a second dam wall BNK2 exposed by the first opening OP1.

[0128] The first dam wall BNK1 may comprise organic materials such as acrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfides resin, or benzocyclobutene (BCB). However, this disclosure is not limited thereto. The first dam wall BNK1 may comprise various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0129] The light-emitting element LD can be disposed in the emission region EMA defined by the first embankment BNK1. The light-emitting element LD can be disposed on the first insulating layer INS1 between the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3. The first light-emitting element LD1 can be disposed between the first electrode ELT1 and the second electrode ELT2. The second light-emitting element LD2 can be disposed between the second electrode ELT2 and the third electrode ELT3.

[0130] The light-emitting element (LD) can be prepared by diffusion in a predetermined solution and provided to the emitting region (EMA) of each pixel PXL via inkjet printing or a similar method. For example, the LD can be diffused in a volatile solvent and provided to each emitting region EMA. Here, by providing a predetermined voltage (or alignment voltage) to the first electrode ELT1, second electrode ELT2, and third electrode ELT3 of each pixel PXL, an electric field can be formed between the first electrode ELT1, second electrode ELT2, and third electrode ELT3, allowing the LD to be aligned between the first electrode ELT1, second electrode ELT2, and third electrode ELT3. After the LD is aligned, the solvent can be removed by evaporation or other methods. In this way, the LD can be reliably arranged between the first electrode ELT1, second electrode ELT2, and third electrode ELT3.

[0131] The second insulating layer INS2 may be disposed on the first insulating layer INS1, the first embankment BNK1, and / or the light-emitting element LD. The second insulating layer INS2 may be partially disposed on the first insulating layer INS1, the first embankment BNK1, and / or the light-emitting element LD. For example, the second insulating layer INS2 may at least partially cover (or overlap) the first embankment BNK1. The second insulating layer INS2 may be directly disposed on the first embankment BNK1.

[0132] The second opening OP2 can penetrate the second insulating layer INS2. The second opening OP2 can overlap with the first embankment BNK1 on the third-direction DR3. Furthermore, the second opening OP2 can overlap with the first opening OP1 on the third-direction DR3. However, this disclosure is not limited to this.

[0133] The second opening OP2 can penetrate the second insulating layer INS2 and expose the first dam wall BNK1 disposed beneath it. Even during the manufacturing process of the display device, the passivation layer PSV and / or the second dam wall BNK2 formed of organic material generate venting, which can be discharged outward through the second opening OP2 formed in the second insulating layer INS2. Therefore, defects attributable to venting can be minimized.

[0134] Furthermore, a second insulating layer INS2 can be disposed on the light-emitting element LD, such that the first end EP1 and the second end EP2 of the light-emitting element LD are exposed from the second insulating layer INS2. When the second insulating layer INS2 is formed on the light-emitting element LD after the alignment of the light-emitting element LD has been completed, it can prevent the light-emitting element LD from being removed from the alignment position.

[0135] The second embankment BNK2 can be formed as a single layer or multiple layers and contains various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx) and titanium oxide (TiOx).

[0136] The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be disposed on the first end EP1 and the second end EP2 of the light-emitting element LD exposed through the second insulating layer INS2. For example, the first connecting electrode CNE1 can be disposed on the first end EP1 of the light-emitting element LD. The first connecting electrode CNE1 can electrically contact the first end EP1 of the light-emitting element LD exposed through the second insulating layer INS2. The first connecting electrode CNE1 can be disposed on the first electrode ELT1. The first connecting electrode CNE1 can extend to the periphery of the first embankment BNK1 and electrically contact the first electrode ELT1 through the first contact hole CH1 that penetrates the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. In other words, the first connecting electrode CNE1 can electrically connect the first electrode ELT1 and the first light-emitting element LD1.

[0137] The second connecting electrode CNE2 can be disposed on the second end EP2 of the first light-emitting element LD1. The second connecting electrode CNE2 can electrically contact the second end EP2 of the first light-emitting element LD1 exposed from the second insulating layer INS2. Further, the second connecting electrode CNE2 can be disposed on the first end EP1 of the second light-emitting element LD2. The second connecting electrode CNE2 can electrically contact the first end EP1 of the second light-emitting element LD2 exposed from the second insulating layer INS2. The second connecting electrode CNE2 can electrically connect the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2. In one embodiment, the second connecting electrode CNE2 can overlap with the second electrode ELT2 and / or the third electrode ELT3 on the third-direction DR3, but this disclosure is not limited thereto.

[0138] The third connecting electrode CNE3 can be disposed on the second end EP2 of the second light-emitting element LD2. The third connecting electrode CNE3 can electrically contact the second end EP2 of the second light-emitting element LD2 exposed from the second insulating layer INS2. The third connecting electrode CNE3 can be disposed on the second electrode ELT2. The third connecting electrode CNE3 can extend to the periphery of the first embankment BNK1 and electrically contact the second electrode ELT2 through the second contact hole CH2 that penetrates the first insulating layer INS1, the second insulating layer INS2 and the third insulating layer INS3.

[0139] In one embodiment, the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be formed from different conductive layers. For example, as illustrated in Figure 6, after the second connecting electrode CNE2 is disposed on the second insulating layer INS2 and a third insulating layer INS3 is formed to cover (or overlap) the second connecting electrode CNE2, the first connecting electrode CNE1 and / or the third connecting electrode CNE3 can be disposed on the third insulating layer INS3. The first connecting electrode CNE1 and the third connecting electrode CNE3 can be formed from the same conductive layer. In other words, the first connecting electrode CNE1 and the third connecting electrode CNE3 can be formed simultaneously through the same process, but this disclosure is not limited thereto.

[0140] The order in which the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 are formed can be varied according to the embodiments. In other words, after the first connecting electrode CNE1 and the third connecting electrode CNE3 are formed first, and a third insulating layer INS3 is formed to cover (or overlap) the first connecting electrode CNE1 and the third connecting electrode CNE3, the second connecting electrode CNE2 can be formed on the third insulating layer INS3. The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be formed simultaneously through the same process.

[0141] The first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be formed from various transparent conductive materials. For example, the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can contain at least one of various transparent conductive materials, including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine tin oxide (FTO), and can be formed transparently or semi-transparently to meet a predetermined transmittance. Therefore, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD can pass through the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 and be emitted to the outside of the display panel PNL.

[0142] A third insulating layer INS3 can be disposed between the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3, which are formed from different conductive layers. For example, as shown in Figure 6, the third insulating layer INS3 can be disposed on the second connecting electrode CNE2. The third insulating layer INS3 can cover (or overlap) the second connecting electrode CNE2 and expose the first end EP1 of the first light-emitting element LD1 and the second end EP2 of the second light-emitting element LD2. The first connecting electrode CNE1 can be disposed on the first end EP1 of the first light-emitting element LD1 exposed from the third insulating layer INS3. The third connecting electrode CNE3 can be disposed on the second end EP2 of the second light-emitting element LD2 exposed from the third insulating layer INS3. As described above, when the third insulating layer INS3 is disposed between the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3, which are formed from different conductive layers, the first connecting electrode CNE1, the second connecting electrode CNE2, and the third connecting electrode CNE3 can be reliably separated from each other through the third insulating layer INS3, thereby ensuring the electrical stability between the first end EP1 and the second end EP2 of the light-emitting element LD. Therefore, it can effectively prevent short-circuit defects between the first terminal EP1 and the second terminal EP2 of the light-emitting element LD.

[0143] Furthermore, the third insulating layer INS3 can be disposed on the second insulating layer INS2 covering the first embankment BNK1. The third insulating layer INS3 can be directly disposed on the second insulating layer INS2.

[0144] The third opening OP3 can penetrate the third insulating layer INS3. In one embodiment, the third opening OP3 can penetrate not only the third insulating layer INS3, but also the second insulating layer INS2 disposed below it. The third opening OP3 of the third insulating layer INS3 and the third opening OP3 of the second insulating layer INS2 can be formed simultaneously through the same process, but this disclosure is not limited thereto.

[0145] The third opening OP3 may overlap with the first embankment BNK1 on the third-direction DR3. Furthermore, the third opening OP3 may overlap with the first opening OP1 on the third-direction DR3, but this disclosure is not limited thereto.

[0146] The third opening OP3 can penetrate the third insulating layer INS3 and / or the second insulating layer INS2, exposing the first dam wall BNK1 disposed beneath it. Even during the manufacturing process of the display device, venting occurs in the passivation layer PSV and / or the second dam wall BNK2 formed of organic material, and this venting can be discharged outward through the third opening OP3 formed in the third insulating layer INS3 and / or the second insulating layer INS2. Therefore, defects attributable to venting can be minimized.

[0147] The third insulating layer INS3 can be formed as a single layer or multiple layers and contains various inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx) and titanium oxide (TiOx).

[0148] In the display device according to the above embodiment, even during the manufacturing process of the display device, the passivation layer PSV and / or the second dam wall BNK2 formed of organic material generate exhaust gas, which can be discharged outward through the first opening OP1, the second opening OP2 and the third opening OP3 formed around the emission region EMA. Therefore, defects attributable to exhaust gas can be minimized.

[0149] Another embodiment will be described below. In the following description of the embodiment, the same element symbols will be used to represent the same elements as described above, and repeated descriptions will be omitted or simplified.

[0150] Figure 8 is a schematic plan view illustrating pixels according to one embodiment. Figure 9 is a schematic cross-sectional view taken along line C-C' of Figure 8.

[0151] Referring to Figures 8 and 9, the difference between this embodiment and the embodiments in Figures 1 to 7 is at least that the entirety of each first opening OP1 overlaps with the corresponding second opening OP2 and / or third opening OP3.

[0152] In detail, the first opening OP1 may completely overlap with the second opening OP2 on the third-direction DR3. However, this disclosure is not limited to this. For example, the first opening OP1 may partially overlap with the second opening OP2, or it may not overlap with the second opening OP2. When the first opening OP1 and the second opening OP2 completely overlap each other, the surface area of ​​the first opening OP1 may be smaller than the surface area of ​​the second opening OP2, but this disclosure is not limited to this.

[0153] Furthermore, the first opening OP1 may completely overlap with the third opening OP3 on the third-direction DR3. However, this disclosure is not limited to this. For example, the first opening OP1 may partially overlap with the third opening OP3 or may not overlap with the third opening OP3. In the case where the first opening OP1 and the third opening OP3 completely overlap each other, the surface area of ​​the first opening OP1 may be smaller than the surface area of ​​the third opening OP3, but this disclosure is not limited to this. In addition, the surface area of ​​the third opening OP3 may be substantially the same as the surface area of ​​the second opening OP2, but this disclosure is not limited to this.

[0154] The first opening OP1, the second opening OP2, and the third opening OP3 have been described in detail with reference to Figures 1 to 7, and their repeated descriptions will be omitted.

[0155] Figure 10 is a schematic plan view illustrating pixels according to one embodiment. Figure 11 is a schematic cross-sectional view taken along line D-D' of Figure 10.

[0156] Referring to Figures 10 and 11, the display device according to this embodiment differs from the embodiments of Figures 1 to 7 in that the first opening OP1 extends in the first direction DR1.

[0157] In detail, the first opening OP1 can extend in the first direction DR1, and the second opening OP2 and / or the third opening OP3 can be separated from each other in the first direction DR1. For example, the second opening OP2 and the third opening OP3 can be alternately arranged in the first direction DR1. In other words, each second opening OP2 can be arranged between adjacent third openings OP3, and each third opening OP3 can be arranged between adjacent second openings OP2. However, this disclosure is not limited to this, and the arrangement and position of the first opening OP1, the second opening OP2, and the third opening OP3 can be changed in various ways as long as the first opening OP1, the second opening OP2, and the third opening OP3 overlap with the first embankment BNK1. For example, the first opening OP1 can extend not only in the first direction DR1, but also in various directions, and the second opening OP2 and / or the third opening OP3 can be separated from each other not only in the first direction DR1, but also in various directions. The second openings OP2 can be arranged consecutively in the first direction DR1, and the third openings OP3 can be arranged consecutively in the first direction DR1.

[0158] Each second opening OP2 may overlap with the corresponding first opening OP1 on the third direction DR3. Although Figure 10 illustrates the case where each second opening OP2 is entirely overlapped with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each second opening OP2 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the second opening OP2 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the second opening OP2 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0159] Each third opening OP3 may overlap with the corresponding first opening OP1 on the third-direction DR3. Although Figure 10 illustrates the case where each third opening OP3 overlaps entirely with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each third opening OP3 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the third opening OP3 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the third opening OP3 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto. Furthermore, the surface area of ​​the third opening OP3 may be substantially the same as the surface area of ​​the second opening OP2, but this disclosure is not limited thereto.

[0160] The first opening OP1, the second opening OP2, and the third opening OP3 have been described in detail with reference to Figures 1 to 7, and their repeated descriptions will be omitted.

[0161] Figure 12 is a schematic plan view illustrating pixels according to one embodiment. Figure 13 is a schematic cross-sectional view taken along line E-E' of Figure 12.

[0162] Referring to Figures 12 and 13, the display device according to this embodiment differs from the embodiments in Figures 1 to 7 in that the first opening OP1, the second opening OP2, and the third opening OP3 extend in the first direction DR1.

[0163] In detail, the first opening OP1 may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2. The second opening OP2 and / or the third opening OP3 may extend in the first direction DR1 and be spaced apart from each other in the second direction DR2. The second opening OP2 and the third opening OP3 may be alternately arranged in the second direction DR2. In other words, each second opening OP2 may be arranged between adjacent third openings OP3. However, this disclosure is not limited to this, and the arrangement and position of the first opening OP1, the second opening OP2 and the third opening OP3 may be changed in various ways as long as the first opening OP1, the second opening OP2 and the third opening OP3 overlap with the first embankment BNK1. For example, the first opening OP1, the second opening OP2 and the third opening OP3 may extend not only in the first direction DR1, but also in various directions.

[0164] Each second opening OP2 may overlap with the corresponding first opening OP1 in the first direction DR1. Although Figure 12 illustrates that each second opening OP2 completely overlaps with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each second opening OP2 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the second opening OP2 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the second opening OP2 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0165] Each third opening OP3 may overlap with the corresponding first opening OP1 on the third-direction DR3. Although Figure 12 illustrates that each third opening OP3 overlaps entirely with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each third opening OP3 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the third opening OP3 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the third opening OP3 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto. Furthermore, the surface area of ​​the third opening OP3 may be substantially the same as the surface area of ​​the second opening OP2, but this disclosure is not limited thereto.

[0166] The first opening OP1, the second opening OP2, and the third opening OP3 have been described in detail with reference to Figures 1 to 7, and their repeated descriptions will be omitted.

[0167] Figure 14 is a schematic plan view illustrating pixels according to one embodiment. Figure 15 is a schematic cross-sectional view taken along line F-F' of Figure 14.

[0168] Referring to Figures 14 and 15, the display device according to this embodiment differs from the embodiments in Figures 1 to 7 in that the third opening OP3 is omitted.

[0169] In detail, the pixel PXL may include a first opening OP1 and a second opening OP2 disposed around the emission region EMA.

[0170] Each of the first opening OP1 and the second opening OP2 may overlap with the first embankment BNK1. The first openings OP1 may be separated from each other. For example, as illustrated in Figure 14, the first openings OP1 may be separated from each other in the first direction DR1. However, this disclosure is not limited thereto, and the arrangement and position of the first openings OP1 may be changed in various ways as long as they overlap with the first embankment BNK1.

[0171] The second openings OP2 can be separated from each other. For example, as shown in Figure 14, the second openings OP2 can be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the second openings OP2 can be changed in various ways as long as the second openings OP2 overlap with the first embankment BNK1.

[0172] The second opening OP2 may overlap with the first opening OP1. Although Figure 14 illustrates the case where the second opening OP2 completely overlaps with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each second opening OP2 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the second opening OP2 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the second opening OP2 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0173] The first opening OP1 and the second opening OP2 have been described in detail with reference to Figures 1 to 7, and their repeated descriptions will be omitted.

[0174] Figure 16 is a schematic plan view illustrating pixels according to one embodiment. Figure 17 is a schematic cross-sectional view taken along line G-G' of Figure 16.

[0175] Referring to Figures 16 and 17, the display device according to this embodiment differs from the embodiments in Figures 1 to 7 in that the second opening OP2 is omitted.

[0176] In detail, the pixel PXL may include a first opening OP1 and a third opening OP3 disposed around the emission region EMA.

[0177] The first opening OP1 and the third opening OP3 may overlap with the first embankment BNK1. The first opening OP1 may be separated from each other. For example, as shown in Figure 16, the first openings OP1 may be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the first opening OP1 may be changed in various ways as long as the first opening OP1 overlaps with the first embankment BNK1.

[0178] The third opening OP3 can be separated from each other. For example, as shown in Figure 16, the third opening OP3 can be separated from each other in the first direction DR1. However, this disclosure is not limited to this, and the arrangement and position of the third opening OP3 can be changed in various ways as long as the third opening OP3 overlaps with the first embankment BNK1.

[0179] The third opening OP3 may overlap with the first opening OP1. Although Figure 16 illustrates the case where the entire third opening OP3 overlaps with the corresponding first opening OP1, this disclosure is not limited thereto. In other words, each third opening OP3 may partially overlap with the corresponding first opening OP1, or may not overlap with the first opening OP1. The surface area of ​​the third opening OP3 may differ from the surface area of ​​the first opening OP1. For example, the surface area of ​​the third opening OP3 may be smaller than the surface area of ​​the first opening OP1, but this disclosure is not limited thereto.

[0180] The first opening OP1 and the third opening OP3 have been described in detail with reference to Figures 1 to 7, and their repeated descriptions will be omitted.

[0181] According to one embodiment, even if venting occurs from the organic layer during the manufacturing process of the display device, the venting can be discharged outward through openings formed in the insulating layer. Therefore, defects attributable to venting can be minimized.

[0182] The effects of this disclosure are not limited to those described above, and various other effects can be expected herein.

[0183] It will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Therefore, the above embodiments should be considered illustrative only and not for limiting purposes. The scope of the invention is not defined by the detailed description of this disclosure, but by the appended claims, and all differences within that scope shall be interpreted as included in this disclosure.

[0184] PNL: Display Panel SUB:Substrate DA: Display area NDA: Non-display area PXU: Pixel Unit PXL: pixels PXL1: First pixel PXL2: Second pixel PXL3: Third Pixel LD: Light-emitting element LD1: First light-emitting element LD2: Second light-emitting element EP1: First End EP2: Second End D: Diameter L: Length BNK1: First Embankment BNK2: Second Embankment EMA: Launch Area ELT1: First electrode ELT2: Second electrode ELT3: Third Electrode OP1: First opening OP2: Second opening OP3: Third opening CH1: First contact hole CH2: Second contact hole CNE1: First connecting electrode CNE2: Second connecting electrode CNE3: Third connecting electrode INF: Insulating film BFL: Buffer Layer GI: Gate Insulation Layer ILD: Interlayer Insulation Layer PSV: Passivation layer INS1: First insulating layer INS2: Second insulating layer INS3: Third Insulation Layer BML: Lower conductive layer GE: Gate electrode SCL: Semiconductor Pattern PXC: Pixel Circuit LSU: Transmitter Circuit PL1: First power line PL2: Second power supply line PL2_1: Lower power cord PL2_2: Power cord Cst: Storage capacitor Si: Scan line SSi: Scan Signal SLj: Sensing line SENj: Sensor signal SCLi: Sensing control line SCSi: Sensing control signal Dj: Data Line DSj: Data Signal T: Transistor T1: First transistor T2: Second transistor T3: Third transistor TE1: First transistor electrode TE2: Second transistor electrode TE3: Third transistor electrode N1: First node VDD: First power supply VSS: Second Power Supply 11: First semiconductor layer 12: Active Layer 13: Second semiconductor layer DR1: First direction DR2: Second Direction DR3: Third-party

Claims

1. A display device comprising: a substrate including a plurality of pixels; a first embankment defining an emitting region for each of the plurality of pixels; a first electrode and a second electrode spaced apart from each other in a plan view of the emitting region; a first insulating layer disposed on the first electrode and the second electrode; a plurality of light-emitting elements disposed on the first insulating layer between the first electrode and the second electrode; a second insulating layer disposed on the first embankment; a first opening penetrating the first insulating layer; and a second opening penetrating the second insulating layer, wherein the first opening and the second opening overlap the first embankment, and one end of each of the plurality of light-emitting elements is electrically connected to one of the first electrode and the second electrode, and the other end of each of the plurality of light-emitting elements is electrically connected to the other of the first electrode and the second electrode.

2. The display device as claimed in claim 1, wherein the second opening exposes the first embankment.

3. The display device as claimed in claim 1, wherein the first opening overlaps with the second opening.

4. The display device as claimed in claim 1, wherein the surface area of ​​the first opening is greater than the surface area of ​​the second opening.

5. The display device as claimed in claim 1, wherein the surface area of ​​the first opening is smaller than the surface area of ​​the second opening.

6. The display device as claimed in claim 1, wherein the first opening and the second opening extend in a first direction.

7. The display device as claimed in claim 1, wherein the first dam is disposed between the first insulating layer and the second insulating layer.

8. The display device as claimed in claim 1, further comprising a second dam wall disposed between the substrate and the first dam wall.

9. The display device as claimed in claim 8, wherein the first opening exposes the second embankment.

10. The display device as claimed in claim 8, wherein the first embankment contacts the second embankment through the first opening.

11. The display device as claimed in claim 1, further comprising: a third insulating layer disposed on the second insulating layer; and a third opening penetrating the second insulating layer and the third insulating layer.

12. The display device as claimed in claim 11, wherein the third insulating layer overlaps with the first embankment.

13. The display device as claimed in claim 11, wherein the third opening exposes the first embankment.

14. The display device as claimed in claim 11, wherein the third insulating layer contacts the first embankment through the second opening.

15. The display device as claimed in claim 11, wherein the second opening and the third opening are alternately arranged in a first direction.

16. The display device as claimed in claim 11, wherein the second opening and the third opening extend in a first direction.

17. The display device as claimed in claim 16, wherein the second opening and the third opening are separated from each other in a second direction intersecting the first direction.

18. The display device as claimed in claim 11, further comprising: a first connecting electrode disposed on the third insulating layer; and a second connecting electrode disposed between the second insulating layer and the third insulating layer.

19. The display device as claimed in claim 18, wherein the first connecting electrode electrically contacts one end of each of the plurality of light-emitting elements, and the second connecting electrode electrically contacts the other end of each of the plurality of light-emitting elements.

20. The display device as claimed in claim 11, wherein at least one of the first insulating layer, the second insulating layer and the third insulating layer comprises an inorganic material.

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