Memory having flying bitlines for improved burst mode read operations

Abstract

This invention provides a memory and related methods having flying bit lines for improved short-pulse read operations. The memory system includes a memory array comprising a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line. The memory system includes a control unit configured to generate control signals for simultaneously: determining a first word line signal on the first inner word line coupled to each of a plurality of inner bit lines, and determining a second word line signal on the first outer word line coupled to each of a plurality of outer bit lines, wherein each of the plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line, and outputting data from each of the first and second sets of memory cells as part of a short pulse.

Description

Technical Field

[0001] This disclosure relates to a memory with a flying bit line for improved short-pulse read operation. Prior Technology

[0002] Processors typically include at least one or more processing cores coupled to random access memory (SRAM), which is integrated as a single die on an integrated circuit or as a multi-die component of a stack of integrated circuits. Processors used for machine learning or other artificial intelligence applications require fast access to large amounts of data. For example, a processor may need to access and process large amounts of training data and weights for machine learning. Other applications of processors also require high-bandwidth access to large amounts of data.

[0003] To meet the processor requirements of applications that need to access large amounts of data quickly, we need to continuously improve memory systems. Summary of the Invention

[0004] In one instance, this disclosure relates to a method of operating a memory system comprising a first memory subarray and a second memory subarray, wherein the first memory subarray includes a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, and wherein the second memory subarray includes a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line. The method may include responding to a short pulse read request while: (1) determining a first word line signal on a first inner word line coupled to each of a first plurality of inner bit lines; (2) determining a second word line signal on a first outer word line coupled to each of a first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line; (3) determining a third word line signal on a second inner word line coupled to each of a second plurality of inner bit lines; and (4) determining a fourth word line signal on a second outer word line coupled to each of a second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a second portion configured to fly above or below the corresponding inner bit line. The method may further include outputting data from each of a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells as part of a short pulse.

[0005] In another example, this disclosure relates to a memory system including a memory array comprising a first set of memory cells coupled to a first internal word line and a second set of memory cells coupled to a first external word line. The memory system may further include a control unit configured to generate control signals in response to a short pulse read request, while: (1) determining a first word line signal coupled to each of the plurality of internal word lines on the first internal word line, and (2) determining a second word line signal coupled to each of the plurality of external word lines on the first external word line, wherein each of the plurality of external word lines includes a first portion configured to fly above or below the corresponding internal word line, and outputs data from each of the first set of memory cells and the second set of memory cells as part of a short pulse.

[0006] In another instance, this disclosure relates to a memory system comprising a first memory subarray and a second memory subarray, wherein the first memory subarray comprises a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, wherein the second memory subarray comprises a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line, wherein each of the first group of memory cells and the second group of memory cells is organized in a first plurality of rows, and wherein each of the third group of memory cells and the fourth group of memory cells is organized in a second plurality of rows. The memory system may further include a control unit configured to generate a control signal in response to a first short pulse read request, while: (1) determining a first word line signal coupled to each of the first plurality of inner word lines on a first inner word line; (2) determining a second word line signal coupled to each of the first plurality of outer word lines on a first outer word line, wherein each of the first plurality of outer word lines includes a first portion configured to fly above or below the corresponding inner word line; (3) determining... (4) Determine the third word line signal on the second inner word line coupled to each of the second plurality of inner bit lines, and determine the fourth word line signal on the second outer word line coupled to each of the second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a second portion configured to fly above or below the corresponding inner bit line, and uses a common line circuit system, and outputs data from each of the first group of memory units, the second group of memory units, the third group of memory units and the fourth group of memory units as part of a short pulse. Alternatively, in the second short pulse, the control unit may be configured to generate a control signal in response to the second short pulse read request, while: (1) determining a first word line signal on a first inner word line coupled to each of the first plurality of inner bit lines, and (2) determining a second word line signal on a first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line, and outputs data from each of the first set of memory units and the second set of memory units.

[0007] This invention provides a simplified overview of a series of concepts, which will be further described below in the embodiments. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Simple Explanation of the Diagram

[0008] This disclosure is illustrated by example and is not limited to the accompanying drawings, in which the same symbols represent the same elements. The elements in the drawings are illustrated for the sake of simplicity and clarity and are not necessarily drawn to scale.

[0009] Figure 1 illustrates a schematic diagram of a memory with fly-through bit lines for short-pulse read operations, based on an example.

[0010] Figure 2 illustrates a portion of the memory from Figure 1, based on an example.

[0011] Figure 3 illustrates a cross-sectional view of an implementation of the flight bit line for the memory in Figure 1, according to an example;

[0012] Figure 4 illustrates a memory system that includes the memory in Figure 1;

[0013] Figure 5 illustrates the waveform associated with a short-pulse read using the memory system in Figure 4, based on an example; and

[0014] Figure 6 illustrates a flowchart of a method for short-pulse reading using the memory system in Figure 4, based on an example. Implementation

[0015] The examples described in this disclosure relate to memory with flying bit lines for improved memory read operations, specifically short-pulse read operations. Traditionally, even reading data from memory as part of a short-pulse operation is not energy-efficient and may not have sufficient bandwidth to meet the demands of data from a faster processing core. This results in low energy efficiency of processor-coupled memory, requiring longer wait times to receive data from memory in response to read requests. Some examples in this disclosure relate to memory systems that improve the energy efficiency of short-pulse read operations and support higher bandwidth to meet the demands of data from a faster processing core or other processing logic (e.g., FPGA logic).

[0016] Figure 1 illustrates a schematic diagram of a memory 100 with flying bit lines for short-pulse read operations according to an example. Memory 100 may include memory subarray 110 and memory subarray 150. Memory subarray 110 may include a set of word lines (WL) corresponding to the inner column (e.g., word line 120) and a set of word lines (WL) corresponding to the outer column (e.g., word line 130). Memory subarray 110 may further include a set of inner bit lines 112, 114, 116, and 118 and a set of outer bit lines 122, 124, 126, and 128. Similarly, memory subarray 150 may include a set of inner word lines (WL) (e.g., word line 160) and another set of outer word lines (WL) (e.g., word line 170). The memory subarray 150 may further include a set of inner bit lines 152, 154, 156, and 158 and a set of outer bit lines 162, 164, 166, and 168. In one example, during a short-pulse read operation, each of the word lines 120 and 130 of the memory subarray 110 and each of the word lines 160 and 170 of the memory subarray 150 may be determined simultaneously to allow access to memory cells connected to the inner and outer bit lines of each of the memory subarrays.

[0017] Referring again to Figure 1, each of the inner bit lines 112, 114, 116, and 118 and the outer bit lines 122, 124, 126, and 128 can be coupled to a common mux 132. Each of the outer bit lines can be implemented as part of an integrated circuit, configured to "fly above" or "fly below" the inner bit lines. In this manner, each of the inner bit lines 112, 114, 116, and 118 and the outer bit lines 122, 124, 126, and 128 can be coupled to the common mux 132. The memory subarray 110 may include other sets of inner and outer bit lines that can be coupled to separate common muxes (e.g., muxes 134 and 136). Each of the inner bit lines 152, 154, 156, and 158 and the outer bit lines 162, 164, 166, and 168 may be coupled to a row multiplexer (mux) 172. The memory subarray 150 may include other sets of inner and outer bit lines that may be coupled to separate shared row multiplexers (e.g., row multiplexers 174 and 176). Row multiplexers 132 and 172 may both be coupled to a shared row circuitry system 182. Similarly, row multiplexers 134 and 174 may both be coupled to a shared row circuitry system 184. Additionally, row multiplexers 136 and 176 may both be coupled to a shared row circuitry system 186. As used herein, the term "external word line" includes memory rows that are spatially farther from the row circuitry (e.g., row circuitry 182, 184, or 186), and the term "internal word line" includes memory rows that are spatially closer to the row circuitry. As used herein, the term "external bit line" includes bit lines that have memory cells accessed when an "external word line" is activated, and the term "internal bit line" includes bit lines that have memory cells accessed when an "internal word line" is activated.

[0018] Referring again to Figure 1, a column decoder (not shown in Figure 1) (including a word line driver) can be used to determine the word line signal. The column decoder decodes the address signal and uses the corresponding word line driver to determine the associated word line. A row circuit system (e.g., one of row circuit systems 182, 184, and 186) can be used to determine the bit line signal. A sense amplifier or other similar circuit system can be used to precharge the bit line before sensing the voltage on the bit line. Further details of the operation of memory 100 are described with reference to memory system 400 in Figure 4 and waveform 500 shown in Figure 5.

[0019] Referring again to Figure 1, regarding the short-pulse read operation, in one example, two word lines in each of the memory subarrays can be activated simultaneously, and the read row selection signal address can be sequentially incremented. Thus, in one example, word lines 120 and 130 in memory subarray 110 and word lines 160 and 170 in memory subarray 150 can be activated simultaneously. These word lines remain activated until the inner and outer bit lines corresponding to each row of memory subarrays 110 and 150 output data bits. Advantageously, using this arrangement, more data bits can be output in each short-pulse read operation, and less energy is consumed per short-pulse read cycle. For example, twice the number of bits can be output as part of a short-pulse read operation, and access time is improved. The total bandwidth of memory 100 (measured in bits per ps) is approximately 22 percent higher than that of conventional memory. For example, address decoding time can be saved by simultaneously decoding a larger number of data words. Simultaneously, the energy consumed per bit in a portion of a short-pulse read operation is approximately 25 percent less than that consumed per bit in conventional memory. Furthermore, the effective bit line load can be reduced because, without separating inner and outer bit lines, each bit line can be associated with twice the number of memory cells (e.g., 256 cells compared to 128 cells). The lower effective bit line load can further reduce the signal development time per bit line to approximately 0.6 times that of conventional signal development time. While the memory 100 illustrated in Figure 1 includes a certain number of components arranged in one manner, the memory 100 may include additional or fewer components arranged in a different manner.

[0020] Figure 2 illustrates a schematic diagram of a portion 200 of a memory having flying bit lines for short-pulse read operations according to an example. Portion 200 illustrates further details of a portion of the memory subarray 110 of Figure 1. As explained above with reference to Figure 1, each memory subarray of a shared row circuitry system may include inner bit lines and outer bit lines. For example, Figure 2 illustrates inner bit lines 212 and 214 and outer bit lines 216 and 218. Memory cells (e.g., static random access memory (SRAM) cells) may be coupled to bit lines. For example, as shown in Figure 2, memory cells 222, 224, and 226 are coupled to inner bit lines 212 and 214, and memory cells 232, 234, and 236 are coupled to outer bit lines 216 and 218. Each column of memory cells may be driven by a corresponding word line. Figure 2 illustrates word lines (WL1) 242 coupled to memory cells (including memory cell 232) in an outer row and word lines (WL2) 244 coupled to memory cells (e.g., memory cell 222) in an inner row. Each memory cell may include a cross-coupled inverter and additional transistors. In one example, each memory cell may be implemented as a six-transistor (6T) memory cell. Other numbers of cells arranged in different ways may also be used. Furthermore, memory technology is not limited to SRAM and may include other types of memory, including phase-change memory and magnetic random access memory.

[0021] Referring again to Figure 2, each of the outer bit lines (e.g., outer bit lines 216 and 218) can be implemented as part of an integrated circuit, such that at least a portion of these outer bit lines can "fly above" or "fly below" the corresponding inner bit lines (e.g., inner bit lines 212 and 214). In this manner, each of the inner bit lines 212 and 214 and the outer bit lines 216 and 218 can be coupled to a common line multiplexer (mux) 270 or another common line circuit system. As shown in Figure 2, each outer bit line (including BL and BLB bit lines) may include two portions: a first portion (e.g., each of portions 252 and 262) accessed when an outer word line (e.g., WL1 242) is activated, and a second portion (e.g., each of portions 256 and 266) accessed when an inner word line (e.g., WL2 244) is activated. Individual portions of the outer bit lines can be coupled via an interconnect. For example, portion 252 of the outer bit line (BL) is coupled to portion 256 of the outer bit line (BL) via interconnect 254. Similarly, for example, portion 262 of the outer bit line (BLB) is coupled to portion 266 of the outer bit line (BLB) via interconnect 264. Interconnects 254 and 264 can be implemented as a jumper or another structure electrically connecting the two portions of the outer bit lines. Furthermore, as shown in Figure 2, in this example, portions 256 and 266 of the outer bit lines are portions that are "flying above" or "flying below" the corresponding inner bit lines.

[0022] Referring again to Figure 2, in this example, a read row selection signal (labeled RDYSEL_B) can be used to select the appropriate row associated with the memory used to output data stored in the memory cell. In this example, when the read row selection signal (RDYSEL_B signal) is a logic low compared to a logic high, it indicates that a decision has been made. The sense amplifier 280 can sense the voltage difference between the positive bit line (BL) and the negative bit line (BLB) by amplifying the voltage difference, and can then determine whether the stored bit is a logic 1 bit or a logic 0 bit based on the voltage difference. The output bit can be stored in the output data latch 290. Once the row for reading the data word is selected using the read row selection signal (RDYSEL_B signal), the sense amplifier associated with the selected bit line can be enabled via the signal labeled SAEN in Figure 2. In one example, as shown below with reference to Figure 4, the control unit 430 in Figure 4 can determine the sense enable (SAEN) signal in response to the resolution of the corresponding read row selection signal (RDYSEL_B signal). As shown in Figure 2, before enabling sense amplifier 280 (e.g., by determining a signal labeled SAEN), sense amplifier 280 may be precharged in response to a determination of a signal labeled SAPCHG_B, which is represented as a logic low signal compared to a logic high signal. Further details of these signals and their interrelationships are provided with reference to Figures 4 and 5.

[0023] Figure 3 illustrates a cross-sectional view 300 of an embodiment of the flying bit lines for the memory 100 of Figure 1, according to one example. Cross-sectional view 300 only illustrates a portion of the integrated circuitry that may include the memory 100. Furthermore, cross-sectional view 300 only illustrates details related to the embodiment of the flying bit lines for the memory 100 of Figure 1. The integrated circuitry having the memory 100 may include a substrate 310. The substrate 310 may correspond to a die associated with the integrated circuitry. Various layers, including metal layers, dielectric layers, and other layers, may be formed using semiconductor processing techniques. In this example, a cross-sectional view 320 is shown of one of the inner bit lines (e.g., bit line 212 in Figure 2) that may be formed in the metal layer M0. Cross-sectional view 320 is indicated by dashed lines because the inner bit lines may not be visible in the same plane as the cross-section of the outer bit lines. Additionally, a cross-sectional view 330 showing a portion of one of the outer bit lines (e.g., a portion 252 of outer bit line 216 similar to that in Figure 2) may also be at least partially formed in metal layer M0. A cross-sectional view 340 showing a portion of the outer bit line is shown flying above the cross-sectional view 320 of the inner bit line. In this example, the flying portion of the outer bit line may be formed in metal layer M2. Furthermore, cross-sectional view 350 shows a portion of an interconnect structure (e.g., a jumper) connecting the two portions of the outer bit line. A via or other mechanism may be used to connect a portion of the outer bit line formed in metal layer M0 to a portion of the outer bit line formed in metal layer M2. Although Figure 3 shows a layer and an arrangement of interconnects therein, flying bit lines may be formed using layers with different arrangements of interconnects. For example, although Figure 3 illustrates an outer bit line "flying above" the inner bit line, an outer bit line may also be formed to "fly below" the inner bit line. In addition, the bit lines do not need to be directly above or below each other; they can be offset from each other.

[0024] Figure 4 illustrates a memory system 400 that includes memory 100 from Figure 1. The memory system 400 can be included as SRAM in an integrated circuit having one or more processing cores. This integrated circuit can be implemented as a central processing unit (CPU) (single or multi-core), a graphics processing unit (GPU), or a field-programmable gate array (FPGA). The memory system 400 can be implemented as block RAM (BRAM) as part of an FPGA. Alternatively, the memory system 400 can be implemented as a standalone memory system. Alternatively, the memory system 400 can be integrated with logic as part of a 3D stacked system (e.g., a high bandwidth memory (HBM) system). The memory system 400 may include two memory subarrays: memory subarray 410 and memory subarray 450 arranged as shown in Figure 4. The memory system 400 may further include a word line decoder 412 coupled to the memory subarray 410 and another word line decoder 452 coupled to the memory subarray 450. A row circuit system 414 may be coupled to the memory subarray 410 to interface with the bit lines (inner and outer bit lines) included in the memory subarray 410. Similarly, a row circuit system 454 may be coupled to the memory subarray 450 to interface with the bit lines (inner and outer bit lines) included in the memory subarray 450. An I / O circuit system 440 may be coupled to the row circuit systems 414 and 454. The memory system 400 may further include a control unit 430, which may be at least coupled to the word line decoder 412, word line decoder 452, row circuit system 414, row circuit system 454, and I / O circuit system 440.

[0025] Referring again to Figure 4, the control unit 430 can generate control signals for controlling the operation of various components of the memory system 400. For example, the control unit 430 can process any read / write signals, short pulse signals, and addresses. In one example, the control unit 430 may include a timing circuit system, a finite state machine, and other logic to allow the generation of appropriate control signals. For example, the control unit 430 can generate control signals that (directly or indirectly) generate other signals, resulting in short pulse operation as further described with reference to Figure 5. Although the memory system 400 illustrated in Figure 4 includes a certain number of components arranged in one manner, the memory system 400 may include more or fewer components arranged in a different manner. For example, the control unit 430 can be configured to operate the memory system 400 in multiple different short pulses. In one short pulse, two word lines of each memory subarray (e.g., memory subarrays 410 and 450) can be simultaneously determined to output data from the memory cells. Alternatively, in the second short pulse, only two word lines of one of the memory subarrays (e.g., one of memory subarrays 410 and 450) can be activated at a time. After data is output from the first memory subarray, the other two word lines of the other memory subarray (e.g., the other of memory subarrays 410 and 450) can be activated immediately. As part of the third short pulse, one word line of each memory subarray (e.g., memory subarray 410 or 450) can be determined at a time until all four word lines corresponding to the two memory subarrays are determined sequentially. Data words can still be output as part of a single pulse. Furthermore, although Figure 4 shows two memory subarrays (e.g., memory subarrays 410 and 450), the memory system 400 may contain only one subarray.

[0026] Figure 5 illustrates waveform 500 associated with a short-pulse read operation using the memory system 400 of Figure 4, according to an example. As explained above, the memory system 400 may include memory subarrays with inner and outer bit lines configured to output bits in response to simultaneous determination of two word lines of each memory subarray. The memory system 400 may be configured to output a certain number of data words in each short-pulse cycle. Referring to Figure 5, the operation of the memory system 400 is assumed to be configured to output 16 data words in response to a short-pulse read operation request. The number of data words output may depend on the number of rows in each memory subarray. Waveform 500 shows the internal waveform corresponding to the operation of the memory system 400 including the memory 100 of Figure 1. Waveform 500 shows the internal clock signal (CLK) associated with the memory system 400. This clock signal can be used to coordinate the timing of determination and resolution of various signals associated with the memory system 400. Waveform 500 further illustrates a short pulse signal (BURST), which can be processed by the control unit 430 associated with the memory system 400. Additionally, waveform 500 illustrates the provision of an address (ADDR) for reading data (e.g., ADDR1) within the short pulse. In this example, the determination of the BURST signal indicates to the control unit 430 that the read operation is a short pulse operation compared to a non-short pulse operation. In response, the control unit 430 can activate logic (including finite state machines and timers) to control the internal timing of other signals associated with the memory system 400.

[0027] Referring again to Figure 5, in response to a short pulse signal (BURST) and an address (ADDR1), control unit 430 can determine which of the two word lines needs to be activated for each of the memory subarrays (e.g., the two word lines of memory subarray 410 and the two word lines of memory subarray 450). Before activating the word lines, control unit 430 can precharge the inner and outer bit lines by determining a bit line precharge signal (the waveform labeled BLPCHG_B<1.2> in Figure 5) for memory subarrays 410 and 450. In this example, the bit line precharge signal is represented as a logic low relative to a logic high signal. Once precharged, as shown in Figure 5, the determination of the bit line precharge signals for both subarrays is deactivated, and the appropriate word line signal is determined simultaneously. In one example, the address (ADDR1) may include at least two address bits for selecting the appropriate word line. A character line decoder (e.g., character line decoder 412 and character line decoder 452) can activate the appropriate character line. In this example, the control unit 430 can provide a control signal to the character line decoder to control the timing of the determination of the character line signal. For example, the control unit 430 can determine a control signal that activates the character line a certain period after the determination of the bit line precharge signal (BLPCHG_B<1.2>). For ease of illustration, although waveform 500 shows the activation of a single character line (WL), in this example, four character lines are activated simultaneously: two character lines corresponding to memory subarray 410 and two character lines corresponding to memory subarray 450. Advantageously, in a short pulse read operation, multiple characters can be output without restarting the character lines. This is because the character line signal is kept determined for the duration of the short pulse, ensuring that the accessed inner and outer bit lines are actively held during the short pulse operation.

[0028] Referring again to Figure 5, the row selection signal (which allows reading memory cells coupled to the inner and outer bit lines corresponding to memory subarrays 410 and 450) can be determined sequentially to read one data word at a time. The read row selection signal (labeled RDYSEL_B<15:0>) represents an exemplary signal generated by control unit 430, which selects the appropriate row associated with memory system 400 for outputting data stored in the memory cell. In this example, unlike other signals, when the read row selection signal (RDYSEL_B signal) is a logic low relative to logic high, it indicates that it has been determined. Once the row for reading the data word is selected using the read row selection signal (RDYSEL_B<15:0> signal), the sense amplifier associated with the selected bit line can be enabled via the signal labeled SAEN in Figure 5. In one example, control unit 430 may determine a sense enable (SAEN) signal in response to the resolution of the corresponding read row selection signal (RDYSEL_B<15:0> signal). As shown in Figure 5, before activating the sense amplifier, the sense amplifier associated with the selected row for reading may be precharged by determining the signal labeled SAPCHG_B, which is represented as a logic low signal relative to a logic high signal. In this example, the sense amplifier (e.g., sense amplifier 280 in Figure 2, which may be part of row circuitry 414 and row circuitry 454 of memory system 400 in Figure 4) may sense the voltage difference between the positive bit line (BL) and the negative bit line (BLB) by amplifying the voltage difference, and then determine whether the stored bit is a logic 1 bit or a logic 0 bit based on the voltage difference.

[0029] Referring again to Figure 5, after outputting data word D0 (represented as output as part of the waveform labeled DOUT), the memory system 400 may output another data word (e.g., data words D1, D2, ..., D15) in each clock cycle (e.g., clock cycles CLK2, CLK3...CLK16). Although Figure 5 illustrates a waveform corresponding to a memory system in which the first data word is output a certain period of time (e.g., two clock cycles) after receiving the address associated with the short-pulse read operation, variations of the memory system may increase or decrease the number of clock cycles required to output the first data word after receiving the address. Furthermore, depending on the size of the memory array, additional or fewer data words may be output in each short-pulse read operation. Additionally, the memory system 400 may operate in a normal mode (e.g., the processing logic issuing a read request does not consider the short-pulse signal (BURST)), where only one or two data words are output for each read request.

[0030] Figure 6 illustrates a flowchart 600 of a method for short-pulse reading using the memory system 400 of Figure 4 according to an example. In one example, the steps described in the flowchart 600 may be performed (directly or indirectly) in response to a determination of a control signal associated with the memory system 400 (e.g., a control signal generated by the control unit 430 of Figure 4). Step 610 may include responding to a short pulse read request while: (1) determining a first word line signal on a first inner word line coupled to each of a first plurality of inner bit lines; (2) determining a second word line signal on a first outer word line coupled to each of a first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line; (3) determining a third word line signal on a second inner word line coupled to each of a second plurality of inner bit lines; and (4) determining a fourth word line signal on a second outer word line coupled to each of a second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a second portion configured to fly above or below the corresponding inner bit line. As explained above, a short pulse request may include determining a signal labeled BURST in Figure 5. In response, multiple word lines (e.g., two word lines associated with memory subarray 410 in Figure 4 and two word lines associated with memory subarray 450 in Figure 4) can be determined based on the control signal of control unit 430.

[0031] Step 620 may include outputting data as part of a short pulse from each of the first, second, third, and fourth memory groups. Further details related to the output step are provided with reference to Figures 4 and 5. For example, Figure 5 illustrates a DOUT waveform indicating multiple data characters output as part of a short pulse.

[0032] In summary, in one instance, this disclosure relates to an operation method of a memory system comprising a first memory subarray and a second memory subarray, wherein the first memory subarray includes a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, and wherein the second memory subarray includes a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line. The method may include responding to a short pulse read request while: (1) determining a first word line signal on a first inner word line coupled to each of a first plurality of inner bit lines; (2) determining a second word line signal on a first outer word line coupled to each of a first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line; (3) determining a third word line signal on a second inner word line coupled to each of a second plurality of inner bit lines; and (4) determining a fourth word line signal on a second outer word line coupled to each of a second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a second portion configured to fly above or below the corresponding inner bit line. The method may further include outputting data from each of a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells as part of a short pulse.

[0033] Each of the first and second groups of memory cells can be organized into a first plurality of rows, and the method may further include selecting one row at a time from the first plurality of rows in response to a determination of a read row selection signal for output data as part of a short pulse. Each of the third and fourth groups of memory cells can be organized into a second plurality of rows, and the method may further include selecting one row at a time from the second plurality of rows in response to a determination of a read row selection signal for output data as part of a short pulse.

[0034] The memory system may be formed as part of an integrated circuit, wherein each of a first plurality of inner bit lines and a second plurality of inner bit lines may be formed in a first metal layer associated with the integrated circuit, and wherein each of a first portion configured to fly above or below a corresponding inner bit line and a second portion configured to fly above or below a corresponding inner bit line may be formed in a second metal layer different from the first metal layer. Each of the first plurality of outer bit lines may include a second portion formed in the first metal layer, and wherein the first portion configured to fly above or below a corresponding inner bit line may be interconnected to the second portion formed in the first metal layer. Each of the second plurality of outer bit lines may include a second portion formed in the first metal layer, and wherein the second portion configured to fly above or below a corresponding inner bit line may be interconnected to the second portion formed in the first metal layer.

[0035] The memory system may include a control unit, and the method may further include the control unit generating a control signal in response to receiving an address associated with a short pulse read request and a short pulse signal. The memory system may further include a first word line decoder associated with a first memory subarray and a second word line decoder associated with a second memory subarray. The method may further include the control unit controlling the timing of the determination of the word line signal via the first and second word line decoders, such that each of the first internal word line, the first external word line, the second internal word line, and the second external word line is activated during the short pulse period.

[0036] In another example, this disclosure relates to a memory system including a memory array comprising a first set of memory cells coupled to a first internal word line and a second set of memory cells coupled to a first external word line. The memory system may further include a control unit configured to generate control signals in response to a short pulse read request, while: (1) determining a first word line signal coupled to each of the plurality of internal word lines on the first internal word line, and (2) determining a second word line signal coupled to each of the plurality of external word lines on the first external word line, wherein each of the plurality of external word lines includes a first portion configured to fly above or below the corresponding internal word line, and outputs data from each of the first set of memory cells and the second set of memory cells as part of a short pulse.

[0037] Each of the first and second sets of memory cells can be organized into a first plurality of rows, wherein the control unit can be further configured to generate a control signal that selects one row from the plurality of rows at a time in response to a determination of a read row selection signal for outputting data as part of a short pulse. The memory system may further include a plurality of sense amplifiers coupled to the plurality of rows, such that each of the plurality of rows has a corresponding sense amplifier.

[0038] The memory system may be formed as part of an integrated circuit, wherein each of a plurality of intrinsic bit lines may be formed in a first metal layer associated with the integrated circuit, and wherein a first portion configured to fly above or below the corresponding intrinsic bit line may be formed in a second metal layer different from the first metal layer. Each of a plurality of extrinsic bit lines may include a second portion formed in the first metal layer, and wherein the first portion configured to fly above or below the corresponding intrinsic bit line may be interconnected to the second portion formed in the first metal layer.

[0039] In another instance, this disclosure relates to a memory system comprising a first memory subarray and a second memory subarray, wherein the first memory subarray comprises a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, wherein the second memory subarray comprises a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line, wherein each of the first group of memory cells and the second group of memory cells is organized in a first plurality of rows, and wherein each of the third group of memory cells and the fourth group of memory cells is organized in a second plurality of rows. The memory system may further include a control unit configured to generate a control signal in response to a first short pulse read request, while: (1) determining a first word line signal coupled to each of the first plurality of inner word lines on a first inner word line; (2) determining a second word line signal coupled to each of the first plurality of outer word lines on a first outer word line, wherein each of the first plurality of outer word lines includes a first portion configured to fly above or below the corresponding inner word line; (3) determining... (4) Determine the third word line signal on the second inner word line coupled to each of the second plurality of inner bit lines, and determine the fourth word line signal on the second outer word line coupled to each of the second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a second portion configured to fly above or below the corresponding inner bit line, and uses a common line circuit system, and outputs data from each of the first group of memory units, the second group of memory units, the third group of memory units and the fourth group of memory units as part of a short pulse. Alternatively, in the second short pulse, the control unit may be configured to generate a control signal in response to the second short pulse read request, while: (1) determining a first word line signal on a first inner word line coupled to each of the first plurality of inner bit lines, and (2) determining a second word line signal on a first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below the corresponding inner bit line, and outputs data from each of the first set of memory units and the second set of memory units.

[0040] The control unit may be further configured to generate a control signal that selects one row at a time from a first plurality of rows in response to a determination of a read row selection signal that is part of the output data in a short pulse. The control unit may be further configured to select one row at a time from a second plurality of rows in response to a determination of a read row selection signal that is part of the output data in a short pulse. The memory system may include a plurality of sense amplifiers coupled to the first plurality of rows and the second plurality of rows, such that each of the first plurality of rows and the second plurality of rows has a corresponding common sense amplifier from the plurality of sense amplifiers.

[0041] The memory system may be formed as part of an integrated circuit, wherein each of a first plurality of inner bit lines and a second plurality of inner bit lines may be formed in a first metal layer associated with the integrated circuit, and wherein each of a first portion configured to fly above or below a corresponding inner bit line and a second portion configured to fly above or below a corresponding inner bit line may be formed in a second metal layer different from the first metal layer. Each of the first plurality of outer bit lines may include a second portion formed in the first metal layer, and wherein the first portion configured to fly above or below a corresponding inner bit line may be interconnected to the second portion formed in the first metal layer. Each of the second plurality of outer bit lines may include a second portion formed in the first metal layer, and wherein the second portion configured to fly above or below a corresponding inner bit line may be interconnected to the second portion formed in the first metal layer.

[0042] It should be understood that the methods, modules, and components described herein are merely illustrative. Alternatively or additionally, the functionality described herein may be performed, at least partially, by one or more hardware logic components. For example, and not limitingly, exemplary types of hardware logic components that may be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip Systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract but still definitive sense, any arrangement of components that implement the same functionality is actually "related" to achieve the desired functionality. Therefore, any two components in this document combined to achieve a particular functionality may be considered "related" to each other to achieve the desired functionality, regardless of the components between the architecture or media. Similarly, any two related components may be considered "operationally connected" or "coupled" to each other to achieve the desired functionality. The fact that a component described herein (which may be any other embodiment of a device, structure, system, or function) is coupled to another component does not imply that such components are separate components. For example, another component B described as being coupled to a component A may be a sub-component of component A, or component A may be a sub-component of component B.

[0043] Functionality related to some of the examples described in this case may also include instructions stored in non-transitory media. As used herein, the term "non-transitory media" means any media that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transitory media include non-volatile and / or volatile media. For example, non-volatile media include hard disks, solid-state drives, magnetic disks or magnetic tapes, optical disks or optical tapes, flash memory, EPROM, NVRAM, PRAM, or other such media or networked versions of such media. For example, volatile media include dynamic memory, such as DRAM, SRAM, cache, or other such media. Non-transitory media differs from transmission media but can be used in conjunction with them. Transmission media are used to transfer data and / or instructions from a machine or to a medium. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media, such as radio waves.

[0044] Furthermore, those skilled in the art will understand that the boundaries between the functionalities of the operations described above are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments.

[0045] While the disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the disclosure set forth in the following claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications shall be within the scope of this disclosure. Any benefit, advantage, or solution described herein with respect to specific examples should be construed as a key, required, or essential feature or element of any or all claims.

[0046] Furthermore, the term "a(a)" or "an(an)" as used herein is defined as one or more. Additionally, introductory terms such as "at least one" or "one or more" used in a claim should not be construed as indicating that any particular claim containing this introductory claim element is limited to an invention containing only that element, even when the same claim includes the introductory terms "one or more" or "at least one" and indefinite articles such as "a(a)" or "an(an)". The same applies to the use of definite articles.

[0047] Unless otherwise indicated, terms such as "first" and "second" are used arbitrarily to distinguish the elements described by these terms. Thus, these terms do not necessarily indicate the temporality or other priority of such elements.

[0048] 100: Memory 110: Memory Subarray 112: Inner dimension line 114: Inner Element Line 116: Inner dimension line 118: Inner dimension line 120: Character Line 122: Exterior element line 124: Exterior element line 126: Exterior element line 128: Exterior element line 130: Character Line 132: Line Multiplexer 134: Line Multiplexer 136: Line Multiplexer 152: Inner Element Line 154: Inner Element Line 156: Inner Element Line 158: Inner dimension line 160: Character Line 162: Exterior element line 164: Exterior element line 166: Exterior element line 168: Exterior element line 170: Character Line 172: Line Multiplexer 174: Line Multiplexer 176: Line Multiplexer 182: Linear Circuit System 184: Linear Circuit System 186: Linear Circuit System 200: Part 212: Inner Element Line 214: Inner Element Line 216: Exterior element line 218: Exterior element line 222: Memory Unit 224: Memory unit 226: Memory unit 232: Memory unit 234: Memory Unit 236: Memory unit 242: Character Line 244: Character Line 252: Part 254: Interconnection 256: Part 262: Part 264: Interconnection 266: Part 270: Line Multiplexer 280: Sensing Amplifier 290: Output Data Latch 300: Sectional view 310:Substrate 320: Cross-sectional view 330: Sectional view 340: Cross-sectional view 350: Sectional view 400: Memory System 410: Memory Subarray 412: Character Line Decoder 414: Linear Circuit System 430: Control Unit 440: I / O Circuit System 450: Memory Subarray 452: Character Line Decoder 454: Linear Circuit System 500: Waveform 600: Flowchart 610: Steps 620: Steps BL: Exogenous Line BLB: External Line CLK2: Clock cycle CLK3: Clock cycle CLK4: Clock cycle CLK16: Clock cycle D0: Data Characters D1: Data Characters D2: Data Characters D15: Data Characters DOUT: Waveform WL: Character Line WL1: Character Line WL2: Character Line

[0049] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of operating a memory system, the memory system comprising a first memory subarray and a second memory subarray, wherein the first memory subarray includes a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, wherein each of the first group of memory cells and the second group of memory cells is organized into a first plurality of rows, wherein the second memory subarray includes a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line, and wherein each of the third group of memory cells and the fourth group of memory cells is organized into a second plurality of rows, the method comprising the following steps: In response to a short pulse read request, simultaneously: (1) determining a first word line signal on the first inner word line coupled to each of the first plurality of inner bit lines; (2) determining a second word line signal on the first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below a corresponding inner bit line; (3) determining a second word line signal on the first outer word line coupled to each of the second plurality of inner bit lines. (3) a third word line signal on a second inner word line, and (4) determining a fourth word line signal on the second outer word line coupled to each of the second plurality of outer word lines, wherein each of the second plurality of outer word lines includes a second portion configured to fly above or below a corresponding inner word line; and as part of a short pulse, outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells and the fourth set of memory cells, wherein the method further includes the steps of: (1) selecting a row from the first plurality of rows one at a time in response to a determination of a read row selection signal for outputting the data as part of the short pulse; and (2) selecting a row from the second plurality of rows one at a time in response to a determination of a read row selection signal for outputting the data as part of the short pulse.

2. The method as claimed in claim 1, wherein the memory system is formed as part of an integrated circuit, wherein each of the first plurality of internal bit lines and the second plurality of internal bit lines is formed in a first metal layer associated with the integrated circuit, and wherein each of the first portion configured to fly above or below a corresponding internal bit line and the second portion configured to fly above or below a corresponding internal bit line is formed in a second metal layer different from the first metal layer.

3. The method as described in claim 2, wherein each of the first plurality of outer bit lines includes a second portion formed in the first metal layer, and wherein the first portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect.

4. The method as described in claim 3, wherein each of the second plurality of outer bit lines includes a second portion formed in the first metal layer, and wherein the second portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect.

5. The method as described in claim 4, wherein the memory system includes a control unit, the method further comprising the step of: the control unit generating a control signal in response to receiving an address associated with a short pulse read request and a short pulse signal.

6. The method as claimed in claim 5, wherein the memory system includes a first word line decoder associated with the first memory subarray and a second word line decoder associated with the second memory subarray, the method further comprising the step of: the control unit controlling a timing of a determination of a word line signal by means of the first word line decoder and the second word line decoder, such that each of the first inner word line, the first outer word line, the second inner word line and the second outer word line is activated in the short pulse.

7. The method of claim 1, wherein the memory system further includes a plurality of sense amplifiers coupled to the first plurality of rows and the second plurality of rows, such that each of the first plurality of rows and the second plurality of rows has a corresponding shared sense amplifier among the plurality of sense amplifiers.

8. The method as described in claim 1, further comprising the step of: determining a bit line precharge signal for bit lines in both the first memory subarray and the second memory subarray before determining the first word line signal, the second word line signal, the third word line signal and the fourth word line signal.

9. A memory system comprising: a first memory array including a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line; a second memory array including a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line; and a control unit configured to generate control signals for: In response to a short pulse read request, simultaneously: (1) determining a first word line signal on the first inner word line coupled to each of the first plurality of inner bit lines; (2) determining a second word line signal on the first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below a corresponding inner bit line; (3) determining a third word line signal on the second inner word line coupled to each of the second plurality of inner bit lines; and (4) determining a fourth word line signal on the second outer word line coupled to each of the second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a first portion configured to fly above or below a corresponding inner bit line; A second portion configured to fly above or below a corresponding memory line, and as part of a short pulse, outputs data from each of the first, second, third, and fourth memory units, wherein the memory system is formed as part of an integrated circuit, wherein each of the first plurality of memory lines and the second plurality of memory lines is formed in a first metal layer associated with the integrated circuit, and wherein each of the first portion configured to fly above or below a corresponding memory line and each of the second portion configured to fly above or below a corresponding memory line is formed in a second metal layer different from the first metal layer. Each of the plurality of first outer bit lines includes a second portion formed in the first metal layer, wherein the first portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect, and wherein each of the plurality of second outer bit lines includes a second portion formed in the first metal layer, wherein the second portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect.

10. The memory system of claim 9, wherein each of the first group of memory cells, the second group of memory cells, the third group of memory cells, and the fourth group of memory cells is organized into a plurality of rows, and wherein the control unit is further configured to generate a control signal for selecting one row from the plurality of rows at a time in response to a determination of a read row selection signal for outputting the data as part of the short pulse.

11. The memory system as claimed in claim 10, further comprising a plurality of sense amplifiers coupled to the plurality of rows such that each of the plurality of rows has a corresponding sense amplifier.

12. The memory system as claimed in claim 9, wherein the control unit is further configured to: determine a bit line precharge signal for bit lines in both the first memory subarray and the second memory subarray before determining the first word line signal, the second word line signal, the third word line signal and the fourth word line signal.

13. A memory system comprising: a first memory subarray and a second memory subarray, wherein the first memory subarray includes a first group of memory cells coupled to a first internal word line and a second group of memory cells coupled to a first external word line, wherein the second memory subarray includes a third group of memory cells coupled to a second internal word line and a fourth group of memory cells coupled to a second external word line, wherein each of the first group of memory cells and the second group of memory cells is organized in a first plurality of rows, and each of the third group of memory cells and the fourth group of memory cells is organized in a second plurality of rows; and a control unit configured to generate control signals for: In a first short pulse, in response to a short pulse read request, simultaneously: (1) determining a first word line signal on the first inner word line coupled to each of the first plurality of inner bit lines; (2) determining a second word line signal on the first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first portion configured to fly above or below a corresponding inner bit line; (3) determining a third word line signal on the second inner word line coupled to each of the second plurality of inner bit lines; and (4) determining a fourth word line signal on the second outer word line coupled to each of the second plurality of outer bit lines, wherein each of the second plurality of outer bit lines includes a fourth word line signal configured to fly above or below a corresponding inner bit line. The second part of the flight, and using a common line circuit system, and as part of a short pulse, outputting data from each of the first group of memory cells, the second group of memory cells, the third group of memory cells and the fourth group of memory cells, or responding to a second short pulse read request in a second short pulse, while: (1) determining a first word line signal on the first inner word line coupled to each of the first plurality of inner bit lines, (2) determining a second word line signal on the first outer word line coupled to each of the first plurality of outer bit lines, wherein each of the first plurality of outer bit lines includes a first part configured to fly above or below a corresponding inner bit line, and outputting data from each of the first group of memory cells and the second group of memory cells.

14. The memory system as claimed in claim 13, wherein the control unit is further configured to generate a control signal that selects one row at a time from the first plurality of rows in response to a determination of a read row selection signal for outputting the data as part of the short pulse.

15. The memory system as claimed in claim 14, wherein the control unit is further configured to generate a control signal that responds to a determination of a read row selection signal for outputting the data as part of the short pulse, selecting one row from the second plurality of rows at a time.

16. The memory system of claim 15, further comprising a plurality of sense amplifiers coupled to the first plurality of rows and the second plurality of rows such that each of the first plurality of rows and the second plurality of rows has a corresponding common sense amplifier from the plurality of sense amplifiers.

17. The memory system as claimed in claim 13, wherein the memory system is formed as part of an integrated circuit, wherein each of the first plurality of internal bit lines and the second plurality of internal bit lines is formed in a first metal layer associated with the integrated circuit, and wherein each of the first portion configured to fly above or below a corresponding internal bit line and the second portion configured to fly above or below a corresponding internal bit line is formed in a second metal layer different from the first metal layer.

18. The memory system of claim 17, wherein each of the first plurality of outer bit lines includes a second portion formed in the first metal layer, and wherein the first portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect.

19. The memory system of claim 18, wherein each of the second plurality of outer bit lines includes a second portion formed in the first metal layer, and wherein the second portion configured to fly above or below the corresponding inner bit line is coupled to the second portion formed in the first metal layer via an interconnect.

20. The memory system as claimed in claim 13, wherein the control unit is further configured to: (1) in the first short pulse, before determining the first word line signal, the second word line signal, the third word line signal and the fourth word line signal, determine a bit line precharge signal for bit lines in both the first memory subarray and the second memory subarray; and (2) in the second short pulse, before determining the first word line signal and the second word line signal, determine a bit line precharge signal for bit lines in the first memory subarray.

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