Sacrificial capping layer for contact etch

Abstract

One method includes providing a substrate having a source / drain region and an etch stop layer on the source / drain region. An etch gas is used to perform a plasma etching process, the etch gas system removing the etch stop layer and forming a sacrificial oxide capping layer on the source / drain region. The sacrificial oxide capping layer is then removed from the source / drain region.

Description

Technical Field

[0001] This invention relates generally to semiconductor device manufacturing, and more particularly to a method for forming a sacrificial cap layer for contact window etching. [Cross-reference to related applications]

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 195,436, filed June 1, 2021, and U.S. Patent Application No. 17 / 721,620, filed April 15, 2022, the full contents of which are incorporated herein by reference. Prior Technology

[0003] Advances in semiconductor technology rely on continuous improvements in manufacturing processes. Innovations in semiconductor technology have led to the introduction of new types of structures (e.g., FinFET devices) and stacked structures (e.g., 3D NAND devices). However, these new structures require new manufacturing methods to overcome, or else they diminish the manufacturing challenges. For example, dry etching processes (e.g., reactive ion etching (RIE)) can be used to open contact windows in traditional mid-stage (MOL) process flows. Dry etching can often be quite aggressive on certain layers in a semiconductor process. Typically, dry etching involves a plasma source that generates an ion sea, which is accelerated to bombard sensitive device layers with ions. As a result, plasma etching can damage the underlying material, potentially leading to uncontrolled variations in device electrical properties and yield losses. Summary of the Invention

[0004] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices.

[0005] (1) A method is provided comprising providing a substrate including a source / drain region and an etch stop layer thereon. An etch gas is used to perform a plasma etch process, the etch gas system removing the etch stop layer and forming a sacrificial oxide capping layer on the source / drain region. The sacrificial oxide capping layer is then removed from the source / drain region.

[0006] The state (2) includes the method of the state (1), wherein the substrate includes a metal gate stack separated from the source / drain region by spacers, the etch stop layer having a first portion and a second portion of a conformal layer, the first portion covering the source / drain region, and the second portion covering the spacers and the metal gate stack.

[0007] State (3) includes a method of state (2), wherein performing plasma etching includes: completely removing the first portion of the etch stop layer to expose the source / drain region before completely removing the second portion of the etch stop layer; forming the sacrificial oxide capping layer on the exposed source / drain region while completely removing the second portion of the etch stop layer.

[0008] The state (4) includes the method of the state (1), wherein the source / drain region contains Si, Ge or both Si and Ge.

[0009] The state (5) includes the method of the state (1), wherein the plasma etching process includes: forming a sacrificial oxide capping layer comprising SiO2, GeO2 or SiGeOx.

[0010] The state (6) includes the method of the state (1), wherein the etch stop layer includes a nitride layer.

[0011] The state (7) includes the method of the state (1), wherein the etch stop layer comprises SiN.

[0012] The state (8) includes the method of the state (1), wherein the plasma etching process includes: using an etching gas, the etching gas including a fluorocarbon gas and an oxygen-containing gas.

[0013] The state sample (9) includes the method of the state sample (8), wherein the fluorocarbon gas includes fluorocarbon gas, hydrofluorocarbon gas or a combination thereof.

[0014] The state sample (10) includes the method of the state sample (8), wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2 or combinations thereof.

[0015] The state (11) includes a method of the state (1), wherein removing the sacrificial oxide cap layer includes performing a wet etching process on the substrate.

[0016] The state (12) includes a method of the state (1), wherein removing the sacrificial oxide cap layer includes performing a dry etching process on the substrate.

[0017] Another embodiment (13) provides a method comprising providing a substrate including a source / drain region and a SiN etch stop layer on the source / drain region, the source / drain region comprising Si, Ge, or both Si and Ge. An etching gas is used to perform a plasma etching process, the etching gas including a fluorocarbon gas and an oxygen-containing gas, the etching gas system removing the SiN etch stop layer and forming a sacrificial oxide capping layer on the source / drain region. A wet or dry etching process is used to remove the sacrificial oxide capping layer from the source / drain region.

[0018] The state (14) includes a method of the state (13), wherein the substrate includes a metal gate stack separated from the source / drain region by spacers, the SiN etch stop layer having a first portion and a second portion of conformal layer, the first portion covering the source / drain region, and the second portion covering the spacers and the metal gate stack.

[0019] State (15) includes a method of state (14), wherein performing plasma etching includes: completely removing the first portion of the etch stop layer to expose the source / drain region before completely removing the second portion of the etch stop layer; forming the sacrificial oxide capping layer on the exposed source / drain region while completely removing the second portion of the etch stop layer.

[0020] The state (16) includes the method of the state (13), wherein the sacrificial oxide capping layer comprises SiO2, GeO2 or SiGeOx.

[0021] The state sample (17) includes the method of the state sample (13), wherein the fluorocarbon gas includes fluorocarbon gas, hydrofluorocarbon gas or a combination thereof.

[0022] The state sample (18) includes the state sample (13) in a method, wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2 or a combination thereof.

[0023] Another embodiment (19) provides a method comprising providing a substrate including a source / drain region and a SiN etch stop layer on the source / drain region, the source / drain region comprising Si, Ge, or both Si and Ge. Plasma etching is performed using an etching gas system comprising CH3F and O2 to remove the SiN etch stop layer and form a sacrificial oxide capping layer on the source / drain region, the sacrificial oxide capping layer comprising SiO2, GeO2, or SiGeOx. A wet or dry etching process is used to remove the sacrificial oxide capping layer from the source / drain region.

[0024] State (20) includes a method of state (19), wherein the substrate includes a metal gate stack separated from the source / drain region by spacers, the SiN etch stop layer having a first portion and a second portion of conformal layer, the first portion covering the source / drain region, and the second portion covering the spacers and the metal gate stack. Performing a plasma etching process includes: completely removing the first portion of the etch stop layer to expose the source / drain region before completely removing the second portion of the etch stop layer; forming a sacrificial oxide capping layer on the exposed source / drain region while completely removing the second portion of the etch stop layer.

[0025] It should be noted that this summary does not explicitly describe every embodiment and / or incremental novel aspects of the present disclosure or the claimed invention. Rather, this summary provides only a preliminary discussion of different embodiments and corresponding novel aspects relative to the prior art. For additional details and / or possible viewpoints regarding the present disclosure and embodiments, please refer to the following further discussion of the implementation methods of the disclosure and the corresponding drawings. Simple Explanation of the Diagram

[0026] The nature of this disclosure can be best understood by referring to the following embodiments and the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In practice, the dimensions of the various features may be enlarged or reduced for clarity of discussion.

[0027] According to an exemplary embodiment of this disclosure, FIG1A shows a partial cross-sectional fin view of a semiconductor device during manufacturing along the direction of the fin; FIG1B shows a cross-sectional gate view of the semiconductor device along a direction orthogonal to the direction of the fin; FIG1C shows a top view of a semiconductor according to an exemplary embodiment of this disclosure.

[0028] According to an exemplary embodiment of this disclosure, Figures 2A-2B respectively illustrate cross-sectional fin and gate views of a semiconductor device during subsequent manufacturing stages;

[0029] According to an exemplary embodiment of this disclosure, Figures 3A-3B respectively illustrate cross-sectional fin views and gate views of a semiconductor device during subsequent manufacturing stages;

[0030] According to an exemplary embodiment of this disclosure, Figures 4A-4B respectively illustrate cross-sectional fin views and gate views of a semiconductor device during subsequent manufacturing stages;

[0031] According to an exemplary embodiment of this disclosure, Figures 5A-5B respectively illustrate cross-sectional fin views and gate views of a semiconductor device during subsequent manufacturing stages;

[0032] According to an exemplary embodiment of this disclosure, Figures 6A-6B respectively illustrate cross-sectional fin and gate views of a semiconductor device during subsequent manufacturing stages;

[0033] According to an exemplary embodiment of this disclosure, Figures 7A-7B respectively illustrate cross-sectional fin views and gate views of a semiconductor device during subsequent manufacturing stages; and

[0034] Figures 8A-8B show a comparison of experimental results of substrate processing according to embodiments of the present invention with conventional methods. Implementation

[0035] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not limitations. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features so that the first and second features may not be in direct contact. Furthermore, in the various examples of this disclosure, element symbols and / or letters may be repeated. This repetition is for simplification and clarity and does not in itself limit the relationship between the various embodiments and / or configurations discussed. Moreover, for ease of explanation, spatial relative terms such as "top," "bottom," "below," "under," "lower," "above," "upper," etc., may be used herein to describe the relationship between one element or feature shown in the figures and one or more other elements or features. The purpose of these spatial relative terms is to refer to the different orientations of components in addition to those shown in the diagrams during use or operation. Devices may be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative terms used herein can be interpreted similarly.

[0036] As described in the prior art section above, damage to the epitaxial source / drain materials caused by contact window opening etching is one of the MOL challenges in manufacturing FinFETs for logic ICs. This type of damage can lead to uncontrolled variations in the electrical performance of the device. Embodiments of the present invention propose a novel approach to protect the epitaxial source / drain materials from damage by forming a thin sacrificial cap layer in situ on the epitaxial source / drain materials during contact window opening etching. Subsequently, the sacrificial cap layer can be removed using a gentle process that does not damage the epitaxial source / drain materials and provides high etch selectivity between the sacrificial cap layer and the epitaxial source / drain materials.

[0037] Embodiments of this application disclose a method for preventing damage to semiconductor regions during plasma etching. The proposed integration scheme uses a sacrificial cap layer formed directly on top of the semiconductor region to be protected. The sacrificial cap layer is designed to protect the semiconductor region during the plasma etching process, which would otherwise damage the semiconductor region. In subsequent processing, the sacrificial cap layer can be removed using a gentle dry or wet cleaning process.

[0038] The embodiments of this application can be applied to various types of devices, such as finned transistors and stacked memory devices. Specific embodiments of the above processing will be described below.

[0039] According to an embodiment of the present invention, FIG1A shows a partial cross-sectional view of a semiconductor device during manufacturing along the direction of the fins, FIG1B shows a cross-sectional view of the semiconductor device along a direction orthogonal to the direction of the fins, and FIG1C shows a top view showing the cutting lines 1A-1A shown in FIG1A and 1B-1B shown in FIG1B. FIG1A is a partial cross-sectional view and does not show the fins and substrate below.

[0040] As shown in Figures 1A-1C, at this stage of processing, the semiconductor device 100 has already passed most of the front-end process (FEOL) manufacturing. For example, as shown in Figure 1B, a transistor structure with multiple fins 109 is formed on the substrate 111.

[0041] In various embodiments, substrate 111 may include silicon, silicon germanium, silicon carbide, and compound semiconductors, such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, etc. Substrate 111 may include a semiconductor wafer, which may include a semiconductor epitaxial layer, including a heteroepitaxy layer. For example, in one or more embodiments, one or more heteroepitaxy layers including a compound semiconductor may be formed over the semiconductor substrate. In various embodiments, a portion or all of substrate 111 may be amorphous, polycrystalline, or monocrystalline. In various embodiments, substrate 111 may be doped, undoped, or contain both doped and undoped regions.

[0042] The plurality of fins 109 can be formed by epitaxial growth from the substrate 111 or by leaving the plurality of fins 109 using an etch-back process. The plurality of fins 109 can be isolated from each other by a shallow isolation region 112. Therefore, the shallow isolation region 112 and the plurality of fins 109 can form an alternating pattern.

[0043] In one embodiment, the shallow isolation region 112 may be formed by depositing an oxide filler material after patterning the plurality of fins 109, and then planarizing it, for example, using a chemical mechanical planarization process. After planarization, the shallow isolation region 112 may be recessed, thereby raising the plurality of fins 109.

[0044] A plurality of virtual gates 102 are formed above the substrate 111 and the plurality of fins 109. In one embodiment, the plurality of virtual gates 102 may be formed by patterning an amorphous silicon or polycrystalline silicon layer deposited above the plurality of fins 109.

[0045] Next, a plurality of spacers 101 are formed on the sidewalls of the plurality of virtual gates 102. The plurality of spacers 101 can be formed by depositing an insulating layer followed by an anisotropic etching process. For example, reactive ion etching (RIE) can be used to form the spacers 101. The material of the insulating layer is selected to be selectively not etched during subsequent processing, during the removal of the plurality of virtual gates 102, for example, not etched by chemicals (e.g., TMAH or NH4OH). In one example, the spacers 101 may comprise a low-k material.

[0046] Next, epitaxial regions 103 are grown above portions of the plurality of fins 109 located between the plurality of virtual gates 102 to form raised source / drain regions. As shown, due to the growth pattern of the corresponding epitaxial material, the upper surface of the raised source / drain regions can form a faceted surface. In some embodiments, the source / drain regions comprise Si, Ge, or both Si and Ge.

[0047] In one or more embodiments, the epitaxial region 103 may be formed in a single epitaxial growth process. In other embodiments, the growth of the epitaxial region 103 may consist of a multi-stage process. For example, it may begin by growing an initial epitaxial layer with a first dopant to a predetermined thickness on a plurality of fins 109, followed by the growth of a second layer with a second dopant. For example, the second dopant may be higher than the first dopant. Similarly, the different layers may have different compositions, such as germanium or other compounds. The epitaxial growth process may use any type of epitaxial process, including molecular beam epitaxy (MBE) or various types of chemical vapor deposition (CVD).

[0048] In one or more embodiments, epitaxial regions 103 may be grown to introduce strain into the plurality of fins 109, for example, due to lattice mismatch.

[0049] In one or more embodiments, the source / drain (S / D) region may be formed by doping the fin and epitaxial region 103, for example by ion implantation / annealing.

[0050] Figures 2A-2B show cross-sectional views of the semiconductor device 100 after an etch stop layer (ESL) 105 has been formed over the semiconductor device 100 during subsequent manufacturing stages. Figure 2A shows a cut line similar to that in Figure 1A, and Figure 2B shows a cut line similar to that in Figure 1B.

[0051] ESL 105 can be conformally deposited across the entire wafer surface. In various embodiments, ESL 105 comprises silicon nitride (SiN) or silicon oxide nitride (SiON). In various embodiments, ESL 105 can have a thickness ranging from 0.5 nm to about 10 nm. In one embodiment, ESL 105 can have a thickness ranging from 2 nm to about 5 nm.

[0052] According to an embodiment of the present invention, Figures 3A-3B illustrate partial cross-sectional views of a semiconductor device 100 during manufacturing, after the deposition of oxide 106. Figure 3A shows a cut line similar to that in Figure 1A, and Figure 3B shows a cut line similar to that in Figure 1B.

[0053] Referring to Figures 3A and 3B, oxide 106 is filled between the complex virtual gates 102. Oxide 106 is overfilled on the top surface of ESL 105 and above the complex virtual gates 102.

[0054] In various embodiments of semiconductor device 100, oxide 106 may be a flowable oxide, including spin-coated glass. In one example, a layer of one of borosilicate glass (BPSG), phosphosilicone glass (PSG), borosilicate glass (BSG), arsenic silicate glass (ArSG), or other types of glass may be deposited and heated for reflow. In one or more embodiments, oxide 106 may also include oxides of, for example, tetraethoxysilane (TEOS), fluorinated TEOS (FTEOS), organosilicon glass (OSG), fluorinated silicate glass (FSG), or spin-coated glass.

[0055] According to an embodiment of the present invention, Figures 4A-4B illustrate cross-sectional views of a semiconductor device 100 during manufacturing, after the formation of a replacement metal gate (RMG). Figure 4A shows a cut line similar to that in Figure 1A, and Figure 4B shows a cut line similar to that in Figure 1B.

[0056] As shown in Figures 4A and 4B, oxide 106 is planarized to expose the underlying ESL 105. Anisotropic etching can be used to remove ESL 105 to expose the plurality of dummy gates 102. Then, for example, wet etching or an alternative plasma etching process is used to remove the plurality of dummy gates 102. During the removal of the plurality of dummy gates 102, spacers 101 maintain the shape of the gate stack. During the etching process, oxide 106 protects the area beneath epitaxial region 103.

[0057] After removing the plurality of dummy gates 102, the inner sidewalls of the plurality of spacers 101 are exposed, leaving grooves. The grooves are filled with replacement gate material 107. After the replacement gate material 107 is in place, a contact cap 108 is formed. The contact cap 108 can be formed using a self-alignment process so that it can be selectively formed only over the replacement gate material 107.

[0058] The replacement gate material 107, together with the contact cap 108, forms a replacement metal gate (RMG) stack 102'. The RMG stack 102' helps to set the power function of the gate and form the final gate electrode of the semiconductor device 100.

[0059] According to an embodiment of the present invention, Figures 5A-5B illustrate partial cross-sectional views of the semiconductor device 100 after etching of oxide 106 during the next manufacturing stage. Figure 5A illustrates a cut line similar to that in Figure 1A, and Figure 5B illustrates a cut line similar to that in Figure 1B.

[0060] As shown in Figure 5A, etching of oxide 106 leaves empty, unfilled trenches or recessed features in place. In various embodiments, the oxide etching process can be a wet etching process, or a dry etching process such as reactive ion etching (RIE), or any process currently known in the semiconductor manufacturing industry. Etching of oxide 106 exposes ESL 105 retained between the plurality of spacers 101 arranged along the replacement gate material 107 and contact cap 108.

[0061] According to an embodiment of the present invention, Figures 6A-6B illustrate partial cross-sectional views of the semiconductor device 100 after ESL etching during the next manufacturing stage. Figure 6A shows a cut line similar to that in Figure 1A, and Figure 6B shows a cut line similar to that in Figure 1B.

[0062] The ESL etching process includes performing a plasma etching process using an etching gas that removes ESL 105 and forms a sacrificial oxide capping layer 113 on the source / drain regions. During the plasma etching process, once the ESL 105 is removed and the epitaxial region 103 is exposed, oxygen present in the etching gas reacts with the epitaxial region 103 to form a thin sacrificial capping layer 113 on the epitaxial region 103. The presence of the thin sacrificial capping layer 113 protects the epitaxial region 103 from plasma damage caused by other reactive gases in the etching gas. The ESL etching process is performed until the ESL 105 is completely removed from the semiconductor device 100. This requires the protection of the epitaxial region 103 by the sacrificial oxide capping layer 113, as the ESL etching process can be performed to remove the remaining ESL 105 from areas other than the epitaxial region 103. The sacrificial oxide capping layer 113 is resistant to other reactive gases in the etching gas. The protection of the epitaxial region 103 is to prevent or reduce material loss, chemical doping, and damage to the main crystal structure of the epitaxial region 103. In some embodiments, the sacrificial oxide capping layer 113 comprises SiO2, GeO2, or SiGeOx.

[0063] In various embodiments, the sacrificial cap layer 113 may have a thickness ranging from 0.5 nm to about 5 nm on top of the epitaxial region 103. In one embodiment, the sacrificial cap layer 113 may have a thickness ranging from 1 nm to about 3 nm, and may be about 2 nm.

[0064] In various embodiments, the etching gas in the ESL etching process may comprise a fluorocarbon gas and an oxygen-containing gas. The etching gas may further include argon (Ar) as a diluent gas. The fluorocarbon gas may include fluorocarbon gases, hydrofluorocarbon gases, or combinations thereof. The chemical formula of the fluorocarbon gas is CxXy, where C and X represent carbon and halogen, respectively, and x and y are integers. The chemical formula of the hydrofluorocarbon gas is CxXyHz, where C, X, and H represent carbon, halogen, and hydrogen, respectively, and x, y, and z are integers. The oxygen-containing gas may, for example, include O2, O3, CO, CO2, SO2, or combinations thereof.

[0065] In one example, the etching gas includes CH3F, O2, and Ar. An exemplary gas flow includes approximately 10-100 sccm of CH3F, approximately 10-100 sccm of O2, and approximately 50-200 sccm of Ar. In one example, the plasma etching process can be performed in a processing chamber comprising an upper electrode and a lower electrode, wherein the lower electrode supports the substrate to be processed. Exemplary processing conditions may include a substrate temperature of approximately 20-100 °C, a gas pressure between approximately 5-100 mTorr, an RF power of approximately 50-500 W to the upper electrode, and an RF power of approximately 50-500 W to the lower electrode.

[0066] According to an embodiment of the present invention, Figures 7A-7B illustrate partial cross-sectional views of a semiconductor device 100 after the removal of the sacrificial oxide capping layer from the source / drain regions during the next manufacturing stage. Figure 7A shows a cut line similar to that in Figure 1A, and Figure 7B shows a cut line similar to that in Figure 1B.

[0067] Removal of the sacrificial cap layer 113 can be performed by an etching process, such as dry etching or wet etching, which is effective and does not damage the epitaxial region 103. In one example, wet etching may include exposing the substrate to dilute hydrofluoric acid (DHF). In one example, dry etching may include a chemical oxide removal process (COR), which includes exposing the substrate to HF gas and NH3 gas, followed by heat treatment to desorb reaction byproducts from the substrate.

[0068] According to an embodiment of the present invention, Figures 8A-8B show the experimental results of substrate processing. Figure 8A shows a transmission electron microscope (TEM) image after removing SiN ESL from a SiGe substrate using an etching gas containing CH3F, O2, and Ar that is excited by plasma. After removing SiN ESL, a sacrificial capping layer containing SiGeOx and approximately 2 nm thick is formed on the SiGe substrate. The TEM in Figure 8A clearly shows that the crystal structure of the SiGe substrate is not damaged by the plasma etching process. In contrast, Figure 8B shows a TEM image after removing SiN ESL from a SiGe substrate using an etching gas containing CH3F, H2, and Ar that is excited by plasma. Because there is no oxygen-containing gas in the etching gas, no sacrificial capping layer is formed on the SiGe substrate after removing SiN ESL. The TEM in Figure 8B clearly shows that the crystal structure of the SiGe substrate is severely damaged by the plasma etching process. Chemical analysis further shows that a large amount of hydrogen has been incorporated into the SiGe substrate. Therefore, the results in Figures 8A-8B clearly show how the sacrificial cap layer protects the crystal structure of the SiGe substrate in the semiconductor device.

[0069] Specific details, such as the particular geometry of the processing system and the various components used therein, as well as the description of the processing, have been presented in the foregoing description. However, it should be understood that the techniques described herein can be implemented in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limiting purposes. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific numbers, materials, and configurations have been presented to provide a complete understanding. Nevertheless, embodiments may be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any redundant descriptions may be omitted.

[0070] Various techniques have been described as multiple separate operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations are necessarily sequentially related. In fact, these operations do not need to be performed in the order stated. The operations may be performed in a different order than in the embodiments described. In additional embodiments, various additional operations may be performed, and / or the operations may be omitted.

[0071] As used herein, "substrate" or "wafer" generally refers to an object processed according to the present invention. A substrate may contain any material portion or structure of an element, particularly a semiconductor or other electronic element, and may be, for example, a substrate structure, such as a semiconductor wafer, a photomask, or a layer, such as a thin film, on or covering a substrate structure. Therefore, a substrate is not limited to any particular substrate structure, underlayer or overlayer, patterned or unpatterned, but is contemplated to include any such layer or substrate structure, and any combination of layers and / or substrate structures. The description may refer to specific types of substrates, but this is for illustrative purposes only.

[0072] Those skilled in the art will also understand that many variations can be made to the operation of the above-described technique while still achieving the same objective of the present invention. Such variations should be covered by the scope of this disclosure. Therefore, the above description of the embodiments of the present invention is not restrictive. Any limitations of the embodiments of the present invention are presented in the following claims.

[0073] 100: Semiconductor components 101: Spacer 102: Virtual Gate 102': Metal gate stack 103: Piezoresistive Zone 105: Etching Stop Layer 106: Oxides 107: Replacement of gate material 108: Contact cap 109: Fins 111:Substrate 112: Shallow isolation zone 113: Sacrificial oxide capping layer

Claims

1. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate including an epitaxial source / drain region and an etch stop layer on the epitaxial source / drain region; an etch gas is used to perform a plasma etching process, the etch gas system removing the etch stop layer and forming a sacrificial oxide capping layer on the epitaxial source / drain region; and an etching process is used to remove the sacrificial oxide capping layer from the epitaxial source / drain region, the etching process not damaging the epitaxial source / drain region below the sacrificial oxide capping layer.

2. As in request item 1, where: The substrate includes a metal gate stack separated from the epitaxial source / drain region by a spacer, and the etch stop layer has a first portion and a second portion as a conformal layer, the first portion covering the epitaxial source / drain region, and the second portion covering the spacer and the metal gate stack.

3. As in request item 2, wherein: The plasma etching process includes: completely removing the first portion of the etch stop layer to expose the epitaxial source / drain region before completely removing the second portion of the etch stop layer, and forming the sacrificial oxide capping layer on the exposed epitaxial source / drain region while completely removing the second portion of the etch stop layer.

4. The method of claim 1, wherein the epitaxial source / drain region comprises Si, Ge, or both Si and Ge.

5. The method of claim 1, wherein performing a plasma etching process includes: A sacrificial oxide capping layer containing one of SiO2, GeO2, or SiGeOx is formed.

6. The method of claim 1, wherein the etch stop layer comprises a nitride layer.

7. The method of claim 1, wherein the etch stop layer comprises SiN.

8. The method of claim 1, wherein performing a plasma etching process includes: An etching gas is used, which includes a fluorocarbon compound gas and an oxygen-containing gas.

9. The method of claim 8, wherein the fluorocarbon gas includes a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

10. The method of claim 8, wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2 or combinations thereof.

11. The method of claim 1, wherein removing the sacrificial oxide capping layer comprises: A wet etching process is performed on the substrate.

12. The method of claim 1, wherein removing the sacrificial oxide capping layer comprises: A dry etching process is performed on the substrate.

13. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate including an epitaxial source / drain region and a SiN etch stop layer on the epitaxial source / drain region, the epitaxial source / drain region comprising Si, Ge, or both Si and Ge; an etching gas is used to perform a plasma etching process, the etching gas including a fluorocarbon gas and an oxygen-containing gas, the etching gas system removing the SiN etch stop layer and forming a sacrificial oxide capping layer on the epitaxial source / drain region; and a wet or dry etching process is used to remove the sacrificial oxide capping layer from the epitaxial source / drain region, the wet or dry etching process not damaging the epitaxial source / drain region below the sacrificial oxide capping layer.

14. As in request item 13, wherein: The substrate includes a metal gate stack separated from the epitaxial source / drain region by a spacer, and the SiN etch stop layer having a first portion and a second portion as a conformal layer, the first portion covering the epitaxial source / drain region, and the second portion covering the spacer and the metal gate stack.

15. As in request item 14, wherein: The plasma etching process includes: completely removing the first portion of the etch stop layer to expose the epitaxial source / drain region before completely removing the second portion of the etch stop layer, and forming the sacrificial oxide capping layer on the exposed epitaxial source / drain region while completely removing the second portion of the etch stop layer.

16. The method of claim 13, wherein the sacrificial oxide capping layer comprises SiO2, GeO2 or SiGeOx.

17. The method of claim 13, wherein the fluorocarbon gas comprises a fluorocarbon gas, a hydrofluorocarbon gas, or a combination thereof.

18. The method of claim 13, wherein the oxygen-containing gas includes O2, O3, CO, CO2, SO2 or combinations thereof.

19. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate including an epitaxial source / drain region and a SiN etch stop layer on the epitaxial source / drain region, the epitaxial source / drain region comprising Si, Ge, or both Si and Ge; an etching gas is used to perform a plasma etching process, the etching gas including CH3F gas and O2 gas, the etching gas system removing the SiN etch stop layer and forming a sacrificial oxide capping layer on the epitaxial source / drain region, the sacrificial oxide capping layer comprising SiO2, GeO2, or SiGeOx; and a wet or dry etching process is used to remove the sacrificial oxide capping layer from the epitaxial source / drain region, the wet or dry etching process not damaging the epitaxial source / drain region below the sacrificial oxide capping layer.

20. As in request item 19, wherein: The substrate includes a metal gate stack separated from the epitaxial source / drain region by a spacer, and the SiN etch stop layer has a first portion and a second portion as a conformal layer, the first portion covering the epitaxial source / drain region, and the second portion covering the spacer and the metal gate stack. The plasma etching process includes: completely removing the first portion of the etch stop layer to expose the epitaxial source / drain region before completely removing the second portion of the etch stop layer; and forming the sacrificial oxide capping layer on the exposed epitaxial source / drain region while completely removing the second portion of the etch stop layer.

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