Data processing device, data driving device, and display panel driving device

Abstract

This invention provides a data processing apparatus, a data driving apparatus, and a display panel driving apparatus. This disclosure relates to technology for driving a display panel, wherein setting data for setting up a high-speed communication environment is transmitted via low-speed communication before high-speed communication of image data, thereby reducing errors in high-speed communication and increasing communication speed.

Description

Technical Field

[0001] This disclosure relates to technology for driving display devices. Prior Technology

[0002] The display panel consists of multiple pixels arranged in a matrix. Each pixel can have a color such as R (red), G (green), and B (blue), and displays the image on the display panel while emitting light at a grayscale corresponding to the image data.

[0003] Image data is sent from a data processing unit, called a timing controller, to a data driving unit, called a source driver. The image data is sent as a digital value, and the data driving unit converts the image data into analog voltages to drive each pixel.

[0004] Since image data indicates the grayscale value of each pixel individually or independently, the amount of image data increases with the number of pixels arranged on the display panel. Furthermore, as the playback rate increases, the amount of image data to be transmitted per unit time also increases.

[0005] With the recent increase in display panel resolution, both the number of pixels arranged on the display panel and the image playback rate are increasing, and data communication in display devices is accelerating to handle the increased amount of image data. Summary of the Invention

[0006] In view of the above, this disclosure provides techniques for improving the performance of high-speed data communication.

[0007] According to one embodiment, a data driving device is provided, comprising: a low-speed communication circuit that receives setting data at a first data rate via a first communication line; a high-speed communication circuit that operates according to setting values ​​included in the setting data and receives image data at a second data rate higher than the first data rate via the first communication line; and a data driving circuit that drives pixels of a display panel according to the image data.

[0008] According to another embodiment, a data processing apparatus is provided, comprising: an image data processing circuit that processes image data for driving pixels of a display panel; a low-speed communication circuit that transmits setting data for communicating at the high-speed communication rate via a first communication line at a low communication rate lower than the high-speed communication rate; and a high-speed communication circuit that, after transmitting the setting data, transmits the image data via the first communication line at the high-speed communication rate.

[0009] According to another embodiment, a display panel driving device is provided, comprising: a first communication line for LVDS (Low Voltage Differential Transmission) communication; a data processing device for transmitting setting data to the first communication line at a low-speed communication rate; and a data driving device for driving pixels of the display panel, wherein the display panel performs high-speed communication via the first communication line at a high-speed communication rate higher than the low-speed communication rate, sets a high-speed communication environment according to setting values ​​included in the setting data, receives image data via the high-speed communication, and drives pixels of the display panel.

[0010] The display panel driving device may further include: a second communication line, wherein a status signal is transmitted via the second communication line, and when an anomaly is detected in the high-speed communication, each data driving device transmits the status signal to the data processing device via the second communication line.

[0011] The first communication line can be connected one-to-one between the data processing device and each data driving device, and the second communication line can be connected between the data processing device and the data driving devices in a cascaded configuration.

[0012] After the driving voltage is supplied to the data processing device and the data driving device, the setting data can be sent from the data processing device to the data driving device within the setting data range.

[0013] During the display period after the setting data is sent, the image data can be sent from the data processing device to the data driving device.

[0014] As described above, according to embodiments of this disclosure, by checking the validity of data in data communication in different ways based on the type of data sent / received and the operating mode, the accuracy and efficiency of data verification can be improved. Furthermore, according to embodiments of this disclosure, power consumption during data communication can be reduced, and the possibility of malfunctions such as incorrectly entering power-saving mode due to communication errors can be minimized. Moreover, according to embodiments of this disclosure, even if one of the multiple data driving devices malfunctions, all data driving devices can be initialized simultaneously, and the operating modes of the data driving devices and data processing devices can be easily synchronized. Furthermore, according to embodiments of this disclosure, the operating modes of the data driving devices and data processing devices are easily managed, and recovery time in error situations can be minimized. Simple Explanation of the Diagram

[0015] Figure 1 is a configuration diagram of a display device according to one embodiment.

[0016] Figure 2 is a configuration diagram showing the main communication and auxiliary communication between a data processing apparatus and a data driving apparatus according to one embodiment.

[0017] Figure 3 is a configuration diagram of a portion of the first data drive integrated circuit for processing auxiliary communication signals in Figure 2.

[0018] Figure 4 is a configuration diagram of a data processing apparatus according to one embodiment.

[0019] Figure 5 is an example diagram illustrating the protocol for transmitting main communication signals in Manchester code.

[0020] Figure 6 is a configuration diagram of a data driving device according to one embodiment.

[0021] Figure 7 is a diagram illustrating the main signal sequence according to one embodiment.

[0022] Figure 8 is a configuration diagram of a configuration data packet according to one embodiment.

[0023] Figure 9 is a configuration diagram of line data packets according to one embodiment.

[0024] Figure 10 is a configuration diagram of control data packets according to one embodiment.

[0025] Figure 11 is a flowchart of a data verification method according to one embodiment.

[0026] Figure 12 is a diagram showing that auxiliary communication signals sent from other data driving circuits are ignored in a data driving circuit according to one embodiment.

[0027] Figure 13 is a diagram showing that auxiliary communication signals transmitted from other data driver circuits are bypassed in a data driver circuit according to one embodiment.

[0028] Figure 14 is an example diagram of symbol setting values ​​according to one embodiment.

[0029] Figure 15 is a diagram illustrating the correction of bit errors in a symbol according to one embodiment.

[0030] Figure 16 is a diagram illustrating a mode switching sequence of a display driver according to one embodiment.

[0031] Figure 17 is a diagram illustrating a sequence of low-power operation of a display driver according to one embodiment. Implementation

[0032] Figure 1 is a configuration diagram of a display device according to one embodiment.

[0033] Referring to Figure 1, the display device 100 may include a data processing device 110, a data driving device 120, a display panel 130, a gate driving device 140, etc.

[0034] The data processing device 110 can receive image data from other devices. These other devices are those that generate the image data, also known as host devices.

[0035] The data processing device 110 can process image data received from other devices (e.g., a host computer) to suit the data driving device 120, and send the processed image data to the data driving device 120. The data processing device 110 can perform digital gamma correction processing on the grayscale values ​​of each pixel included in the image data, or perform compensation processing according to the characteristics of each pixel.

[0036] The data driving device 120 can receive image data from the data processing device 110, generate a data voltage VD based on the grayscale values ​​of the pixels included in the image data, and supply the data voltage VD to the pixel P.

[0037] Multiple pixels P can be arranged on the display panel 130. In addition, each pixel P can be connected to the data driving device 120 via data line DL, and can be connected to the gate driving device 140 via gate line GL.

[0038] Scanning transistors can be arranged in each pixel P. The gate terminals of the scanning transistors can be connected to the gate line GL, and the source terminals can be connected to the data line DL. When the gate drive device 140 supplies a scan signal SCN to the gate line GL, the scanning transistors are turned on and the data line DL is connected to the pixel P. Then, after the data line DL is connected to the pixel P, the data voltage VD supplied by the data drive device 120 is sent to the pixel P.

[0039] In order to match the timing of the gate drive device 140 and the data drive device 120, the data processing device 110 can send timing control signals to the gate drive device 140 and the data drive device 120.

[0040] The data processing device 110 can send a gate control signal GCS to the gate driving device 140. The gate control signal GCS may include the timing control signal described above. The gate driving device 140 can generate a scan signal SCN according to the gate control signal GCS, and supply the scan signal SCN to the pixel P via the gate line GL.

[0041] At least two types of communication lines, CLM and CLA, can be arranged between the data processing device 110 and the data driving device 120. The data processing device 110 can transmit a first communication signal MDT via the first communication line CLM and transmit or receive a second communication signal LCK via the second communication line CLA. In the following description, for ease of description, the first communication line CLM is referred to as the main communication line, and the second communication line CLA is referred to as the auxiliary communication line. In addition, the first communication signal MDT is referred to as the main communication signal, and the second communication signal LCK is referred to as the auxiliary communication signal.

[0042] The data processing device 110 can send image data and timing control signals to the data driving device 120 via the main communication signal MDT, and the data driving device 120 can send status information to the data processing device 110 via the auxiliary communication signal LCK.

[0043] Figure 2 is a configuration diagram showing the main communication and auxiliary communication between a data processing apparatus and a data driving apparatus according to one embodiment.

[0044] Referring to Figure 2, the data driving device may include multiple data driving integrated circuits 120a, 120b, 120c and 120d.

[0045] Additionally, the data processing device 110 can be communicatively connected to data driver integrated circuits 120a, 120b, 120c, and 120d via a main communication line (CLM). The data processing device 110 can be connected to each of the data driver integrated circuits 120a, 120b, 120c, and 120d for one-to-one communication. For example, the data processing device 110 can be connected to the first data driver integrated circuit 120a for one-to-one communication and can also be connected to the second data driver integrated circuit 120b in a one-to-one communication manner.

[0046] Each main communication line (CLM) may include m (m is a natural number) electrically insulated lines. Furthermore, the m lines can be paired into multiple pairs, and each pair can perform low-voltage differential transmission (LVDS) communication.

[0047] Such a communication connection structure and the main communication signals (see MDT in Figure 1) transmitted / received between the data processing device 110 and the data driving integrated circuits 120a, 120b, 120c and 120d can be collectively referred to as main communication.

[0048] In addition to main communication, the data processing device 110 and the data driving integrated circuits 120a, 120b, 120c and 120d can also send / receive information via auxiliary communication.

[0049] Auxiliary communication between data driver circuits 120a, 120b, 120c, and 120d can be cascaded. For example, the first data driver circuit 120a, located at the beginning of the cascade, can send a first auxiliary communication signal LKa to the second data driver circuit 120b via a first auxiliary communication line CLAa. Furthermore, the second data driver circuit 120b can generate a second auxiliary communication signal LCKb by combining an internally generated status signal and the first auxiliary communication signal LKa, and send the second auxiliary communication signal LCKb to the third data driver circuit 120c via the second auxiliary communication line CLAb. Additionally, the third data driver circuit 120c can generate a third auxiliary communication signal LCKc by combining an internally generated status signal and the second auxiliary communication signal LCKb, and send the third auxiliary communication signal LCKc to the fourth data driver circuit 120d via the third auxiliary communication line CLAc.

[0050] The fourth data driver integrated circuit 120d, located at the end of the cascade, can generate a fourth auxiliary communication signal LCKd by combining an internally generated status signal and a third auxiliary communication signal LCKc, and transmit the fourth auxiliary communication signal LCKd to the data processing device 110 via the fourth auxiliary communication line CLAd. Here, the fourth data driver integrated circuit 120d, located at the end of the cascade, transmits the auxiliary communication signal to the data processing device 110 via auxiliary communication.

[0051] The data processing apparatus 110 can check the status of data driving circuits 120a, 120b, 120c, and 120d based on auxiliary communication signals received from the fourth data driving circuit 120d disposed at the end of the cascade. Additionally, the data processing apparatus 110 can send an auxiliary communication feedback signal LCKf, corresponding to the auxiliary communication signal, to the first data driving circuit 120a disposed at the beginning of the cascade via the auxiliary communication feedback line CLAF. For example, the data processing apparatus 110 can generate the auxiliary communication feedback signal LCKf in the same form as the auxiliary communication signal received from the fourth data driving circuit 120d and send it to the first data driving circuit 120a.

[0052] Figure 3 is a configuration diagram of a portion of the first data drive integrated circuit for processing auxiliary communication signals in Figure 2.

[0053] Referring to Figure 3, the first data driving integrated circuit may include an auxiliary communication input terminal TML1 and an auxiliary communication output terminal TML2, and may include a signal combination circuit 310 and a status signal generation circuit 320.

[0054] The signal combination circuit 310 can generate an output signal by combining the input signal received from the auxiliary communication input terminal TML1 and the status signal SIG1 generated by the status signal generation circuit 320, and output the output signal to the auxiliary communication output terminal TML2. The input signal can be the aforementioned auxiliary communication feedback signal LCKf, and the output signal can be the aforementioned first auxiliary communication signal LKa.

[0055] The status signal generation circuit 320 can check the communication status of the main communication line and generate a status signal SIG1 based on the communication status of the main communication line. For example, when the communication status of the main communication line is normal, the status signal generation circuit 320 can generate a status signal SIG1 with a high level voltage, and when the communication status of the main communication line is abnormal, the status signal generation circuit 320 can generate a status signal SIG1 with a low level voltage.

[0056] The signal combination circuit 310 can generate an output signal by combining signals using an AND operation. For example, the signal combination circuit 310 can generate an output signal by combining an input signal received from the auxiliary communication input terminal TML1 with a status signal SIG1 generated by the status signal generation circuit 320 using an AND operation.

[0057] The first data driver integrated circuit may also include a performance evaluation feedback circuit 330, which can evaluate the communication performance of the main communication line and generate a performance evaluation feedback signal SIG2 indicating the communication performance.

[0058] In addition, the signal combination circuit 310 can generate an output signal by combining the status signal SIG1 and the performance evaluation feedback signal SIG2.

[0059] For example, the first data driving integrated circuit can receive a bit error rate (BER) test pattern from the data processing device and evaluate communication performance based on the recognition rate of the BER test pattern. Furthermore, when the recognition rate is equal to or greater than a given value, the performance evaluation feedback circuit 330 can generate a performance evaluation feedback signal SIG2 with a high-level voltage, and when the recognition rate is less than a given value, the performance evaluation feedback circuit 330 can generate a performance evaluation feedback signal SIG2 with a low-level voltage.

[0060] The signal combination circuit 310 can have various combination modes. For example, in a first combination mode, the signal combination circuit 310 can generate an output signal by simply ANDing the input signal received from the auxiliary communication input terminal TML1 and the status signal SIG1 generated by the status signal generation circuit 320. Furthermore, in a second combination mode, the signal combination circuit 310 can generate an output signal by simply ANDing the status signal SIG1 and the performance evaluation feedback signal SIG2. Additionally, in a third combination mode, the signal combination circuit 310 can bypass the input signal as is to generate an output signal.

[0061] Figure 3 shows a portion of the processing auxiliary communication signals in the first data driver integrated circuit, and the same components can be included in other data driver integrated circuits. The individual data driver integrated circuits may differ only in their arrangement within the cascade.

[0062] Referring to Figures 2 and 3, each of the data driving integrated circuits 120a, 120b, 120c, and 120d may include the same terminals TML1 and TML2 as the first data driving integrated circuit 120a, and may include a signal combination circuit 310, a status signal generation circuit 320, and a performance evaluation feedback circuit 330, etc. Regarding the auxiliary communication connections, the auxiliary communication input terminal of the first data driving integrated circuit 120a, located at the beginning of the cascade, can be connected to the data processing device 110, and the auxiliary communication output terminal can be connected to the second data driving integrated circuit 120b. Furthermore, the auxiliary communication input terminal of the fourth data driving integrated circuit 120d, located at the end of the cascade, can be connected to the third data driving integrated circuit 120c, and the auxiliary communication output terminal can be connected to the data processing device 110.

[0063] Each of the data-driven integrated circuits 120a, 120b, 120c, and 120d can use the cascaded connection structure and the auxiliary communication feedback signal LCKf to confirm whether an anomaly has occurred in itself or in other data-driven integrated circuits.

[0064] As an example, when the internal status signal SIG1 has a low-level voltage, the fourth data drive circuit 120d can determine that it has malfunctioned. Additionally, when the input signal has a low-level voltage, the fourth data drive circuit 120d can determine that at least one of the first data drive circuit 120a, the second data drive circuit 120b, and the third data drive circuit 120c has malfunctioned.

[0065] As another example, when the internal status signal SIG1 has a low level voltage, the first data driving circuit 120a can determine that it has malfunctioned. Furthermore, when the input signal has a low level voltage, the first data driving circuit 120a can determine that at least one of the second data driving circuit 120b, the third data driving circuit 120c, and the fourth data driving circuit 120d has malfunctioned. The first data driving circuit 120a receives an auxiliary communication feedback signal LCKf from the data processing device 110. On the other hand, since the data processing device 110 generates the auxiliary communication feedback signal LCKf based on the fourth auxiliary communication signal LCKd reflecting the status of the data driving circuits 120a, 120b, 120c, and 120d, the first data driving circuit 120a can determine the status of each of the data driving circuits 120a, 120b, 120c, and 120d.

[0066] When a data driver circuit determines that an anomaly has occurred in itself or in another data driver circuit, the data driver circuit can switch to the mode corresponding to the anomaly.

[0067] For example, when the first data driving circuit 120a determines that an anomaly has occurred in itself or in at least one of the second data driving circuit 120b, the third data driving circuit 120c, and the fourth data driving circuit 120d, the first data driving circuit 120a can switch to a mode for retraining the communication clock of the main communication line. When a communication anomaly is determined in the main communication line, the status signal SIG1 can have a low-level voltage, and therefore, the auxiliary communication signal can have a low-level voltage. Furthermore, when it is confirmed that the auxiliary communication signal has a low-level voltage, the data processing device 110 can switch to a mode for retraining the communication clock of the main communication line and send a clock training signal for retraining the communication clock to the data driving circuits 120a, 120b, 120c, and 120d.

[0068] When an error occurs in one of the data-driven integrated circuits 120a, 120b, 120c, and 120d in a cascaded structure, other than the first data-driven integrated circuit 120a, the first data-driven integrated circuit 120a may be unable to detect the anomaly in the other data-driven integrated circuits using only the auxiliary communication signal in the cascaded structure. The auxiliary communication feedback signal LCKf is a signal that compensates for this problem and enables the data-driven integrated circuits 120a, 120b, 120c, and 120d bundled in a cascaded structure to detect anomalies almost simultaneously.

[0069] On the other hand, the data processing device 110 can use the auxiliary communication feedback signal LCKf for other purposes. For example, the data processing device 110 can send a reset signal via the auxiliary communication feedback signal LCKf. The data processing device 110 can generate a reset signal (e.g., a signal with a low-level voltage) independent of the fourth auxiliary communication signal LCKd, and send the reset signal to the first data driver integrated circuit 120a via the auxiliary communication feedback line CLAF. Furthermore, the reset signal can be propagated sequentially via auxiliary communication in a cascaded structure of the data driver integrated circuits 120a, 120b, 120c, and 120d. Through such auxiliary communication, all the data driver integrated circuits 120a, 120b, 120c, and 120d can receive the reset signal.

[0070] When a reset signal is received, each of the data driver circuits 120a, 120b, 120c, and 120d can enter an initialization state. For example, each of the data driver circuits 120a, 120b, 120c, and 120d can reduce the data rate of the main communication via the main communication line after receiving the reset signal.

[0071] In summary, the data driving device may include multiple data driving integrated circuits for receiving image data from the data processing device via a main communication line. The multiple data driving integrated circuits may be cascaded via auxiliary communication. A fourth data driving integrated circuit located at the end of the cascade may transmit a fourth auxiliary communication signal to the data processing device via auxiliary communication, and a first data driving integrated circuit located at the beginning of the cascade may receive an auxiliary communication feedback signal from the data processing device in response to the fourth auxiliary communication signal.

[0072] Each data driver circuit can perform auxiliary communication by combining the input signal received from the auxiliary communication input terminal with a status signal indicating the communication status of the main communication line and outputting it to the auxiliary communication output terminal. Additionally, each data driver circuit can output an auxiliary communication signal obtained by ANDing the input signal and the status signal to the auxiliary communication output terminal.

[0073] The auxiliary communication output terminal of the fourth data driver circuit can be connected to the data processing device, and the auxiliary communication input terminal of the first data driver circuit can be connected to the data processing device.

[0074] When the input signal or status signal has a low level voltage, each data driver circuit can be identified as having an anomaly in at least one of the multiple data driver circuits.

[0075] When the input signal or status signal has a low level voltage, each data driver circuit can switch to a mode for retraining the communication clock of the main communication line.

[0076] When the first auxiliary communication signal has a low-level voltage, the data processing device can generate and send a low-level auxiliary communication feedback signal.

[0077] The data processing device can send a reset signal via a feedback signal, and multiple data driver circuits can receive the reset signal via auxiliary communication. Furthermore, after receiving the reset signal, each data driver circuit can reduce the data rate of the main communication via the main communication line. Additionally, each data driver circuit can receive image data in a high-speed mode and receive setting data for the high-speed mode in a low-speed mode with a lower data rate than the high-speed mode.

[0078] The data processing apparatus may include a main communication circuit and an auxiliary communication circuit. Furthermore, the main communication circuit can transmit image data to multiple data driver integrated circuits via a main communication line. Additionally, the auxiliary communication circuit can receive a fourth auxiliary communication signal from a fourth data driver integrated circuit located at the end of a cascade of multiple data driver integrated circuits connected in a cascaded manner, and send an auxiliary communication feedback signal in response to the auxiliary communication signal to a first data driver integrated circuit located at the beginning of the cascade.

[0079] When the fourth auxiliary communication signal indicates an abnormal state of at least one main communication line, the main communication circuit can send a clock training signal for retraining the communication clock for image data to the main communication line.

[0080] In addition, the main communication circuit can transmit image data in high-speed mode and transmit configuration data for high-speed mode to the main communication line in a low-speed mode with a data rate lower than that of high-speed mode.

[0081] In addition, when the fourth auxiliary communication signal indicates an abnormal state of at least one main communication line, the main communication circuit can switch from high-speed mode to low-speed mode.

[0082] The auxiliary communication circuit can send a reset signal via the auxiliary communication feedback signal to reset multiple data drive integrated circuits.

[0083] Additionally, when the fourth auxiliary communication signal has a low-level voltage, the auxiliary communication circuit can generate and transmit a low-level voltage feedback signal. Furthermore, when the fourth auxiliary communication signal has a low-level voltage, the main communication circuit can send a clock training signal used to retrain the communication clock for image data to the main communication line.

[0084] Figure 4 is a configuration diagram of a data processing apparatus according to one embodiment.

[0085] Referring to Figure 4, the data processing device may include a P main communication circuit 410, a P auxiliary communication circuit 420, a P control circuit 430, a P memory 440, and an image data processing circuit 450.

[0086] The P main communication circuit 410 can send the main communication signal MDT to the data driving device via the main communication line CLM. The P main communication circuit 410 can send image data and first control data during the active period via the main communication line CLM, and can send second control data during the blanking period. Additionally, the data driving device can drive the pixels of the display panel according to the image data. The first control data may include control values ​​applied in line units or pixel units of the display panel, and the second control data may include control values ​​applied for a time period longer than line units or pixel units, or control values ​​applied in frame units.

[0087] The P main communication circuit 410 can transmit setting data at a first data rate via the main communication line CLM. Additionally, the P main communication circuit 410 can transmit image data, first control data, and second control data at a second data rate higher than the first data rate via the main communication line CLM. The mode of communication at the first data rate can be referred to as a low-speed communication mode, and the mode of communication at the second data rate can be referred to as a high-speed communication mode.

[0088] The P main communication circuit 410 may include a P high-speed communication circuit 411 for high-speed communication and a P low-speed communication circuit 416 for low-speed communication.

[0089] The high-speed communication circuit 411 may include a packet sealer 412, a code generator 413, an encoder 414, and a first serializer 415, etc.

[0090] The packetizer 412 can receive image data from the image data processing circuit 450 that processes image data. Additionally, the packetizer 412 can receive first control data and / or second control data from the P control circuit 430 or the P memory 440. The packetizer 412 can generate transmission data by packetizing at least one of the image data, the first control data, and the second control data.

[0091] The code-mixer 413 can mix the transmitted data. Code mixing is the process of mixing the bits of the transmitted data to prevent the same bits (e.g., 1 or 0) from appearing consecutively K times (K is a natural number equal to or greater than 2) in the transmitted data stream. Code mixing is performed according to a specified protocol. According to the specified protocol, the data drive device can restore the mixed data stream to the original data.

[0092] The code mixer 413 can code only the image data and can not apply code mixing to the first control data or the second control data.

[0093] Encoder 414 can encode P bits of the transmitted stream into Q bits of the transmitted data. P can be, for example, 6, and Q can be, for example, 7. Encoding 6 bits of data into 7 bits of data is also called 6B7B encoding. 6B7B encoding is an encoding method that uses DC balanced codes.

[0094] Encoder 414 can encode the transmitted data, increasing the number of bits in the transmitted stream. Furthermore, the encoded data can be decoded by the data driver into DC balanced code (e.g., 6B7B). Conversely, the encoded transmitted data can be restored to its original bit count by the data driver.

[0095] Encoder 414 may use Limiting Run-Length Code (LRLC) when encoding transmitted data. “Run-length” means consecutive identical bits, and LRLC encodes the transmitted data such that the “run-length” appears in the transmitted data as not exceeding a given size.

[0096] When encoder 414 uses LRLC to encode data, the data drive device can decode the data according to the LRLC method used by encoder 414.

[0097] The encoder 414 can divide the transmitted data into predetermined units and encode the transmitted data of each unit. Then, the encoder 414 can perform DC balanced encoding or LRLC encoding according to the encoding table stored in the P memory 440. The data driving device has a decoding table corresponding to the encoding table and can decode each unit of data according to the decoding table.

[0098] The data to be transmitted in parallel in the data processing device 110 can be serialized by the first serializer 415. Then, the first serializer 415 can send the serialized data to the data driving device. In this case, the series of data transmitted in serial order can form a transmission stream, and can be in the form of a main communication signal MDT as a signal.

[0099] The main communication line CLM may include m (m is a natural number) electrically insulated wires. Additionally, the m wires may be paired into multiple pairs, each pair allowing Low Voltage Differential Transmission (LVDS) communication. When the main communication line CLM includes two or more pairs, the first serializer 415 can distribute and transmit data among each pair.

[0100] Transmitted data can consist of bits, and multiple bits can form a symbol. A symbol can consist of 8 bits or 10 bits. Furthermore, multiple symbols can form pixel data. Pixel data can sequentially include information corresponding to sub-pixels such as R (red), G (green), B (blue), etc. The data driving device can arrange the received data, which is serialized in bit units, in byte units and in pixel units.

[0101] The low-speed communication circuit 416 may include a data processing circuit 417 and a second serializer 418.

[0102] The setting data processing circuit 417 can receive setting values ​​from the P memory 440 and / or the P control circuit 430, and generate setting data corresponding to the setting values.

[0103] The setup data is data transmitted at low speed and may include settings for the data drive device necessary before high-speed communication. For example, the setup data may include settings for circuitry in the data drive device that enables high-speed communication.

[0104] The second serializer 418 can serialize and convert configuration data, and send the serialized configuration data to the data driver via the main communication line CLM.

[0105] The second serializer 418 can convert the configuration data into Manchester code and send the configuration data.

[0106] Figure 5 is an example diagram illustrating the protocol for transmitting main communication signals in Manchester code.

[0107] Referring to Figure 5, the main communication signal transmitted in Manchester code can be composed of six parts from P1 to P6.

[0108] The low-speed communication clock can be transmitted via the first part P1. In the main communication signal, data bits can be encoded in Manchester-II code, and in this case, one bit can consist of two unit pulses UI. In Manchester-II encoding, when the data bits transmitted in the first part P1 represent all 0s or all 1s, pulses synchronized with the low-speed communication clock can be transmitted.

[0109] The receiving side (data driving device) can be trained based on the low-speed communication clock received from the first part P1.

[0110] After sending the low-speed communication clock, a start signal indicating the start of the message can be sent in the second part P2, and an end signal indicating the end of the message can be sent in the sixth part P6, which is the last part of the message.

[0111] In Part 3, page 3, the message header is sent. The message header may include parameter values ​​such as data type, mode, receiver identification code (ID), data length, and receiver settings register address.

[0112] In addition, Part 4, P4, may include information sent / received via messages.

[0113] Additionally, Part 5, P5, may include a Cyclic Redundancy Check (CRC) value.

[0114] Referring back to Figure 4, the data processing device may include a P-assisted communication circuit 420, and the P-assisted communication circuit 420 may include a P-assisted communication control circuit 422 and a P-assisted communication signal processing circuit 421.

[0115] The auxiliary communication signal processing circuit 421 can receive the auxiliary communication signal LCK from the auxiliary communication line CLA, or send the auxiliary communication signal LCK to the auxiliary communication line CLA. The auxiliary communication signal (LCK) to be sent can be called the auxiliary communication feedback signal.

[0116] The P-auxiliary communication control circuit 422 checks the auxiliary communication signal LCK received from the auxiliary communication line CLA, and if the auxiliary communication signal LCK indicates an abnormality in the data drive device, the P-auxiliary communication control circuit 422 can send an auxiliary communication feedback signal with the same form as the auxiliary communication signal LCK to the auxiliary communication line CLA. Here, the line for receiving the auxiliary communication signal LCK from the data drive device and the line for sending the auxiliary communication feedback signal can be physically separate lines.

[0117] The P-auxiliary communication control circuit 422 can generate an auxiliary communication feedback signal independent of the auxiliary communication signal LCK received from the auxiliary communication line CLA, and send it to the auxiliary communication line CLA. For example, when the P-auxiliary communication control circuit 422 intends to switch the mode of the data drive device, the P-auxiliary communication control circuit 422 can incorporate a reset signal into the auxiliary communication feedback signal and send it to it.

[0118] The P control circuit 430 is a circuit that controls the overall function of the data processing device 110. The P control circuit 430 can determine the operating mode of the data processing device and can determine the circuitry performed in each operating mode.

[0119] Figure 6 is a configuration diagram of a data driving device according to one embodiment. When the data driving device includes multiple data driving integrated circuits, the configuration shown in Figure 6 can be understood as a configuration included in one data driving integrated circuit.

[0120] Referring to Figure 6, the data driving device 120 includes a D main communication circuit 610, a D auxiliary communication circuit 620, a D control circuit 630, a D memory 640, and a data driving circuit 650, etc.

[0121] The main communication circuit 610 can receive the main communication signal MDT from the data processing device via the main communication line CLM. The main communication circuit 610 can receive image data and first control data during the active period via the main communication line CLM, and can receive second control data during the blanking period. Additionally, the data driving circuit 650 can drive the pixels of the display panel according to the image data. The first control data may include control values ​​applied in line units or pixel units of the display panel, and the second control data may include control values ​​applied for a longer time period than line units or pixel units, or control values ​​applied in frame units.

[0122] The D main communication circuit 610 can receive setting data at a first data rate via the main communication line CLM. Additionally, the D main communication circuit 610 can receive image data, first control data, and second control data at a second data rate higher than the first data rate via the main communication line CLM. The mode of communication at the first data rate can be referred to as a low-speed communication mode, and the mode of communication at the second data rate can be referred to as a high-speed communication mode.

[0123] The main communication circuit 610 may include a high-speed communication circuit 611 for high-speed communication and a low-speed communication circuit 616 for low-speed communication.

[0124] The main communication circuit 610 may include a first deserializer 612, a decoder 613, a descrambler 614, and a depacker 615, etc.

[0125] The first deserializer 612 can parallelize the main communication signal MDT received by the main communication line CLM in byte or symbol units.

[0126] In addition, decoder 613 can decode data encoded using DC balanced codes (e.g., 6B7B codes) or LRLC codes.

[0127] Decoder 613 can decode each cell of data according to the decoding table stored in D memory 640. In this case, if it is confirmed that a cell of data included in the data is not included in the decoding table, decoder 613 can generate an error signal.

[0128] Then, decoder 613 can check whether the received data meets the LRLC encoding standard. For example, when it is confirmed that the run length of the received data exceeds the reference value, decoder 613 can generate an error signal.

[0129] The unmixer 614 can restore the mixing data to the original data according to the prescribed agreement.

[0130] The unpacker 615 can arrange the received data in pixel units and send the image data of each pixel to the data driving circuit 650.

[0131] The low-speed communication circuit 616 may include a second deserializer 617 and a data storage circuit 618.

[0132] The second deserializer 617 can parallelize the configuration data received via the main communication line CLM serialization. The configuration data can be received in Manchester code, and the second deserializer 617 can decode the received configuration data into Manchester code and then send it to the configuration data storage circuit 618.

[0133] The setting data storage circuit 618 can receive setting data and store the setting values ​​included in the setting data in the D memory 640, or apply them to the circuit corresponding to the setting values.

[0134] The P memory in the data processing device and the D memory in the data driving device can be in the form of a temporary register, read-only memory (ROM), or random access memory (RAM).

[0135] The D-auxiliary communication circuit 620 may include a D-auxiliary communication control circuit 621 and a D-auxiliary communication signal processing circuit 622.

[0136] The D-auxiliary communication control circuit 621 may include a status signal generation circuit 320 (see FIG3) and a performance evaluation feedback circuit 330 (see FIG3) as described with reference to FIG3, and the D-auxiliary communication signal processing circuit 622 may include a signal combination circuit 310 (see FIG3) as described with reference to FIG3.

[0137] The D-auxiliary communication control circuit 621 can check for abnormal states of the main communication signal MDT, the main communication circuit 610, and / or other components, and generate status signals. Alternatively, the D-auxiliary communication control circuit 621 can evaluate the performance of the main communication based on the recognition rate of the received test pattern used to assess the performance of the main communication, and generate a performance evaluation feedback signal based on the evaluation results.

[0138] The auxiliary communication signal processing circuit 622 can use status signals or performance evaluation feedback signals to generate an auxiliary communication signal LCK and send the auxiliary communication signal LCK to the auxiliary communication line CLA.

[0139] The auxiliary communication signal processing circuit 622 combines auxiliary communication signals sent from other data driving circuits or auxiliary communication feedback signals sent from data processing devices, as well as status signals or performance evaluation feedback signals, via the auxiliary communication line CLA to generate the auxiliary communication signal LCK.

[0140] The D control circuit 630 is a circuit that controls the overall function of the data drive device 120. The D control circuit 630 can determine the operating mode of the data drive device and can determine the circuitry performed in each operating mode.

[0141] Figure 7 is a diagram illustrating the main signal sequence according to one embodiment.

[0142] Referring to Figure 7, the waveform of the drive voltage VCC is shown. The drive voltage VCC initially has a low level voltage, and then the waveform changes to a high level voltage at a certain point. The time it takes for the drive voltage VCC to change to a high level voltage can be understood as the driving time of the display drive device (e.g., a data processing device or a data drive device).

[0143] After the driving time, the data processing device and the data driving device can operate in the data setting mode. Furthermore, after the operation in the data setting mode is completed, the data processing device and the data driving device can operate in the display mode.

[0144] In the data setting interval T710, the data processing device can continuously send the pre-packet P710 and the setting data packet P720 via the main communication signal MDT.

[0145] The data processing unit can change the voltage of the auxiliary communication feedback signal LCKf from a low level to a high level while sending the preamble packet P710. This voltage change allows the data processing unit to notify the preamble packet that it is being sent to the data drive unit.

[0146] The voltage of the main communication signal MDT in the preamble P710 can change periodically between high and low levels, and the data drive device can use the preamble P710 to train the low-speed communication clock for receiving the data packet P720.

[0147] The data processing device can send a preamble packet P710 and a setup data packet P720 at a relatively low first data rate. The low-speed communication clock becomes the first data rate, and the data driving device can use the preamble packet P710 to train the low-speed communication clock.

[0148] When the low-speed communication clock is being trained, the data driver can notify the data processing device of the clock learning status via the auxiliary communication signal LCKd. For example, when the low-speed communication clock is being trained, the data driver can change the voltage of the auxiliary communication signal LCKd from a low level to a high level. The waveform of the auxiliary communication signal LCKd shown in Figure 7 is the auxiliary communication signal of the data driver integrated circuits arranged at the ends of multiple data driver integrated circuits forming a cascaded structure in the data driver device.

[0149] After confirming that the data drive device has trained the low-speed communication clock using the auxiliary communication signal LCKd, the data processing device can send the configuration data packet P720.

[0150] Figure 8 is a configuration diagram of a configuration data packet according to one embodiment.

[0151] Referring to Figure 8, setting the data packet P720 may include setting the data start packet P810, setting the data header packet P820, setting the data header verification packet P830, setting the data body packet P840, setting the data body verification packet P850, and setting the data end packet P860.

[0152] The start packet P810 indicates the start of the data setup packet P720. Furthermore, the end packet P860 indicates the end of the data setup packet P720.

[0153] Setting the header packet P820 may include setting indication values ​​for communication in the body packet P840. For example, setting the header packet P820 may include setting indication values ​​for the length of the body packet P840.

[0154] The data header verification packet P830 may include verification values ​​used to verify the validity of the data in the data header verification packet P820. For example, the data header verification packet P830 may include the CRC value of the data header verification packet P820.

[0155] Setting the data body packet P840 can include settings for the data drive device required for high-speed communication. For example, setting the data body packet P840 can include settings for the circuitry in the data drive device that enables high-speed communication.

[0156] The Set Data Body Validation Packet P850 may include a validation value used to validate the validity of the data in the Set Data Body Packet P840. For example, the Set Data Body Validation Packet P850 may include the CRC value of the Set Data Body Packet P840.

[0157] Referring back to Figure 7, after completing the transmission of the setting data packet P720, the data processing device can maintain the main communication signal MDT at a high-level voltage or a low-level voltage for a predetermined time. Such a packet can be referred to as a high-voltage packet or a low-voltage packet P730, and when a high-voltage packet or a low-voltage packet P730 is received, the data driving device can recognize that the setting data interval T710 has been completed. When the data driving device receives a signal maintained at a high-level voltage or a low-level voltage for a predetermined time, the clock is interrupted, and the data driving device can recognize this as the completion of the setting data interval T710.

[0158] On the other hand, after the first communication signal MDT identifies the end packet P860 of the setting data (see Figure 8), when the first communication signal MDT is maintained at a high level voltage or a low level voltage for a predetermined time, the data driving device can determine the end of the setting data interval T710 and enter the display interval T720.

[0159] After the data interval T710 is set up, the data processing device and the data driving device can enter the display interval T720. The display interval T720 may include the clock training interval T730 and the frame interval T740. After the high-speed communication clock is trained in the clock training interval T730, the frame interval T740 is displayed repeatedly.

[0160] During the clock training interval T730, the data processing device can send the clock training pattern P740 to the data driving device at a second data rate. Furthermore, the data driving device can train a high-speed communication clock corresponding to the second data rate within the clock training pattern P740. Here, the second data rate can have a frequency higher than the first data rate.

[0161] When the data driver fails to train the high-speed communication clock within the clock training interval T730, it can send a clock training failure signal via the auxiliary communication signal LCKd. For example, the data driver can notify the data processing unit of the clock training failure while simultaneously reducing the voltage of the auxiliary communication signal LCKd from a high level to a low level.

[0162] When clock training for high-speed communication clocks fails, the data processing device can either send another clock training pattern P740 or return to the setting data mode.

[0163] When the clock training for the high-speed communication clock is completed, the data processing device and the data driving device can enter the frame interval T740.

[0164] Frame interval T740 may include active interval T750 and blanking interval T760. Active interval T750 may be an interval in which image data and control data are transmitted in line units, and blanking interval T760 may be an interval in which image data is not transmitted in line units. Blanking interval T760 may be divided into horizontal blanking interval and vertical blanking interval. In the following text, for ease of description, blanking interval T760 will be described as vertical blanking interval.

[0165] Within the active range T750, the data processing device can send line data packets P750 in each line unit.

[0166] Figure 9 is a configuration diagram of line data packets according to one embodiment.

[0167] Referring to Figure 9, the line data packet P750 may include a line data start packet P910, a first control data body packet P920, an image data packet P930, and a clock training pattern P940.

[0168] Line start packet P910 can indicate the start of line data packet P750. LRLC encoding or scrambling may not be applied to line start packet P910.

[0169] The control data body packet P920 may include setting values ​​that can be changed in row units or frequently. For example, the first control data body packet P920 may include polarity values ​​indicating the polarity of each pixel, and may include values ​​indicating whether the codebreaker has been reset.

[0170] Image data packet P930 may include grayscale values ​​of pixels arranged in a row.

[0171] Additionally, the clock training pattern P940 may include a pattern signal capable of training a high-speed communication clock.

[0172] Referring back to Figure 7, in the active interval T750, the data processing device can enter the blanking interval T760 after sending the row data packet P750 of all rows.

[0173] During the blanking interval T760, the data processing device can send control data packets P760 in virtual row units.

[0174] Figure 10 is a configuration diagram of control data packets according to one embodiment.

[0175] Referring to Figure 10, the control data packet P760 may include a control data start packet P1010, a second control data body packet P1020, a verification packet P1030, a virtual packet P1040, and a clock training pattern P1050.

[0176] The start of control data packet P1010 can indicate the start of control data packet P760. LRLC encoding or scrambling may not be applied to the start of control data packet P1010.

[0177] The second control data body packet P1020 may include setting values ​​that change on a frame-by-frame basis or change infrequently. Alternatively, according to one embodiment, the second control data body packet P1020 may include setting values ​​that are similar to or equal to the setting values ​​of the first control data body packet.

[0178] Verification packet P1030 may include CRC data. Here, the CRC data may include the CRC value received within the configuration data range. For example, the CRC data may include the CRC value of the configuration header packet P820 (see Figure 8) included in the configuration header verification packet P830 (see Figure 8). Furthermore, the CRC data may include the CRC value of the configuration body packet P840 (see Figure 8) included in the configuration body verification packet P850 (see Figure 8).

[0179] The data drive device can check for communication errors while comparing the CRC value received in the set data range with the CRC value received in the verification packet P1030.

[0180] As described above, in one embodiment, different types of communication are performed for each interval. Under these conditions, in one embodiment, a data verification method optimized for the communication type in each interval is proposed to improve the efficiency of data verification.

[0181] Figure 11 is a flowchart of a data verification method according to one embodiment.

[0182] Referring to FIG11, the data processing device 110 can generate setting data (S1102). The setting data may include high-speed communication settings for smooth high-speed communication (e.g., communication for sending / receiving data at a second data rate).

[0183] The data processing device 110 can transmit setting data to the data driving device 120 at a first data rate via the main communication line. In addition, the data driving device 120 can receive setting data at the first data rate (S1104).

[0184] The data driving device 120 can determine errors in the setting data according to the first rule (S1106). In addition, the data driving device 120 can provide feedback to the data processing device 110 via the auxiliary communication line to check whether there are errors in the setting data (S1108).

[0185] The data processing device 110 can convert image data into a format suitable for the data driving device 120 (S1110).

[0186] Additionally, the data processing device 110 can transmit image data to the data driving device 120 at a second data rate via the main communication line. Furthermore, the data driving device 120 can receive image data at the second data rate (S1112). In this case, the second data rate can be higher than the first data rate. Communication at the first data rate can be considered low-speed communication, and communication at the second data rate can be considered high-speed communication.

[0187] The data driving device 120 can determine errors in the image data according to a second rule different from the first rule (S1114). In addition, the data driving device 120 can provide feedback to the data processing device 110 via an auxiliary communication line regarding whether there are errors in the image data (S1116).

[0188] In the data drive device 120, communication at a first data rate can be performed by the D low-speed communication circuit, and communication at a second data rate can be performed by the D high-speed communication circuit.

[0189] As an example of identifying communication errors, low-speed communication circuits can use CRC checks to determine errors in configuration data.

[0190] As another example, when an error is detected during the decoding of image data, the D high-speed communication circuit can identify the image data as erroneous data.

[0191] When it is confirmed that a unit of data included in the image data is not included in the decoding table, the D high-speed communication circuit can determine that the image data is erroneous. The data processing device can perform LRLC encoding or 6B7B encoding on a unit of data, and when the D high-speed communication circuit cannot retrieve the corresponding unit of data from the LRLC encoding or 6B7B encoding decoding table, it can determine that there is an error in the communication processing of the corresponding unit of data.

[0192] When the run length in the received image data exceeds a reference value, the D high-speed communication circuit can identify the image data as erroneous. Even if the data processing device transmits image data using LRLC encoding to ensure the run length does not exceed the reference value, if the D high-speed communication circuit receives data with a run length exceeding the reference value, an error is likely to occur during communication processing. Therefore, when the run length in the received image data exceeds the reference value, the D high-speed communication circuit can identify the image data as erroneous.

[0193] Errors can also be double-checked. For example, a low-speed communication circuit (D) can determine errors in the configuration data using a CRC check. Furthermore, the CRC check value can be stored in memory. Alternatively, a high-speed communication circuit (D) can receive second control data at a second data rate, and this second control data may include a CRC comparison value. The high-speed communication circuit (D) can determine communication errors by comparing the CRC comparison value with the CRC check value. An error may exist in the CRC comparison value received at the second data rate via high-speed communication, or in the CRC check value received at the first data rate via low-speed communication. The high-speed communication circuit (D) can determine that one of the CRC comparison value or the CRC check value is incorrect and report the communication error to the data processing device.

[0194] The main communication signal can be an embedded clock signal. Because the clock is embedded in the main communication signal, the data drive device may need to perform clock training in the initial interval of the communication.

[0195] The high-speed communication circuit may include a clock recovery circuit that can receive a clock training signal from a data processing device at a second data rate and train a high-speed communication clock.

[0196] The clock training signal can have a specific pattern. For example, the clock training signal can have a pattern of alternating high-level and low-level voltages at a frequency equal to the second data rate. After the clock recovery circuit receives the clock training signal and completes the training of the high-speed communication clock, the clock recovery circuit can determine communication errors by examining the pattern in the clock training signal. For example, the clock recovery circuit can determine communication errors by recognizing the clock training signal as data after completing clock training and then checking whether the data pattern is normal.

[0197] The clock frequency recovered from the embedded clock signal may also vary slightly. However, when the frequency changes significantly, the likelihood of communication errors is high.

[0198] The D-type high-speed communication circuit trains the high-speed communication clock by receiving a clock training signal via the main communication line at a second data rate, and maintains the high-speed communication clock by receiving an embedded clock signal via the main communication line. Furthermore, the D-type high-speed communication circuit can determine communication errors by comparing the frequency of the high-speed communication clock at the training completion time with the frequency of the high-speed communication clock at a time point after the training completion time. In this case, the clock recovery circuit in the D-type high-speed communication circuit can be of the phase-locked loop (PLL) type or the delay-locked loop (DLL) type.

[0199] On the other hand, the D high-speed communication circuit can evaluate its communication performance by using a bit error rate (BER) test pattern received at a second data rate.

[0200] The data processing unit can send the BER test pattern to the data driving unit. Furthermore, the data driving unit can use the BER test pattern to count the number of reception errors. Additionally, when the number of reception errors equals or exceeds a threshold, the data driving unit can provide feedback on the communication errors via an auxiliary communication line.

[0201] When a data driving device includes multiple data driving integrated circuits, the BER (Bit Error Rate) tests of the multiple data driving integrated circuits can be performed sequentially, one after another. For example, after performing a BER test on the first data driving integrated circuit, a BER test on the second data driving integrated circuit can be performed.

[0202] The data-driven integrated circuits performing BER testing can ignore auxiliary communication signals sent from other data-driven integrated circuits. Alternatively, the data-driven integrated circuits performing BER testing can bypass auxiliary communication signals sent from other data-driven integrated circuits and output them.

[0203] Figure 12 is a diagram showing that auxiliary communication signals transmitted from other data driving circuits are ignored in a data driving circuit according to one embodiment, and Figure 13 is a diagram showing that auxiliary communication signals transmitted from other data driving circuits are bypassed in a data driving circuit according to one embodiment.

[0204] Referring to Figure 12, in the data drive integrated circuit, the performance evaluation feedback circuit 330 can generate a performance evaluation feedback signal SIG2 based on the BER test results. For example, when the number of reception errors in the BER test is equal to or greater than a threshold, or when the normal reception rate is less than a predetermined value, the performance evaluation feedback circuit 330 can reduce the voltage of the performance evaluation feedback signal SIG2 from a high level to a low level.

[0205] In this case, the signal combination circuit 310 can generate an auxiliary communication signal LCK that combines the performance evaluation feedback signal SIG2 and the status signal SIG1.

[0206] Furthermore, when the performance evaluation feedback circuit 330 performs BER testing, the signal combination circuit 310 can ignore the auxiliary communication signal LCK' received from other data driving integrated circuits.

[0207] Referring to Figure 13, when BER testing is not performed, the data driver integrated circuit cannot generate the performance evaluation feedback signal SIG2 or the status signal SIG1. Additionally, the signal combination circuit 310 can bypass and output the auxiliary communication signal LCK' received from other data driver integrated circuits.

[0208] In this way, the data drive device can receive feedback on the BER test results of the data drive integrated circuit independently.

[0209] On the other hand, the data processing device sends a symbol consisting of N (N is a natural number greater than or equal to 2) bits, and the data driving device can match each symbol with a value consisting of M (M is a natural number less than N) bits.

[0210] This method of transmitting / receiving bit values ​​of symbol units can be used to transmit / receive power-saving control values, or to transmit / receive packets for which the possibility of errors needs to be reduced, such as line data packets or control data packets.

[0211] Figure 14 is an example diagram of symbol setting values ​​according to one embodiment.

[0212] Referring to Figure 14, the data driving device can receive a first symbol 1410 consisting of 8 bits. Additionally, the data driving device can match the first symbol 1410 with a 1-bit value having a value of 1.

[0213] Additionally, the data driver can receive a second symbol 1420 consisting of 8 bits. Furthermore, the data driver can match the second symbol 1420 with a 1-bit value having a value of 0.

[0214] In this way, the possibility of errors in the setting values ​​can be reduced when sending and receiving bit values ​​in symbol units. Furthermore, even if errors occur in some bits, the data drive itself can correct them.

[0215] Figure 15 is a diagram illustrating the correction of bit errors in a symbol according to one embodiment.

[0216] Referring to FIG15, the data driving device can receive a third symbol 1510 consisting of 8 bits. When the data driving device is preset to receive only the first and second symbols described with reference to FIG14, the data driving device can determine that there is an error in the third symbol 1510 and compare the third symbol 1510 with the first symbol and / or the second symbol 1420. Alternatively, the data driving device can select a second symbol 1420 that is more similar to the third symbol 1510, and can use the second symbol 1420 to correct the erroneous bits of the third symbol 1510.

[0217] Alternatively, the data driving device can use a symbol received before or after receiving the third symbol 1510 to confirm that the third symbol 1510 is not a conventional symbol, and can recover some bit errors of the third symbol 1510.

[0218] Considering the data driving device, some aspects related to the validity of the aforementioned data are summarized. The data driving device may include: a first communication circuit that receives first data via a communication line at a first data rate and determines errors in the first data according to a first rule; a second communication circuit that receives second data via a communication line at a second data rate higher than the first data rate and determines errors in the second data according to a second rule different from the first rule; and a data driving circuit that drives the pixels of the display panel based on image data included in the second data.

[0219] When it is confirmed that a unit data included in the second data is not included in the decoding table, the second communication circuit can identify the second data as erroneous data.

[0220] Furthermore, when it is confirmed that the run length in the second data exceeds the reference value, the second communication circuit can determine that the second data is erroneous data.

[0221] In addition, when an error is detected during the decoding process of the second data, the second communication circuit can determine that the second data is erroneous data.

[0222] The first communication circuit can determine errors in the first data using a cyclic redundancy check (CRC) check. Furthermore, the first communication circuit can store the CRC check value in memory, and the second communication circuit can receive third data at a second data rate and compare the CRC comparison value included in the third data with the CRC check value to determine communication errors.

[0223] The second communication circuit can receive clock training signals at the second data rate to train the communication clock, and can determine communication errors by checking the clock training pattern in the clock training signals after training is completed.

[0224] The second communication circuit trains the communication clock by receiving a clock training signal via the communication line at a second data rate, and maintains the communication clock by receiving an embedded clock signal via the communication line. Furthermore, it can determine communication errors by comparing the frequency of the communication clock at the training completion time with the frequency of the communication clock at a time point after the training completion time.

[0225] The second communication circuit can evaluate communication performance using a bit error rate (BER) test pattern received at a second data rate. Furthermore, the first communication circuit can receive setting values ​​for the BER test at a first data rate.

[0226] The second communication circuit can receive symbols consisting of N bits (N is a natural number of 2 or greater) via the second data, and can match each symbol with a value consisting of M bits (M is a natural number less than N). Furthermore, the second communication circuit can use other symbols received before or after a symbol to recover an error in a single bit included in that symbol.

[0227] Considering a data processing apparatus, some aspects related to data validity are summarized. The data processing apparatus may include: a first communication circuit that transmits first data and first verification data for the first data via a communication line at a first data rate; and a second communication circuit that transmits second data, including image data for driving pixels of a display panel, via a communication line at a second data rate higher than the first data rate, and transmits second verification data corresponding to the first verification data at the second data rate.

[0228] The first verification data may include a cyclic redundancy check (CRC) value for the first data, and the second verification data may include a CRC comparison value corresponding to the CRC value. Additionally, the second communication circuit may transmit the second data within an active interval included in a frame interval, and may transmit third data including the second verification data within a blanking interval included in a frame.

[0229] The second communication circuit can encode the second data using a limited run-length code (LRLC) method according to a predetermined encoding table.

[0230] The first communication circuit can transmit the bit error rate (BER) test setting value at a first data rate, and the second communication circuit can transmit the BER test pattern at a second data rate.

[0231] In addition, the second communication circuit can match a value consisting of M (M is a natural number) bits with a symbol consisting of N (N is a natural number greater than M) bits, and incorporate the symbol into the second data to transmit the symbol.

[0232] When an error is determined to be related to data validity, the data processing unit and the data driving unit can recover from the error while switching operating modes. Alternatively, when all operations in one mode are completed, the data processing unit and the data driving unit can switch to another mode.

[0233] Figure 16 is a diagram illustrating a mode switching sequence of a display driver according to one embodiment.

[0234] Referring to Figure 16, in the data setting interval T710, the data processing device and the data driving device operate in a first mode, and in the first mode, the P low-speed communication circuit of the data processing device and the D low-speed communication circuit of the data driving device can send / receive setting data at a first data rate.

[0235] When an error occurs in the first mode (LF11), the data processing device and the data driving device can re-enter the first mode.

[0236] When all operations in the data setting interval T710 are performed normally (LP11), the data processing device and the data driving device can switch from the first mode to the second mode and perform operations in the clock training interval T730.

[0237] In the second mode, the data processing device sends a clock training signal at a second data rate, and the data driving device can train a high-speed communication clock to communicate at the second data rate.

[0238] When an error occurs in the second mode (LF12), the data processing device and the data driving device can resume the operation of the first mode after switching to the first mode.

[0239] When all operations in the clock training interval T730 have been performed normally (LP12), the data processing device and the data driving device can switch from the second mode to the third mode and perform operations in the activity interval T750.

[0240] In the third mode, the data processing device sends image data and first control data at a second data rate, and the data driving device can drive the pixels of the display panel according to the image data.

[0241] In the third mode, the data processing device and the data driving device can send image data and first control data in line units, and in this case, when the operation on one line is performed normally (AL1), the same operation on the next line can be performed.

[0242] When an error occurs in the third mode (LF2), the data processing unit and the data driving unit can re-perform clock training after switching back to the second mode. When an error occurs in the third mode, the data processing unit and the data driving unit are switched to the second mode instead of the first mode, and using this sequence, the data processing unit and the data driving unit can shorten the error recovery time. Specifically, since the third mode is the active period, according to this sequence, image quality can be improved by minimizing the time period of screen interruption.

[0243] When all operations in the active range T750 have been performed normally (VB1), the data processing device and the data driving device can switch from the third mode to the fourth mode and perform operations in the blanking range T760.

[0244] In the fourth mode, the data processing device sends the second control data at the second data rate, and the data driving device can apply the settings required to drive the display panel according to the second control data.

[0245] In the fourth mode, the data processing device and the data driving device can send the second control data in virtual row units, and in this case, when an operation on a virtual row is performed normally (VB2), the same operation on the next virtual row can be performed.

[0246] When all operations in the blanking interval T760 have been performed normally (AL2), the data processing device and the data driving device can switch from the fourth mode to the third mode and perform operations in the active interval T750.

[0247] When an error occurs in the fourth mode (LF13), the data processing unit and the data driving unit can switch back to the first mode. When switching to the first mode, the data processing unit and the data driving unit can re-establish most settings from the initial state. Since the fourth mode is performed in the blanking interval T760 without updating the display panel, image quality issues can be minimized even if the recovery time is somewhat long.

[0248] Regarding the data driving device for this sequence, the data driving device may include a D low-speed communication circuit, a D high-speed communication circuit, a D control circuit, and a data driving circuit.

[0249] The D low-speed communication circuit can receive configuration data at a first data rate in the first mode.

[0250] The high-speed communication circuit can train a high-speed communication clock in the second mode to communicate at the second data rate, use the high-speed communication clock to receive image data and first control data in the third mode, and use the high-speed communication clock to receive second control data in the fourth mode.

[0251] The D control circuit can switch the mode to the second mode when the first mode is completed, switch the mode to the third mode when the second mode is completed, switch the mode back to the second mode when an abnormal state is confirmed in the third mode, and switch the mode back to the first mode when an abnormal state is confirmed in the fourth mode.

[0252] In addition, the data driving circuit can drive the pixels of the display panel according to the image data.

[0253] Here, the second data rate can be a value higher than the first data rate.

[0254] When an abnormal state is confirmed in the second mode, the D control circuit can switch the mode back to the first mode.

[0255] The high-speed communication circuit may include a clock recovery circuit, and the configuration data may include the configuration values ​​of the clock recovery circuit.

[0256] The high-speed communication circuit may include an equalizer circuit, and the configuration data may include the configuration values ​​of the equalizer circuit.

[0257] When the first mode is repeated L times (L is a natural number of 2 or greater) or more, the setting value of the equalizer circuit can be changed and received. For example, when the operation of switching from the first mode to the second mode is repeated L times or more within one frame after switching from the first mode to the second mode, the data processing device can change the setting value of the equalizer circuit of the D high-speed communication circuit and send the setting value.

[0258] The data drive device may also include a D-auxiliary communication circuit for transmitting auxiliary communication signals via an auxiliary communication line.

[0259] When the D control circuit detects an abnormal state in the third or fourth mode, the D auxiliary communication circuit can send a signal indicating the abnormal state to the data processing device via an auxiliary communication signal.

[0260] The image data, the first control data, and the second control data are embedded clock signals, and the D high-speed communication circuit can extract the clock signal from the embedded clock signal to maintain the high-speed communication clock.

[0261] When there is no communication clock, the D control circuit can determine the abnormal state.

[0262] The third mode can then be performed in the active interval for updating the display within a frame interval, and the fourth mode can be performed in the blanking interval within a frame interval.

[0263] Regarding the data processing device for this sequence, the data processing device may include a P low-speed communication circuit, a P high-speed communication circuit, and a P control circuit.

[0264] The P-type low-speed communication circuit can transmit configuration data at a first data rate in the first mode.

[0265] The P-type high-speed communication circuit can transmit a clock training signal at a second data rate in the second mode to train the high-speed communication clock, transmit image data and first control data according to the high-speed communication clock in the third mode, and transmit second control data according to the high-speed communication clock in the fourth mode.

[0266] The P control circuit can switch the mode to the second mode when the first mode is completed, switch the mode to the third mode when the second mode is completed, switch the mode to the second mode when an abnormal state is confirmed in the third mode, and switch the mode to the first mode when an abnormal state is confirmed in the fourth mode.

[0267] The second data rate can be higher than the first data rate.

[0268] When an abnormal state is confirmed in the second mode, the P control circuit can switch the mode to the first mode.

[0269] When the switching from the second mode to the first mode is repeated L times (L is a natural number of 2 or greater) or more, the P low-speed communication circuit can change the setting value used for communication at the second data rate and incorporate the changed setting value into the setting data to send the setting value.

[0270] The data processing device may also include an auxiliary communication circuit for receiving auxiliary communication signals via an auxiliary communication line. Additionally, the P control circuit can use the auxiliary communication signals to check for abnormal states in each mode.

[0271] In addition, when the auxiliary communication signal switches from a high-level voltage to a low-level voltage, the P control circuit can identify that an abnormal state has occurred.

[0272] On the other hand, the display driver according to one embodiment can also operate at low power.

[0273] Figure 17 is a diagram illustrating a sequence of low-power operation of a display driver according to one embodiment.

[0274] Referring to Figure 17, in normal mode, the display device can alternately perform operations in the active range T750 and the blanking range T760. Additionally, the display device can refresh the image on the display panel during the active range T750.

[0275] To update the image on the display panel, the data processing device can send image data RGB to the data driving device within the active range T750. The image data RGB can be sent in row units, and to send setting values ​​in row units, the data processing device can also send first control data within the active range T750.

[0276] On the other hand, for low-power operation, the data processing device can send second control data during the blanking interval T760. Furthermore, the second control data may include power-saving control values ​​for low-power operation.

[0277] In normal mode, the power-saving control value can be set to disable D and sent. When the power-saving control value set to disable D is received, the data drive device can control the output circuit to operate normally.

[0278] In order to reduce the refresh rate in power-saving mode, the data processing device can set the power-saving control value to enable E1 and E2 and send the power-saving control value.

[0279] When a power-saving control value set to enable E1 and E2 is received, the data driver can disable certain circuits. For example, the data driver circuitry of the data driver may include a latch circuit that latches image data for each pixel, a digital-to-analog converter (DAC) that converts the output data of the latch circuit into an analog data voltage, and an output buffer that outputs the data voltage to the pixel. Furthermore, the data driver can determine whether the DAC and the output buffer are enabled or disabled based on the power-saving control value.

[0280] When a power-saving control value set to enable E1 and E2 is received, the data driver can also disable the main communication circuit. In this case, since the high-speed communication clock does not resume when the main communication circuit is disabled, the data driver can switch the voltage of the auxiliary communication signal LCK to a low level. The data processing unit recognizes this switching of the auxiliary communication signal LCK voltage and can confirm that the data driver has entered power-saving mode.

[0281] The main communication circuit can receive a clock training signal and train a high-speed communication clock, or it can receive an embedded clock signal and maintain a high-speed communication clock. However, when the main communication signal is not supplied in power-saving mode, the data drive unit cannot maintain a high-speed communication clock. Therefore, before the active range T750 is restarted, the data drive unit can send a clock operation signal CT. Additionally, the data drive unit can retrain the high-speed communication clock using the clock training signal CT, and can notify the data processing unit of the training completion using the auxiliary communication signal LCK.

[0282] When switching from power-saving mode to normal mode, the display device can send the setting data CFG again. The image data RGB can be sent at a second data rate, and the setting data CFG can be sent at a first data rate lower than the second data rate.

[0283] When the operation of receiving and setting data CFG is completed, the data driving device can switch the voltage of the auxiliary communication signal LCK from a low level to a high level.

[0284] The power-saving control value can be used to determine whether to restart the data drive device from the high-speed communication clock after power-saving mode, or to resend / receive configuration data.

[0285] The power-saving control value may include a first power-saving control value and a second power-saving control value.

[0286] Here, the first power-saving control value may include a value that determines whether to enter a power-saving mode. For example, when the first power-saving control value is set to enabled, the data drive device can enter a power-saving mode, while when the first power-saving control value is set to disabled, the data drive device can operate in normal mode without entering a power-saving mode.

[0287] Next, the second power-saving control value can indicate which process should be restarted after the power-saving mode is completed. For example, if the second power-saving control value is a value indicating the display mode, the data processing device and the data driving device can restart from the clock training process used for high-speed communication. Furthermore, when the second power-saving control value is a value indicating the setting data mode, the data processing device and the data driving device can restart from the process that sends and receives setting data via low-speed communication.

[0288] Considering the data driving device, regarding aspects related to the aforementioned power-saving operation, the data driving device may include a D main communication circuit and a data driving circuit. The D main communication circuit can receive image data and first control data in the active range via the main communication line, and can receive second control data in the blanking range. Furthermore, the data driving circuit can drive the pixels of the display panel according to the image data, and can determine the power-saving operation of the output circuit based on the power-saving control value included in the second control data.

[0289] The data drive circuit can also control the power-saving operation of the D main communication circuit according to the power-saving control value.

[0290] The data drive device may also include a D auxiliary communication circuit, which transmits auxiliary communication signals via an auxiliary communication line and indicates that the D main communication circuit has entered a power-saving mode via the auxiliary communication signals.

[0291] The D main communication circuit receives a clock training signal to train a high-speed communication clock for receiving image data, and after training the high-speed communication clock, an auxiliary communication signal can instruct the D main communication circuit to enter normal mode.

[0292] The power-saving control values ​​may include a first power-saving control value that controls the power-saving operation of the D main communication circuit and a second power-saving control value that controls the process of switching from power-saving mode to normal mode.

[0293] When the second power-saving control value is the first value, the D main communication circuit can receive the clock training signal to train the high-speed communication clock used to receive image data.

[0294] When the second power-saving control value is the second value, the D main communication circuit can wait to receive data at a first data rate that is lower than the second data rate used to receive image data.

[0295] The D main communication circuit can receive the corresponding clock training signal at a second data rate after receiving the setting data at a first data rate.

[0296] The D main communication circuit can receive symbols consisting of N (N is a natural number of 2 or greater) bits and can match each symbol with a power-saving control value consisting of M (a natural number less than N) bits.

[0297] The data driving circuit includes a latch circuit that latches the image data of each pixel, a digital-to-analog converter (DAC) that converts the output data of the latch circuit into an analog data voltage, and an output buffer that outputs the data voltage to the pixel. The DAC and the output buffer can be turned on / off according to the power saving control value.

[0298] Considering the data processing device, regarding aspects related to the aforementioned power-saving operation, the data processing device may include an image data processing circuit and a P main communication circuit. The image data processing circuit can process image data used to drive the pixels of the display panel. Additionally, the P main communication circuit can transmit image data and first control data via the main communication line during the active period, and transmit second control data including power-saving control values ​​during the blanking period.

[0299] The data processing apparatus may also include a P-auxiliary communication circuit for receiving auxiliary communication signals via an auxiliary communication line. Additionally, the P-main communication circuit sends a power-saving control value to instruct the data drive device to operate in power-saving mode, and the P-auxiliary communication circuit confirms that the data drive device has entered power-saving mode via an auxiliary communication signal.

[0300] When it is confirmed that the data drive device has entered power saving mode, the P main communication circuit can operate in power saving mode for a predetermined time.

[0301] The P main communication circuit can send a clock training signal after a predetermined time, and can send image data when the data driving device is confirmed to be clock trained by the P auxiliary communication circuit.

[0302] After sending the power-saving control value to indicate the normal operation of the data drive device, when the P auxiliary communication circuit confirms that the data drive device has entered the power-saving mode, the P main communication circuit can send a clock training signal to the data drive device.

[0303] The power-saving control value may include a first power-saving control value for controlling the power-saving operation of the data drive device and a second power-saving control value for controlling the process of switching from power-saving mode to normal mode. After a predetermined time has elapsed after the second power-saving control value is set to the first value, the P main communication circuit may send a clock training signal to the data drive device.

[0304] After a predetermined time has elapsed since the second power-saving control value was set to the first value, the P main communication circuit can transmit setting data at a first data rate that is lower than the second data rate used to transmit image data.

[0305] As described above, according to this embodiment, the validity of data in data communication is checked in different ways according to the type of data sent and received and the operating mode, thereby improving the accuracy and efficiency of data verification. According to this embodiment, power consumption during data communication can be reduced, and the possibility of malfunctions such as incorrectly entering power-saving mode due to communication errors can be minimized. Furthermore, according to this embodiment, even if one of multiple data driving devices malfunctions, the entire data driving device can be initialized simultaneously, and the operating modes of the data driving device and the data processing device can be easily synchronized. Additionally, according to this embodiment, the management of the operating modes of the data driving device and the data processing device can be facilitated, and error recovery time can be minimized.

[0306] Cross-references to related applications

[0307] This application claims priority to Korean Patent Application No. 10-2021-0069767, filed May 31, 2021, and Korean Patent Application No. 10-2022-0042268, filed April 5, 2022, the entire contents of which are incorporated herein by cross-reference.

[0308] 100: Display device 110: Data processing device 120: Data-driven device 120a: Data-driven integrated circuit, first data-driven integrated circuit 120b: Data driver integrated circuit, second data driver integrated circuit 120c: Data driver integrated circuit, third data driver integrated circuit 120d: Data-driven integrated circuit, fourth data-driven integrated circuit 130: Display panel 140: Gate drive device 310: Signal Combination Circuit 320: Status signal generation circuit 330: Performance Evaluation Feedback Circuit 410:P Main Communication Circuit 411:P High-speed communication circuit 412: Packaging Device 413: Mixer 414: Encoder 415: First serializer 416:P Low-speed communication circuit 417: Set up data processing circuit 418: Second serializer 420:P Auxiliary Communication Circuit 421:P Auxiliary Communication Signal Processing Circuit 422:P Auxiliary Communication Control Circuit 430:P control circuit 440:P memory 450: Image data processing circuit 610:D Main Communication Circuit 611:D High-Speed ​​Communication Circuit 612: First Deserializer 613: Decoder 614: Mixer 615: Unpacker 616:D Low-Speed ​​Communication Circuit 617: Second Deserializer 618: Set up data storage circuit 620:D Auxiliary Communication Circuit 621:D Auxiliary Communication Control Circuit 622:D Auxiliary Communication Signal Processing Circuit 630:D Control Circuit 640:D Memory 650: Data drive circuit 1410: First symbol 1420: Second symbol 1510: Third symbol AL1: Operating Steps AL2: Operating Procedures CFG: Settings CFGD: Set the main data packet CFGE: Sets the end of the data packet CFGS: Set data to start packetization CLA: Communication line, second communication line, auxiliary communication line CLAa: First Auxiliary Communication Line CLAb: Second Auxiliary Communication Line CLAc: Third Auxiliary Communication Line CLAd: Fourth Auxiliary Communication Line CLAF: Auxiliary Communication Feedback Line CLM: Communication line, first communication line, main communication line CT: Clock training (Figure 7), clock training pattern (Figures 9-10), clock operation signal (Figure 17) CTRAD: First Control Data Body Packet CTRAS: Line data begins to be packetized. CTRBD: Second Control Data Body Encapsulation CTRBS: Control data begins packetization D: Disable DL: Data Line DMMD: Virtual Packet E1: Enable E2: Enable GCS: Gate Control Signal GL: Gate line H: High-level position HDR: Sets the header packet L: Low level LCK: Second communication signal, auxiliary communication signal LCK': Auxiliary communication signal LKa: First Auxiliary Communication Signal LCKb: Second Auxiliary Communication Signal LCKc: Third Auxiliary Communication Signal LCKd: Fourth auxiliary communication signal, auxiliary communication signal LCKf: Auxiliary communication feedback signal LF2: Operating Procedures LF11: Operating Procedures LF12: Operating Procedures LF13: Operating Procedures LP11: Operating Procedures LP12: Operating Procedures m:m items MDT: first communication signal, main communication signal P: pixel P1: Part, First Part P2: Part, Second Part P3: Part 3 P4: Part 4 P5: Part 5 P6: Part 6 P710: Pre-packet P720: Setting Data Packets P730: High-voltage packet or low-voltage packet P740: Clock Training Pattern P750: Line Data Packet P760: Control Data Packets P810: Set up data packetization P820: Set Data Header Packet P830: Set Data Header Verification Packet P840: Setting the Data Body Packet P850: Set Data Body Verification Packet P860: Set data end packet P910: Line data begins to be packetized P920: First Control Data Body Encapsulation P930: Image Data Packet P940: Clock Training Pattern P1010: Control data begins to be packetized P1020: Second Control Data Body Encapsulation P1030: Verification Packet P1040: Virtual Packet P1050: Clock Training Pattern PXLD: Image Data Packet RGB: Image data S1102: Steps S1104: Steps S1106: Steps S1108: Steps S1110: Steps S1112: Steps S1114: Steps S1116: Steps SCN: Scan Signal SIG1: Status signal, internal status signal SIG2: Performance Evaluation Feedback Signal T710: Set data range T720: Display Range T730: Clock Training Zone T740: Frame Interval T750: Activity Range T760: Blanking interval TML1: Auxiliary communication input terminal, terminal TML2: Auxiliary communication output terminal, terminal UI: Unit Pulse VB1: Operation Steps VB2: Operation Steps VCC: Drive voltage VD: Data Voltage

Claims

1. A data driving device, comprising: A low-speed communication circuit that receives setup data at a first data rate via a first communication line; A high-speed communication circuit that operates according to setting values ​​included in the setting data and receives image data via the first communication line at a second data rate higher than the first data rate; and a data driving circuit that drives the pixels of the display panel according to the image data.

2. The data driving device according to claim 1, wherein, The high-speed communication circuit includes a clock recovery circuit that recovers a high-speed communication clock from an embedded clock signal received at the second data rate. The high-speed communication circuit extracts the image data from the embedded clock signal based on the high-speed communication clock. The setting data includes setting values ​​of the clock recovery circuit.

3. The data driving device according to claim 2, wherein, The high-speed communication circuit includes a deserializer, and the deserializer parallelizes the image data extracted from the embedded clock signal in byte or symbol units.

4. The data driving device according to claim 3, wherein, The high-speed communication circuit includes a decoder, which decodes the image data encoded using DC balanced codes or limited run-length codes based on a decoding table stored in memory.

5. The data driving device according to claim 4, wherein, The high-speed communication circuit includes a descrambler, which restores the image data, which has been mixed according to a specified protocol, to its original state.

6. The data driving device according to claim 4, wherein, The high-speed communication circuit includes a depacketizer, wherein the depacketizer arranges the image data in pixel units and sends the arranged image data to the data driving circuit.

7. The data driving device according to claim 1, wherein, The low-speed communication circuit includes a deserializer, wherein the deserializer parallelizes the communication signals received in serial form via the first communication line and decodes the communication signals using Manchester code.

8. The data driving device according to claim 7, wherein, The communication signal includes multiple parts, wherein, among the multiple parts, the first part includes a low-speed communication clock, the second part includes a start signal, the third part includes a message header, the fourth part includes the setting data, the fifth part includes an error check value, and the sixth part includes an end signal.

9. The data driving device according to claim 1, further comprising: A status signal transmitting circuit transmits status signals for the high-speed communication circuit via a second communication line distinct from the first communication line.

10. The data driving device according to claim 9, further comprising: A performance evaluation feedback circuit sends a performance evaluation feedback signal for a communication evaluation result, which is obtained based on the recognition rate of a test pattern received via the first communication line.

11. The data driving device according to claim 10, further comprising: A signal combining circuit that combines the status signal with the performance evaluation feedback signal and sends the combined signal to the second communication line.

12. A data processing apparatus, comprising: Image data processing circuit, which processes image data used to drive the pixels of the display panel; A low-speed communication circuit that transmits setting data for communication at the high-speed communication rate via a first communication line at a low-speed communication rate lower than the high-speed communication rate; and a high-speed communication circuit that, after transmitting the setting data, transmits the image data via the first communication line at the high-speed communication rate.

13. The data processing apparatus according to claim 12, wherein, In the high-speed communication circuit, each frame time is divided into an active interval and a blanking interval. The image data and the first control data are transmitted in the active interval, and the second control data is transmitted in the blanking interval. The first control data includes control values ​​applied in row units or pixel units of the display panel, and the second control data includes control values ​​applied in time periods longer than the row units or control values ​​applied in frame units.

14. The data processing apparatus according to claim 12, wherein, The high-speed communication circuit includes: a packetizer that generates transmission data by packetizing at least one of the image data, first control data, and second control data; a code mixer that mixes some or all of the transmission data; an encoder that encodes the transmission data using DC balanced code or limited run-length code; and a serializer that converts the transmission data into a serialized form to form a transmission stream.

15. The data processing apparatus according to claim 14, wherein, The serializer distributes the transmission data to each of two or more pairs to transmit the distributed transmission data.

16. A display panel driving device, comprising: The first communication line is used for low-voltage differential communication. A data processing device for transmitting setting data to a first communication line at a low-speed communication rate; and a plurality of data driving devices for performing high-speed communication via the first communication line at a high-speed communication rate higher than the low-speed communication rate, setting a high-speed communication environment according to setting values ​​included in the setting data, receiving image data via the high-speed communication, and driving pixels of a display panel.

17. The display panel driving device according to claim 16, further comprising: A second communication line is used to send and receive status signals. When an anomaly is detected in the high-speed communication, each data driving device sends the status signal to the data processing device via the second communication line.

18. The display panel driving device according to claim 17, wherein, The first communication line connects the data processing device and each data driving device in the data driving device in a one-to-one manner, and the second communication line connects the data processing device and the data driving devices in a cascaded manner.

19. The display panel driving device according to claim 16, wherein, After the driving voltage has been supplied to the data processing device and the data driving device, the setting data is sent from the data processing device to the data driving device in the setting data interval.

20. The display panel driving device according to claim 19, wherein, After the setting data has been sent, the image data is sent from the data processing device to the data driving device in the display area.

Images