Etching metal during processing of a semiconductor structure

Abstract

In some embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes using the patterned layer as an etching mask and patterning the copper layer by performing a cyclic etching process to form recesses in the copper layer. The cyclic etching process includes, in a first etching step, forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas. The passivation layer replaces at least a portion of the surface layer of the copper layer. The cyclic etching process includes, in a second etching step, subsequently etching the passivation layer using a first plasma comprising a noble gas. Each cycle of the cyclic etching process extends the recesses in the copper layer.

Description

Technical Field

[0001] This disclosure is generally about semiconductor manufacturing, and in a particular embodiment about metal etching during the processing of a semiconductor structure. [Cross-reference to related applications]

[0002] This application claims priority to U.S. Nonprovisional Application No. 17 / 339,436, filed on June 4, 2021, the entire system of which is incorporated herein by reference. Prior Technology

[0003] Typically, semiconductor devices, such as integrated circuits (ICs), are manufactured by sequentially depositing dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then patterning them using photolithography and etching. This forms structures that serve as circuit components (e.g., transistors, resistors, and capacitors) and interconnect components (e.g., wires, contacts, and vias). Examples of metals used to form conductive features (e.g., conductive features in a metal layer) in a semiconductor device include copper and aluminum.

[0004] The semiconductor industry has repeatedly reduced the smallest feature size of semiconductor devices to within nanometers to increase component stacking density. This miniaturization, reaching the nanometer level, has exacerbated various challenges associated with semiconductor manufacturing. Manufacturing processes, including plasma and other processes, are expected to uniformly provide precise dimensions (e.g., linewidth, etch depth, and film thickness) across a wide (e.g., 300 mm) wafer, as well as precisely controlled features such as conformality, anisotropy, selectivity, surface and line edge roughness, and edge profiles (typically at the atomic scale). Summary of the Invention

[0005] In some embodiments, a semiconductor structure processing method includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed above a substrate. The method includes using the patterned layer as an etching mask and patterning the copper layer by performing a cyclic etching process to form recesses in the copper layer. The cyclic etching process includes, in a first etching step, forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas. The passivation layer replaces at least a portion of the surface layer of the copper layer. The cyclic etching process includes, in a second etching step, subsequently etching the passivation layer using a first plasma comprising a noble gas. Each cycle of the cyclic etching process extends the recesses in the copper layer.

[0006] In some embodiments, a method of processing a semiconductor structure includes receiving a substrate on which a copper-containing layer is formed. The method includes performing a cyclic etching process to progressively etch a portion of the copper-containing layer. The copper-containing layer has a target exposure surface that defines the portion of the copper-containing layer to be etched. The cyclic etching process includes, in a chlorine exposure step, exposing the substrate having the copper-containing layer to chlorine gas (Cl₂) to convert a portion of the copper-containing layer into a complex copper chloride (CuCl) structure. The cyclic etching process includes, in a plasma etching step, subsequently exposing the substrate having the copper-containing layer to a first plasma. The first plasma comprises a precious gas and is directed to the target exposure surface of the copper-containing layer, possessing sufficient energy to remove at least a portion of the CuCl structures from the copper-containing layer.

[0007] In some embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes using the patterned layer as an etching mask and patterning the copper layer by performing a cyclic etching process to progressively form a recess in the copper layer. The cyclic etching process includes, in a chlorine exposure step, exposing the substrate having the copper layer to chlorine gas (Cl₂), causing a plurality of CuCl structures to form at one or more exposed surfaces of the copper layer. The cyclic etching process includes, in a plasma etching step, subsequently exposing the substrate having the copper layer to an argon-containing plasma, the argon-containing plasma being directed to a target exposed surface of the copper layer and having sufficient energy to remove at least a portion of the CuCl structures at the one or more exposed surfaces of the copper layer from the copper layer, causing the recess to extend into the copper layer. Initially, in the chlorine exposure step, the one or more exposed surfaces of the copper layer include the target exposed surface, which is the top surface of the copper layer located at the bottom of the recess. In subsequent steps of the plasma etching process, the one or more exposed surfaces of the copper layer include the target exposed surface and the plurality of sidewall surfaces of the copper layer in the recess. Simple Explanation of the Diagram

[0008] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following embodiments in conjunction with the accompanying drawings, wherein:

[0009] Figures 1A-1C illustrate cross-sectional and plan views of a semiconductor structure during processing according to certain embodiments of the present disclosure;

[0010] Figures 2A-2E illustrate cross-sectional views of a semiconductor structure during a cyclic etching process for processing a semiconductor structure, according to certain embodiments of the present disclosure;

[0011] Figures 3A-3C illustrate example details of a semiconductor structure during a cyclic etching process for etching metal, according to certain embodiments of the present disclosure;

[0012] Figure 4 illustrates example methods for processing semiconductor structures according to certain embodiments of this disclosure;

[0013] Figure 5 illustrates example methods for processing semiconductor structures according to certain embodiments of this disclosure; and

[0014] Figure 6 illustrates a general schematic diagram of an example plasma processing system according to certain embodiments of the present disclosure. Implementation

[0015] For years, and even today, chip manufacturers have used aluminum to form conductive features in semiconductor devices, such as wires, conductive contacts, and conductive vias. As device sizes continue to shrink, using aluminum for certain conductive features becomes increasingly challenging. For example, the resistivity of a metal increases as the critical size of wires and vias decreases, which can lead to an increase in the resistive-capacitive (RC) delay of interconnects. Copper typically exhibits a lower resistivity than aluminum. Furthermore, copper is likely more durable than aluminum, exhibiting higher electromigration resistance. This greater electromigration resistance allows higher currents to flow through a copper conductor of a given size compared to an aluminum conductor of the same dimensions. At smaller feature sizes, the ability of copper conductors to carry higher currents can be advantageous. Joule heating associated with electromigration can further exacerbate it; therefore, metals with lower resistivity may be preferable.

[0016] Other metals, such as gold and silver, offer similar advantages to copper, but are more expensive. Given these advantages, copper has become, and remains overall, the preferred choice for forming conductive features in semiconductor devices, particularly in interconnect layers.

[0017] However, using copper in semiconductor devices, whether for interconnects or otherwise, presents challenges. For example, etching copper using techniques applicable in semiconductor manufacturing and mass production environments can be difficult.

[0018] Traditionally, copper structures in semiconductor devices are formed using additive processes rather than subtractive processes. For example, damascene or dual damascene processes can be used to form copper conductive features. Damascene is an additive process that involves etching openings in the layer (e.g., a dielectric layer) where the copper conductive features are to be formed, then filling these openings with copper, typically accompanied by the deposition of one or more barrier layers and one or more intermediate layers, and / or performing subsequent etching (e.g., chemical mechanical polishing). Damascene presents several challenges for smaller device sizes (including the inability to achieve certain tiny pitch dimensions and poor gap filling in damascene recesses), and many of the processes involved in damascene can damage other materials, such as dielectric materials (e.g., low-k materials). Furthermore, damascene involves complex etch integration and includes the formation of etch-stop barrier (capping) layers, which consume valuable size budgets, and this problem is exacerbated at smaller node sizes.

[0019] Attempts to use subtractive etching to form copper conductive features have presented other challenges.

[0020] For example, one subtractive method for etching copper involves exposing the copper layer to a chloride plasma, which forms copper chloride salts on the surface of the copper layer to be etched. These salts may be non-volatile and readily grow. The resulting salt layer is then removed by wet removal. This wet removal of the salt layer involves exposing the semiconductor substrate to non-selective chemicals, meaning that these chemicals may unintentionally and undesirably etch materials other than copper, potentially causing surface damage to the resulting copper structure and other surfaces. Furthermore, salt growth is isotropic and not self-limiting when mediated by plasma and chloride radicals. Moreover, such a process is not feasible for mass production.

[0021] As another example of a subtractive method for etching copper, continuous plasma etching of copper is also problematic, with the resulting morphology being a key issue. Plasma processes using ions to continuously remove copper chloride formed during the exposure of copper to chlorine plasma (e.g., removing copper chloride at a rate faster than the rate at which copper chloride can accumulate) can result in degraded morphology due to low effective chlorine coverage. In this case, etching byproducts may be non-volatile and may require significant ion energy. Removal of copper chloride can generate sputtering and mixtures of various chemical components. For example, etching copper using continuous reactive ion etching (RIE) processes may employ high temperatures that cause the copper to react even with the plasma. However, these high temperatures can damage semiconductor features. For example, continuous plasma processes and the associated high temperatures can negatively impact the forming IC device (e.g., via dopant diffusion or other undesirable effects), cause etch masks covering the copper layer (e.g., via patterned photoresist layers) (e.g., affecting the contours of etched features), and / or cause stress migration at lower layers. Furthermore, some dry etching processes use chlorine, which can contaminate or damage the copper. Furthermore, copper may be redeposited during continuous processing, which could exacerbate surface roughness and etching front profile issues.

[0022] For these and possibly other reasons, the combination of copper and chlorine was largely considered impractical.

[0023] At least in part, due to the lack of feasible subtractive etching processes for etching copper and forming copper conductive features, additive damascene processing remains the primary method for forming copper conductive features, despite the numerous associated problems with damascene processing. Therefore, the semiconductor manufacturing industry has once again shown interest in subtractive copper etching processes, as traditional dual damascene methods have reached, or may soon reach, limitations in the use of smaller feature sizes.

[0024] In some embodiments of this disclosure, a cyclic etching process provides a subtractive process for progressively etching a copper layer. For example, a cyclic etching process can be used to etch one or more recesses in a copper or other metal layer. As described in more detail below, the cyclic etching process of embodiments of this disclosure is not a single plasma or other etching step, but may include repeatedly performing two main steps to progressively form a feature in a copper (or other metal) layer: a passivation layer formation step (e.g., a chlorine exposure step), which forms a passivation layer at the exposed surface of the copper layer by exposing the exposed surface to chlorine gas, for example, in a plasma or thermal treatment; and an etching step, which etches the passivation layer to remove a portion of the copper layer (e.g., forming a recess in the copper layer, and ultimately forming a feature of the copper layer, such as a conductive feature). In some embodiments, the cyclic etching process for etching copper can be used in a mass production environment.

[0025] Figures 1A-1C illustrate cross-sectional and plan views of the semiconductor structure 104 during process 100 for processing the semiconductor structure 104 according to certain embodiments of the present disclosure. In the illustrated examples, process 100 includes stages 102a-102f for processing the semiconductor structure 104. The semiconductor structure 104 is merely one example of a structure that can be processed according to the disclosed techniques, and the present disclosure contemplates processing any suitable semiconductor device. Throughout this disclosure, "semiconductor structure" may also be referred to as a semiconductor device, substrate, or semiconductor wafer (or simply wafer).

[0026] In stage 102a, the semiconductor structure 104 includes a substrate 106, a copper-containing layer 108 formed over the substrate 106, and a patterned layer 110 (the layer to be patterned in stage 102a) formed over the copper-containing layer 108 and the substrate 106. While these specific layers are shown and described, this disclosure also takes into account semiconductor structures 104 with any suitable layers. For example, the semiconductor structure 104 may include one or more intermediate layers between the substrate 106 and the copper-containing layer 108 and / or between the copper-containing layer 108 and the patterned layer 110.

[0027] Substrate 106 may be formed using any suitable semiconductor manufacturing steps or combinations thereof. Substrate 106 may comprise silicon, silicon germanium (SiGe), silicon carbide (SiC), compound semiconductors (e.g., gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP), etc.), or combinations thereof. This disclosure takes into account substrate 106 comprising any suitable material. Substrate 106 may comprise silicon-on-insulator (SOI) structures, semiconductor wafers (e.g., silicon wafers), or wafer-derived grains. In some embodiments, a portion or all of substrate 106 may be amorphous, polycrystalline, or monocrystalline. Substrate 106 may be doped, undoped, or comprise both doped and undoped regions.

[0028] The substrate 106 may comprise any suitable type of substrate. In some embodiments, the substrate 106 includes one or more IC elements, such as one or more transistors, one or more diodes, one or more capacitors, one or more resistors, and / or other electronic components. These IC elements may have any suitable design, including any suitable planar or non-planar and two-dimensional or three-dimensional (e.g., FinFET, GAA FET, etc.) design. In some embodiments, these IC elements may be front-end process (FEOL) devices.

[0029] In addition, substrate 106 may include one or more metallization layers. In some embodiments, regardless of whether a metallization layer is considered (or included), substrate 106 includes one or more conductive features, such as one or more conductive contacts, one or more conductive vias, one or more wires, and / or one or more other conductive features.

[0030] A copper-containing layer 108 is formed over the substrate 106. In some embodiments, the copper-containing layer 108 is made of pure copper (100% copper); however, this disclosure considers a copper-containing layer 108 that includes copper and is accompanied by certain amounts of one or more other materials. In some embodiments, the copper-containing layer 108 includes 100% copper, or includes copper and less than about 20 ppm of one or more other materials (e.g., sulfur, chlorine, carbon, nitrogen, silver, aluminum, or another material). The copper-containing layer 108 may include a metal or a metal alloy, and for the purposes of this embodiment, metals and metal alloys are used interchangeably.

[0031] The copper-containing layer 108 is a layer to be patterned into one or more features, said features being conductive features in a semiconductor device manufactured via the processing of semiconductor structure 104. The features etched into the copper-containing layer 108 in this disclosure are contemplated as any suitable features. For example, while this disclosure primarily describes "recesses," it will be understood that other suitable features can be formed in the copper-containing layer 108 using embodiments of this disclosure, including (whether or not considered "recesses") lines, holes, trenches, vias, and / or other suitable structures. In some embodiments, the copper-containing layer 108 is intended to be part of a back-end process (BEOL) stack, such as a metallization layer of a BEOL stack.

[0032] The copper-containing layer 108 can be deposited using any technique suitable for the material to be deposited. Suitable deposition processes for forming the copper-containing layer 108 may include spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, or other processes.

[0033] In some embodiments, one or more pad layers (e.g., on the surface of substrate 106) may be deposited prior to the deposition of the copper-containing layer 108. The pad layers (also referred to as barrier layers) may include, for example, titanium nitride (TiN) layers and / or tantalum nitride (TaN) layers, and may have a thickness of about 0.3 to about 3.5 nm. Any suitable number of pad layers may use any suitable type of material. In some embodiments, the one or more pad layers may be considered part of substrate 106 (e.g., as a surface layer of substrate 106). In some embodiments, the one or more pad layers may reduce or eliminate copper diffusion to another layer (e.g., to other portions of substrate 106), and / or be used as an etch stop layer at appropriate manufacturing stages. The one or more pad layers may be capping layers, such as a cobalt (Co)-tungsten (W)-phosphorus (P) (CoWP) capping layer or a Co-W-boron (B) (CoWB) capping layer.

[0034] Semiconductor structure 104 includes a patterned layer 110. In the state shown in stage 102a, since the patterned layer 110 has not yet been patterned, it is a layer to be patterned. In some embodiments, the patterned layer 110 is made of a material suitable for use as a hard mask. For example, the patterned layer 110 may include organic (amorphous carbon, organosilicon, etc.) or inorganic materials (silicon nitride (SiN), silicon oxynitride (SiON), TiN, etc.). In some embodiments, the patterned layer 110 includes multiple material layers. The patterned layer 110 can be deposited using any technique suitable for the material to be deposited. Suitable deposition processes may include spin coating, CVD, PECVD, ALD, PVD, chemical solution deposition, or other processes. For example, the patterned layer 110 may be or include an amorphous carbon layer formed by CVD or ALD processing.

[0035] Moving to stage 102b, patterned layer 110 is patterned to provide a mask suitable for forming features (e.g., recesses) in the underlying layer (copper-containing layer 108 in this example). This disclosure contemplates patterned layer 110 in any suitable manner.

[0036] As an example only, a photoresist layer may be formed on the patterned layer 110 (e.g., before patterning the patterned layer 110), and the photoresist layer may be patterned according to a desired pattern of the patterned layer 110 to facilitate the formation of corresponding features in the patterned layer 110. The photoresist layer may be patterned in any suitable manner, such as using extreme ultraviolet lithography or any other suitable lithography technique.

[0037] In some embodiments, one or more intermediate layers may be formed between the photoresist layer and the patterned layer 110 (before the patterned layer 110 is patterned) for various purposes. These intermediate layers may include, for example, a SiON layer, an organic dielectric layer, a silicon antireflective coating (SiARC) or other antireflective coating, and / or any other suitable intermediate layer. While these specific intermediate layers are described, the semiconductor structure 104 may not have these intermediate layers or may include different intermediate layers (with or without these exemplary intermediate layers).

[0038] Patterned layer 110 can be formed by performing an etching process and using a photoresist layer (and any suitable intermediate layer) as an etching mask. Through this technique, the pattern defined by the photoresist layer is transferred to patterned layer 110. The photoresist layer and any intermediate layer can be removed during a portion of this process or can be removed subsequently. In some embodiments, patterned layer 110 is used as an etching mask when forming features from copper-containing layer 108. In other words, features of patterned layer 110 can drive the retention of corresponding features in copper-containing layer 108 during subsequent etching processes as described below. For example, patterned layer 110 includes recesses 112, which will be used in a later stage of process 100 to form corresponding recesses 112 in copper-containing layer 108. Furthermore, patterned layer 110 can help retain a portion of copper-containing layer 108 in subsequent etching steps to form those retained conductive features (e.g., wires, vias, or contacts).

[0039] Moving on to the next stage after stage 102b in process 100, as shown in FIG1B, the disclosed embodiments use a cyclic etching process 113 to pattern the copper-containing layer 108, in which the patterned layer 110 is used as an etching mask. In the embodiments shown in FIG1A-1C (particularly FIG1B), the cyclic etching process 113 includes two main steps. For example, as shown in stage 102c, the first step is a passivation layer formation step, in which a passivation layer is formed on one or more exposed surfaces of the copper-containing layer 108 using chlorine gas. For example, as shown in stage 102d, the second step is an etching step, in which the passivation layer is removed from at least a portion of the copper-containing layer 108, thereby removing at least a portion of the copper-containing layer 108. Stages 102c and 102d are described in more detail below. In some embodiments, surface oxides may be present on the exposed surfaces of the copper-containing layer 108 before stage 102c is performed one or more times. Suitable removal processes (e.g., argon sputtering steps) may be performed to remove the surface oxides to a large extent or completely.

[0040] In stage 102c, a passivation layer 116 is formed at least a portion of the copper-containing layer 108 during the first etching step of the cyclic etching process 113. In some embodiments, the passivation layer 116 is formed on the exposed surface of the copper-containing layer 108. During the initial operation of the cyclic etching process 113, the exposed surface of the copper-containing layer 108 may be the top surface 114 of the copper-containing layer 108 (e.g., at the bottom of the recess in the patterned layer 110 that exposes the copper-containing layer 108), and the passivation layer 116a may be formed on the exposed top surface of the copper-containing layer 108. During subsequent cyclic etching processes 113, additional surfaces of the copper-containing layer 108 are exposed, and the passivation layer 116 may also be formed on those additional exposed surfaces of the copper-containing layer 108 (e.g., as passivation layers 116b and 116c, illustrated and described later). For ease of description, the passivation layer 116 may be collectively referred to as passivation layer 116, while in some cases it may be appropriate to specifically refer to it as passivation layer 116a, 116b and / or 116c for a given purpose. For example, the formation of passivation layer 116 on the sidewall surface of copper layer 108 is illustrated and described below with reference to FIG2A-2E.

[0041] Passivation layer 116 may be formed by exposing semiconductor structure 104 (and the exposed surface of copper-containing layer 108, such as top surface 114) to a chlorine treatment 115 including chlorine gas (Cl2). Passivation layer 116 may include copper atoms at the exposed surface of copper-containing layer 108 (e.g., top surface 114) and compounds formed by the Cl2 exposed to those copper atoms. Passivation layer 116 may include CuyClx structures formed at one or more exposed surfaces of copper-containing layer 108 (e.g., top surface 114). For example, one or more chlorine particles may bond to one or more copper atoms at or near the surface of copper-containing layer 108 to form CuyClx structures (e.g., partial or soft surface states) at or near the surface of copper-containing layer 108, thereby forming passivation layer 116. Therefore, the passivation layer 116 consumes at least a portion of the copper-containing layer 108, such that subsequent etching of the passivation layer 116 (e.g., in stage 102d of the cyclic etching process 113) removes a portion of the copper-containing layer 108. For the formed Cu yCl x structure, y and x are integers greater than or equal to 1. In some embodiments, one or more of the following holds: 1 ≤ y ≤ 6; or 1 ≤ x ≤ 6. As just a few specific examples, the formed Cu yCl x structure may include CuCl, CuCl 2, CuCl 3, CuCl 4, Cu 2Cl, and / or Cu 3Cl. It should be understood that these y and x values ​​and their combinations are provided only as examples.

[0042] Neutral chlorine gas (Cl₂) can bind to copper in a self-limiting manner. Exposing the exposed surface of the copper-containing layer 108 to chlorine gas can form a self-limiting passivation layer 116 of chlorine and copper compounds at the exposed surface of the copper-containing layer 108. In some embodiments, exposing the exposed surface of the copper-containing layer 108 to chlorine gas can form a monolayer of chlorine and copper compounds at the exposed surface of the copper-containing layer 108. It should be understood that a monolayer does not necessarily imply 100% chlorine and copper compounds.

[0043] The passivation layer 116 may be formed in any suitable manner. This disclosure contemplates exposing the semiconductor structure 104 (and the exposed surface containing the copper layer 108) to a chlorine treatment 115 (e.g., chlorine gas) in any suitable manner, including, for example, using heat treatment, plasma treatment, or any other suitable type of treatment. In other words, the chlorine treatment 115 may be implemented as a heat treatment, plasma treatment, or any other suitable type of treatment.

[0044] In some embodiments, the chlorine treatment 115 is a heat treatment that includes exposing the semiconductor structure 104 (and the exposed surface of the copper layer 108) to chlorine gas at a suitable temperature, so that the Cu yCl x structure is formed on one or more exposed surfaces of the copper layer 108 (e.g., top surface 114).

[0045] In some embodiments, the chlorine treatment 115 is a plasma treatment, which includes forming a plasma from chlorine gas and exposing the semiconductor structure 104 (and the exposed surface of the copper layer 108) to the generated plasma chlorine gas, so that a Cu yCl x structure is formed on one or more exposed surfaces (e.g., top surface 114) of the copper layer 108.

[0046] According to a particular embodiment, the process used to form the passivation layer 116 can be anisotropic or isotropic. Anisotropic processing (e.g., anisotropic plasma processing) may result in the passivation layer 116 being formed only on certain exposed surfaces of the copper-containing layer 108, or alternatively, may result in the passivation layer 116 being formed at different thicknesses on different surfaces of the copper-containing layer 108 as required. Isotropic processing (e.g., isotropic plasma processing or thermal processing) may form the passivation layer 116, wherein the passivation layer 116 has a substantially uniform (but not necessarily identical) thickness on all possible exposed surfaces of the copper-containing layer 108.

[0047] In transition phase 102d, during the second etching step of cyclic etching process 113, some or all of the passivation layer 116 is etched to gradually form / extend the recesses 112 in the copper-containing layer 108. In some embodiments, the etching process of the passivation layer 116 is a plasma etching process, wherein the plasma etching process uses a plasma generated from an inert gas (e.g., argon) that selectively etches the passivation layer 116 relative to copper.

[0048] In some embodiments (e.g., where the objective is to extend the recess 112 through the substrate 106), the etching step of stage 102d is designed to be selective, removing a portion of the copper-containing layer 108 to complete the recess 112, but not etching (or etching only minimally) the top material of the substrate 106 when the recess 112 opens to the substrate 106. Therefore, in this example, the etching step of the cyclic etching process 113 is designed to terminate automatically after the recess 112 in the copper-containing layer 108 is fully formed, such that the top surface of the substrate 106 is exposed at the bottom of the recess 112 (in some embodiments).

[0049] In some embodiments, the etching step of stage 102d is a plasma etching step performed using plasma 118. In a particular example, the plasma 118 used to etch the passivation layer 116 includes argon or another noble gas. Additional details of the example etching process of stage 102d are described below in conjunction with the example passivation layer 116 deposition process of stage 102c.

[0050] The etching step of stage 102d may initially expose or further expose additional surfaces of the copper-containing layer 108. For example, the etching step of stage 102d may initially expose or further expose the surface of the sidewall 119 of the copper-containing layer 108 in the recess 112. After exposure (e.g., after the recess 112 has been opened into the copper-containing layer 108, exposing the surface at the sidewall 119 of the copper-containing layer 108 in the recess 112), a passivation layer 116 may be formed on these additional surfaces (e.g., the surface of the sidewall 119) during subsequent execution of stage 102c. In some embodiments, partial etching of the copper-containing layer 108 may be performed before the cyclic etching process 113 and without first forming the passivation layer 116 to begin forming the recess 112 in the copper-containing layer 108 according to the pattern defined by the patterning layer 110. In other embodiments, such partial etching is not performed first.

[0051] Depending on the specific implementation objective, the etching process used in the etching step of stage 102d may be an anisotropic etching process. The anisotropic etching process (e.g., anisotropic plasma processing) may be performed in a specific direction (e.g., the downward direction in the recess 112) to further extend the recess 112 into the copper-containing layer 108 by removing the passivation layer 116a at the top surface 114 of the copper-containing layer 108.

[0052] As indicated by circular arrow 120, the steps of the cyclic etching process 113 (e.g., the passivation layer 116 formation step of stage 102c, and the etching step of stage 102d) may be repeated one or more times to gradually form the recess 112 in the copper-containing layer 108. It should be understood that this disclosure is contemplated to perform the cyclic etching process 113 any suitable number of times.

[0053] In some embodiments, the recess 112 can be further extended into the copper-containing layer 108 by each cycle of the cyclic etching process 113. For a given embodiment, the appropriate number of cycles of the cyclic etching process 113 depends on various factors, including the exact material of the copper-containing layer 108; the material of the passivation layer 116; the desired size of the recess 112; the acceptable amount of time that the cyclic etching process 113 can be introduced into the entire manufacturing process of the semiconductor structure 104; the substances (e.g., gases) used in a portion of the cyclic etching process 113, including substances for depositing the passivation layer 116 and for etching the passivation layer 116; and / or other suitable factors.

[0054] In some embodiments, the appropriate number of cycles of the cyclic etching process 113 is predetermined by processing the test wafer (before manufacturing operations). The wafer (e.g., semiconductor structure 104) can be sampled at various stages to measure various aspects of the wafer, including the dimensions of etched features (e.g., recesses 112) and one or more possible pattern defects. For example, samples can be analyzed after one or more of these stages 102.

[0055] As a more specific example, the first wafer can be sampled after a first predetermined number of cycles of the cyclic etching process 113, stopping after the etching step of stage 102d, and the measured values ​​of characteristics (e.g., the recess 112 and the critical dimensions of possible pattern defects) can be compared with desired values ​​of these characteristics (e.g., with technology node parameters). Furthermore, it can be determined whether the surface of the substrate 106 (hereinafter referred to as the top surface 122) is exposed at the bottom of the recess 112. Then, depending on the results of the comparison and other factors (e.g., any of the other factors listed above), it can be determined whether a new wafer should be tested after a second predetermined number of cycles, where the second predetermined number of cycles is less than or greater than the first predetermined number of cycles. This sampling process can be repeated until a suitable number of cycles for a given embodiment is determined.

[0056] Furthermore, adjustments to these steps of the cyclic etching process 113 can be included as part of the testing and analysis. For example, the semiconductor structure 104 can be analyzed for different exposure times to the chlorine treatment 115 and / or plasma 118 to determine the impact on the size of the recess 112, the duration of the cyclic etching process 113, and / or other factors.

[0057] Optical techniques can be used to measure characteristics (e.g., the dimensions of semiconductor structure 104), such as scatterometers, scanning electron microscopes (SEM), transmission electron microscopes (TEM), high-resolution TEM (HR-TEM), scanning probe microscopes (SPM), atomic force microscopes (AFM), scanning tunneling microscopes (STM), or other suitable equipment.

[0058] The techniques described above for determining the appropriate number of cycles for the cyclic etching process 113 are merely examples. This disclosure envisions any suitable techniques for determining the appropriate number of cycles for performing the cyclic etching process 113.

[0059] Regarding the processing conditions and related parameters for the passivation layer 116 formation step in stage 102c and the etching step in stage 102d as described above, in some embodiments, both the passivation layer 116 formation step in stage 102c and the etching step in stage 102d are performed using plasma processing. In some other embodiments, the passivation layer 116 formation step in stage 102c may be performed using thermal deposition (or another suitable type of deposition process), while the etching step in stage 102d may be performed using plasma processing.

[0060] In some embodiments, these steps of the cyclic etching process 113 (e.g., deposition and etching associated with stages 102c and 102d) may be performed in the same processing chamber of the processing tool. As an example, the processing tool may be an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, a helical wave source (HWS) tool, a helical resonator, a spiral resonator, a microwave or electron beam generated plasma tool, a thermal processing tool, or any other suitable type of tool or combination of tool types. Depending on the implementation details, gas purging of the processing chamber may or may not be performed between these steps of the cyclic etching process 113. For example, purging the processing chamber between stages 102c and 102d of the cyclic etching process 113 may reduce the chance that the gas used in the passivation layer 116 (stage 102c) remains in the processing chamber during the etching step (stage 102d) and interferes with the etching step. As another example, given the cyclic nature of the cyclic etching process 113, purging the processing chamber between stage 102d and the subsequent stage 102c of the cyclic etching process 113 can reduce the chance that the gas used in the etching step (stage 102d) remains in the processing chamber during the passivation layer 116 formation step (stage 102c) and interferes with that passivation layer 116 formation step. Alternatively, this disclosure envisions not performing purging at one or both of these times (between stages 102c and 102d, and / or between stage 102d and the subsequent stage 102c). For example, in addition to purging or instead of purging, after the chlorine flow associated with stage 102c is terminated, the activation of the precious gas plasma associated with stage 102d (e.g., turning on Ar or other precious gas radio frequency (RF)) can be delayed (e.g., for more than about 1 second) to reduce or eliminate chlorine dissociation that may occur during the etching process associated with stage 102d.

[0061] In some embodiments, the steps of the cyclic etching process 113 (e.g., deposition and etching associated with stages 102c and 102d) can be performed in different processing chambers of the same processing tool. As an example, the processing tool can be an ICP tool, CCP tool, HWS tool, helical resonator, spiral resonator, microwave or electron beam plasma tool, thermal processing tool, or any other suitable type of tool or combination of tool types. For example, stage 102c can be performed in the first chamber of the processing tool (e.g., a plasma chamber or a thermal processing chamber), while stage 102d can be performed in individual plasma chambers of the same processing tool.

[0062] In some embodiments, the steps of the cyclic etching process 113 (e.g., passivation and etching associated with stages 102c and 102d, respectively) can be performed in the processing chambers of different processing tools. As an example, the processing tool can be an ICP tool, a CCP tool, an HWS tool, a helical resonator, a spiral resonator, a microwave or electron beam plasma-generating tool, a thermal treatment tool, or any other suitable type of tool or combination of tool types. For example, stage 102c can be performed in the chamber of a first processing tool (e.g., a plasma chamber or a thermal treatment chamber), while stage 102d can be performed in the plasma chambers of different processing tools.

[0063] The example processing conditions and related parameters to be considered include: processing tool parameters for each of stages 102c and 102d, depending on the processing type, such as, if applicable, the gas and its quantity to be introduced into the processing chamber in each of stages 102c and 102d, the pressure to be applied in each of stages 102c and 102d, the source RF power and bias RF power to be used in each of stages 102c and 102d, the temperature in each of stages 102c and 102d, and the... The time, the number of times each of stages 102c and 102d is performed (e.g., the number of cycles), whether the processing parameters differ for any case of stages 102c and 102d, whether the processing chamber is purged between multiple processing steps (in embodiments where stages 102c and 102d are performed in the same processing chamber), whether anisotropic passivation and / or etching processes and related processing conditions are used, the desired amount by which the recess 112 extends into the copper-containing layer 108, and / or any other processing conditions and related parameters.

[0064] The selected processing conditions and related parameters can be determined based on various factors, such as the appropriate number of cycles for the cyclic etching process 113 described above. Furthermore, the selected processing conditions and related parameters for stages 102c and 102d can be optimized relative to each other. For example, to achieve an optimal processing combination that satisfies one or more of the aforementioned factors, it may be appropriate to consider the processing conditions and related parameters of passivation (stage 102c) and etching (stage 102d) together.

[0065] For example, specific example processing conditions used in the cyclic etching process 113 are described below. The passivation layer 116 may be formed using thermal deposition or plasma deposition in stage 102c, while the etching step may be performed using plasma deposition in stage 102d. These processing conditions are provided for illustrative purposes only. Depending on the specific implementation objectives, this disclosure contemplates using any suitable processing conditions to perform the cyclic etching process 113.

[0066] In some embodiments, the passivation layer 116 formation step of stage 102c (e.g., chlorine treatment 115) is performed as a thermal deposition process and may include introducing chlorine gas (Cl2) into a processing chamber and raising the temperature of the semiconductor structure 104 to a temperature in the range of about 100°C to about 300°C, causing the Cl2 to dissociate and react with one or more exposed surfaces containing a copper layer to form a CuyClx structure (passivation layer 116).

[0067] In some embodiments, the passivation layer 116 formation step of stage 102c (e.g., chlorination treatment 115) is performed as a plasma deposition process and may include introducing chlorine gas (Cl2) into a processing chamber and generating a plasma comprising chlorine gas (Cl2). In some embodiments, the plasma is generated using a relatively high voltage (e.g., greater than about 200 mTorr). In some embodiments, the plasma is generated using a pressure greater than about 300 mTorr. High-voltage discharge can reduce the energy of ions directed to the exposed surface of the copper-containing layer 108 (e.g., the top surface 114), because such ion bombardment can cause alloying at the exposed surface of the copper-containing layer 108, thereby undesirably altering the surface morphology of the copper-containing layer 108.

[0068] In some embodiments, chlorine is the only gas intentionally introduced to form plasma. In some other embodiments, chlorine and one or more other gases may be used to form plasma. For example, a relatively small amount of a precious gas (e.g., argon) may be added to the plasma chamber (in addition to chlorine) to promote plasma ignition.

[0069] As a specific example only, the plasma deposition process for forming the passivation layer 116 may include chlorine (Cl 2) at a flow rate of about 100 standard cubic centimeters (sccm) to about 300 sccm per minute, a pressure of about 50 mTorr to about 300 mTorr, a source power of about 10 W to about 60 W, a bias power of about 10 W to about 50 W, and a temperature of about 100°C.

[0070] In some embodiments, the etching step of stage 102d is performed as a plasma process (e.g., plasma 118) and may include introducing a precious gas (e.g., argon) into the processing chamber and using argon to generate plasma 118. Other example precious gases that can be used include helium and xenon, but using argon can provide certain cost advantages. In some embodiments, an inert gas (e.g., argon) is the only gas deliberately introduced to form plasma 118. In some other embodiments, chlorine and one or more other gases may be used to form the plasma. In some embodiments, the power conditions for generating plasma 118 are an attempt to strike a balance between absorption and sputtering. For example, the power may be set high enough to promote absorption of the compound (e.g., CuCl) of the passivation layer 116, but low enough to attempt to keep ion sputtering at an acceptable and / or minimized level. As an example only, it may be necessary to keep the ion energy below about 40 eV, and in some embodiments below about 20 eV. As another example, relatively low pressure (e.g., ≤ about 10 mTorr) can be used to etch the passivation layer 116, and the ability to complete the etching at such low pressure can mitigate the risk of re-deposition of etching byproducts.

[0071] As a specific example only, the plasma treatment for etching the passivation layer 116 may include a pressure of about 10 mTorr to about 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, an Ar flow rate of about 300 sccm, a temperature of about 100 °C or less, and an ion energy of about 10 eV to about 40 eV.

[0072] In a first specific example embodiment where stage 102c is a heat treatment and stage 102d is a plasma treatment, the processing conditions and related parameters for the passivation layer 116 formation step (stage 102c) and the etching step (stage 102d) of the cyclic etching process 113 may include the following. Example processing conditions for stage 102c may include: a passivation time of ≤ about 5 seconds, a Cl2 flow rate of about 100 sccm to about 300 sccm, and a temperature of about 100°C to about 300°C. Example processing conditions for stage 102d may include (e.g., in a CCP tool): an etching time of ≤ about 5 seconds, a pressure of 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, a temperature below about 100°C, and an Ar flow rate of about 300 sccm. In one example, the cyclic etching process 113 is performed in different processing chambers (of the same or different processing tools).

[0073] In a second specific example embodiment where stage 102c is a plasma process and stage 102d is a plasma process, the processing conditions and related parameters for the passivation layer 116 formation step (stage 102c) and etching step (stage 102d) of the cyclic etching process 113 may include the following. Example processing conditions for stage 102c may include: a passivation time ≤ about 5 seconds, a pressure > 200 mTorr, a source power of about 10 W to about 60 W, a bias power of about 10 W to about 50 W, a temperature of about 100°C, and a Cl2 flow rate of about 100 sccm to about 300 sccm. Example processing conditions for stage 102d may include (e.g., in a CCP tool): an etching time ≤ about 5 seconds, a pressure of 100 mTorr, a source power of about 50 W to about 100 W, a bias power of about 10 W to about 50 W, a temperature of about 100°C or lower, and an Ar flow rate of about 300 sccm. In one example, the cyclic etching process 113 is performed in different processing chambers (with the same or different processing tools). In another example, the cyclic etching process 113 is performed in the same processing chamber, wherein purging is performed between stages 102c and 102d, and between stage 102d and returning to stage 102c for another cycle. The purging time may depend on the pressure used and the volume of the processing chamber.

[0074] At stage 102e of FIG. 1C, the cyclic etching process 113 has been completed, and the recess 112 in the copper-containing layer 108 has been fully formed, including, in this example, the top surface 122 of the substrate 106 exposed at the bottom of the recess 112. Furthermore, portions of the passivation layers 116 (e.g., passivation layers 116b and 116c) remain on the sidewalls 119 of the copper-containing layer 108 in the recess 112. As described above, when the recess 112 opens the copper-containing layer 108, the passivation layers 116 (especially passivation layers 116b and 116c) can be formed on the surface of the sidewalls 119, thereby causing the surface of the sidewalls 119 to become exposed during the passivation step of the subsequent stage 102c. In some embodiments, a "clean" etching can be used to remove the passivation layers 116b and 116c partially or entirely from the sidewalls 119. By way of example only, argon or another suitable material can be used to perform the clean etching. This cleaning etching can be performed using any suitable dry etching process, wet etching process, or a combination thereof.

[0075] The remaining portion of the copper layer 108 may form structures 123a, 123b, and 123c (collectively referred to as structure 123). Structure 123 may be formed as a conductive feature of the semiconductor device being formed. Such conductive features may be, for example, wires, vias, contacts, etc. This disclosure envisions structure 123 as any suitable type of conductive feature. Furthermore, the type of conductive feature may be different for one or more of structures 123a, 123b, and 123c.

[0076] As shown in Figure 1C, at stage 102f, a suitable filler material 124 can be used to fill the recess 112. In some embodiments, the filler material 124 includes a dielectric material to, for example, isolate the remaining portions of the copper-containing layer 108 from each other. Specific examples of dielectric materials may include any material suitable for use as a pre-metal dielectric (PMD), inter-metal dielectric (IMD), interlayer dielectric (ILD), etc. This disclosure contemplates that the filler material 124 may include any suitable dielectric material or a combination of multiple dielectric materials. As a specific example, the dielectric material may include SiN; SiON; silicon dioxide (SiO2); silicon, carbon, oxygen, hydrogen (SiCOH), or any other suitable dielectric material or a combination of multiple dielectric materials.

[0077] In some embodiments, one or more additional materials may be deposited prior to the deposition of the dielectric material. For example, one or more barrier layers, such as thin alloy layers, may be deposited before the remaining portion of the recess 112 is filled with a dielectric material. Such barrier layers can be used for various purposes, such as mediating electromigration at the sidewalls 119 of the copper-containing layer 108 between the copper-containing layer 108 and the dielectric material to be deposited in the filling material 124. Example barrier layers include TaN or TiN. When initially deposited, the barrier layer may cover the semiconductor structure 104, including above the top surface of the semiconductor structure 104. The barrier layer portion above the top of the semiconductor structure 104 may be removed using any suitable etching technique (e.g., anisotropic etching technique), leaving the barrier layer portion above the surface of the sidewalls 119 in the recess 112. The remaining portion of the recess 112 may then be filled with any other suitable material, including dielectric materials.

[0078] While the version of semiconductor structure 104 shown in stage 102f includes the remainder of patterned layer 110 (at the top of structure 123), depending on the specific implementation, the remainder of patterned layer 110 may or may not be removed. In embodiments where the remainder of patterned layer 110 is removed, the remainder of patterned layer 110 may be removed before or after stage 102f.

[0079] In stage 102f, the remaining portion of the copper-containing layer can then be used as a conductive feature in the resulting semiconductor device. For example, the remaining portion of the copper-containing layer 108 can be used as a conductive contact, a conductive via, a conductive line, or any other suitable type of conductive feature.

[0080] Although process 100 is shown as including specific stages, this section contemplates that process 100 may include additional or fewer stages that may be suitable for a particular implementation. For example, process 100 may include a purge stage between stages 102c and 102d and between stage 102d and return 102c.

[0081] The embodiments disclosed herein may provide one or more technical advantages. Specific embodiments may provide some, not all, or all of these advantages.

[0082] In some embodiments, the cyclic nature of the cyclic etching process 113 facilitates the progressive etching of the copper-containing layer 108. The cyclic etching process 113 in some embodiments provides a progressive copper etching process, wherein this progressive copper etching process can be tightly controlled due to the layer-by-layer etching method, and reduces or eliminates morphological changes on the surface of the copper layer being etched. Furthermore, the minimal-to-no morphological changes on the copper surface provided by some embodiments can reduce or eliminate surface roughness on the improved profile of the copper-containing layer 108 (and the resulting structure 123 made of the copper-containing layer 108) and the resulting structure 123 made of the copper-containing layer 108. Furthermore, the passivation layer 116 formation step (e.g., exposing the surface of the copper-containing layer 108 to chlorine treatment 115) can be self-limiting, and the etching performed using plasma 118 can be highly selective for etching the passivation layer 116. Both of these factors can reduce or eliminate the surface roughness of the copper-containing layer 108 (and the resulting structure 123 made from the copper-containing layer 108) and the improved profile of the resulting structure 123 made from the copper-containing layer 108. In other words, the self-limiting nature of the passivation layer 116 and the selectivity of the plasma 118 for etching the passivation layer 116 can help control the etching rate of the recesses 112 in the copper-containing layer 108, while reducing or eliminating pattern defects in the copper-containing layer 108.

[0083] Some embodiments provide copper etching techniques suitable for mass production. For example, some embodiments provide a progressive and self-limiting process that can be incorporated into larger processes for forming semiconductor devices. As another example, some embodiments reduce or eliminate damage to the copper layer and / or other parts of the semiconductor structure being processed, compared to other attempts to etch copper in a subtractive manner.

[0084] In addition to other types of features, some embodiments also provide the ability to etch relatively deep recesses 112 to form high aspect ratio conductive features, wherein the depth of the recess 112 is significantly greater than the width of the recess (potentially significantly larger). At least in part due to the controllable nature of the etching process, some embodiments may be able to be used for advanced packaging and three-dimensional (3D) integration (e.g., for FinFETs, gate-all-around (GAA) transistors, 3D NAND devices, etc.).

[0085] Figures 2A-2E illustrate cross-sectional views of the semiconductor structure 104 during a cyclic etching process 113 for processing the semiconductor structure 104 according to certain embodiments of the present disclosure. Specifically, Figures 2A-2E illustrate the semiconductor structure 104 during five example iterations of the cyclic etching process 113 to illustrate the layer-by-layer removal of a portion of the copper-containing layer 108. These five iterations of stages 102c and 102d are stages 102c(1) and 102d(1) labeled as iteration 1, stages 102c(2) and 102d(2) labeled as iteration 2, stages 102c(3) and 102d(3) labeled as iteration 3, stages 102c(4) and 102d(4) labeled as iteration 4, and stages 102c(5) and 102d(5) labeled as iteration 5. The specific number of iterations is shown only for illustrative purposes.

[0086] Generally speaking, the states of stages 102c(1) to 102c(5) correspond to the states of stage 102c described above with reference to FIG1B, and for the sake of brevity, many details will not be repeated. In addition, generally speaking, the states of stages 102d(1) to 102d(5) correspond to the states of stage 102d described above with reference to FIG1B, and for the sake of brevity, many details will not be repeated.

[0087] As shown in Figure 2A, in stage 102c(1), the top surface 114 of the copper-containing layer 108 is exposed to chlorine treatment 115 at the opening of the recess 112 defined by the patterned layer 110, so that a passivation layer 116 is formed on those exposed top surfaces 114. In stage 102d(1), by exposing the semiconductor structure 104 to plasma 118, all or part of the passivation layer 116 formed in stage 102c(1) is removed. Since the passivation layer 116 consumes some of the copper-containing layer 108, removing the passivation layer 116 formed at the top surface 114 of the copper-containing layer 108 will remove a portion of the copper-containing layer 108, so that the recess 112 extends into the copper-containing layer 108, and also exposes the sidewalls 119 of the copper-containing layer 108 in the recess 112.

[0088] As shown in Figure 2B, in stage 102c(2), the top surface 114 and the sidewall 119 of the copper-containing layer 108 are exposed to chlorine treatment 115, so that passivation layer 116a is formed on the exposed top surfaces of the copper-containing layer 108 at the bottom of the recess 112, and passivation layers 116b and 116c are formed on the sidewall 119 of the copper-containing layer 108. In stage 102d(2), the passivation layer 116a is completely or partially removed by exposing the semiconductor structure 104 to plasma 118. Since passivation layer 116a consumes a portion of the copper-containing layer 108, removing passivation layer 116a formed at the top surface 114 of the copper-containing layer 108 will remove a portion of the copper-containing layer 108, causing the recess 112 to extend into the copper-containing layer 108 and exposing more of the sidewall 119 of the copper-containing layer 108 in the recess 112. In some embodiments, due to the directional nature of the applied plasma 118, which is directed towards the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112 (and the passivation layer 116a formed thereon), some or all of the passivation layers 116b and 116c may remain at the surface of the sidewall 119. It should be noted that when passivation layer 116a is formed on the top surface 114 of the copper-containing layer 108, passivation layer 116a can also be considered as the top surface 114 of the copper-containing layer 108.

[0089] As shown in Figure 2C, in stage 102c (3), the top surface 114 and the sidewall 119 of the copper-containing layer 108 are exposed to chlorine treatment 115, so that passivation layer 116a is formed on the exposed top surface 114 of the copper-containing layer 108, and passivation layers 116b and 116c are formed on the exposed sidewall 119 surface portions in stage 102d (2). In stage 102d (3), passivation layer 116a is completely or partially removed by exposing semiconductor structure 104 to plasma 118. Since passivation layer 116a consumes some of the copper-containing layer 108, removing passivation layer 116a formed at the top surface of the copper-containing layer 108 (located at the bottom of the recess 112) removes a portion of the copper-containing layer 108, extending the recess 112 into the copper-containing layer 108 and exposing more of the sidewall 119. In some embodiments, due to the directional nature of the applied plasma 118, which is directed toward the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112 (and the passivation layer 116a formed thereon), some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0090] As shown in Figure 2D, in stage 102c (4), the top surface 114 and the sidewall 119 of the copper layer 108 are exposed to chlorine treatment 115, so that passivation layer 116a is formed on the exposed top surface 114 of the copper layer 108, and passivation layers 116b and 116c are formed on the exposed sidewall 119 surface portion in stage 102d (3). In stage 102d (4), passivation layer 116a is completely or partially removed by exposing semiconductor structure 104 to plasma 118. Since passivation layer 116a consumes some portion of the copper layer 108, removing passivation layer 116a formed at the top surface 114 of the copper layer 108 (located at the bottom of the recess 112) removes a portion of the copper layer 108, causing the recess 112 to extend into the copper layer 108, and also exposing more of the sidewall 119. In some embodiments, due to the directional nature of the applied plasma 118, which is directed toward the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112 (and the passivation layer 116a formed thereon), some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0091] As shown in Figure 2E, in stage 102c (5), the top surface 114 and the sidewall 119 of the copper layer 108 are exposed to chlorine treatment 115, so that passivation layer 116a is formed on the exposed top surface 114 of the copper layer 108, and passivation layers 116b and 116c are formed on the exposed sidewall 119 surface portion in stage 102d (4). In stage 102d (5), passivation layer 116a is completely or partially removed by exposing semiconductor structure 104 to plasma 118. Since passivation layer 116a consumes some portion of the copper layer 108, removing passivation layer 116a formed at the top surface 114 of the copper layer 108 (located at the bottom of the recess 112) removes a portion of the copper layer 108, causing the recess 112 to extend into the copper layer 108, and also exposing more of the sidewall 119. In some embodiments, due to the directional nature of the applied plasma 118, which is directed toward the top surface 114 of the copper-containing layer 108 at the bottom of the recess 112 (and the passivation layer 116a formed thereon), some or all of the passivation layers 116b and 116c may remain on the surface of the sidewall 119.

[0092] As can be seen in the examples shown and described with reference to Figures 2A-2E, process 100, particularly the cyclic etching process 113, progressively etches the target exposed surface of the copper-containing layer 108 (e.g., top surface 114), where in this example this causes the recess 112 to progressively extend into the copper-containing layer 108. A portion of the copper-containing layer 108 (where this portion is consumed by the passivation layer 116a) is removed using a selectively directional anisotropic etching process on the passivation layer 116, which provides a controlled etching process.

[0093] Figures 3A-3C illustrate example details of a semiconductor structure 104 during the cyclic etching process 113 of the process 100 for etching metal, according to certain embodiments of the present disclosure. Specifically, Figure 3A generally corresponds to stage 102c of Figure 1B when the semiconductor structure 104 begins to be exposed to the chlorine treatment 115, Figure 3B (which illustrates a cross-sectional and planar view of the semiconductor structure 104) generally corresponds to stage 102c when the passivation layer has been formed, and Figure 3C generally corresponds to stage 102d during the exposure of the semiconductor structure 104 to the plasma 118.

[0094] As shown in Figure 3A, the copper-containing layer 108 includes copper particles 300, and the chlorine treatment 115 includes chlorine particles 302. For the purposes of this embodiment, the particles may be atoms, molecules, ions, or any other suitable subdivision of the corresponding layer (where the particles are a part thereof). In some embodiments, the copper particles 300 are copper atoms, while the chlorine particles 302 are a compound of two chlorine atoms (Cl₂), wherein the compound is neutral chlorine gas.

[0095] As shown in Figure 3B, at least some of the chlorine particles 302 of the chlorine treatment 115 have dissociated from each other (as chlorine particles 304, e.g., chlorine atoms) and bonded to copper particles 300 at the surface of the copper-containing layer 108 to form a passivation layer 116a of Cu yCl x structure 306 (e.g., Cu yCl x compound). The copper particles 300 of the copper-containing layer 108 are self-limiting to exposure to chlorine gas (e.g., chlorine particles 302), and the chlorine molecules (e.g., Cl 2) readily dissociate and bond with copper atoms (e.g., copper particles 300) to form Cu yCl x structure 306 (e.g., Cu yCl x compound).

[0096] While this disclosure envisions forming the Cu yCl x structure 306 over any suitable percentage of the surface of the copper-containing layer 108, in some embodiments, stage 102c (e.g., exposing the semiconductor structure 104 to chlorine treatment 115) results in approximately 30% to approximately 70% of the exposed surface of the copper-containing layer 108 being converted to Cu yCl x. In some embodiments, stage 102c (e.g., exposing the semiconductor structure 104 to chlorine treatment 115) results in approximately 50% coverage. For example, in some embodiments, a limitation on chlorine absorption may be a steric barrier associated with adjacent chlorine particles 304 that have attached to copper particles 300 at the surface of the copper-containing layer 108. A rougher surface of the copper-containing layer 108 may have a larger surface area, which may allow more chlorine particles 304 to attach to the copper particles 300 at the surface of the copper-containing layer 108.

[0097] For example, in some embodiments, the dissociation of chlorine molecules (e.g., Cl₂) and the subsequent bonding with copper atoms (e.g., copper particles 300) on the crystalline copper surface can be stopped after reaching a certain coverage value (e.g., about 50%). In some embodiments, when the passivation layer 116 coverage is less than 100%, adjacent, unpassivated copper atoms on the exposed surface of the copper-containing layer 108 can move to attempt to bond with another chlorine atom. This can open pathways for copper atoms at the subsurface level of the copper-containing layer 108. However, since the energy absorbed by the chlorine atom at the subsurface level is relatively large (e.g., > about 3V), such subsurface absorption may be avoided or at least limited, thereby restricting morphological changes on the exposed surface of the copper-containing layer 108.

[0098] As shown in Figure 3C, a passivation layer 116 (e.g., passivation layer 116a) containing a copper layer 108 is exposed to a plasma 118, which etches the passivation layer 116a. The plasma 118 includes argon particles 308, and exposing the passivation layer 116a containing the copper layer 108 to the plasma 118 includes guiding the argon particles 308 toward the passivation layer 116a containing the copper layer 108 in direction 310. This allows for anisotropic etching of the passivation layer 116a, thereby removing copper particles 300 (Cu yCl x structure 306 as shown in Figure 3B) bonded to the chlorine particles 304 of the chlorine treatment 115. For example, argon particles 308 can bombard the copper-containing layer 108 (including the passivation layer 116a) with sufficient energy to separate the Cu yCl x structure 306 (e.g., a Cu yCl x compound) from the surface of the copper-containing layer 108; in some embodiments, the energy is low enough to minimize ion sputtering.

[0099] In some embodiments, a relatively small amount of energy is required to release the Cu yCl x structure 306. This capability, associated with the self-limiting formation nature of the passivation layer 116a (e.g., see Figure 3B), provides for the layer-by-layer removal of one or more target surfaces (e.g., top surface 114) similar to the copper-containing layer 108. In some embodiments, while the low ionic energy required to remove the passivation layer 116 allows the cyclic etching process 113 to be performed at any suitable pressure, the cyclic etching process 113 can be performed at low pressures (e.g., ≤ about 10 mTorr) because the chlorine mediated by the Cl 2 gas can rapidly saturate the copper (e.g., during stage 102c during the formation of the passivation layer 116). In some embodiments, this low pressure can reduce or eliminate the risk of byproducts being redeposited during the etching process of stage 102d.

[0100] Variations in copper chloride etching byproducts may occur during the etching steps (e.g., stage 102d). For example, CuCl, CuCl₂, and CuCl₃ are likely stable etching byproducts with ΔE values ​​of approximately -1.33 eV, +0.28 eV, and +2.19 eV, respectively. In some embodiments, CuCl₃ is typically only produced through cooperative interactions with physically adsorbed Cl₂ molecules, which may limit CuCl₃ production. In some embodiments, the plasma concentration and power are selectively used to disrupt the approximately 0.86 eV copper surface bonds of the copper-containing layer 108.

[0101] Figure 4 illustrates an example method 400 for processing a semiconductor structure 104 according to certain embodiments of the present disclosure. The method begins at step 402. At step 404, a substrate 106 is received. The substrate 106 includes a copper-containing layer 108 formed thereon. In some embodiments, the copper-containing layer 108 is pure copper. At step 406, a patterned layer 110 is formed over the copper-containing layer 108, which is formed over the substrate 106. For example, a patterned photoresist layer may be used as an etching mask to pattern the patterned layer 110. In some embodiments, forming the patterned layer 110 includes defining a pattern in the patterned layer 110 that defines an etch pattern in which features (e.g., recesses 112 and structures 123) are formed in the copper-containing layer 108 using a cyclic etching process 113. For example, the pattern defined by the patterning layer 110 can define a recess 112, and the corresponding recess 112 can be etched in the copper layer 108, so that the remaining portion of the copper layer 108 after the cyclic etching process 113 defines the conductive features of the semiconductor device, such as conductive contacts, conductive lines, conductive vias and / or the like.

[0102] In step 408, the copper-containing layer 108 is patterned by performing a cyclic etching process 113 and using the patterned layer 110 as an etching mask. In some embodiments, the cyclic etching process 113 includes step 408a in a first etching step (e.g., a chlorine exposure step), forming a passivation layer 116 by exposing one or more exposed surfaces of the copper-containing layer 108 to a chlorine treatment 115 comprising chlorine gas. In some embodiments, the passivation layer 116 comprises Cu yCl x. The passivation layer 116 replaces at least a portion of the surface layer of the copper-containing layer 108. In some embodiments, the passivation layer 116 is formed in a self-confining process and penetrates the copper-containing layer 108 to a depth of less than three copper atoms at one or more exposed surfaces.

[0103] In some embodiments, forming a passivation layer 116 on one or more exposed surfaces of the copper-containing layer 108 by exposing it to a chlorine treatment 115 in step 408a includes performing a thermal deposition process to dissociate Cl2 and react with the one or more exposed surfaces of the copper-containing layer 108 to form the passivation layer 116 (e.g., CuyClx structure 306). In some embodiments, forming a passivation layer 116 on one or more exposed surfaces of the copper-containing layer 108 by exposing it to a chlorine treatment 115 in step 408a includes a plasma deposition process. For example, the one or more exposed surfaces of the copper-containing layer 108 may be exposed to a chlorine-containing plasma, wherein the chlorine-containing plasma has sufficient energy to dissociate Cl2 and react with the one or more exposed surfaces of the copper layer to form the passivation layer 116 (e.g., CuyClx structure 306).

[0104] In some embodiments, one or more exposed surfaces of the copper-containing layer 108 over which the passivation layer 116 is formed include one or more top surfaces 114 of the copper-containing layer 108, sidewall 119 surfaces of the copper-containing layer 108, or a combination of one or more top surfaces of the copper-containing layer 108 and sidewall 119 surfaces of the copper-containing layer 108.

[0105] In some embodiments, at the initial stage of the first etching step (e.g., chlorine exposure step) in step 408a, one or more exposed surfaces of the copper-containing layer 108 may include a target exposed surface, which in one example is the top surface 114 of the copper-containing layer 108 located at the bottom of the recess 112. In some embodiments, in the subsequent stage of the first etching step (e.g., chlorine exposure step) in step 408a, one or more exposed surfaces of the copper-containing layer 108 may include the target exposed surface (e.g., top surface 114) and the sidewall 119 surface of the copper-containing layer 108 in the recess 112.

[0106] In some embodiments, the cyclic etching process 113 includes etching at least a portion of the passivation layer 116 of the copper-containing layer 108 using plasma 118 during step 408b of the second etching step (e.g., a plasma etching step). In some embodiments, the plasma 118 comprises a precious gas, such as argon. Each etching of the passivation layer 116 removes at least a portion of the copper-containing layer 108, which extends the recesses 112 in the copper-containing layer 108.

[0107] In some embodiments, step 408b includes exposing the substrate 106 having the copper-containing layer 108 to a plasma 118 (e.g., argon plasma) in a plasma etching step, wherein the plasma 118 is directed to a target exposed surface of the copper-containing layer 108 (e.g., top surface 114), and the plasma 118 has sufficient energy to remove at least a portion of the Cu yCl x structure 306 from one or more exposed surfaces of the copper-containing layer 108, thereby extending the recess 112 into the copper-containing layer 108. In some embodiments, the sufficient energy is less than or equal to about 40 eV.

[0108] The cyclic nature of the cyclic etching process 113 means that it can be repeated a suitable number of times to progressively form recesses 112 in the copper-containing layer 108, such that the depth of the recesses 112 increases with each iteration of the cyclic etching process 113. Furthermore, the cyclic nature of the cyclic etching process 113 (which is associated with the formation of the passivation layer 116) helps to reduce or eliminate surface morphology changes in the copper-containing layer 108 during etching. For example, the cyclic etching process 113 can be performed a predetermined number of times. As another example, the cyclic etching process 113 can be performed until the top surface 122 of the substrate 106 is exposed at the bottom of the recesses 112 in the copper-containing layer 108.

[0109] In some embodiments, and in examples where steps 408a and 408b are performed in the same processing chamber, the processing chamber (in which steps 408a and 408b are performed) may be purged after step 408a of the cyclic etching process 113 of method 400 and before step 408b of the cyclic etching process 113 to remove residual gas or other material associated with step 408a.

[0110] In step 410, the recess 112 may be filled with filler material 124. Filler material 124 may include any suitable material or combination of materials. In some embodiments, the filler material includes a dielectric material. This disclosure contemplates the use of any suitable type of processing or combination of processing types to fill the recess with filler material 124. In some embodiments, method 400 includes removing portions of passivation layer 116 (e.g., passivation layers 116b and 116c) formed at the sidewalls 119 of the copper-containing layer 108 in the recess 112 before filling the recess 112 with filler material 124.

[0111] Method 400 ends at step 412.

[0112] Figure 5 illustrates an example method 500 for processing a semiconductor structure 104 according to certain embodiments of the present disclosure. The method begins at step 502. At step 504, a substrate 106 is received. The substrate 106 includes a copper-containing layer 108 formed thereon. In some embodiments, the copper-containing layer 108 is pure copper.

[0113] In step 506, a cyclic etching process 113 is performed to progressively etch a portion of the copper-containing layer 108. In some embodiments, the copper-containing layer 108 has a target exposed surface that defines the portion of the copper-containing layer to be progressively etched. For example, the target exposed surface may be the top surface 114 of the copper-containing layer 108 located at the bottom of the recess 112.

[0114] In some embodiments, the cyclic etching process 113 includes exposing the substrate 106 having the copper-containing layer 108 to chlorine gas (Cl2) during step 506a of the chlorine exposure step, causing a portion of the copper-containing layer 108 to transform into a copper chloride (CuyClx) structure 306 located at the target exposed surface of the copper-containing layer 108. The copper of the (CuyClx) structure 306 may be a surface portion of the copper-containing layer 108 at the target exposed surface (and possibly at other exposed surfaces of the copper-containing layer 108). In some embodiments, the chlorine exposure step 506a transforms less than 100% of the target exposed surface of the copper-containing layer 108 into a copper chloride (CuyClx) structure, and as a specific example, transforms approximately 50% of the target exposed surface of the copper-containing layer 108 into a copper chloride (CuyClx) structure.

[0115] In some embodiments, according to a thermal deposition process, step 506a includes injecting Cl2 into a processing chamber of a processing tool and raising the temperature of the processing chamber to cause the Cl2 to dissociate and react with the exposed target surface of the copper-containing layer 108 to form a CuyClx structure 306. In some embodiments, according to a plasma deposition process, step 506a includes injecting Cl2 into a processing chamber of a processing tool and generating a chloride-containing plasma (e.g., plasma 118) from the Cl2 in the processing chamber, and exposing the target exposed surface of the copper-containing layer 108 to the chloride-containing plasma (e.g., plasma 118), wherein the chloride-containing plasma has sufficient energy to cause the Cl2 to dissociate and react with the target exposed surface of the copper-containing layer 108 to form a CuyClx structure 306.

[0116] In some embodiments, the cyclic etching process 113 includes exposing the substrate 106 to the plasma 118 during step 506b of the plasma etching step. In some embodiments, the plasma 118 comprises a precious gas, such as argon. In some embodiments, the plasma 118 is directed to a target exposed surface of the copper-containing layer 108 (e.g., top surface 114) and the plasma 118 has sufficient energy such that at least a portion of the Cu yCl x structure at the target exposed surface of the copper-containing layer 108 is removed from the copper-containing layer 108, thereby etching a portion of the copper-containing layer 108 at the target exposed surface of the copper-containing layer 108. In some embodiments, the sufficient energy is less than or equal to about 40 eV.

[0117] The cyclic nature of the cyclic etching process 113 means that it can be repeated a suitable number of times to progressively etch the copper-containing layer 108 (e.g., to form a recess 112 in the copper-containing layer 108). Furthermore, the cyclic nature of the cyclic etching process 113 (which is related to the formation of a copper chloride structure 306 at the target exposed surface of the copper-containing layer 108) helps to reduce or eliminate morphological changes to the target exposed surface of the copper-containing layer 108 during etching. For example, the cyclic etching process 113 can be performed a predetermined number of times. As another example, the cyclic etching process 113 can be performed until the top surface 122 of the substrate 106 is exposed at the bottom of the recess 112 in the copper-containing layer 108.

[0118] In some embodiments, the chlorine exposure step (e.g., step 506a) and the plasma etching step (e.g., step 506b) are performed using different processing tools or in different processing chambers of the same processing tool. In some embodiments, and in examples where steps 506a and 506b are performed in the same processing chamber, the processing chamber (in which steps 506a and 506b are performed) may be purged after step 506a of the cyclic etching process 113 of method 500 and before step 506b of the cyclic etching process 113 to remove residual gas or other material associated with step 506a.

[0119] In step 508, the recess 112 may be filled with filler material 124. Filler material 124 may include any suitable material or combination of materials. In some embodiments, the filler material includes a dielectric material. This disclosure contemplates the use of any suitable type of treatment or combination of treatment types to fill the recess with filler material 124.

[0120] Method 500 ends at step 510.

[0121] Figure 6 illustrates a general schematic diagram of an example plasma treatment system 600 according to certain embodiments of the present disclosure. Although a particular example plasma treatment system 600 is shown and described, the present disclosure contemplates the use of any suitable type of plasma treatment system 600. The plasma treatment system 600 can be used to perform some or all of the plasma treatment steps.

[0122] The plasma processing system 600 includes a processing chamber 610, a gas delivery system 620, a vacuum exhaust system 630, a temperature controller 640, and power sources 650 and 660. The processing chamber 610 includes electrodes 652 and a substrate holder 654.

[0123] Some or all of the steps described in Figures 1-5 may be performed using a plasma processing system 600, wherein the semiconductor structure 104 is located on a substrate holder 654 in a processing chamber 610. For example, for the plasma processing to form a passivation layer 116 or to etch a copper-containing layer 108, the semiconductor structure 104 may be positioned in the processing chamber 610 and exposed to a suitable plasma 670, which, depending on the stage of the processing, may be, for example, a chlorine treatment 115 implemented as a plasma, or plasma 118.

[0124] The gas delivery system 620, vacuum exhaust system 630, temperature controller 640, power sources 650 and 660, and electrode 652 can be programmed or otherwise operated according to the required processing conditions for a given processing step. For example, for the purpose of plasma processing to form a passivation layer 116, these components of the plasma processing system 600 can be configured according to the exemplary processing conditions and related parameters described with respect to the formation of the passivation layer 116. As another example, for the purpose of plasma processing to etch the recesses 112 in the copper-containing layer 108, these components of the plasma processing system 600 can be configured according to the exemplary processing conditions and related parameters described with respect to the etching of the recesses 112 in the copper-containing layer 108.

[0125] Although this disclosure describes or illustrates specific processing / method steps as occurring in a particular order, it is contemplated that processing / method steps may occur in any suitable order. Furthermore, this disclosure is contemplated that processing / method steps may be repeated one or more times in any suitable order. While this disclosure describes or illustrates specific process / method steps as performed sequentially, where appropriate, this disclosure is contemplated that processing / method steps may occur substantially simultaneously.

[0126] Although this disclosure has been described with reference to a plurality of illustrative embodiments, these embodiments are not intended to be limiting. Various modifications and combinations of these illustrative embodiments, as well as other embodiments of this disclosure, will become apparent to those skilled in the art upon reference to these embodiments. Therefore, the appended claims are intended to cover any such modifications or embodiments.

[0127] 100: Processing 104: Semiconductor Structure 106:Substrate 108: Copper-containing layer 110: Patterned Layer 112: Depression 113: Cyclic Etching Process 114: Top surface 115: Chlorine Treatment 116, 116a, 116b, 116c: Passivation layers 118: Plasma 119: Sidewall 120: Circular arrow 122: Top surface 123a, 123b, 123c: Structure 124: Filling material 300: Copper microparticles 302: Chlorine particles 304: Chlorine microparticles 306:Cu yCl x structure 308: Argon particles 310: Direction 400: Method 402-412: Steps 500: Methods 502-510: Steps 600: Plasma Treatment System 610: Processing Chamber 620: Gas delivery system 630: Vacuum Exhaust System 640: Temperature Controller 650: Power Source 652: Electrode 654:Substrate holder 660: Power Source 670: Plasma

Claims

1. A method for processing a semiconductor structure, comprising: A patterned layer is formed on top of the copper layer to be etched, which is placed on top of the substrate; The patterned layer is used as an etching mask, and the copper layer is patterned by performing a cyclic etching process to form a recess in the copper layer. The cyclic etching process includes: in a first etching step, forming a passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas, the passivation layer replacing at least a portion of the surface layer of the copper layer; and in a second etching step, etching the passivation layer using a first plasma, the first plasma including a noble gas, each cycle of the cyclic etching process extending the recess in the copper layer, wherein during one or more of the first etching steps, the passivation layer is formed along a plurality of sidewall surfaces of the copper layer in the recess exposed by the second etching step; And after the cyclic etching process is completed, the recess is filled with a filler material including dielectric material, wherein the passivation layer at the sidewall surfaces of the copper layer in the recess is removed before the recess is filled with the filler material.

2. The semiconductor structure processing method of claim 1, wherein in the first etching step, forming the passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas includes a thermal deposition process.

3. The semiconductor structure processing method of claim 1, wherein in the first etching step, forming the passivation layer on the exposed surface of the copper layer by exposing the exposed surface of the copper layer to chlorine gas includes plasma deposition.

4. The semiconductor structure processing method of claim 1, wherein the exposed surface of the copper layer on which the passivation layer is formed includes the top surface of the copper layer, a plurality of sidewall surfaces of the copper layer, or a combination of the top surface of the copper layer and the sidewall surfaces of the copper layer.

5. A method for processing a semiconductor structure as claimed in claim 1, wherein the passivation layer comprises a complex copper chloride (CuCl) structure.

6. The semiconductor structure processing method of claim 5, wherein about 30% to about 70% of the exposed surface of the copper layer is converted into the CuCl structure.

7. The method for processing a semiconductor structure as described in claim 1, wherein the precious gas is argon.

8. A method of processing a semiconductor structure as claimed in claim 1, wherein during the second etching step, the first plasma is directed to a portion of the passivation layer, the portion being formed on the top surface of the copper layer located at the bottom of the recess.

9. A method for processing a semiconductor structure, comprising: A receiving substrate, wherein a copper layer is formed on the substrate; A cyclic etching process is performed to progressively etch a portion of the copper-containing layer, thereby forming a recess in the copper-containing layer, the copper-containing layer having a target exposure surface that defines the portion of the copper-containing layer to be etched. The cyclic etching process includes: in a chlorine exposure step, exposing the substrate having the copper-containing layer to chlorine gas (Cl2) to convert a portion of the copper-containing layer into a plurality of copper chloride (CuCl) structures; and in a plasma etching step, subsequently exposing the substrate having the copper-containing layer to a first plasma comprising a precious gas and directed to the target exposure surface of the copper-containing layer with sufficient energy to remove at least a portion of the CuCl structures from the copper-containing layer. And after the cyclic etching process is completed, the recess is filled with a filler material including dielectric material, wherein before filling the recess with the filler material, the CuCl structures located on the sidewall surface of the copper-containing layer in the recess are removed.

10. The semiconductor structure processing method of claim 9, wherein the chlorine exposure step and the plasma etching step are performed using different processing tools or in different processing chambers of the same processing tool.

11. A method for processing the semiconductor structure as described in claim 9, wherein: The chlorine exposure step and the plasma etching step are performed in the same processing chamber of the same processing tool; and the method further includes, during each cycle of the cyclic etching process, performing a purge of the same processing chamber between the chlorine exposure step and the plasma etching step.

12. A method for processing a semiconductor structure as claimed in claim 9, comprising repeating the cyclic etching process a sufficient number of times to etch the portion containing the copper layer.

13. A method for processing a semiconductor structure as claimed in claim 9, wherein exposing the substrate having the copper-containing layer to the Cl2 comprises: According to thermal deposition, Cl2 is injected into the processing chamber of a processing tool, and the temperature of the processing chamber of the processing tool is raised to decompose the Cl2 and react with the target exposed surface of the copper-containing layer, thereby forming the CuCl structure; or according to plasma deposition, Cl2 is injected into the processing chamber of a processing tool, and a chlorine-containing plasma is generated from the Cl2 in the processing chamber of the processing tool, and the target exposed surface of the copper-containing layer is exposed to the chlorine-containing plasma, which has sufficient energy to decompose the Cl2 and react with the target exposed surface of the copper-containing layer, thereby forming the CuCl structure.

14. A method for processing a semiconductor structure, comprising: A patterned layer is formed on top of the copper layer to be etched, which is placed on top of the substrate; The patterned layer is used as an etching mask, and the copper layer is patterned by performing a cyclic etching process to progressively form recesses in the copper layer. The cyclic etching process includes: in a chlorine exposure step, exposing the substrate having the copper layer to chlorine gas (Cl2) to form a plurality of CuCl structures at one or more exposed surfaces of the copper layer; and in a plasma etching step, subsequently exposing the substrate having the copper layer to an argon-containing plasma, which is guided to the target exposed surface of the copper layer and has sufficient energy to remove at least a portion of the CuCl structures at the one or more exposed surfaces of the copper layer from the copper layer, causing the recesses to extend into the copper layer; wherein: In the initial stage of the chlorine exposure step, the one or more exposed surfaces of the copper layer include the target exposed surface, which is the top surface of the copper layer located at the bottom of the recess; and in the subsequent stage of the chlorine exposure step, the one or more exposed surfaces of the copper layer include the target exposed surface and a plurality of sidewall surfaces of the copper layer in the recess; and after the cyclic etching process is completed, the recess is filled with a filler material including a dielectric material, wherein the CuCl structures located at the sidewall surfaces of the copper layer in the recess are removed before the recess is filled with the filler material.

15. A method for processing a semiconductor structure as claimed in claim 14, wherein the chlorine exposure step includes performing a thermal deposition process to decompose the Cl2 and react it with the one or more exposed surfaces of the copper layer to form the CuCl structure.

16. A method for processing a semiconductor structure as claimed in claim 14, wherein the chlorine exposure step includes generating a chlorine-containing plasma from the Cl2 and exposing one or more exposed surfaces of the copper layer to the chlorine-containing plasma, the chlorine-containing plasma having sufficient energy to decompose the Cl2 and react with the one or more exposed surfaces of the copper layer to form the CuCl structures.

17. The method of processing the semiconductor structure of claim 14, wherein the sufficient energy is less than or equal to about 40 eV.

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