Semiconductor device

Abstract

This invention provides a semiconductor device that improves device performance and reliability. The semiconductor device includes: a gate structure including a gate electrode and a gate cap pattern on an upper surface of the gate electrode; a source / drain pattern located on at least one side of the gate structure; and a source / drain contact located on and connected to the upper surface of the source / drain pattern, the source / drain contact extending along a sidewall of the gate electrode, wherein the upper surface of the source / drain contact includes a protruding curved surface.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. [Cross-reference to related applications]

[0002] This application claims priority to and all rights arising therefrom to Korean Patent Application No. 10-2021-0108752, filed with the Korean Intellectual Property Office on August 18, 2021, the contents of which are incorporated herein by reference in their entirety. Prior Technology

[0003] As a solution for increasing the density of semiconductor devices, multi-gate transistors have been proposed for forming multi-channel active patterns (and / or silicon bodies) in the shape of fins and / or nanowires on a substrate and forming gates on the surface of the multi-channel active patterns.

[0004] Because this multi-gate transistor uses a three-dimensional channel, it is easy to scale. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed.

[0005] Meanwhile, as the spacing between semiconductor devices decreases, research will be needed to reduce capacitance while ensuring electrical stability between contacts in the semiconductor device. Summary of the Invention

[0006] Some of the objectives of the exemplary embodiments disclosed herein are to provide a semiconductor device that can improve device performance and reliability.

[0007] The objectives of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description of this disclosure any additional objectives not mentioned herein.

[0008] According to the present disclosure, a semiconductor device is provided, comprising: a gate structure including a gate electrode and a gate capping pattern on an upper surface of the gate electrode; a source / drain pattern located on at least one side of the gate structure; and a source / drain contact located on and connected to the upper surface of the source / drain pattern, the source / drain contact extending along a sidewall of the gate electrode, wherein the upper surface of the source / drain contact includes a protruding curved surface.

[0009] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a gate structure including a gate electrode and a gate capping pattern on an upper surface of the gate electrode; a source / drain pattern located on at least one side of the gate structure; and a source / drain contact located on and connected to the upper surface of the source / drain pattern, wherein at least a portion of the source / drain contact protrudes above the upper surface of the gate capping pattern, and the upper surface of the gate capping pattern includes a recessed curved surface.

[0010] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: an active pattern including a lower pattern and a wafer pattern on the lower pattern; a gate structure located on the active pattern, the gate structure including a gate electrode and a gate capping pattern, the gate electrode surrounding the wafer pattern and the gate capping pattern located on an upper surface of the gate electrode; a source / drain pattern located on at least one side of the gate structure; a source / drain contact located on and connected to the upper surface of the source / drain pattern; and a gate contact passing through the gate capping pattern and connected to the gate electrode, wherein a portion of the source / drain contact and a portion of the gate contact protrude above the upper surface of the gate capping pattern, and the upper surface of the source / drain contact includes a protruding curved surface. Simple Explanation of the Diagram

[0011] The above and other features and characteristics disclosed herein will become more apparent from the illustrative embodiments thereof described in detail with reference to the accompanying drawings, in which: Figure 1 is an example layout diagram illustrating a semiconductor device according to some embodiments. Figures 2A and 2B are cross-sectional views taken along line AA in Figure 1. Figure 3 is a cross-sectional view taken along line BB in Figure 1. Figure 4 is a cross-sectional view taken along line CC in Figure 1. Figure 5 is an enlarged view showing part P of Figure 2A. Figure 6 is an enlarged view showing part Q of Figure 3. Figures 7 and 8 are views illustrating a semiconductor device according to some embodiments. Figures 9 to 11 are views illustrating a semiconductor device according to some embodiments. Figures 12 to 14 are views illustrating a semiconductor device according to some embodiments. Figures 15 to 17 are views illustrating a semiconductor device according to some embodiments. Figures 18 and 19 are views illustrating a semiconductor device according to some embodiments. Figures 20 and 21 are views illustrating a semiconductor device according to some embodiments. Figures 22 and 23 are views illustrating a semiconductor device according to some embodiments. Figure 24 is a view illustrating a semiconductor device according to some embodiments. Figure 25 is a view illustrating a semiconductor device according to some embodiments. Figures 26 to 29 are views illustrating a semiconductor device according to some embodiments. Figure 30 is a view illustrating a semiconductor device according to some embodiments. Figures 31 to 33 are views illustrating a semiconductor device according to some embodiments. Figures 34 to 38 are views illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Implementation

[0012] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this specification, for ease of description, spatially relative terms such as "lower," "upper," "above," "below," etc., are used to describe the relationship between one element and another as shown in the figures. In addition to the orientations depicted in the figures, such spatially relative terms are also intended to cover different orientations of the device during use or operation. For example, the device may also be oriented in other ways (e.g., flipped and / or rotated 90 degrees and / or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0013] As shown, semiconductor devices according to some embodiments of this disclosure include, but are not limited to: fin transistors (FinFETs) comprising channel regions with fin-patterned shapes, transistors comprising nanowires and / or nanosheets, and, for example, multi-bridged channel field-effect transistors (MBCFET™). However, embodiments are not so limited, and semiconductor devices according to some embodiments may include tunneling transistors (e.g., tunneling FETs) and / or three-dimensional (3D) transistors. Semiconductor devices according to some embodiments may include planar transistors. Furthermore, the technical spirit of this disclosure can be applied to transistors (FETs) based on two-dimensional (2D) materials and / or their heterostructures.

[0014] Additionally, a semiconductor device according to some embodiments may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and / or similar transistors.

[0015] A semiconductor device according to some embodiments will be described with reference to Figures 1 through 6.

[0016] Figure 1 is an example layout diagram illustrating a semiconductor device according to some embodiments. Figures 2A and 2B are cross-sectional views taken along line AA of Figure 1. Figure 3 is a cross-sectional view taken along line BB of Figure 1. Figure 4 is a cross-sectional view taken along line CC of Figure 1. Figure 5 is an enlarged view showing portion P of Figure 2A. Figure 6 is an enlarged view showing portion Q of Figure 3.

[0017] For ease of description, the source / drain via plug 180, the gate via plug 185, and the wiring 205 are not shown in Figure 1. Furthermore, although the gate contact 175 is shown disposed on one of the plurality of first gate electrodes 120, this is merely an example of an exemplary embodiment, and the exemplary embodiment is not limited thereto.

[0018] Referring to Figures 1 to 6, a semiconductor device according to some embodiments may include: a first active pattern AP1, a second active pattern AP2, at least one first gate electrode 120, a source / drain contact 170, a gate contact 175, a source / drain via plug 180, a gate via plug 185, and wiring 205.

[0019] The semiconductor device may include a substrate 100. The substrate 100 may be a semiconductor substrate, and / or may be bulk silicon and / or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate and / or may contain other materials, such as germanium silicon, germanium-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and / or the like, but not limited thereto.

[0020] The first active pattern AP1 and the second active pattern AP2 can be disposed on the substrate 100. The first active pattern AP1 and the second active pattern AP2 can each extend in a first direction D1. The first active pattern AP1 and the second active pattern AP2 can be disposed separately from each other in a second direction D2. For example, the first direction D1 can be a direction that intersects with the second direction D2.

[0021] In some exemplary embodiments, at least one of the first active pattern AP1 and / or the second active pattern AP2 may be a p-channel metal-oxide-semiconductor (PMOS) formation region and / or an n-channel metal-oxide-semiconductor (NMOS) formation region. For example, one of the first active pattern AP1 or the second active pattern AP2 may be a PMOS formation region and the other may be an NMOS formation region. In another example, both the first active pattern AP1 and the second active pattern AP2 may be NMOS formation regions. In other examples, both the first active pattern AP1 and the second active pattern AP2 may be PMOS formation regions.

[0022] The first active pattern AP1 and the second active pattern AP2 may be placed in logic and / or memory areas. For example, the first active pattern AP1 and / or the second active pattern AP2 may be placed in static random-access memory (SRAM) areas; and / or the first active pattern AP1 and / or the second active pattern AP2 may be placed in input / output (I / O) areas.

[0023] The first active pattern AP1 and the second active pattern AP2 can be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and multiple first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and multiple second sheet patterns NS2.

[0024] Each of the first lower pattern BP1 and the second lower pattern BP2 may protrude from the base 100. Each of the first lower pattern BP1 and the second lower pattern BP2 may extend in the first direction D1.

[0025] The first lower pattern BP1 may be spaced apart from the second lower pattern BP2 in the second direction D2. The first lower pattern BP1 and the second lower pattern BP2 may be separated from each other by a fin groove FT extending in the first direction D1.

[0026] Multiple first patterns NS1 can be disposed on the upper surface of a first lower pattern BP1. The multiple first patterns NS1 can be spaced apart from the first lower pattern BP1 in a third direction D3. Individual first patterns NS1 can also be spaced apart from each other in the third direction D3. The third direction D3 can be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 can be the thickness direction of the substrate 100. The first direction D1 can be a direction intersecting the second direction D2.

[0027] Multiple second patterns NS2 can be disposed on the upper surface of the second lower pattern BP2. Multiple second patterns NS2 can be spaced apart from the second lower pattern BP2 in the third direction D3. Individual second patterns NS2 can also be spaced apart from each other in the third direction D3.

[0028] Although the first pattern NS1 and the second pattern NS2 are shown as three pattern sheets stacked on a third-party D3, the exemplary embodiments are not limited thereto. For example, the first pattern NS1 and the second pattern NS2 may contain fewer and / or more pattern sheets.

[0029] The first lower pattern BP1 and the second lower pattern BP2 may be formed by etching a portion of the substrate 100 and / or may include an epitaxial layer grown from the substrate 100. In some exemplary embodiments, the first lower pattern BP1 and the second lower pattern BP2 may include the same material as the substrate 100. For example, each of the first lower pattern BP1 and the second lower pattern BP2 may include silicon and / or germanium (which are elemental semiconductor materials); and / or the first lower pattern BP1 may include a compound semiconductor, such as a group IV-IV compound semiconductor and / or a group III-V compound semiconductor.

[0030] Group IV-IV compound semiconductors may be binary and / or ternary compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge) and / or tin (Sn), and / or compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge) and / or tin (Sn), which are doped with Group IV elements.

[0031] Group III-V compound semiconductors may be, for example, binary, ternary, and / or quaternary compounds, wherein the compound semiconductor is formed by a combination of at least one of aluminum (Al), gallium (Ga), and / or indium (In) (which are Group III elements) and at least one of phosphorus (P), arsenic (As), and / or antimony (Sb) (which are Group V elements).

[0032] Each of the first pattern NS1 and the second pattern NS2 may contain, for example, an elemental semiconductor (e.g., silicon and / or germanium), a group IV-IV compound semiconductor, and / or a group III-V compound semiconductor. The first pattern NS1 may contain the same material as the first lower pattern BP1 and / or may contain a different material than the first lower pattern BP1. Similarly, the second pattern NS2 may contain the same material as the second lower pattern BP2 and / or may contain a different material than the second lower pattern BP2.

[0033] In some exemplary embodiments, the first lower pattern BP1 and the second lower pattern BP2 may contain silicon and may be referred to as silicon lower patterns, and / or the first sheet pattern NS1 and the second sheet pattern NS2 may contain silicon and may be referred to as silicon sheet patterns.

[0034] In some exemplary embodiments, the width of the first pattern NS1 in the second direction D2 may increase or decrease proportionally to the width of the first lower pattern BP1 in the second direction D2. For example, although the width of the first pattern NS1 in the second direction D2 is shown as uniform, this is merely for descriptive purposes and the exemplary embodiments are not limited thereto. For example, unlike the illustrated example, the width of the first pattern NS1 in the second direction D2 may be reduced based on, for example, the distance from the first lower pattern BP1.

[0035] The field insulating layer 105 may be formed on the substrate 100 and may fill at least a portion of the fin trench FT.

[0036] For example, the field insulating layer 105 may be disposed on the sidewalls of the first lower pattern BP1 and the second lower pattern BP2. The field insulating layer 105 may, for example, not be disposed on the upper surface of the first lower pattern BP1 and the upper surface of the second lower pattern BP2.

[0037] In some exemplary embodiments, the field insulating layer 105 may completely cover the sidewalls of the first lower pattern BP1, but the exemplary embodiments are not limited thereto. For example, unlike the illustrated example, the field insulating layer 105 may cover a portion of the sidewalls of the first lower pattern BP1. In this case, a portion of the first lower pattern BP1 may protrude beyond the upper surface of the field insulating layer 105 on the third direction D3.

[0038] Each of the first pattern NS1 and the second pattern NS2 is disposed above the upper surface of the field insulating layer 105. The field insulating layer 105 may comprise, for example, an insulator, such as an oxide layer, a nitride layer, an oxynitride layer, and / or combinations thereof. Although the field insulating layer 105 is shown as a single layer, this is for ease of description only, and exemplary embodiments are not limited thereto. For example, the field insulating layer 105 may comprise one or more layers.

[0039] At least one gate structure GS may be disposed on the substrate 100. For example, at least one gate structure GS may be disposed on the field insulating layer 105. The gate structure GS may extend in the second direction D2. Adjacent gate structures GS may be spaced apart from each other in the first direction D1.

[0040] The gate structure GS can be mounted on the first active pattern AP1 and the second active pattern AP2. The gate structure GS can intersect with the first active pattern AP1 and the second active pattern AP2.

[0041] Although the gate structure GS is shown positioned above the first active pattern AP1 and the second active pattern AP2, this is merely for descriptive purposes, and the exemplary embodiments are not limited thereto. For example, a portion of the gate structure GS may be divided into two parts, which may then be positioned on the first active pattern AP1 and the second active pattern AP2, respectively.

[0042] The gate structure GS can intersect with the first lower pattern BP1 and the second lower pattern BP2. The gate structure GS can surround the first pattern NS1 and the second pattern NS2.

[0043] The gate structure GS may include a first gate electrode 120, a first gate insulating layer 130, a first gate spacer 140, and a first gate cover pattern 145.

[0044] The gate structure GS may include an inter-gate structure GS_INT disposed between first patterns NS1 adjacent to each other in the third direction and between a first lower pattern BP1 and the first pattern NS1. The inter-gate structure GS_INT may include a first gate electrode 120 and a first gate insulating layer 130 disposed between the first patterns NS1 and between the first lower pattern BP1 and the first pattern NS1. Although not shown, the inter-gate structure GS_INT may also be disposed between second patterns NS2 adjacent to each other in the third direction D3 and between the second lower pattern BP2 and the second pattern NS2.

[0045] For example, the first gate electrode 120 may be disposed on the first lower pattern BP1 and the second lower pattern BP2. The first gate electrode 120 may intersect with the first lower pattern BP1 and the second lower pattern BP2. The first gate electrode 120 may surround the first pattern NS1. The first gate electrode 120 may surround the second pattern NS2.

[0046] The upper surface of the first gate electrode 120 may be a recessed curved surface that is recessed toward the upper surface AP1_US of the first active pattern. For example, the upper surface AP1_US of the first active pattern may be the upper surface of the first pattern NS1 disposed at the uppermost portion of the first pattern NS1. However, the exemplary embodiments are not limited to this. For example, unlike the illustrated example, the upper surface of the first gate electrode 120 may be a flat plane.

[0047] The first gate electrode 120 may comprise a conductive material. For example, the conductive material may be (and / or comprise) at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. For example, the first gate electrode 120 may comprise, but is not limited to, at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride... Tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof and / or similar substances. Conductive metal oxides and conductive metal nitrides may include, but are not limited to, the conductive oxide forms of the materials described above.

[0048] The first gate electrode 120 may be disposed on both sides of the first source / drain pattern 150, which will be described later. The gate structure GS may be disposed on both sides of the first source / drain pattern 150, for example, in a first direction D1.

[0049] For example, in some embodiments, the first gate electrode 120 disposed on both sides of the first source / drain pattern 150 may be a normal gate electrode used as the gate of a transistor. In some embodiments, the first gate electrode 120 disposed on one side of the first source / drain pattern 150 may be used as the gate of a transistor, but the first gate electrode 120 disposed on the other side of the first source / drain pattern 150 may be a dummy gate electrode.

[0050] Although not shown, the first gate electrode 120 may be disposed on both sides of the second source / drain pattern 250, which will be described later. The gate structure GS may be disposed on both sides of the second source / drain pattern 250 in the first direction D1.

[0051] The first gate insulating layer 130 may extend along the upper surface of the field insulating layer 105, the upper surface of the first lower pattern BP1, and the upper surface of the second lower pattern BP2. The first gate insulating layer 130 may also surround the first pattern NS1. The first gate insulating layer 130 may also surround the second pattern NS2. For example, the first gate insulating layer 130 may be disposed around the first pattern NS1 and around the second pattern NS2. The first gate electrode 120 is disposed on the first gate insulating layer 130. For example, the first gate insulating layer 130 may be disposed between the first gate electrode 120 and the first pattern NS1, and between the first gate electrode 120 and the second pattern NS2.

[0052] The first gate insulating layer 130 may be an insulating material. For example, the insulating material may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and / or a high dielectric constant material. In this document, a high dielectric constant material may refer to a material with a dielectric constant greater than that of silicon oxide. A high dielectric constant material may, for example, include one (or more) of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0053] Although the first gate insulating layer 130 is shown as a single layer, this is for ease of description only, and the exemplary embodiments are not limited thereto. For example, the first gate insulating layer 130 may comprise multiple layers. The first gate insulating layer 130 may include an interface layer disposed between the first pattern NS1 and the first gate electrode 120 and / or between the second pattern NS2 and the first gate electrode 120, and a high dielectric constant insulating layer.

[0054] According to some embodiments, the semiconductor device may include a negative capacitance (NC) FET. For example, the first gate insulating layer 130 may include a ferroelectric material layer having ferroelectric properties and / or a paraelectric material layer having paraelectric properties.

[0055] Ferroelectric material layers can have negative capacitance, and paraelectric material layers can have positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is smaller compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance can be positive and can be greater than the absolute value of each individual capacitor.

[0056] Therefore, when a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric material layers can be increased. Based on the increased total capacitance, at room temperature, a transistor with a ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade.

[0057] The ferroelectric material layer may comprise a material with ferroelectric properties. For example, the material with ferroelectric properties may comprise at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. The material with ferroelectric properties may be doped with a dopant to, for example, improve at least one property of the material and / or promote the material phase with ferroelectric properties. For example, the dopant may comprise at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), zirconium (Zr), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), thorium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn).

[0058] The type of dopant contained in the ferroelectric material layer can vary depending on the ferroelectric material itself. For example, when the ferroelectric material layer contains hafnium oxide, the dopant contained in the ferroelectric material layer may contain at least one of thorium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y). For example, a material with ferroelectric properties may be hafnium zirconium oxide, which may be a material containing hafnium oxide (HfO) doped with zirconium (Zr) and / or a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0059] The amount of dopant can be less than the amount of another component and / or multiple components. For example, when the compound is hafnium oxide (HfO) and the dopant is aluminum (Al), the ferroelectric material layer can contain an aluminum ratio of 3 atomic% to 8 atomic% (atomic %). In this case, the dopant ratio can be, for example, the ratio of aluminum to hafnium and, for example, the sum of aluminum.

[0060] When the dopant is silicon (Si), the ferroelectric material layer can contain 2 atomic% to 10 atomic% silicon. When the dopant is yttrium (Y), the ferroelectric material layer can contain 2 atomic% to 10 atomic% yttrium. When the dopant is thorium (Gd), the ferroelectric material layer can contain 1 atomic% to 7 atomic% thorium. When the dopant is zirconium (Zr), the ferroelectric material layer can contain 50 atomic% to 80 atomic% zirconium.

[0061] The paraelectric material layer may contain a material having paraelectric properties. The paraelectric material may contain at least one of silicon oxide and / or metal oxides, for example, those having a high dielectric constant. The metal oxide contained in the paraelectric material layer may contain, but is not limited to, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide.

[0062] The ferroelectric and paraelectric material layers can contain the same material. Although they can contain the same material, the ferroelectric material layer may exhibit ferroelectric properties, while the paraelectric material layer may not. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer may differ from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0063] The ferroelectric material layer may have a thickness that indicates ferroelectric properties. For example, the ferroelectric material layer may have a thickness at or greater than the threshold thickness for ferroelectric properties. In some exemplary embodiments, for example, the thickness of the ferroelectric material layer may be from 0.5 nanometers to 10 nanometers, but the exemplary embodiments are not limited thereto. For example, since the threshold thickness indicating ferroelectric properties may vary depending on each ferroelectric material, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0064] In some exemplary embodiments, the first gate insulating layer 130 may include a ferroelectric material layer and / or may include a plurality of ferroelectric material layers spaced apart from each other. The first gate insulating layer 130 may have a deposition layer structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are deposited alternately.

[0065] The gate isolation structure GCS can separate the first gate electrodes 120 aligned in the second direction D2. Although the gate isolation structure GCS is shown as cutting a plurality of first gate electrodes 120 adjacent to each other in the first direction D1, this is only for illustrative purposes and the exemplary embodiments are not limited thereto. The gate isolation structure GCS may contain insulating material.

[0066] The first gate spacer 140 may be disposed on the sidewall 120_SW of the gate electrode. The first gate spacer 140 may extend in the second direction D2.

[0067] In Figure 2A, the first gate spacer 140 is not positioned between the first patterns NS1 adjacent to each other on the third direction D3, nor between the first pattern NS1 and the first lower pattern BP1. The first gate spacer 140 may consist only of the outer spacer.

[0068] In Figure 2B, the first gate spacer 140 may be disposed between the first patterns NS1 adjacent to each other on the third direction D3 and between the first pattern NS1 and the first lower pattern BP1. The first gate spacer 140 may include an outer spacer 141 and an inner spacer 142. The inner spacer 142 may be disposed between the first patterns NS1 adjacent to each other on the third direction D3 and between the first pattern NS1 and the first lower pattern BP1. The inner spacer 142 may contact the first gate insulating layer 130 of the gate inter-gate structure GS_INT.

[0069] The first gate spacer 140 may include an insulating material. The insulating material may be (and / or include) at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), combinations thereof, and / or similar materials.

[0070] Although not shown in Figure 1, a cross-sectional view taken along the second active pattern AP2 may resemble one of Figures 2A and 2B.

[0071] The gate cover pattern 145 can be disposed on the upper surface of the first gate electrode 120 and the upper surface of the first gate spacer 140. Unlike the example shown, the gate cover pattern 145 can also be disposed between the first gate spacers 140.

[0072] In a semiconductor device according to some embodiments, the upper surface 145_US of the gate cap pattern 145 may include a curved surface. For example, the upper surface 145_US of the gate cap pattern 145 may include a recessed curved surface. The upper surface 145_US of the gate cap pattern 145 may include a curved surface recessed toward the upper surface AP1_US of the first active pattern. The recessed curved surface of the gate cap pattern 145 may, for example, correspond to the recessed curved surface of the first gate electrode 120.

[0073] For example, in at least a portion of the gate cap pattern 145, as the gate cap pattern 145 moves further away from the source / drain contact 170 and the gate contact 175, the height of the upper surface 145_US of the gate cap pattern 145, measured in terms of the upper surface AP1_US of the first active pattern, decreases.

[0074] The gate cover pattern 145 may include an insulating material. The insulating material may be (and / or include) at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), combinations thereof, and / or similar materials.

[0075] The first source / drain pattern 150 may be formed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 may be disposed on the side of the gate structure GS. The first source / drain pattern 150 may be disposed between the gate structures GS.

[0076] The first source / drain pattern 150 may be disposed on at least one side of the gate structure GS. For example, the first source / drain pattern 150 may be disposed on both sides of the gate structure GS. Unlike the example shown, the first source / drain pattern 150 may also be disposed on one side of the gate structure GS and may not be disposed on the other side of the gate structure GS.

[0077] The second source / drain pattern 250 may be disposed on the second lower pattern BP2. Although not shown, the shape of the second source / drain pattern 250 disposed on the second lower pattern BP2 may be similar to the shape of the first source / drain pattern 150 disposed in Figures 2A and 2B.

[0078] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial pattern. The first source / drain pattern 150 and the second source / drain pattern 250 may include, for example, a semiconductor material.

[0079] The first source / drain pattern 150 may be included in the source / drain of a transistor that uses the first active pattern AP1 (e.g., the first pattern NS1) as the channel region. The second source / drain pattern 250 may be included in the source / drain of a transistor that uses the second pattern NS2 as the channel region.

[0080] The source / drain etch termination layer 156 can be disposed on the upper surface of the field insulating layer 105, the sidewall of the gate structure GS, the upper surface of the first source / drain pattern 150, the sidewall of the first source / drain pattern 150, the upper surface of the second source / drain pattern 250, and the sidewall of the second source / drain pattern 250.

[0081] The source / drain etch stop layer 156 may comprise a material having etch selectivity relative to the first interlayer insulating layer 191, which will be described later. The source / drain etch stop layer 156 may comprise an insulating material, such as at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), combinations thereof, and / or the like. However, exemplary embodiments are not limited thereto, and unlike the illustrated examples, the source / drain etch stop layer 156 may not be formed.

[0082] The first interlayer insulating layer 191 may be formed on the field insulating layer 105. The first interlayer insulating layer 191 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250.

[0083] In a semiconductor device according to some embodiments, the first interlayer insulating layer 191 may not cover the upper surface 145_US of the gate cap pattern.

[0084] In a semiconductor device according to some embodiments, the upper surface of the first interlayer insulating layer 191 may include a recessed curved surface. For example, the upper surface of the first interlayer insulating layer 191 may include a curved surface recessed toward the field insulating layer 105.

[0085] In at least a portion of the first interlayer insulation layer 191, as the first interlayer insulation layer 191 moves further away from the source / drain contact 170, the height of the upper surface of the first interlayer insulation layer 191, measured from the upper surface of the field insulation layer 105, decreases.

[0086] The first interlayer insulation layer 191 may comprise an insulating material. The insulating material may be (and / or comprise) at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. For example, low dielectric constant materials may include, but are not limited to, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silses quioxane (HSQ), bis-benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyl disiloxane (HMDS), trimethyl silyl borate (TMSB), diacetoxyditertiary siloxane (DADBS), and trimethyl silyl phosphate (Trimethyl silyl borate). Phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen SilaZen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicone glass (OSG), silicon low-K (SiLK), amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, combinations thereof and / or the like.

[0087] Source / drain contacts 170 may be disposed on the first active pattern AP1 and the second active pattern AP2. Source / drain contacts 170 may be disposed on the first source / drain pattern 150. Source / drain contacts 170 may be connected to the first source / drain pattern 150 on the first active pattern AP1. Source / drain contacts 170 may extend along the sidewall 120_SW of the gate electrode in a third direction D3.

[0088] Furthermore, the source / drain contact 170 can be disposed on the second source / drain pattern 250. The source / drain contact 170 can be connected to the second source / drain pattern 250 on the second active pattern AP2.

[0089] Unlike the illustrated example, a portion of the source / drain contact 170 connected to the first source / drain pattern 150 may be directly connected to the source / drain contact 170 connected to the second source / drain pattern 250. For example, in a semiconductor device according to some embodiments, at least one source / drain contact 170 may be disposed above the first active pattern AP1 and the second active pattern AP2.

[0090] Source / drain contacts 170 may be disposed within a first interlayer insulating layer 191. Source / drain contacts 170 may be surrounded by the first interlayer insulating layer 191. Source / drain contacts 170 extend through a source / drain etch-stop layer 156. Source / drain contacts 170 are shown in contact with the source / drain etch-stop layer 156, but exemplary embodiments are not limited thereto.

[0091] A first silicide layer 155 may be formed between the source / drain contact 170 and the first source / drain pattern 150. A second silicide layer 255 may be formed between the source / drain contact 170 and the second source / drain pattern 250. The first silicide layer 155 is shown as being formed along the outline of the boundary between the first source / drain pattern 150 and the source / drain contact 170, and the outline of the boundary between the second source / drain pattern 250 and the source / drain contact 170, but the exemplary embodiments are not limited thereto. The first silicide layer 155 and the second silicide layer 255 may contain, for example, a metallic silicide material.

[0092] The source / drain contact 170 may include a source / drain barrier layer 171 and a source / drain fill layer 172. The source / drain fill layer 172 may be disposed on the source / drain barrier layer 171. The source / drain barrier layer 171 may extend along the bottom surface of the source / drain fill layer 172 and the sidewall 172_SW of the source / drain fill layer 172. A first source / drain pattern 150 and a second source / drain pattern 250 are respectively connected to the source / drain barrier layer 171 and the source / drain fill layer 172.

[0093] Gate contact 175 may be disposed in gate structure GS. Gate contact 175 may be connected to first gate electrode 120 by passing through gate cover pattern 145. For example, gate contact 175 may be surrounded by gate cover pattern 145.

[0094] The gate contact 175 may be positioned at a location overlapping the gate structure GS. Although Figure 1 shows the gate contact 175 positioned where it does not overlap with the first active pattern AP1 and the second active pattern AP2, the gate contact 175 is not limited thereto. The gate contact 175 may be positioned at a location overlapping with at least one of the first active pattern AP1 or the second active pattern AP2.

[0095] The gate contact 175 may include a gate contact barrier layer 176 and a gate contact filler layer 177. The gate contact filler layer 177 may be disposed on the gate contact barrier layer 176. The gate contact barrier layer 176 may extend along the bottom surface of the gate contact filler layer 177 and the sidewall 177_SW of the gate contact filler layer. The first gate electrode 120 is electrically connected to the gate contact barrier layer 176 and the gate contact filler layer 177.

[0096] A portion of the source / drain contact 170 may protrude above the upper surface 145_US of the gate cap pattern. For example, a portion of the source / drain contact 170 may protrude above the upper surface 145_US of the gate cap pattern, taking into account the point most adjacent to the source / drain contact 170. A portion of the source / drain contact 170 may protrude above the upper surface of the first interlayer insulation layer 191. Taking into account the point most adjacent to the source / drain contact 170, a portion of the source / drain contact 170 may protrude above the upper surface of the first interlayer insulation layer 191. For example, in a portion of the source / drain contact 170, the upper surface 170_US of the source / drain contact may include a protruding curved surface relative to the recessed curved surface of the gate cap pattern 145. For example, the upper surface 170_US of the source / drain contact may include a protruding curved surface. The upper surface 170_US of the source / drain contact may protrude away from the substrate 100. For example, the upper surface 172_US of the source / drain fill layer may include a protruding curved surface.

[0097] For example, in Figure 2A, the upper surface 170_US of the source / drain contact, measured from the upper surface AP1_US of the first active pattern, may be higher than the upper surface 145_US of the gate cap pattern. However, the exemplary embodiments are not limited to this. For example, in Figure 4, the upper surface 170_US of the source / drain contact, measured from the upper surface of the first lower pattern BP1, may be higher than the upper surface of the first interlayer insulating layer 191.

[0098] A portion of the source / drain barrier layer 171 and a portion of the source / drain fill layer 172 may protrude above the upper surface 145_US of the gate cap pattern, respectively. The source / drain barrier layer 171 and the source / drain fill layer 172 may protrude above the upper surface of the first interlayer insulating layer 191.

[0099] In Figure 5, the upper surface 170_US of the source / drain contact may include the upper surface 171_US of the source / drain barrier layer and the upper surface 172_US of the source / drain fill layer. The sidewall portion extending along the sidewall 172_SW of the source / drain fill layer of the source / drain barrier layer 171 includes the upper surface 171_US of the source / drain barrier layer.

[0100] In Figure 2A, taking the upper surface AP1_US of the first active pattern as a reference, the upper surface 171_US of the source / drain barrier layer and the upper surface 172_US of the source / drain fill layer can be higher than the upper surface 145_US of the gate cap pattern. In Figure 5, taking the upper surface of the first lower pattern BP1 as a reference, the upper surface 171_US of the source / drain barrier layer and the upper surface 172_US of the source / drain fill layer can be higher than the upper surface of the first interlayer insulating layer 191.

[0101] A portion of the source / drain fill layer 172 may protrude above the upper surface 171_US of the source / drain barrier layer. A portion of the source / drain fill layer 172 is positioned above the upper surface 171_US of the source / drain barrier layer. The upper surface 172_US of the source / drain fill layer may be higher than the upper surface 171_US of the source / drain barrier layer, measured in terms of the upper surface AP1_US of the first active pattern or the upper surface BP1 of the first lower pattern.

[0102] In Figure 5, the source / drain barrier layer 171 is shown to completely cover the sidewall 172_SW of the source / drain fill layer, but the exemplary embodiment is not limited thereto. The source / drain barrier layer 171 may not cover a portion of the sidewall 172_SW of the source / drain fill layer.

[0103] A portion of the gate contact 175 may protrude above the upper surface 145_US of the gate cover pattern. For example, taking the point most adjacent to the gate contact 175 as an example, a portion of the gate contact 175 may protrude above the upper surface 145_US of the gate cover pattern.

[0104] In Figures 2A and 3, taking the upper surface AP1_US of the first active pattern as a reference, the upper surface 175_US of the gate contact can be higher than the upper surface 145_US of the gate cover pattern.

[0105] Each of a portion of the gate contact barrier layer 176 and a portion of the gate contact filler layer 177 may protrude above the upper surface 145_US of the gate cover pattern.

[0106] The upper surface 175_US of the gate contact may include the upper surface 176_US of the gate contact barrier layer and the upper surface 177_US of the gate contact filler layer. A sidewall portion extending along the sidewall 177_SW of the gate contact filler layer of the gate contact barrier layer 176 includes the upper surface 176_US of the gate contact barrier layer. With respect to the upper surface AP1_US of the first active pattern, the upper surface 176_US of the gate contact barrier layer and the upper surface 177_US of the gate contact filler layer may be higher than the upper surface 145_US of the gate capping pattern.

[0107] A portion of the gate contact filler layer 177 may protrude above the upper surface 176_US of the gate contact barrier layer. A portion of the gate contact filler layer 177 is positioned above the upper surface 176_US of the gate contact barrier layer. With respect to the upper surface AP1_US of the first active pattern, the upper surface 177_US of the gate contact filler layer may be higher than the upper surface 176_US of the gate contact barrier layer.

[0108] In Figure 6, the gate contact barrier layer 176 is shown to completely cover the sidewall 177_SW of the gate contact filler layer, but the exemplary embodiment is not limited thereto. The gate contact barrier layer 176 may not cover a portion of the sidewall 177_SW of the gate contact filler layer.

[0109] The upper surface 175_US of the gate contact may include a protruding curved surface. The upper surface 175_US of the gate contact may protrude away from the substrate 100. For example, the upper surface 177_US of the gate contact filler layer may include a protruding curved surface.

[0110] Each of the source / drain barrier layer 171 and / or the gate contact barrier layer 176 may comprise a conductive material. The conductive material may be (and / or comprise) at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and / or two-dimensional (2D) materials. In a semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. Two-dimensional (2D) materials may include two-dimensional allotropes and / or two-dimensional compounds, and may include, but are not limited to, at least one of graphene, molybdenum disulfide (MoS₂), molybdenum diselenide (MoSe₂), tungsten diselenide (WSe₂), or tungsten disulfide (WS₂). Since two-dimensional materials are listed by way of example only, the two-dimensional materials that may be included in the semiconductor devices disclosed herein are not limited to the aforementioned example materials.

[0111] Each of the source / drain fill layer 172 and / or the gate contact fill layer 177 may contain a conductive material. The conductive material may be (and / or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), combinations thereof, and / or the like.

[0112] The second interlayer insulation layer 192 may be disposed on the first interlayer insulation layer 191 and the gate structure GS. The second interlayer insulation layer 192 may contain an insulating material. The insulating material may be (and / or include) at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, low dielectric constant materials, combinations thereof and / or similar materials.

[0113] The lower etch stop layer 195 may be disposed between the first interlayer insulating layer 191 and the second interlayer insulating layer 192. The lower etch stop layer 195 may extend along the upper surface 145_US of the gate cap pattern, the upper surface of the first interlayer insulating layer 191, the upper surface 170_US of the source / drain contact, and the upper surface 175_US of the gate contact.

[0114] The lower etch stop layer 195 may comprise a material with etch selectivity relative to the second interlayer insulating layer 192. The lower etch stop layer 195 may comprise at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), boron silicon nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum carbonitride (AlOC), combinations thereof, and / or the like. The lower etch stop layer 195 is shown as a single layer, but exemplary embodiments are not limited thereto. Unlike the illustrated examples, in some embodiments, the lower etch stop layer 195 may not be formed.

[0115] The wiring structure is disposed on the source / drain contact 170 and the gate contact 175. The wiring structure may include a source / drain via plug 180, a gate via plug 185, and wiring lines 205.

[0116] Source / drain via plug 180 and gate via plug 185 can be disposed in the second interlayer insulating layer 192. Source / drain via plug 180 can be directly connected to source / drain contact 170 by passing through the lower etch stop layer 195. Gate via plug 185 can be directly connected to gate contact 175 by passing through the lower etch stop layer 195.

[0117] The boundary where the source / drain via plug 180 and the source / drain contact 170 meet may include an upwardly convex curved surface, such as the upper surface 170_US of the source / drain contact. The boundary where the gate via plug 185 and the gate contact 175 meet may include an upwardly convex curved surface, such as the upper surface 170_US of the source / drain contact.

[0118] Because the upper surface 170_US of the source / drain contact has a protruding curved surface, the contact surface between the source / drain contact 170 and the source / drain via 180 can be increased. Furthermore, because the upper surface 175_US of the gate contact has a protruding curved surface, the contact surface between the gate contact 175 and the gate via plug 185 can be increased. Therefore, the resistance between the source / drain contact 170 and the source / drain via plug 180, and the resistance between the gate contact 175 and the gate via plug 185, can be reduced, and the performance and reliability of the semiconductor device according to the exemplary embodiments of this disclosure can be improved.

[0119] The source / drain via plug 180 may include a first via barrier layer 180a and a first via fill layer 180b. The gate via plug 185 may include a second via barrier layer 185a and a second via fill layer 185b. The first via barrier layer 180a may extend along the sidewall and bottom surface of the first via fill layer 180b. The second via barrier layer 185a may extend along the sidewall and bottom surface of the second via fill layer 185b.

[0120] Each of the first through-hole barrier layer 180a and the second through-hole barrier layer 185a may contain a conductive material. The conductive material may be (and / or include) at least one of the following: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), two-dimensional (2D) materials, combinations thereof, and / or similar materials.

[0121] Each of the first via filling layer 180b and the second via filling layer 185b may contain a conductive material. The conductive material may be (and / or include) at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), combinations thereof, and / or similar substances.

[0122] In Figure 5, at the point where the source / drain via plug 180 and the source / drain contact 170 are in contact with each other, the width of the source / drain contact 170 in the first direction D1 is the same as the width of the source / drain via plug 180 in the first direction D1, but the example embodiment is not limited to this.

[0123] In Figure 6, at the point where the gate through-hole plug 185 and the gate contact 175 are in contact with each other, the width of the gate contact 175 in the second direction D2 is the same as the width of the gate through-hole plug 185 in the second direction D2, but the example embodiment is not limited to this.

[0124] The upper etch stop layer 196 may be disposed between the second interlayer insulating layer 192 and the third interlayer insulating layer 193. The upper etch stop layer 196 may extend along the upper surface of the second interlayer insulating layer 192.

[0125] The upper etch stop layer 196 may comprise a material with etch selectivity relative to the third interlayer insulating layer 193. The upper etch stop layer 196 may comprise at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), boron silicon nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum carbonitride (AlOC), combinations thereof, and / or the like. The upper etch stop layer 196 is shown as a single layer, but exemplary embodiments are not limited thereto. Unlike the illustrated example, in some exemplary embodiments, the upper etch stop layer 196 may not be formed.

[0126] Wiring line 205 can be placed in the third interlayer insulation layer 193. Wiring line 205 is connected to source / drain via plug 180. Wiring line 205 is in contact with source / drain via plug 180. Wiring line 205 is connected to gate via plug 185. Wiring line 205 is in contact with gate via plug 185.

[0127] The cabling line 205 may include a cabling barrier layer 205a and a cabling fill layer 205b.

[0128] The wiring barrier layer 205a may contain a conductive material. The conductive material may be (and / or contain) at least one of the following: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), or two-dimensional (2D) materials. The wiring filler layer 205b may contain at least one of the following: aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), combinations thereof, and / or similar materials.

[0129] In some exemplary embodiments, unlike the illustrated example, the first via barrier layer 180a may not be positioned between the first via filling layer 180b and the wiring filling layer 205b, and / or the second via barrier layer 185a may not be positioned between the second via filling layer 185b and the wiring filling layer 205b.

[0130] Although not shown, a first connection point connecting the source / drain via plug 180 to the source / drain contact 170 may be further disposed between the source / drain via plug 180 and the source / drain contact 170. Furthermore, a second connection point connecting the gate via plug 185 to the gate contact 175 may be further disposed between the gate via plug 185 and the gate contact 175.

[0131] Figures 7 and 8 are views illustrating a semiconductor device according to some embodiments. Figures 9 to 11 are views illustrating a semiconductor device according to some embodiments. Figures 12 to 14 are views illustrating a semiconductor device according to some embodiments. Figures 15 to 17 are views illustrating a semiconductor device according to some embodiments. Figures 18 and 19 are views illustrating a semiconductor device according to some embodiments. For ease of description, the following description will be based on the differences from Figures 1 to 6.

[0132] For reference, Figures 8, 14, and 17 are enlarged views showing portions P of Figures 7, 12, and 15. Figures 8, 14, and 17 are enlarged views showing the boundary portions of the source / drain contact 170 and the source / drain via plug 180. Although not shown, the boundary portions of the gate contact 175 and the gate via plug 185 can be easily inferred from Figures 8, 14, and 17.

[0133] Referring to Figures 7 and 8, in a semiconductor device according to some embodiments, the upper surface 171_US of the source / drain barrier layer 171, measured from the upper surface AP1_US of the first active pattern AP1, is lower than the upper surface 145_US of the gate capping pattern 145. However, the upper surface 172_US of the source / drain filling layer 172 is higher than the upper surface 145_US of the gate capping pattern 145.

[0134] The upper surface 171_US of the source / drain barrier layer 171 may be lower than the upper surface 145_US of the gate cap pattern 145 by up to a first height HD. The source / drain barrier layer 171 may be completely disposed below the upper surface 145_US of the gate cap pattern 145.

[0135] Although the source / drain via plug 180 is shown in contact with the upper surface 171_US of the source / drain barrier layer, the source / drain via plug 180 is not limited thereto. Unlike the illustrated example, a portion of the lower etch-stop layer 195 may be inserted between the bottom surface of the source / drain via plug 180 and the upper surface 171_US of the source / drain barrier layer. As another example, a portion of the source / drain fill layer 172 may be movable to cover the upper surface 171_US of the source / drain barrier layer.

[0136] Referring to Figures 9 to 11, in a semiconductor device according to some embodiments, the upper surface 145_US of the gate cap pattern 145 may be a flat surface.

[0137] As the gate cap pattern 145 moves further away from the source / drain contact 170 and the gate contact 175, the height of the upper surface 145_US of the gate cap pattern 145, measured by the upper surface AP1_US of the first active pattern AP1, can be constant.

[0138] The upper surface of the first interlayer insulation layer 191 can be a flat plane. As the first interlayer insulation layer 191 moves away from the source / drain contact 170, the height of the upper surface of the first interlayer insulation layer 191, measured from the upper surface of the field insulation layer 105, can be constant.

[0139] In some exemplary embodiments, unlike the illustrated example, one of the upper surface 145_US of the gate cap pattern and the upper surface of the first interlayer insulation layer 191 may be a flat plane. The other of the upper surface 145_US of the gate cap pattern and the upper surface of the first interlayer insulation layer 191 may include a recessed curved surface.

[0140] In Figures 12 to 14, in a semiconductor device according to some embodiments, at the point where the source / drain via plug 180 and the source / drain contact 170 are in contact with each other, the boundary between the source / drain via plug 180 and the source / drain contact 170 may be a flat plane.

[0141] In a cross-sectional view of the source / drain contact 170 taken along the first direction D1, the upper surface 170_US of the source / drain contact where the source / drain through-hole plug 180 is not landed may include a protruding curved surface.

[0142] In a cross-sectional view of the source / drain contact 170 taken along the second direction D2, a portion of the source / drain via plug 180 may be recessed into the source / drain contact 170. At the boundary between the source / drain via plug 180 and the source / drain contact 170, the upper surface 170_US of the source / drain contact may include a recessed curved portion 170_USV. For example, in FIG. 13, the upper surface 170_US of the source / drain contact may include a protruding curved portion and a recessed curved portion 170_USV.

[0143] Referring to Figures 15 to 17, in a semiconductor device according to some embodiments, the upper surface 170_US of the source / drain contact may include a protruding bent portion 170_USX and a recessed bent portion 170_USV.

[0144] On the upper surface 170_US of the source / drain contact, the protruding curved portion 170_USX is a portion that does not form a boundary with the source / drain through-hole plug 180, and the recessed curved portion 170_USV may be a portion that forms a boundary with the source / drain through-hole plug 180.

[0145] The upper surface 175_US of the gate contact may include a protruding curved portion and a recessed curved portion. On the upper surface 175_US of the gate contact, the recessed curved portion may be the boundary portion between the gate contact 175 and the gate through-hole plug 185.

[0146] At the point where the source / drain through-hole plug 180 and the source / drain contact 170 are in contact with each other, the width of the source / drain contact 170 in the first direction D1 may be greater than the width of the source / drain through-hole plug 180 in the first direction D1.

[0147] At the point where the gate through-hole plug 185 and the gate contact 175 are in contact with each other, the width of the gate contact 175 in the second direction D2 may be greater than the width of the gate through-hole plug 185 in the second direction D2.

[0148] Referring to Figures 18 and 19, in a semiconductor device according to some embodiments, a first interlayer insulating layer 191 may cover the upper surface 145_US of a gate cap pattern.

[0149] The first interlayer insulation layer 191 may cover the source / drain contact 170, which protrudes more than the upper surface 145_US of the gate cap pattern. The first interlayer insulation layer 191 may cover the upper surface 170_US of the source / drain contact, which has a protruding curved surface.

[0150] The upper surface of the first interlayer insulating layer 191 may be a flat plane. The lower etch stop layer 195 may be formed along the contour of the upper surface of the first interlayer insulating layer 191.

[0151] The gate contact 175 protrudes above the upper surface 145_US of the gate cover pattern. The first interlayer insulation layer 191 may cover the sidewall of the gate contact 175, which protrudes further than the upper surface 145_US of the gate cover pattern.

[0152] In a semiconductor device according to some embodiments, the upper surface 175_US of the gate contact may be a flat plane. The first interlayer insulating layer 191 does not cover the upper surface 175_US of the gate contact.

[0153] In some exemplary embodiments, unlike the illustrated example, the boundary portion between the gate contact 175 and the gate through-hole plug 185 may include a recessed bend as shown in FIG16.

[0154] Figures 20 and 21 are views illustrating a semiconductor device according to some embodiments. Figures 22 and 23 are views illustrating a semiconductor device according to some embodiments. Figure 24 is a view illustrating a semiconductor device according to some embodiments. Figure 25 is a view illustrating a semiconductor device according to some embodiments. For ease of description, the following description will be based on differences from Figures 1 to 6. However, the exemplary embodiments are not limited thereto, and may also apply to embodiments included in Figures 7 to 19.

[0155] Referring to Figures 20 and 21, in a semiconductor device according to some embodiments, the source / drain contact 170 and the gate contact 175 do not include a barrier layer.

[0156] The source / drain contact 170 may contain only the source / drain fill layer 172 without the source / drain barrier layer 171. The gate contact 175 may contain only the gate contact fill layer 177 without the gate contact barrier layer 176.

[0157] Each of the source / drain contact 170 and the gate contact 175 may have a single-layer structure. For example, the source / drain contact 170 and the gate contact 175 may be formed from a single layer. Each of the source / drain contact 170 and the gate contact 175 may have a single conductive layer structure. In some exemplary embodiments, unlike this, as shown in Figures 2A and 3, the source / drain contact 170 and the gate contact 175 (each of which includes a barrier layer and a filler layer) may have a multi-conductive layer structure.

[0158] In some exemplary embodiments, unlike the illustrated example, one of the source / drain contact 170 and the gate contact 175 may have a single conductive layer structure, while the other may have a multi-conductive layer structure.

[0159] Referring to Figures 22 and 23, in a semiconductor device according to some embodiments, the source / drain via plug 180 and the gate via plug 185 do not include a barrier layer.

[0160] The source / drain via plug 180 may contain only the first via filling layer 180b without the first via barrier layer 180a. The gate via plug 185 may contain only the second via filling layer 185b without the second via barrier layer 185a.

[0161] Each of the source / drain via plug 180 and the gate via plug 185 may have a single-layer structure. Each of the source / drain via plug 180 and the gate via plug 185 may have a single conductive layer structure.

[0162] In some exemplary embodiments, unlike the illustrated example, one of the source / drain via plug 180 and the gate via plug 185 may have a single conductive layer structure, while the other may have a multi-conductive layer structure.

[0163] Referring to FIG24, in a semiconductor device according to some embodiments, the source / drain contact 170 may include a first portion 170A and a second portion 170B. The first portion 170A of the source / drain contact may be directly connected to the second portion 170B of the source / drain contact.

[0164] The first portion 170A of the source / drain contact 170 is the portion where the source / drain via plug 180 lands (e.g., where the source / drain contact 170 contacts the source / drain via plug 180). The source / drain contact 170 can be connected to wiring 205 via the first portion 170A of the source / drain contact. The second portion 170B of the source / drain contact 170 is not the portion where the source / drain via plug 180 lands.

[0165] The upper surface of the first portion 170A of the source / drain contact is higher than the upper surface of the second portion 170B of the source / drain contact 170. With respect to the upper surface of the field insulating layer 105, the upper surface of the first portion 170A of the source / drain contact 170 is higher than the upper surface of the second portion 170B of the source / drain contact 170. For example, the upper surface 170_US of the source / drain contact 170 can be the upper surface of the first portion 170A of the source / drain contact 170.

[0166] A portion of the first portion 170A of the source / drain contact 170 may protrude above the upper surface of the first interlayer insulation layer 191. Although not shown, a portion of the first portion 170A of the source / drain contact 170 may protrude above the upper surface of the gate cap pattern 145 (upper surface 145_US of FIG. 2A).

[0167] The upper surface of the first portion 170A of the source / drain contact 170 may include a protruding curved surface.

[0168] The source / drain contact 170 may have a T-shape that can be rotated up to 180°, but is not limited thereto. Alternatively, the source / drain contact 170 may have an L-shape.

[0169] Referring to FIG25, in a semiconductor device according to some embodiments, the source / drain contact 170 may include a lower source / drain contact 170B and an upper source / drain contact 170U.

[0170] The lower source / drain contact 170B may include a lower source / drain barrier layer 171B and a lower source / drain fill layer 172B. The upper source / drain contact 170U may include an upper source / drain barrier layer 171U and an upper source / drain fill layer 172U.

[0171] A portion of the upper source / drain contact 170U may protrude above the upper surface of the first interlayer insulation layer 191. Although not shown, a portion of the upper source / drain contact 170U may protrude above the upper surface of the gate cap pattern (upper surface 145_US of FIG. 2A).

[0172] The upper surface 170_US of the source / drain contact 170 may be the upper surface of the upper source / drain contact 170U. The upper surface 170_US of the upper source / drain contact 170 may include a protruding curved surface.

[0173] The materials contained in the lower source / drain barrier layer 171B and the upper source / drain barrier layer 171U may be the same as the material of the source / drain barrier layer 171 described above. The materials contained in the lower source / drain filling layer 172B and the upper source / drain filling layer 172U may be the same as the material of the source / drain filling layer 172 described above.

[0174] For example, the upper source / drain contact 170U can be connected to the wiring 205 without a passive / drain via plug (source / drain via plug 180 in FIG. 2A). Although not shown, the gate contact (gate contact 175 in FIG. 3) can be connected to the wiring 205 without a gate via plug (gate via plug 185 in FIG. 3). In this case, the wiring 205 can be housed within the second interlayer insulating layer 192 and the lower etch-stop layer 195.

[0175] In some exemplary embodiments, unlike the illustrated example, a source / drain via plug (source / drain via plug 180 of FIG. 2A) may be positioned between the upper source / drain contact 170U and the wiring line 205. A gate via plug (gate via plug 185 of FIG. 3) may be positioned between the gate contact 175 and the wiring line 205.

[0176] Figures 26 to 29 are views illustrating a semiconductor device according to some embodiments. For ease of description, the following description will be based on differences from Figures 1 to 6. However, the exemplary embodiments are not limited thereto, and may also refer to the embodiments included in Figures 7 to 25. For reference, Figure 26 is an example layout diagram illustrating a semiconductor device according to some embodiments, and Figures 27 to 29 are cross-sectional views taken along lines AA, BB, and DD of Figure 26.

[0177] Referring to Figures 26 to 29, in a semiconductor device according to some embodiments, the first active pattern AP1 and the second active pattern AP2 may be fin-shaped patterns protruding above the upper surface of the field insulating layer 105.

[0178] Each of the first active pattern AP1 and the second active pattern AP2 may be placed within an active zone defined by the deep trench DT. The deep trench DT defines the field area placed between the active zones.

[0179] Two first active patterns AP1 and two second active patterns AP2 are shown as being placed in the active region, but the example embodiment is not limited thereto. One first active pattern AP1 and one second active pattern AP2 may be placed in the active region, and / or three or more first active patterns AP1 and three or more second active patterns AP2 may be placed in the active region.

[0180] The first active pattern AP1 and the second active pattern AP2, which are placed in the active area, can be separated from each other by a fin groove FT extending in the first direction D1.

[0181] Each of the first active pattern AP1 and the second active pattern AP2 may contain a semiconductor material, such as an elemental semiconductor (e.g., silicon and / or germanium) or a compound semiconductor (e.g., group IV-IV compound semiconductors and / or group III-V compound semiconductors). For example, the first active pattern AP1 and the second active pattern AP2 may contain the same material and / or the first active pattern AP1 may contain a material different from the material of the second active pattern AP2. When the first active pattern AP1 is disposed in a PMOS formation region and the second active pattern AP2 is disposed in an NMOS formation region, the first active pattern AP1 may be, but is not limited to, a silicon-germanium fin pattern, and the second active pattern AP2 may be, but is not limited to, a silicon fin pattern.

[0182] The field insulation layer 105 can be filled into the deep trench DT.

[0183] The gate structure GS does not include the inter-gate structure (the inter-gate structure GS_INT in Figure 2A).

[0184] In Figure 29, the first source / drain pattern 150 disposed on the first active pattern AP1 can be a connected epitaxial pattern that combines two epitaxial patterns. Unlike the example shown, the epitaxial patterns formed on each of the individual first active patterns AP1 can be separated from each other.

[0185] Figure 30 is a view illustrating a semiconductor device according to some embodiments. For ease of description, the following description will be based on differences from Figures 26 to 29.

[0186] Referring to Figure 30, in a semiconductor device according to some embodiments, a dummy protrusion pattern DPF may be placed in a field area that distinguishes the active region.

[0187] The deep trench (DT in Figure 28) is not formed in the field area. The upper surface of the dummy protrusion pattern DPF is covered by the field insulation layer 105.

[0188] Figures 31 to 33 are views illustrating a semiconductor device according to some embodiments. For reference, Figure 31 is a plan view illustrating a semiconductor device according to some embodiments. Figure 32 is a cross-sectional view taken along lines EE and FF of Figure 31. Figure 33 is a cross-sectional view taken along line GG of Figure 31.

[0189] Referring to Figures 31 to 33, a logic unit LC may be disposed on the substrate 100. A logic unit LC may refer to a logic element that performs a specific function (such as an inverter, flip-flop, etc.). A logic unit LC may include vertical transistors constituting logic elements and wires connecting the vertical transistors to each other.

[0190] The logic cell LC on the substrate 100 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a positive metal-oxide-semiconductor field-effect transistor (PMOSFET) region, and the second active region RX2 may be a negative MOSFET (NMOSFET) region. The first active region RX1 and the second active region RX2 may be defined by a trench TR formed on the upper portion of the substrate 100. The first active region RX1 and the second active region RX2 may be spaced apart from each other in the second direction D2.

[0191] A first lower epitaxial pattern SPO1 can be disposed on a first active region RX1, and a second lower epitaxial pattern SPO2 can be disposed on a second active region RX2. In a plan view, the first lower epitaxial pattern SPO1 can overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 can overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 can be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 can be disposed in a first recessed region RS1 of the substrate 100, and the second lower epitaxial pattern SPO2 can be disposed in a second recessed region RS2 of the substrate 100.

[0192] A third active pattern AP3 may be disposed on the first active region RX1, and a fourth active pattern AP4 may be disposed on the second active region RX2. Each of the third active pattern AP3 and the fourth active pattern AP4 may have a vertically protruding fin shape. In a plan view, each of the third active pattern AP3 and the fourth active pattern AP4 may have a strip shape extending in the second direction D2. The third active pattern AP3 may be configured along the first direction D1, and the fourth active pattern AP4 may be configured along the first direction D1.

[0193] Each of the third active patterns AP3 may include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each of the fourth active patterns AP4 may include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0194] A component isolation layer ST may be disposed on the substrate 100 to fill the trench TR. The component isolation layer ST may cover the upper surfaces of the first lower epitaxial pattern SpO1 and the second lower epitaxial pattern SpO2. The third active pattern AP3 and the fourth active pattern AP4 may protrude vertically above the component isolation layer ST.

[0195] A plurality of second gate electrodes 320 extending parallel to each other in the second direction D2 may be disposed on the element isolation layer ST. The second gate electrodes 320 may be arranged along the first direction D1. The second gate electrodes 320 may surround the first channel pattern CHP1 of the third active pattern AP3 and the second channel pattern CHP2 of the fourth active pattern AP4. For example, the first channel pattern CHP1 of the third active pattern AP3 may have a first sidewall SW1 to a fourth sidewall SW4. The first sidewall SW1 and the second sidewall SW2 may face each other in the first direction D1, and the third sidewall SW3 and the fourth sidewall SW4 may face each other in the second direction D2. The second gate electrodes 320 may be disposed on the first sidewall SW1 to the fourth sidewall SW4. In other words, the second gate electrodes 320 may surround the first sidewall SW1 to the fourth sidewall SW4.

[0196] The second gate insulating layer 330 can be inserted between the second gate electrode 320 and each of the first channel pattern CHP1 and the second channel pattern CHP2. The second gate insulating layer 330 can cover the bottom surface and the inner sidewall of the second gate electrode 320. For example, the second gate insulating layer 330 can directly cover the first sidewall SW1 to the fourth sidewall SW4 of the third active pattern AP3.

[0197] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may protrude vertically above the second gate electrode 320. The upper surface of the second gate electrode 320 may be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the third active pattern AP3 and the fourth active pattern AP4 may have a structure that protrudes vertically from the substrate 100 to pass through the second gate electrode 320.

[0198] A semiconductor device according to some embodiments may include a vertical transistor in which carriers move in a third direction D3. For example, when a voltage is applied to the second gate electrode 320 to turn the transistor "on", carriers can move from the lower epitaxial patterns SpO1 and SpO2 to the upper epitaxial patterns DOP1 and DOP2 via channel patterns CHP1 and CHP2. In a semiconductor device according to some embodiments, the second gate electrode 320 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to this disclosure may be a three-dimensional field-effect transistor (e.g., a vertical FET; VFET) with a surrounding gate structure. Because the gate surrounds the channel, the semiconductor device according to some embodiments may have excellent electrical characteristics.

[0199] Spacer 340 covering the second gate electrode 320, the third active pattern AP3, and the fourth active pattern AP4 may be disposed on the device isolation layer ST. Spacer 340 may include an insulating material layer, such as a silicon nitride layer and / or a silicon oxynitride layer. Spacer 340 may include a lower spacer 340LS, an upper spacer 340US, and a gate spacer 340GS between the lower spacer 340LS and the upper spacer 340US.

[0200] The lower spacer 340LS can directly cover the upper surface of the device isolation layer ST. The second gate electrode 320 can be spaced from the device isolation layer ST on the third direction D3 by the lower spacer 340LS. The gate spacer 340GS can cover the upper surface and outer sidewall of each of the second gate electrodes 320. The upper spacer 340 can cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 340US can expose the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 without covering them.

[0201] A first lower interlayer insulating layer 191BP may be disposed on the spacer 340. The upper surface of the first lower interlayer insulating layer 191BP may be substantially coplanar with the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. A first upper interlayer insulating layer 191UP, a lower etch stop layer 195, a second interlayer insulating layer 192, an upper etch stop layer 196, and a third interlayer insulating layer 193 may be sequentially deposited on the first lower interlayer insulating layer 191BP. The first lower interlayer insulating layer 191BP and the first upper interlayer insulating layer 191UP may be contained within the first interlayer insulating layer 191. The first upper interlayer insulating layer 191UP may cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0202] At least one first vertical source / drain contact 370 may be provided to connect to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 by passing through the first upper interlayer insulation layer 191UP. At least one second vertical source / drain contact 470 may be provided to connect to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 by sequentially passing through the first interlayer insulation layer 191, the lower spacer 340LS, and the element isolation layer ST. A vertical gate contact 380 may be provided to connect to the second gate electrode 320 by sequentially passing through the first upper interlayer insulation layer 191UP, the first lower interlayer insulation layer 191BP, and the gate spacer 340GS.

[0203] The lower etch stop layer 195, the second interlayer insulating layer 192, and the upper etch stop layer 196 can be disposed between the first upper interlayer insulating layer 191UP and / or the third interlayer insulating layer 193.

[0204] Source / drain via plug 180 and gate via plug 185 may be disposed in the lower etch-stop layer 195 and the second interlayer insulating layer 192. Wiring line 205 may be disposed in the third interlayer insulating layer 193 and the upper etch-stop layer 196. Although the first vertical source / drain contact 370, the second vertical source / drain contact 470, the source / drain via plug 180, the gate via plug 185, and the wiring line 205 are shown as a single layer, this is only for ease of description, and the exemplary embodiment is not limited thereto.

[0205] The descriptions of the first vertical source / drain contact 370, the second vertical source / drain contact 470, and the vertical gate contact 380 are substantially the same as those of the source / drain contact 170 and the gate contact 175 described with reference to Figures 1 to 30.

[0206] Figures 34 to 38 are views illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. For reference purposes, Figures 34 to 38 may be cross-sectional views taken along line AA of Figure 1. The method for manufacturing the semiconductor device will be described below with reference to these cross-sectional views.

[0207] Referring to Figure 34, a first source / drain pattern 150 may be formed on a first lower pattern BP1. A source / drain etch stop layer 156 and a first interlayer insulating layer 191 may be formed sequentially on the first source / drain pattern 150.

[0208] After the first interlayer insulating layer 191 is formed, a first pattern NS1 spaced apart from the first lower pattern BP1 can be formed. A sacrificial layer and an active layer are alternately deposited on the first lower pattern BP1, and then the sacrificial layer is removed, thereby forming the first pattern NS1.

[0209] A first gate insulating layer 130 and a first gate electrode 120 can be formed surrounding the first pattern NS1. A gate capping pattern 145 can be formed on the first gate electrode 120. Therefore, a gate structure GS intersecting the first active pattern AP1 is formed on the first active pattern AP1.

[0210] Subsequently, a sacrificial interlayer insulation layer 192P can be formed on the gate structure GS and the first interlayer insulation layer 191.

[0211] The upper surface 145_US of the gate cap pattern 145 before the formation of the sacrificial interlayer insulation layer 192P can be a flat plane. In addition, the upper surface 145_US of the gate cap pattern 145 can be coplanar with the upper surface of the first interlayer insulation layer 191.

[0212] Next, a source / drain contact hole 170H may be formed in the sacrificial interlayer insulating layer 192P and the first interlayer insulating layer 191. The source / drain contact hole 170H exposes the first source / drain pattern 150.

[0213] Referring to Figure 35, the barrier layer 171PP can be formed along the upper surface of the sacrificial interlayer insulation layer 192P and the sidewalls and bottom surface of the source / drain contact hole 170H.

[0214] A filler layer 172PP is formed on the barrier layer 171PP to fill the source / drain contact hole 170H. A portion of the filler layer 172PP may be disposed on the upper surface of the sacrificial interlayer insulating layer 192P.

[0215] For example, a first silicate layer 155 may be formed before the barrier layer 171PP is formed and / or the first silicate layer 155 may be formed via a silicate reaction between the first source / drain pattern 150 and the barrier layer 171PP.

[0216] Referring to Figure 36, the filler layer 172PP and barrier layer 171PP disposed on the upper surface of the sacrificial interlayer insulation layer 192P can be removed.

[0217] Therefore, a pre-source / drain contact 170P can be formed in the source / drain contact hole 170H. The pre-source / drain contact 170P may include a pre-source / drain barrier layer 171P and a pre-source / drain fill layer 172P.

[0218] Referring to Figure 37, the source / drain contact 170 can be formed, for example, via a first chemical mechanical polishing (CMP) process 50.

[0219] For example, a first CMP process 50 can be performed until the gate cap pattern 145 is exposed. The paste used in the first CMP process 50 may have the characteristic of uniformly polishing the pre-source / drain contacts 170P and the sacrificial interlayer insulation layer 192P.

[0220] For example, after performing the first CMP process 50, the upper surface 145_US of the gate cap pattern can be placed on the same plane as the source / drain contact 170. Compared to the upper surface 145_US of the gate cap pattern, the source / drain contact 170 does not protrude further in the third direction D3.

[0221] Referring to Figure 38, a portion of the source / drain contact 170 may protrude more on the third direction D3 compared to the upper surface 145_US of the gate cap pattern via the second CMP process 55.

[0222] After performing the second CMP process 55, the upper surface 170_US of the source / drain contact may include a protruding curved surface.

[0223] The slurry used in the second CMP process 55 can polish more of the gate cap pattern 145 and the first interlayer insulation layer 191 than the source / drain contact 170. Therefore, a portion of the source / drain contact 170 can protrude more than the upper surface 145_US of the gate cap pattern. In addition, the upper surface of a portion of the source / drain contact 170 adjacent to the gate cap pattern 145 can become a convex curved surface.

[0224] The shape of the upper surface 145_US of the gate cap pattern can be changed by adjusting the slurry used in the second CMP process 55.

[0225] Although not illustrated, for example, after forming the pre-gate contact, the gate contact (gate contact 175 in FIG. 3) can be formed while performing a first CMP process (first CMP process 50 in FIG. 37). Then, a portion of the gate contact 175 may protrude more than the upper surface 145_US of the gate cap pattern via the second CMP process 55.

[0226] In another example, after forming the source / drain contact 170, a pre-gate contact can be formed. Then, the gate contact 175 can be formed via a first CMP process 50.

[0227] In another example, the gate contact 175 may be formed prior to the formation of the pre-source / drain contact 170P. The gate contact 175 may be formed via a process similar to that described with reference to Figures 34 to 37.

[0228] In another example, after forming the source / drain contact 170 with a protruding upper surface, the gate contact 175 can be formed. For example, an additional first interlayer insulating layer (e.g., the first interlayer insulating layer 191 of FIG. 18) can be formed on the gate cap pattern 145 and the first interlayer insulating layer 191. The additional interlayer insulating layer can cover the protruding portion of the source / drain contact 170. Subsequently, a pre-gate contact can be formed via a process similar to that described with reference to FIGS. 34 to 36. Then, a first CMP process (first CMP process 50 of FIG. 37) can be performed until the source / drain contact 170 is exposed, thereby forming the gate contact 175. Thus, the semiconductor device described with reference to FIGS. 18 and 19 can be formed.

[0229] In summary, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the present invention. Therefore, the exemplary embodiments disclosed in this invention are used as examples and are for descriptive purposes only and are not intended to be limiting.

[0230] 50: First Chemical Mechanical Polishing Process 55: Second Chemical Mechanical Polishing Process 100: Base 105: Field insulation layer 120: First gate electrode 120_SW, 172_SW, 177_SW: Sidewall 130: First gate insulation layer 140: First gate spacer 141: External spacer 142: Internal spacers 145: Pattern of the first gate cover 145_US, 170_US, 171_US, 172_US, 175_US, 176_US, 177_US, AP1_US: Upper surface 150: First source / drain pattern 155: First silicate layer 156: Source / Drain Etching Termination Layer 170: Source / Drain Contact 170A: Part 1 170B: Part Two, Lower Source / Drain Contacts 170H: Source / Drain Contact Hole 170P: Pre-source / Drain contact 170U: Upper source / drain contact 170_USV: Concave and curved portion 170_USX: Protruding curved section 171: Source / drain barrier layer 171B: Lower source / drain barrier layer 171P: Pre-source / drain barrier layer 171PP: Barrier layer 172PP: Filler layer 171U: Upper source / drain barrier layer 172: Source / Drain Filler Layer 172B: Lower source / drain filler layer 172P: Pre-source / drain fill layer 172U: Upper source / drain filler layer 175: Gate contact 176: Gate contact barrier layer 177: Gate contact filler layer 180: Source / Drain Through-hole Plug 180a: First through-hole barrier layer 180b: First through-hole filling layer 185: Gate through-hole plug 185a: Second through-hole barrier layer 185b: Second through-hole filling layer 191: First interlayer insulation layer 191BP: First lower interlayer insulation layer 191UP: First upper interlayer insulation layer 192: Second interlayer insulation layer 192P: Sacrificial interlayer insulation 193: Third interlayer insulation layer 195: Lower Etching Termination Layer 196: Upper etch stop layer 205: Wiring Line 205a: Wiring barrier layer 205b: Wiring filler layer 250: Second source / drain pattern 255: Second silicate layer 320: Second gate electrode 330: Second gate insulation layer 340: Spacer 340GS: Gate spacer 340LS: Lower spacer 340US: Upper spacer 370: First vertical source / drain contact 380: Vertical gate contact 470: Second vertical source / drain contact AA, BB, CC, EE, FF, GG: Line AP1: First Active Pattern AP2: Second Active Pattern AP3: Third Active Pattern AP4: Fourth Active Pattern BP1: First lower part pattern BP2: Second lower part pattern CHP1: First Channel Pattern CHP2: Second Channel Pattern D1: First Direction D2: Second Direction D3: Third direction DOP1: First upper epitaxial pattern DOP2: Second upper epitaxial pattern DPF: Dummy Protrusion Pattern DT: Deep Ditch FT: Fin Ditch GCS: Gate Isolation Structure GS: Gate structure GS_INT: Gate-to-gate structure HD: First Height LC: Logic Unit NS1: First Pattern NS2: Second Pattern P, Q: Parts RX1: First Active Zone RX2: Second Active Zone RS1: First groove area RS2: Second recessed area SPO1: First lower epitaxial pattern SPO2: Second lower epitaxial pattern ST: Component isolation layer SW1: First sidewall SW2: Second sidewall SW3: Third sidewall SW4: Fourth sidewall TR: Ditch

Claims

1. A semiconductor device, comprising: A gate structure comprising a gate electrode and a gate cap pattern on the upper surface of the gate electrode; A source / drain pattern on at least one side of the gate structure; a source / drain contact on and connected to the upper surface of the source / drain pattern, the source / drain contact extending along the sidewall of the gate electrode; and a source / drain through-hole plug located on and connected to the source / drain contact, wherein the upper surface of the source / drain contact includes a protruding curved surface that fully contacts the source / drain through-hole plug.

2. The semiconductor device of claim 1, wherein a portion of the source / drain contact protrudes above the upper surface of the gate cap pattern.

3. The semiconductor device of claim 2, wherein the source / drain contact comprises a source / drain filling layer and a source / drain barrier layer extending along the sidewall of the source / drain filling layer, and the source / drain filling layer and the source / drain barrier layer protrude above the upper surface of the gate capping pattern.

4. The semiconductor device of claim 2, wherein the source / drain contact comprises a source / drain filling layer and a source / drain barrier layer extending along a sidewall of the source / drain filling layer, a portion of the source / drain filling layer protruding above the upper surface of the gate capping layer, and the source / drain barrier layer below the upper surface of the gate capping pattern.

5. The semiconductor device of claim 1, wherein the upper surface of the gate cap pattern includes a recessed curved surface.

6. The semiconductor device of claim 1, wherein the upper surface of the gate cap pattern is a flat plane.

7. The semiconductor device as claimed in claim 1, further comprising: A gate contact extends through the gate cap pattern and is connected to the gate electrode, wherein the upper surface of the gate contact includes a protruding curved surface.

8. The semiconductor device as claimed in claim 1, further comprising: A gate contact passes through the gate cover pattern and is connected to the gate electrode, wherein the upper surface of the gate contact is a flat plane.

9. The semiconductor device of claim 1, wherein the source / drain contact includes a source / drain filling layer, and the upper surface of the source / drain filling layer is contained in the upper surface of the source / drain contact including the protruding curved surface.

10. The semiconductor device of claim 9, wherein the source / drain contact further comprises a source / drain barrier layer extending along the sidewall of the source / drain fill layer.

11. The semiconductor device of claim 1, wherein the upper surface of the source / drain contact includes a first portion having the convex curved surface and a second portion having a concave curved surface.

12. A semiconductor device, comprising: A gate structure comprising a gate electrode and a gate cap pattern on the upper surface of the gate electrode; A source / drain pattern on at least one side of the gate structure; a source / drain contact on and connected to the upper surface of the source / drain pattern; and a source / drain through-hole plug located on and connected to the source / drain contact, wherein at least a portion of the source / drain contact protrudes above the upper surface of the gate cap pattern, the upper surface of the source / drain contact includes a protruding curved surface that fully contacts the source / drain through-hole plug, and the upper surface of the gate cap pattern includes a recessed curved surface.

13. The semiconductor device of claim 12, wherein the upper surface of the source / drain contact includes a protruding curved surface.

14. The semiconductor device of claim 12, wherein the upper surface of the source / drain contact includes a first portion having a protruding curved surface and a second portion having a recessed curved surface.

15. The semiconductor device of claim 12, wherein the source / drain contact comprises a source / drain filling layer and a source / drain barrier layer extending along a sidewall of the source / drain filling layer, at least a portion of the source / drain filling layer and the source / drain barrier layer protruding above the upper surface of the gate cap pattern, and at least a portion of the source / drain filling layer protruding above the upper surface of the source / drain barrier layer.

16. The semiconductor device as claimed in claim 12, further comprising: A gate contact extends through the gate cap pattern and is connected to the gate electrode, wherein the upper surface of the gate contact includes a protruding curved surface.

17. A semiconductor device, comprising: An active pattern, comprising a lower pattern and sheet patterns on the lower pattern; A gate structure, on the active pattern, includes a gate electrode and a gate cap pattern, the gate electrode surrounding the sheet pattern and the gate cap pattern on the upper surface of the gate electrode; a source / drain pattern on at least one side of the gate structure; a source / drain contact on and connected to the upper surface of the source / drain pattern; a gate contact passing through the gate cap pattern and connected to the gate electrode; and a source / drain via plug located on and connected to the source / drain contact, wherein a portion of the source / drain contact and a portion of the gate contact protrude above the upper surface of the gate cap pattern, and the upper surface of the source / drain contact includes a protruding curved surface that fully contacts the source / drain via plug.

18. The semiconductor device of claim 17, wherein the upper surface of the gate cap pattern includes a recessed curved surface.

19. The semiconductor device of claim 17, wherein the source / drain contact comprises a source / drain filling layer and a source / drain barrier layer extending along a sidewall of the source / drain filling layer, and a portion of the source / drain filling layer and a portion of the source / drain barrier layer protrude above the upper surface of the gate cap pattern.

20. The semiconductor device of claim 17, wherein the gate contact comprises a gate contact filler layer and a gate contact barrier layer extending along a sidewall of the gate contact filler layer, and the gate contact filler layer and the gate contact barrier layer protrude above the upper surface of the gate capping pattern.

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