Semiconductor device

Abstract

A semiconductor device includes a substrate; a gate electrode located on the substrate; a channel layer located between the substrate and the gate electrode, the channel layer comprising an amorphous oxide semiconductor, and the width of the gate electrode being greater than the width of the channel layer; a first conductive electrode connected to a first side surface of the channel layer; and a second conductive electrode connected to a second side surface of the channel layer.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This patent application claims priority to Korean Patent Application No. 10-2021-0121147, filed on September 10, 2021, with the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference.

[0003] This disclosure relates to a semiconductor device, and more specifically, to an oxide thin-film transistor. Prior Technology

[0004] Transistors are widely used as switching or driving devices in electronic devices. Specifically, thin-film transistors can also be formed on glass or plastic substrates, and therefore can be used in display devices (e.g., organic light-emitting display devices and / or liquid crystal display devices). The performance of thin-film transistors may be mainly affected by the physical properties of the channel layer (e.g., semiconductor layer).

[0005] There is a need to provide thin-film transistors with excellent performance to realize next-generation high-performance and highly integrated semiconductor circuits. Therefore, oxide thin-film transistors using oxide semiconductors with high carrier mobility as channel layer materials have been investigated. Summary of the Invention

[0006] In one embodiment, a semiconductor device may include: a substrate; a gate electrode disposed on the substrate; a channel layer disposed between the substrate and the gate electrode; a first conductive electrode disposed connected to a first side surface of the channel layer; and a second conductive electrode disposed connected to a second side surface of the channel layer. The channel layer may include an amorphous oxide semiconductor. The width of the gate electrode may be greater than the width of the channel layer.

[0007] In one embodiment, a semiconductor device may include: a substrate; a gate electrode disposed on the substrate; a channel layer disposed between the substrate and the gate electrode; a first conductive electrode disposed connected to a first side surface of the channel layer; and a second conductive electrode disposed connected to a second side surface of the channel layer. The channel layer may include an amorphous oxide semiconductor. The width of the channel layer may gradually decrease from the bottom surface of the channel layer towards the top surface of the channel layer.

[0008] In one embodiment, a semiconductor device may include: a substrate; a first conductive electrode disposed on the substrate, the first conductive electrode including a source region and a first via; a second conductive electrode disposed on the substrate, the second conductive electrode including a drain region and a second via; a channel layer disposed between the first conductive electrode and the second conductive electrode located on the substrate; a gate electrode disposed to cover three surfaces of the channel layer; a gate oxide layer disposed between the channel layer and the gate electrode and between the substrate and the gate electrode; and an insulating layer disposed on the substrate to cover the first conductive electrode, the second conductive electrode, the channel layer, and the gate electrode. The first via and the second via can penetrate the insulating layer. The width of the channel layer may be smaller than the width of the gate electrode. Simple Explanation of the Diagram

[0009] The features will become apparent to those skilled in the art by referring to the accompanying drawings, which illustrate exemplary embodiments in detail. Figure 1 is a plan view illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along line I-I' of Figure 1, showing a semiconductor device according to some embodiments. Figure 3 is a cross-sectional view taken along line II-II' of Figure 1, showing a semiconductor device according to some embodiments. Figures 4A, 4B, and 5 are enlarged views of area "A" in Figure 2. Figure 6 is a cross-sectional view taken along line I-I' of Figure 1, showing a semiconductor device according to some embodiments. Figure 7 is a cross-sectional view taken along line II-II' of Figure 1, showing a semiconductor device according to some embodiments. Figures 8 to 14 are cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments. Figures 15 to 17 are views illustrating application examples including semiconductor devices according to some embodiments. Implementation

[0010] Figure 1 is a plan view illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along line I-I' of Figure 1, Figure 3 is a cross-sectional view taken along line II-II' of Figure 1, and Figures 4A, 4B, and 5 are enlarged views of region "A" of Figure 2. Figure 6 is a cross-sectional view taken along line I-I' of Figure 1, illustrating a semiconductor device according to another embodiment, and Figure 7 is a cross-sectional view taken along line II-II' of Figure 1, illustrating a semiconductor device according to another embodiment. Hereinafter, a semiconductor device according to some embodiments will be described with reference to Figures 1 to 7.

[0011] Referring to Figures 1, 2, and 3, a semiconductor device 10 according to some embodiments may include a channel layer CHL, a gate oxide layer GI, a gate electrode GE, a source electrode SE, and a drain electrode DE disposed on a substrate 100. In some embodiments, the semiconductor device 10 may be a transistor comprising an oxide thin film (or oxide layer).

[0012] For example, substrate 100 may be a semiconductor substrate, a glass substrate, or a plastic substrate. The semiconductor substrate may contain, for example, silicon, germanium, and / or silicon-germanium. The semiconductor substrate may be, for example, a silicon wafer. Substrate 100 may be disposed on a plane defined by a first direction D1 and a second direction D2 intersecting the first direction D1.

[0013] The channel layer CHL may be disposed on the substrate 100. The channel layer CHL may contain a semiconductor material that can be formed on the substrate 100 by a deposition process. The channel layer CHL may contain a semiconductor material that can be used as a channel for a thin film transistor, although the channel layer CHL is formed in an amorphous state by a deposition process (e.g., the channel layer CHL may be an amorphous deposition product).

[0014] In some embodiments, the channel layer CHL may comprise an amorphous oxide semiconductor. Specifically, the channel layer CHL may comprise a compound of oxygen (O) and at least two metals (e.g., at least two of zinc (Zn), indium (In), gallium (Ga), and tin (Sn)). For example, the channel layer CHL may comprise indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0015] In some embodiments, the channel layer CHL may include a two-dimensional semiconductor. Specifically, the channel layer CHL may include a metal chalcogenide, a transition metal chalcogenide, graphene, or phosphorene. The metal chalcogenide or transition metal chalcogenide may be a metal compound represented by the chemical formula MX y (e.g., "y" is an integer 1, 2, or 3). In the chemical formula, "M" is a metal atom or a transition metal atom and may include, for example, W, Mo, Ti, Zn, Zs, or Zr, while "X" is a chalcogenide atom and may include, for example, S, Se, O, or Te. For example, the channel layer CHL may include, for example, graphene, phosphorene, MoS₂, MoSe₂, MoTe₂, WS₂, WSe₂, WTe₂, ReS₂, ReSe₂, TiS₂, TiSe₂, TiTe₂, ZnO, ZnS₂, ZsSe₂, WO₃, and MoO₃. The channel layer CHL can have a mono-layered structure or a multi-layered structure in which 2 to 100 layers are stacked. The multi-layered structure can be formed by adjacent monolayers coupled to each other by van der Waals force.

[0016] The source electrode SE and the drain electrode DE can be disposed on opposite sides (e.g., opposite sides) of the channel layer CHL in the second direction D2. The first side surface CHLa of the channel layer CHL can be directly connected to the source electrode SE. The second side surface CHLb of the channel layer CHL can be directly connected to the drain electrode DE.

[0017] The source electrode SE may include a lower source region NSP and a first via VI1. The lower source region NSP may be disposed directly on the substrate 100, for example, and may extend in the first direction D1 and the second direction D2. The side surface of the lower source region NSP may be directly connected to the first side surface CHLa of the channel layer CHL. For example, the first side surface CHLa of the channel layer CHL may extend along the entire length of the side surface of the lower source region NSP in the first direction D1. For example, the horizontal height of the top surface of the lower source region NSP relative to the bottom of the substrate 100 may be the same as or higher than the horizontal height of the top surface of the channel layer CHL. The first via VI1 may extend from the top surface of the lower source region NSP in the third direction D3. The first via VI1 may be spaced apart from the gate oxide layer GI, which will be described in detail later. The first insulating layer 110, which will be described in detail later, may be disposed between the first via VI1 and the gate oxide layer GI.

[0018] The drain electrode DE may include a lower drain region NDP and a second via VI2. The lower drain region NDP may be disposed directly on the substrate 100, for example, and may extend in the first direction D1 and the second direction D2. The side surface of the lower drain region NDP may be directly connected to the second side surface CHLb of the channel layer CHL. For example, the second side surface CHLb of the channel layer CHL may extend along the entire length of the side surface of the lower drain region NDP in the first direction D1. For example, the horizontal height of the top surface of the lower drain region NDP relative to the bottom of the substrate 100 may be the same as or higher than the horizontal height of the top surface of the channel layer CHL. The second via VI2 may extend from the top surface of the lower drain region NDP in the third direction D3. The second via VI2 may be spaced apart from the gate oxide layer GI, which will be described in detail later. The first insulating layer 110, which will be described in detail later, may be disposed between the second via VI2 and the gate oxide layer GI.

[0019] The source electrode SE and the drain electrode DE may contain conductive materials. For example, each of the source electrode SE and the drain electrode DE may contain at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0020] Referring to Figures 2, 4A, and 4B, in some embodiments, the channel layer CHL may have a rectangular cross-section. The width CW of the channel layer CHL may be defined within the cross-section of the channel layer CHL. The width CW of the channel layer CHL may be defined as the length along the second direction D2 from the first side surface CHLa of the channel layer CHL to the opposite side surface (i.e., the second side surface CHLb) of the channel layer CHL.

[0021] For example, in the second direction D2, the width CW of the channel layer CHL can be equal to or less than the width GW of the gate electrode GE. For instance, as shown in FIG4A, the first side surface CHLa of the channel layer CHL can be perpendicularly aligned (e.g., flush) with the first side surface of the gate electrode GE. The second side surface CHLb of the channel layer CHL can be disposed within the opposite side surface of the gate electrode GE; for example, the second side surface CHLb of the channel layer CHL can be located between the opposite side surfaces of the gate electrode GE in the second direction D2. In other words, referring to FIG4A, the width of the gate electrode GE along the second direction D2 can be greater than the width of the channel layer CHL, such that the second side surface CHLb of the channel layer CHL can overlap perpendicularly with the gate electrode GE (rather than its second side surface); for example, the second side surface CHLb of the channel layer CHL can be spaced apart from the second side surface of the gate electrode GE towards the first side surface of the gate electrode GE. At least one of the two side surfaces CHLa and CHLb of the channel layer CHL may overlap perpendicularly with the gate electrode GE. For example, at least one of the side surfaces CHLa and CHLb of the channel layer CHL may overlap perpendicularly with a portion of the gate electrode GE located between opposite side surfaces of the gate electrode GE. In other words, the channel layer CHL may overlap perpendicularly with at least a portion of the gate electrode GE. For example, the gate electrode GE may overlap with the entire width of the channel layer CHL and extend beyond the channel layer CHL in the second direction D2. In another example, as shown in FIG4B, the channel layer CHL may be centered relative to the gate electrode GE.

[0022] Referring to Figures 2 and 5, in some embodiments, the width CW of the channel layer CHL may gradually decrease with increasing horizontal height from the top surface of the substrate 100 in the third direction D3. The width CW of the channel layer CHL may have a minimum width at the portion where it intersects with the gate oxide layer GI, and a maximum width at the portion where it intersects with the top surface of the substrate 100. The minimum and maximum widths may be less than the width GW of the gate electrode GE. In other words, the channel layer CHL may overlap perpendicularly with at least a portion of the gate electrode GE.

[0023] In the embodiment illustrated with reference to Figures 4A, 4B, and 5, when a voltage is applied to the gate electrode GE, a channel can be formed in the upper portion of the channel layer CHL adjacent to the gate oxide layer GI, and current can flow through the channel. Compared to the case where the width of the channel layer is greater than the width of the gate electrode, the length of the channel formed in the upper portion of the channel layer CHL in this embodiment can be shortened. Therefore, when current flows between the source electrode SE and the drain electrode DE, the resistance in the channel layer CHL can be reduced, the leakage current can be reduced, and the drive current can be increased.

[0024] Referring again to Figures 1, 2, and 3, in some embodiments, the gate oxide layer GI and the gate electrode GE may be sequentially disposed on the channel layer CHL. The gate oxide layer GI may be configured to cover the top and side surfaces of the channel layer CHL along a first direction D1 (Figure 3). A portion of the bottom surface of the gate oxide layer GI may be directly disposed on the substrate 100, while another portion of the bottom surface of the gate oxide layer GI may be disposed on the channel layer CHL. In other words, the gate oxide layer GI may be configured to cover the three surfaces of the channel layer CHL along the first direction D1. The gate oxide layer GI may include, for example, a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer.

[0025] The gate oxide layer GI can be configured to surround the bottom and side surfaces of the gate electrode GE. In other words, the gate electrode GE can be disposed in the inner region surrounded by the gate oxide layer GI. The gate oxide layer GI can be disposed between the gate electrode GE and the channel layer CHL, and between the gate electrode GE and the substrate 100. The structure of the gate oxide layer GI and the gate electrode GE can be a tri-gate structure (e.g., a three-dimensional structure that directly contacts and surrounds three different surfaces of the raised element (e.g., the channel layer CHL)). When a voltage is applied to the gate electrode GE, a channel can be formed in the channel layer CHL adjacent to the gate oxide layer GI.

[0026] The gate electrode GE may comprise at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0027] Referring to Figures 1, 6, and 7, in some embodiments, the gate oxide layer GI may be configured to surround the top, bottom, and side surfaces of the channel layer CHL along a first direction D1. The channel layer CHL may be spaced apart from the substrate 100. The gate oxide layer GI and the gate electrode GE may be disposed between the channel layer CHL and the substrate 100. In other words, the structure of the gate oxide layer GI and the gate electrode GE may be a gate-all-around (GAA) structure. When a voltage is applied to the gate electrode GE, a channel can be formed in the channel layer CHL surrounded by the gate oxide layer GI and the gate electrode GE.

[0028] A first insulating layer 110 may be disposed on the lower source region NSP of the source electrode SE and the lower drain region NDP of the drain electrode DE. For example, the first insulating layer 110 may include a first sub-insulating layer IN1, a second sub-insulating layer IN2, and a third sub-insulating layer IN3. Each of the first to third sub-insulating layers IN1, IN2, and IN3 may have etch selectivity relative to the other adjacent sub-insulating layer. For example, each of the first to third sub-insulating layers IN1, IN2, and IN3 may be a silicon oxide layer or a silicon nitride layer.

[0029] The first via VI1, the second via VI2, the gate oxide layer GI, and the gate electrode GE can penetrate the first insulating layer 110. In the first insulating layer 110, the first via VI1 can be spaced apart from the gate oxide layer GI, and the second via VI2 can also be spaced apart from the gate oxide layer GI. In other words, the first insulating layer 110 can be disposed between the gate oxide layer GI and each of the vias VI1 and VI2.

[0030] The top surface of the first insulating layer 110 may be located at substantially the same horizontal height as the top surface of the gate oxide layer GI and the top surface of the gate electrode GE. In other words, the gate oxide layer GI and the gate electrode GE may be exposed on the top surface of the first insulating layer 110. For example, the top surfaces of the gate oxide layer GI and the gate electrode GE may be coplanar with the top surface of the first insulating layer 110.

[0031] A second insulating layer 120 may be disposed on the first insulating layer 110. The second insulating layer 120 may be disposed on the gate oxide layer GI and the gate electrode GE. The first via VI1 of the source electrode SE and the second via VI2 of the drain electrode DE may penetrate the second insulating layer 120. The top surface of the second insulating layer 120 may be located at substantially the same horizontal height as the top surface of the first via VI1 and the top surface of the second via VI2. The first via VI1 and the second via VI2 may be exposed on the top surface of the second insulating layer 120; for example, the top surfaces of the first via VI1 and the second via VI2 may be coplanar with the top surface of the second insulating layer 120.

[0032] A third insulating layer 130 may be disposed on the second insulating layer 120. The third insulating layer 130 may include interconnects EL. Each of the interconnects EL may be connected to the top surface of the first via VI1 or the top surface of the second via VI2. Different voltages may be applied to the interconnects EL respectively. In other words, the voltage applied to the first via VI1 of the source electrode SE may be different from the voltage applied to the second via VI2 of the drain electrode DE. Contacts connected to the gate electrode GE may be further disposed in the second insulating layer 120 to apply voltage to the gate electrode GE.

[0033] Figures 8 to 14 are cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments. Hereinafter, a method for manufacturing a semiconductor device 10 according to some embodiments will be described with reference to Figures 8 to 14.

[0034] Referring to FIG8, the channel layer CHL, the etch stop layer SL, and the first insulating layer 110 may be sequentially formed on the substrate 100 in the third direction D3. The channel layer CHL may be formed using a deposition process. The deposition process may include a low-temperature evaporation process. The deposition process may be performed in an environment of 50 degrees Celsius to 400 degrees Celsius. For example, the deposition process may include a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. Therefore, the semiconductor device according to the embodiment may be formed in the front-end-of-line (FEOL) layer, the back-end-of-line (BEOL) layer, and / or the peripheral structure of the peri-on-cell (POC) structure on the substrate 100 (see FIG16 and FIG17), as described below.

[0035] The etch stop layer SL and the first insulating layer 110 formed on the channel layer CHL may have etch selectivity relative to each other. For example, each of the etch stop layer SL and the first to third sub-insulating layers IN1, IN2 and IN3 may be a silicon oxide layer or a silicon nitride layer. The first insulating layer 110 may include the first to third sub-insulating layers IN1, IN2 and IN3, and in this case, the first to third sub-insulating layers IN1, IN2 and IN3 may have etch selectivity relative to each other.

[0036] Referring to Figure 9, a gate via GH can be formed to penetrate the first insulating layer 110 and the etch stop layer SL. The gate via GH can expose a portion of the top surface of the channel layer CHL. A gate oxide layer GI and a gate electrode GE can be sequentially formed in the gate via GH. The gate oxide layer GI can be formed conformally on the gate via GH, for example, to have an internal space, while covering the inner and bottom surfaces of the gate via GH. For example, the gate oxide layer GI can have a cylindrical shape. The gate electrode GE can be formed in the internal space (e.g., to completely fill the remaining portion of the gate via GH located above the gate oxide layer GI). The formation of the gate electrode GE may include an electroless plating process and / or an electroplating process.

[0037] Referring to FIG10, a second insulating layer 120 may be formed on the first insulating layer 110, the gate oxide layer GI, and the gate electrode GE. The formation of the second insulating layer 120 may include a deposition process. The second insulating layer 120 may be disposed on the gate electrode GE to cover the gate electrode GE.

[0038] Referring to FIG11, electrode holes EH can be formed in the first insulating layer 110 and the second insulating layer 120. The electrode holes EH can be formed at the locations where the source electrode SE and the drain electrode DE will be disposed (see FIGS. 2 and 6). In other words, each of the electrode holes EH can be formed to be spaced apart from the gate oxide layer GI.

[0039] Each of the electrode holes EHs can penetrate both the first insulating layer 110 and the second insulating layer 120 from the top surface of the second insulating layer 120 to the top surface of the etch stop layer SL. In other words, the electrode hole EH can expose the etch stop layer SL.

[0040] Referring to Figures 12 and 13, the etch stop layer SL exposed through the electrode aperture EH and the channel layer CHL located beneath the etch stop layer SL can be gradually removed from their surfaces to form a groove RS. The groove RS can be formed using an isotropic etching process. For example, the formation of the groove RS may include a wet etching process. As the etching process proceeds, the etch stop layer SL and the channel layer CHL can be gradually removed from the portion near the electrode aperture EH toward the portion away from the electrode aperture EH. The etching process can be carried out until the two side surfaces of the channel layer CHL are laterally recessed from the two side surfaces of the gate electrode GE (e.g., until the two side surfaces of the channel layer CHL are below the gate electrode GE). In other words, the etching process can be carried out until the maximum width CW of the channel layer CHL in the second direction D2 is less than the width GW of the gate electrode GE.

[0041] Referring to Figure 14, conductive material can be formed in the electrode hole EH (e.g., completely filling the electrode hole EH) to form the source electrode SE and the drain electrode DE. Therefore, the source electrode SE can be directly connected to the side surface of the channel layer CHL, while the drain electrode DE can be directly connected to the opposite side surface of the channel layer CHL.

[0042] Figures 15 to 17 are views illustrating application examples including semiconductor devices according to some embodiments. These application examples will be described below with reference to Figures 15 to 17.

[0043] Figure 15 is a view illustrating a semiconductor memory cell 11, in which a semiconductor device 10 according to an embodiment is provided. For example, the semiconductor device 10 may be a transistor. For example, the semiconductor memory cell 11 may be a semiconductor dynamic random-access memory (DRAM) cell.

[0044] Referring to FIG15, the semiconductor memory cell 11 may include a substrate 100 and a capacitor CAP located on the substrate 100. A semiconductor device 10 according to an embodiment may be disposed on the substrate 100.

[0045] For example, a pair of adjacent semiconductor devices 10 located on substrate 100 may share a source electrode SE. In other words, the source electrode SE may be disposed between the pair of adjacent semiconductor devices 10.

[0046] According to an embodiment, a first insulating layer 110 may be disposed on a substrate 100 to cover the semiconductor device 10. The first insulating layer 110 may include, for example, a silicon oxide layer or a silicon oxynitride layer.

[0047] Bit lines BL may be provided in the first insulating layer 110. Each of the bit lines BL may be provided on a source electrode SE shared by the pair of adjacent semiconductor devices 10. For example, the bit line BL may comprise at least one of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound.

[0048] Overlap pads LP may be provided in the first insulating layer 110. Each of the overlap pads LP may be provided on the drain electrode DE of the semiconductor device 10. Each of the overlap pads LP may contain a conductive material (e.g., doped silicon and / or metal).

[0049] A capacitor CAP may be disposed on a first insulating layer 110. The capacitor CAP may include a first electrode LEL1, a second electrode LEL2, and a dielectric layer DIL disposed between the first electrode LEL1 and the second electrode LEL2. Each of the first electrodes LEL1 may be disposed on each of the overlapping pads LP. Each of the first electrodes LEL1 may be electrically connected to a drain electrode DE via the overlapping pads LP. The first electrodes LEL1 may be arranged in a line in the second direction D2.

[0050] Each of the first electrodes LEL1 may have a cylindrical shape (or cup shape) having a bottom portion and sidewall portions extending vertically from the bottom portion. The bottom portion and sidewall portions of each of the first electrodes LEL1 may have substantially the same thickness. The planar diameters of the first electrodes LEL1 may be substantially equal to each other.

[0051] The first electrode LEL1 may comprise at least one of a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. For example, each of the first electrodes LEL1 may comprise a metal nitride layer (e.g., a titanium nitride (TiN) layer, a titanium silicon nitride (TiSiN) layer, a titanium aluminum nitride (TiAlN) layer, a tantalum nitride (TaN) layer, a tantalum silicon nitride (TaSiN) layer, a tantalum aluminum nitride (TaAlN) layer, or a tungsten nitride (WN) layer).

[0052] The dielectric layer DIL can be disposed on the surface of the first electrode LEL1 with substantially uniform thickness. For example, the dielectric layer DIL may comprise a high-k dielectric material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and / or TiO2).

[0053] The second electrode LEL2 may be disposed on the dielectric layer DIL. The second electrode LEL2 may cover a plurality of first electrodes LEL1, with the dielectric layer DIL sandwiched between the first electrodes LEL1 and the second electrode LEL2. A portion of the second electrode LEL2 may fill the interior of the first electrodes LEL1, which have a cylindrical (or cup-shaped) shape. The second electrode LEL2 may comprise at least one of, for example, a doped semiconductor material, a conductive metal nitride, a metal, or a metal-semiconductor compound. For example, the second electrode LEL2 may have a structure in which a metal nitride layer and a semiconductor layer are sequentially stacked.

[0054] The semiconductor device 10, the first insulating layer 110, the bonding pad LP and the capacitor CAP located on the substrate 100 can be formed by a front-end process (FEOL).

[0055] The second to fifth insulating layers 120, 130, 140, and 150 may be stacked sequentially on the capacitor CAP. At least one contact CT may penetrate the second insulating layer 120 to be electrically connected to the second electrode LEL2. According to the embodiment, a semiconductor device 10, an interconnect IL, and a via VI may be disposed in the third to fifth insulating layers 130, 140, and 150. An additional semiconductor device 10 may be disposed on one of the second to fifth insulating layers 120, 130, 140, and 150 to be electrically connected to the interconnect IL. The via VI may be vertically connected to the interconnect IL. For example, the interconnect IL of the semiconductor memory cell 11 may be electrically connected to the capacitor CAP via the contact CT.

[0056] Interconnects IL, additional semiconductor devices 10, and vias VI disposed in the second to fifth insulating layers 120, 130, 140, and 150 can be formed by a back-end process (BEOL).

[0057] Figure 16 is a view illustrating an image sensor using a semiconductor device according to an embodiment. For example, the semiconductor device 10 may be a transistor.

[0058] Referring to FIG16, the image sensor chip 12 may include a first sub-chip CH1, a second sub-chip CH2, and an insertion layer 300. The first sub-chip CH1 may include a substrate 100, a circuit layer LL having a semiconductor device 10, and a first to a fifth insulating layer 110, 120, 130, 140, and 150 located on the substrate 100.

[0059] Specifically, the circuit layer LL may include semiconductor devices 10 according to an embodiment. The semiconductor devices 10 may be spaced apart from each other and arranged two-dimensionally on the substrate 100. The semiconductor devices 10 may function as logic transistors and process signals transmitted from the second sub-wafer CH2. First to fifth insulating layers 110, 120, 130, 140, and 150 may be sequentially stacked on the circuit layer LL.

[0060] Lower interconnects EP may be provided in the first insulating layer 110. One of the lower interconnects EP may be disposed together on the source and drain electrodes of a pair of adjacent semiconductor devices 10. The drain and source electrodes of the pair of adjacent semiconductor devices 10 may be electrically connected to each other via the lower interconnects EP. Drain electrodes DE not connected to the lower interconnects EP may penetrate the first insulating layer 110. Each of the lower interconnects EP may contain a conductive material, such as doped silicon and / or metal.

[0061] At least one contact CT can penetrate the second insulating layer 120 to be electrically connected to the drain electrode DE. Interconnects IL and vias VI can be disposed in the third to fifth insulating layers 130, 140, and 150. The vias VI can be vertically connected to the interconnect IL. For example, the interconnect IL of the first sub-wafer CH1 can be electrically connected to the semiconductor device 10 in the circuit layer LL via the contact CT.

[0062] The second sub-wafer CH2 may include a photoelectric conversion device PCD, a floating diffusion region FDA, and a readout circuit device RCX formed in or on an additional substrate 200. The additional substrate 200 may be a semiconductor substrate doped with a dopant to have p-type conductivity.

[0063] The readout circuitry RCX may be disposed on a first surface 200a of an additional substrate 200. The readout circuitry RCX may include a plurality of transistors for transmitting and amplifying electrical signals (e.g., photocharge) corresponding to incident light.

[0064] The color filter CF and microlens ML used to provide incident light to the photoelectric conversion device PCD can be disposed on the second surface 200b of the additional substrate 200. The second surface 200b can be opposite to the first surface 200a.

[0065] Each of the photoelectric conversion devices (PCDs) may include a photodiode. The PCDs may be disposed in an additional substrate 200. The PCDs may generate photocharges corresponding to incident light. For example, electron-hole pairs corresponding to incident light may be generated in each of the PCDs. The PCDs may be doped with dopants to have a conductivity type different from that of the additional substrate 200 (e.g., n-type).

[0066] Each of the color filters (CFs) can be placed on each of the photoelectric conversion devices (PCDs). The color filters (CFs) can be arranged in a matrix to form a color filter array.

[0067] In some embodiments, the color filter array may include a Bayer pattern comprising a red color filter, a green color filter, and a blue color filter. Each of the color filters CF may be one of a red color filter, a green color filter, and a blue color filter.

[0068] In some embodiments, the color filter array may include a Bayer pattern comprising a yellow filter, a magenta filter, and a cyan filter. Each of the color filters CF may be one of a yellow filter, a magenta filter, and a cyan filter.

[0069] Each of the microlenses ML can be positioned on top of each of the color filters CF. Each of the microlenses ML can adjust the path of light incident upon it so that the incident light is concentrated on the photoelectric conversion device PCD located below it. The microlenses ML can be arranged in a matrix to form a microlens array.

[0070] An antireflective layer 205 may be disposed between the second surface 200b of the additional substrate 200 and the color filter CF. The antireflective layer 205 prevents incident light from being reflected at the second surface 200b of the additional substrate 200. For example, the antireflective layer 205 may have a multilayer structure in which material layers with different refractive indices are alternately stacked. As the number of material layers with different refractive indices increases, the transmittance of the antireflective layer 205 can be improved.

[0071] A first to a fourth upper insulating layer 210, 220, 230, and 240 can be stacked on a first surface 200a of an additional substrate 200. Interconnects IL and vias VI can be disposed in the first to fourth upper insulating layers 210, 220, 230, and 240. The vias VI can be vertically connected to the interconnects IL. For example, the interconnects IL of the second sub-wafer CH2 can be electrically connected to the readout circuitry RCX.

[0072] The photoelectric conversion device PCD of the second sub-chip CH2 can generate photocharge in response to light incident through the second surface 200b of the additional substrate 200. In other words, the image sensor chip 12 according to this embodiment can be a backside illuminated image sensor (BIS).

[0073] The insertion layer 300 located between the first sub-wafer CH1 and the second sub-wafer CH2 may include a connection portion 310. The connection portion 310 can electrically connect the internal interconnect IL of the first sub-wafer CH1 to the internal interconnect IL of the second sub-wafer CH2. The connection portion 310 may contain a metal, such as copper and / or tungsten.

[0074] More specifically, the connection portion 310 may include a first conductive pattern 310a and a second conductive pattern 310b. The first conductive pattern 310a is electrically connected to at least one of the interconnect lines IL of the first sub-chip CH1, and the second conductive pattern 310b is electrically connected to at least one of the interconnect lines IL of the second sub-chip CH2. The first conductive pattern 310a and the second conductive pattern 310b may be in direct contact with each other and may be electrically connected to each other.

[0075] The insertion layer 300 may further include a first insulating layer 350a and a second insulating layer 350b. A first conductive pattern 310a and a second conductive pattern 310b may be respectively disposed in the first insulating layer 350a and the second insulating layer 350b. For example, each of the first insulating layer 350a and the second insulating layer 350b may include a silicon oxide layer.

[0076] The insertion layer 300 may further include a first metal diffusion barrier layer 360a, a second metal diffusion barrier layer 360b, and a third metal diffusion barrier layer 360c. The first metal diffusion barrier layer 360a may be disposed between the first sub-wafer CH1 and the first insulating layer 350a, the second metal diffusion barrier layer 360b may be disposed between the first insulating layer 350a and the second insulating layer 350b, and the third metal diffusion barrier layer 360c may be disposed between the second insulating layer 350b and the second sub-wafer CH2. The first to third metal diffusion barrier layers 360a, 360b, and 360c may contain SiN, SiCN, SiOCN, SiON, or SiC. The first to third metal diffusion barrier layers 360a, 360b, and 360c can suppress or prevent the diffusion of the metal self-connection portion 310.

[0077] Figure 17 is a view showing a semiconductor product with a periphery-on-cell (POC) structure.

[0078] Referring to Figure 17, the semiconductor product 13 may include a peripheral circuit structure PS and a cell structure CS, and the peripheral circuit structure PS may be stacked on the cell structure CS. In other words, when viewed in a plan view, the cell structure CS may overlap with the peripheral circuit structure PS.

[0079] The cell structure CS may include a cell array containing multiple memory cells. For example, a memory cell may include the semiconductor memory cell 11 (i.e., a DRAM cell) of FIG15. In another example, a memory cell may include a NAND cell or a static random-access memory (SRAM) cell.

[0080] The peripheral circuitry PS may include column and row decoders configured as an array of control units, page buffers, and control circuitry. The circuitry of the peripheral circuitry PS may include a semiconductor device 10 according to an embodiment.

[0081] In summary, the embodiments provide a semiconductor device including a channel layer, which has high mobility and can be deposited. That is, in the semiconductor device according to the embodiments, the width of the channel layer can be smaller than the width of the gate electrode (e.g., by forming the source and drain electrodes in a region formed by removing some portions of the channel layer), and thus the resistance in the channel layer can be reduced to increase the drive current. Furthermore, the channel layer and gate oxide layer of the semiconductor device according to the embodiments can be formed using etching and deposition processes, and therefore the semiconductor device can be manufactured using a low-temperature process.

[0082] This document discloses exemplary embodiments, and although specific terminology is used, such terminology is for general and illustrative purposes only and not for limiting purposes. In some instances, it will be apparent to those skilled in the art at the time of filing of this application that, unless otherwise specified, the features, characteristics, and / or elements set forth in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements set forth in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

[0083] 10: Semiconductor devices 11: Semiconductor memory cell 12: Image sensor chip 13: Semiconductor products 100, 200: substrate 110: First insulating layer 120: Second insulation layer 130: Third insulation layer 140: Fourth Insulation Layer 150: Fifth Insulation Layer 200a: First surface 200b: Second surface 205: Anti-reflective layer 210: First upper insulating layer 220: Second upper insulation layer 230: Third upper insulation layer 240: Fourth upper insulation layer 300: Insertion layer 310: Connection part 310a: First conductive pattern 310b: Second conductive pattern 350a: First insulating layer 350b: Second insulating layer 360a: First metal diffusion barrier layer 360b: Second metal diffusion barrier layer 360c: Third metal diffusion barrier layer A: District BL: Bitline CAP: Capacitor CF: Color Filter CH1: First Sub-Chip CH2: Second Sub-Chip CHL: Channel Layer CHLa: First side surface / side surface CHLb: Second side surface / side surface CS: Unit structure CT: Contact CW, GW: Width D1: First Direction D2: Second Direction D3: Third direction DE: Electrode DIL: Dielectric layer EH: Electrode Hole EL, IL: Intrawiss EP: Lower Inner Connection FDA: Floating diffusion zone GE: Gate electrode GH: Gate hole GI: Gate oxide layer I-I', II-II': line IN1: First sub-insulating layer IN2: Second sub-insulating layer IN3: Third sub-insulating layer LEL1: First electrode LEL2: Second electrode LL: Circuit layer LP: Overlap joint pad ML: Microlens NDP: Lower Drain Region NSP: Lower source region PCD: Photoelectric conversion device PS: Peripheral circuit structure RCX: Readout circuitry RS: Groove SE: Source electrode SL: Etching stop layer VI: Through hole VI1: First via / via VI2: Second via / through hole

Claims

1. A semiconductor device, comprising: substrate; The gate electrode is located on the substrate; A channel layer, located between the substrate and the gate electrode, the channel layer comprising an amorphous oxide semiconductor, and the width of the gate electrode being greater than the width of the channel layer; a first conductive electrode, located on the substrate, comprising a source region and a first via, wherein the source region is connected to a first side surface of the channel layer, and the first via extends from the source region; and a second conductive electrode, located on the substrate, comprising a drain region and a second via, wherein the drain region is connected to a second side surface of the channel layer, and the second via extends from the drain region, wherein the source region and the first via are integral and there is no gap between them, the drain region and the second via are integral and there is no gap between them, the width of the source region is greater than the width of the first via, and the width of the drain region is greater than the width of the second via.

2. The semiconductor device of claim 1, wherein the channel layer has a rectangular cross-section.

3. The semiconductor device as claimed in claim 1, wherein: The first side surface of the channel layer is perpendicularly aligned with the first side surface of the gate electrode, and the second side surface of the channel layer is spaced apart from the first side surface of the gate electrode, with the second side surface of the gate electrode opposite to the first side surface of the gate electrode.

4. The semiconductor device of claim 1, wherein at least one of the first side surface of the channel layer and the second side surface of the channel layer overlaps perpendicularly with the gate electrode.

5. The semiconductor device of claim 4, wherein the gate electrode extends beyond the channel layer in a direction parallel to the top surface of the substrate.

6. The semiconductor device of claim 1, wherein the channel layer is a deposited product formed by a deposition process performed at a temperature of 50 degrees Celsius to 400 degrees Celsius.

7. The semiconductor device of claim 1, wherein the channel layer comprises at least one of indium gallium zinc oxide and indium tin zinc oxide.

8. The semiconductor device of claim 1, wherein each of the first conductive electrode and the second conductive electrode comprises at least one of titanium, tantalum, tungsten, copper and aluminum.

9. The semiconductor device of claim 1, wherein the substrate is a semiconductor substrate, a glass substrate, or a plastic substrate.

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