Semiconductor high-voltage termination with deep trench and floating field rings

Abstract

A semiconductor device includes a substrate, a semiconductor layer formed on the substrate, and a high-voltage termination. The high-voltage termination includes a plurality of floating field rings, a deep trench, and a dielectric material disposed within the deep trench. The plurality of floating field rings are formed in the semiconductor layer and are respectively disposed around a region of the semiconductor layer. The deep trench is formed in the semiconductor layer and is concentrically disposed around the outermost floating field ring of the plurality of floating field rings. The high-voltage termination may further include a field plate disposed above the floating field rings, the deep trench, or both.

Description

Technical Field

[0001] This invention relates to a semiconductor high-voltage terminal, and more particularly to a semiconductor high-voltage terminal having a deep trench and a floating field ring. Prior Technology

[0002] High-voltage semiconductor devices may require specialized structures, such as the well-known high-voltage terminals, to prevent electrical breakdown around the active regions of the semiconductor device.

[0003] In devices with a rated blocking voltage higher than 1700V, high-voltage terminations can occupy a significant portion of the die area. In such devices, more than half of the device area is consumed by high-voltage terminations, thus increasing the die size and cost.

[0004] To save costs, it is advantageous to have denser high-voltage terminals (i.e., occupying a smaller grain area) but still provide high blocking voltage. Summary of the Invention

[0005] The embodiments relate to semiconductor devices and their manufacturing processes, and particularly to semiconductor devices including high-voltage terminals around the active region of the device.

[0006] In an embodiment, the semiconductor element includes a substrate, a semiconductor layer formed on the substrate, and a high-voltage termination. The high-voltage termination includes a plurality of floating field rings formed on the semiconductor layer and individually disposed in a region surrounding the semiconductor layer, a deep trench formed on the semiconductor layer, the deep trench being disposed concentrically around the outermost floating field ring of the plurality of floating field rings, and a dielectric material disposed within the deep trench.

[0007] The high-voltage termination may further include a field plate. The field plate may be disposed on one or more floating field rings, or on a portion of a deep trench, or on both.

[0008] In one embodiment, a method of manufacturing a semiconductor element includes: forming an epitaxial layer on a semiconductor substrate; forming a plurality of floating field rings concentrically disposed on the epitaxial layer; forming a deep trench in the epitaxial layer, the deep trench surrounding the outermost floating field ring of the plurality of floating field rings; and forming a dielectric material within the deep trench.

[0009] In an embodiment, the method of manufacturing a semiconductor element further includes forming a field plate on a dielectric layer and on at least one of a plurality of floating field rings, on at least a portion of a deep trench, or on both. Simple Explanation of the Diagram

[0010] Figure 1A shows a cross-sectional view of a semiconductor device according to an embodiment.

[0011] Figure 1B shows a plan view of a semiconductor device according to one embodiment.

[0012] Figures 2A to 2E show individual cross-sectional views of semiconductor elements according to other embodiments.

[0013] Figure 3 shows a cross-sectional view of a semiconductor device according to another embodiment.

[0014] Figures 4A to 4D illustrate the steps of a semiconductor device manufacturing process according to one embodiment.

[0015] Figure 5 illustrates a step that occurs after the steps in Figures 4A to 4D in a semiconductor device manufacturing process according to an embodiment.

[0016] Figures 6A to 6D illustrate steps in a semiconductor device manufacturing process according to one embodiment.

[0017] Figure 7 illustrates a step that occurs after the steps in Figures 6A to 6D in a semiconductor device manufacturing process according to an embodiment.

[0018] Figures 8A to 8D illustrate additional steps performed after the steps in Figures 4A to 4D in a semiconductor device manufacturing process according to one embodiment.

[0019] Figure 9 shows the electrical characteristics of a semiconductor element according to an embodiment.

[0020] Figure 10 is a diagram of the reverse breakdown voltage of a semiconductor element according to an embodiment.

[0021] Figure 11 shows the electric field distribution of a semiconductor device undergoing an avalanche breakdown according to one embodiment.

[0022] Figure 12 shows the electric field distribution of a semiconductor element in the event of a sudden collapse according to another embodiment. Implementation

[0023] Embodiments of the present invention relate to semiconductor devices having high-voltage terminations. In an embodiment, the high-voltage termination includes one or more floating field rings and a deep trench disposed around the active region of the semiconductor device.

[0024] The deep trench described herein refers to a trench with a bottom deeper than the metallurgical junction of the relevant doped region in the semiconductor, and can penetrate most or all of the layer in the semiconductor device in which active elements are fabricated, such as an epitaxial layer, which can be used to fabricate diodes, field-effect transistors (FETs), insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), thyristors, or similar devices. In embodiments, the relevant doped region can be a floating field ring, and particularly a floating field ring adjacent to the deep trench.

[0025] Deep trenches are typically lined with a first dielectric material, such as an oxide. Deep trenches can be filled with a second dielectric material, which can be the same dielectric material used to line the deep trench, but embodiments of the invention are not limited thereto.

[0026] The following is a detailed description of embodiments, together with the accompanying drawings. The scope of this invention includes various alternatives, modifications, and equivalent embodiments, and is therefore limited only by the scope of the claims. Although the steps of different processes are presented in a predetermined order, embodiments of the invention are not required to be implemented in the order shown. In some embodiments, certain specific operations may be performed simultaneously, in a different order than described, or not at all.

[0027] The following description sets forth various specific details, which are provided by way of concrete examples to facilitate a full understanding of the scope of the invention, and embodiments may be implemented without these specific details. Therefore, the specific embodiments of the invention are merely illustrative and are not intended to be specific or limiting. For the purpose of clarity, technical details known in the art related to this invention will not be described in detail so as not to unnecessarily obscure the scope of the invention.

[0028] Power semiconductor devices require dedicated high-voltage terminations to prevent premature breakdown around the active region. Examples of high-voltage terminations include floating field rings (FFRs) and deep trenches filled with insulators. However, FFR terminations for high voltages can occupy a large die area. On the other hand, deep trench terminations can occupy less die area, but at the cost of a lower blocking voltage. All structures using high-voltage terminations have significant parasitic capacitance, which negatively impacts high-frequency switching performance and, depending on the design and materials used, can exhibit hysteresis characteristics unsuitable for high-frequency operation.

[0029] Superjunction technologies typically require deep trench etching and semiconductor epitaxial growth filling. These technologies focus on optimizing the trade-off between lower on-resistance and higher blocking voltage. In particular, superjunction devices can break the traditional silicon limitations of power semiconductor devices. However, this concept is not suitable for high-voltage terminations and superjunction devices requiring specific high-voltage termination designs.

[0030] The embodiments include a high-voltage termination for a semiconductor device, the high-voltage termination comprising one or more FFRs, and a deep trench disposed adjacent to one of the FFRs and filled with a dielectric layer. The number of FFRs can be less than the number of FFRs required for a high-voltage termination with the same rated voltage but without a deep trench in the related art, and therefore the combination of FFRs and deep trenches can produce a high-voltage termination occupying a smaller die area than the high-voltage terminations of the related art.

[0031] The embodiments are particularly applicable to silicon carbide (SiC) technology (which can have thin epitaxial layers and high rated voltage), but are also applicable to a wide range of other semiconductor materials, including but not limited to silicon and gallium nitride (GaN).

[0032] Figure 1A illustrates a semiconductor element 100 according to an embodiment. In Figure 1A, element 100 is a vertical pin diode, but the embodiment is not limited to this.

[0033] Component 100 includes a substrate 102 of semiconductor material on which an epitaxial layer (hereinafter referred to as epitaxial layer 104) is formed. Epitaxial layer 104 may be formed on substrate 102. Substrate 102 may be the same semiconductor material as epitaxial layer 104, but more heavily doped (and therefore have higher conductivity).

[0034] In one embodiment, the substrate 102 and epitaxial wafer 104 may comprise a wide-bandgap semiconductor, such as silicon carbide, and may be an n-type material, but the embodiment is not limited thereto. For example, in another embodiment, the substrate 102 and epitaxial wafer 104 may comprise silicon or GaN. In other embodiments, the substrate 102 and epitaxial wafer 104 may be a p-type material.

[0035] The doped region 106 is formed within the region surrounded by the deep trench 108 in the epitaxial layer 104. In the illustrated PIN diode, the doped region 106 is a p-type region, but the embodiment is not limited thereto.

[0036] A first floating field ring 116A, a second floating field ring 116B, and a third floating field ring 116C (collectively referred to as floating field rings 116) are formed within the epitaxial layer 106 surrounding the doped region 106. The floating field rings 116 are doped regions with the same doping type as the doped region 106. In an embodiment, the floating field rings 116 are more heavily doped than the doped region 106.

[0037] The deep trench 108 is filled with dielectric 118, which is also disposed on top of the epitaxial layer 104 and the doped region 106. In embodiments, dielectric 118 may include silicon dioxide (SiO2), polyimide, benzocyclobutene, spin-on glass, or combinations thereof.

[0038] The floating field ring 116 and the deep trench 108 together operate as a tight high-voltage termination. During operation, the blocking voltage across the PIN diode is separated between the floating field ring 116 and the deep trench 108. In this embodiment, the voltage maintained in the floating field ring 116 is higher than the difference between the breakdown voltage of the deep trench 108 and the one-dimensional breakdown voltage of the epitaxial layer 104.

[0039] A first electrode 126 is formed on and electrically contacts the doped region 106. The first electrode 126 provides an anode electrically connected to a PIN diode, which is composed of the doped region 106, a portion of epitaxial 104 below the doped region 106, and a substrate 102.

[0040] In one embodiment, the first electrode 126 may comprise aluminum or other conductors and may be electrically connected to the doped region 106 via a thin conductive layer 122, which in one embodiment may comprise nickel silicon. In another embodiment, the first electrode 126 may comprise gold.

[0041] A second electrode 130, including a conductor (such as gold or silver, and other interface elements for adhesion), is formed on the bottom surface of the substrate 102 and provides an electrical connection to the cathode of the PIN diode.

[0042] A passivation layer 128 is formed over the electrode 126 and the dielectric 118. In an embodiment, the passivation layer comprises silicon oxynitride (SiON).

[0043] Figure 1B shows a plan view of the semiconductor device 100 of Figure 1A along line A-A'. Figure 1B shows that the first floating field ring 116A, the second floating field ring 116B, and the third floating field ring 116C are concentrically disposed around the active region defined by the doped region 106, and the dielectric material filling the deep trench 108 is disposed around the third floating field ring 116C (the outermost floating field ring).

[0044] Figure 1B shows that the doped region 106 is a square shape with rounded corners, and the floating field ring 116 is a square ring shape with rounded corners, but the embodiment is not limited to this. In one embodiment, the rounded square can be replaced by a circle, or it can be a rounded rectangle, etc.

[0045] Figures 2A to 2D illustrate semiconductor device embodiments similar to the semiconductor device 100 of Figure 1A, further including a field plate as part of a high-voltage termination. Figure 2E illustrates an embodiment in which the deep trench arrangement differs from that of the semiconductor device 100 of Figure 1A.

[0046] Figure 2A shows a cross-sectional view of a semiconductor device 200A according to an embodiment. The semiconductor device 200A differs from the semiconductor device 100 of Figure 1A in that it includes a field plate 127A disposed above a deep trench 108. In plan view, the field plate 127A may be circular, elliptical, or a rounded rectangular ring, but the embodiment is not limited to these shapes.

[0047] In the embodiment of FIG2A, the field plate 127A is a floating field plate; that is, the field plate 127A is not electrically connected to any other structure in the semiconductor element 200A; however, the embodiment is not limited thereto.

[0048] Figure 2B shows a cross-sectional view of a semiconductor device 200B according to another embodiment. The semiconductor device 200B differs from the semiconductor device 100 of Figure 1A in that, unlike the first electrode 126 of the semiconductor device 100, the first electrode 126B of the semiconductor device 200B is formed not only on the doped region 106 but also on the floating field ring 116. The portion of the first electrode 126B formed above the floating field ring 116 operates as a "grounded" field plate.

[0049] In the embodiment of FIG2B, the grounding field plate portion of the first electrode 126B extends over all floating field rings 116, but the embodiment is not limited thereto. In the embodiment, the grounding field plate portion of the first electrode 126B may extend over only some of the floating field rings 116.

[0050] Figure 2C shows a cross-sectional view of a semiconductor element 200C according to another embodiment. The semiconductor element 200C differs from the semiconductor element 100 of Figure 1A in that it includes a field plate 127C disposed above a floating field ring 116, and the sidewalls of the deep trench 108V are inclined. In the plan view, the field plate 127C may be a circular, elliptical, or rounded rectangular ring, but the embodiment is not limited to these.

[0051] In the embodiment of Figure 2C, the field plate 127C is a floating field plate.

[0052] In the embodiment of FIG2C, the field plate 127C extends to all the floating field rings 116, but the embodiment is not limited thereto. In the embodiment, the field plate 127C may extend to only some of the floating field rings 116.

[0053] In one embodiment, the field plate 127C may also extend above the deep trench 108V.

[0054] Figure 2D shows a cross-sectional view of a semiconductor device 200D according to another embodiment. The semiconductor device 200D differs from the semiconductor device 200B of Figure 2B in that, unlike the first electrode 126B of semiconductor device 200B, the first electrode 126D of semiconductor device 200D is formed not only on the doped region 106 and the floating field ring 116, but also on the deep trench 108. The portion of the first electrode 126D formed above the floating field ring 116 and the deep trench 108 operates as a "grounded" field plate.

[0055] Figure 2E shows a cross-sectional view of a semiconductor element 200E according to another embodiment. The semiconductor element 200E differs from the semiconductor element 100 of Figure 1A in that the trench 108 of the semiconductor element 200E is not disposed adjacent to the third floating field ring 116C (the outermost floating field ring), but is separated from the third floating field ring 116C, which in this embodiment is separated by a portion of the epitaxial layer 104.

[0056] Figure 3 shows a cross-sectional view of a semiconductor device 300 according to another embodiment. The difference between device 300 and device 100 of Figure 1A is that: - The deep ditch 108S in Figure 3 is not as deep as the deep ditch 108 in Figure 1A, and - The fourth floating field ring 116D is positioned between the third floating field ring 116C and the deep trench 108S. The trench 108S is still a deep trench because it is deeper than the metallurgical junction between the bottom of the fourth floating field ring 116D (i.e. the outermost floating field ring) and the epitaxial layer 104.

[0057] Semiconductor element 300 has an additional fourth floating field ring 116D to compensate for the fact that the deep trench 108S is not as effective as the deep trench 108 in providing blocking voltage as the deep trench 108 in Figure 1A (i.e., it has a lower breakdown voltage), because the deep trench 108S is shallower than the deep trench 108.

[0058] Figures 4A to 8D illustrate the formation process of a semiconductor device according to several embodiments. The structures shown in Figures 4A to 8D can be created using techniques well known in the related art (e.g., via deposition followed by the formation of an optical lithography layer), and for the sake of brevity, a description of the well-known techniques may be omitted.

[0059] Figures 4A to 4D illustrate the steps of a semiconductor device manufacturing process according to one embodiment. The element symbols of the form 1xx appearing in Figure 1A correspond to the element symbols of the form 4xx in Figures 4A to 4D, and each corresponds to substantially the same structure.

[0060] Figure 4A shows substrate 402, epitaxial layer 404, doped region 406, and first floating field ring 416A, second floating field ring 416B, third floating field ring 416C and fourth floating field ring 416D (collectively referred to as floating field ring 416).

[0061] In Figure 4B, a deep trench 408 has been formed to its full depth through the epitaxial layer 404 and with a small amount penetrating into the substrate 402. However, the embodiment is not limited to this; in some embodiments, the deep trench 408 stops at a portion of its penetration into the epitaxial layer 404, as in deep trench 108S of Figure 3. During the formation of the deep trench, a portion of the fourth floating field ring 416D is removed, such that the metallurgical interface between the fourth floating field ring 416D and the epitaxial layer 404 terminates in contact with the sidewall of the deep trench 408.

[0062] In Figure 4C, a thin oxide layer 417 is formed on the surface of the deep trench 408 and on the top surface of the doped region 406, the floating field ring 416, and the epitaxial layer 404. The thin oxide layer 417 may comprise silicon dioxide grown via thermal oxidation. In one embodiment, the thin oxide layer 417 is a sacrificial oxide that is removed before the deep trench 408 is filled. In another embodiment, the thin oxide layer 417 is a pad oxide that is left in place.

[0063] The formation of a thin oxide layer 417 passivates the surface of the deep trench 408, which can improve characteristics such as leakage current and breakdown voltage of the device. However, the formation of the thin oxide layer 417 is selective.

[0064] In Figure 4D, a thicker dielectric layer 418 is formed in the deep trench 408 and on top of the doped region 406, the floating field ring 416, and the epitaxial layer 404. In an embodiment where a thin oxide layer 417 is formed, the dielectric layer 418 may be incorporated into the thin oxide layer 417 of Figure 4C. In an embodiment, the dielectric layer 418 may comprise silicon dioxide.

[0065] Figure 5 illustrates the result of further steps performed after the steps in Figures 4A to 4D in a semiconductor device manufacturing process according to one embodiment.

[0066] In Figure 5, a first contact opening has been formed through the dielectric layer 418 to expose a portion of the doped region 406. A thin conductive layer 522 (comprising nickel silicon in one embodiment) has been formed in the first contact opening, and a first electrode 526 has been formed on the thin conductive layer 522 and a portion of the dielectric layer 418. A passivation layer 528 has been formed on the first electrode 526 and the dielectric layer 418. A second electrode 530 has been formed on the bottom surface of the substrate 402.

[0067] In embodiments, one or more steps performed to produce the features shown in FIG5 require temperatures exceeding 600°C. For example, the formation of the thin conductive layer 522 may require an annealing step, which uses temperatures exceeding 1000°C for several minutes. Therefore, in embodiments, the features formed by the processes illustrated in steps 4A to 4D must be able to withstand such high temperatures without degradation. Therefore, in some embodiments, it may be prohibited to use materials incompatible with high-temperature processing (such as polyimide or benzocyclobutene (BCB)) to fill the deep trench 408.

[0068] Figures 6A to 6D illustrate the steps of a semiconductor device manufacturing process according to one embodiment. The element symbols of the form 4xx appearing in Figures 4A to 4D correspond to the element symbols of the form 6xx in Figures 6A to 6D, and each corresponds to substantially the same structure.

[0069] Figure 6A shows substrate 602, epitaxial layer 604, doped region 606, and first floating field ring 616A, second floating field ring 616B, third floating field ring 616C and fourth floating field ring 616D (collectively referred to as floating field ring 616).

[0070] In Figure 6B, a deep trench 608S has been formed through a portion of the epitaxial layer 604. The deep trench 608S extends at least far enough into the epitaxial layer 604, with its bottom below the metallurgical interface between the fourth floating field ring 616D and the epitaxial layer 604. During the formation of the deep trench, a portion of the fourth floating field ring 616D is removed, such that the metallurgical interface between the fourth floating field ring 616D and the epitaxial layer 604 terminates in contact with the sidewall of the deep trench 608S.

[0071] In Figure 6C, a thin oxide layer 617 has been formed on the surface of the deep trench 608S and on the top surface of the doped region 606, the floating field ring 616, and the epitaxial layer 604. The thin oxide layer 617 may include silicon dioxide grown via thermal oxidation.

[0072] Forming a thin oxide layer 617 passivates the surface of the deep trench 608S, thereby improving characteristics such as leakage current and breakdown voltage of the device. However, the formation of the thin oxide layer 617 is selective.

[0073] In Figure 6D, a thicker dielectric layer 618 is formed in the deep trench 608S and on top of the doped region 606, the floating field ring 616, and the epitaxial layer 604. In an embodiment where a thin oxide layer 617 is formed, the dielectric layer 618 may be incorporated into the thin oxide layer 617 of Figure 6C. In an embodiment, the dielectric layer 618 may include silicon dioxide.

[0074] Figure 7 shows the results of further steps performed after the steps in Figures 6A to 6D in a semiconductor device manufacturing process according to one embodiment.

[0075] In Figure 7, a first contact opening has been formed through the dielectric layer 618 to expose a portion of the doped region 606. A thin conductive layer 722 has been formed in the first contact opening, and a first electrode 726 has been formed on the thin conductive layer 722 and a portion of the dielectric layer 618. Floating field plates 727 have been formed on the second floating field ring 616B, the third floating field ring 616C, and the fourth floating field ring 616D, as well as a portion of the deep trench 608S. A passivation layer 728 has been formed on the first electrode 726, the floating field plate 727, and the dielectric layer 618. A second electrode 730 has been formed on the bottom surface of the substrate 602.

[0076] In embodiments, one or more steps performed to produce the features shown in FIG7 require temperatures exceeding 600°C. For example, the formation of the thin conductive layer 722 may require an annealing step, which uses temperatures exceeding 1000°C for several minutes. Therefore, in embodiments, the features formed in the process illustrated by steps 6A to 6D must be able to withstand such high temperatures without degradation. Therefore, in some embodiments, it may be prohibited to use materials incompatible with high-temperature processing (e.g., polyimide or phenylcyclobutene (BCB)) to fill the deep trench 608S.

[0077] Figures 8A to 8D illustrate additional steps performed after the steps shown in Figures 4A to 4D in a semiconductor device fabrication process according to one embodiment. In particular, Figures 8A to 8D show simplified fabrication steps for a vertical metal-oxide-semiconductor field-effect transistor (VMOSFET). The element symbols of form 8xx appearing in Figures 8A to 8D correspond to the element symbols of form 4xx in Figures 4A to 4D, and respectively correspond to substantially the same structure.

[0078] Before depositing the dielectric layer 418 shown in Figure 8A, a doped source region 826 is formed in the doped region 406. In embodiments where the doped region 406 can be a p-type material, the doped source region 826 can be an n-type material.

[0079] In this embodiment, one or more steps performed between the steps shown in Figure 8A and Figure 8D require temperatures exceeding 600°C. For example, as described below, forming a thin conductive layer on SiC may require an annealing step, which uses temperatures exceeding 1000°C for several minutes. Therefore, in this embodiment, the features formed by the process illustrated in steps 8A to 8D must be able to withstand such high temperatures without degradation.

[0080] In Figure 8A, an opening has been formed in the dielectric layer 418 above the active region of the epitaxial layer 404, and above portions of the doped region 406 and the doped source region 826. Here, the doped region 406 corresponds to the doped p-well that defines the channel in the VMOSFET, although some details of the doped region 406, which are well known in the art, are not shown for clarity.

[0081] In Figure 8B, a shallow trench is formed in the middle of the active region within the opening 832, and a dielectric layer 834 is formed in the shallow trench. In other embodiments, the formation and filling of the shallow trench may be omitted.

[0082] In Figure 8C, an additional dielectric has been formed to create dielectric layer 836, which may include dielectric layers 418 and 834. A portion of dielectric layer 836 includes a gate dielectric, and a gate electrode 838 (formed from doped polysilicon in one embodiment) is formed on the gate dielectric portion of dielectric layer 836.

[0083] In Figure 8D, a passivation layer 846 is formed on the dielectric layer 836 and the gate electrode 838. The passivation layer 846 may include, for example, borosilicate glass (BPSG). Openings are formed in the passivation layer 846 and the dielectric layer 836 to expose portions of the doped region 406, the doped source region 826, and the gate electrode 838.

[0084] A thin conductive layer 840 is formed on the surfaces of the doped regions 406 and 826 exposed in the openings of the dielectric layer 836, and in one embodiment includes nickel silicon. A source electrode 842 has been formed to provide electrical connection to the doped region 406 and the doped source region 826 through the thin conductive layer 840.

[0085] A gate contact 844 has been formed to provide an electrical connection with the gate electrode 838. A drain electrode 848 has been formed on the bottom surface of the substrate 402.

[0086] Accordingly, Figure 8D shows an intermediate stage in the fabrication process of a VMOSFET having a high-voltage termination formed around the active region of the VMOSFET and using one or more floating field rings and deep trenches.

[0087] Figure 9 shows the electrical characteristics of the element according to an embodiment. Specifically, Figure 9 shows the reverse breakdown voltage VR, junction capacitance CJ at 300V, and gate charge QC at 300V for a semiconductor element fabricated using an epitaxial layer with a thickness of 6.4 micrometers. Each semiconductor element's high-voltage termination includes a deep trench with a depth TH TRENCH of 7.0 micrometers (i.e., through the epitaxial layer) or 3.2 micrometers, and the number of floating field rings N RING is 0, 2, 4, or 6. The length L FFR of the floating field rings represents the distance from the inside of the innermost floating field ring to the outside of the outermost floating field ring in the illustrated embodiment.

[0088] Figure 10 is a graph of the reverse breakdown voltage VR of the element in Figure 9 and the element with a floating field ring but no deep trench.

[0089] As can be seen from Figures 9 and 10, compared to components with the same number of floating field rings and no deep trench, adding a deep trench increases the reverse voltage VR. A high-voltage terminal with a trench 7.0 micrometers deep effectively achieves the highest possible reverse voltage VR using only two floating field rings. A high-voltage terminal with a trench 3.2 micrometers deep effectively achieves the highest possible reverse voltage VR using four floating field rings. In contrast, a high-voltage terminal without a deep trench requires ten floating field rings to achieve the highest possible reverse voltage VR.

[0090] As can also be seen from Figure 9, the junction capacitance CJ and gate charge QC are mainly determined by the floating field ring, and are less affected by the size of the deep trench. According to one embodiment, the operating frequency of the element can be limited by the junction capacitance CJ.

[0091] Figures 9 and 10 illustrate that the deep trench depth and the number of floating field rings used in a high-voltage terminal according to one embodiment can be selected based on the required grain area, the required reverse blocking voltage, and the required operating frequency. In one embodiment, the voltage sustained in the floating field ring exceeds the difference between the deep trench collapse voltage and the epitaxial one-dimensional collapse voltage.

[0092] Figure 11 shows the electric field distribution during a sudden collapse in a semiconductor device having a high-voltage terminal comprising four floating field rings and a deep trench penetrating the entire depth of the epitaxial layer (hereinafter referred to as "full-depth terminal") according to one embodiment. Figure 12 shows the electric field distribution during a sudden collapse in a semiconductor device having a high-voltage terminal comprising four floating field rings and a deep trench penetrating to half the depth of the epitaxial layer (hereinafter referred to as "half-depth terminal") according to another embodiment.

[0093] As can be seen from Figures 11 and 12, the electric field profile of the full-depth terminal is straighter and more uniformly spaced than that of the half-depth terminal. Because of this, for a given reverse voltage, the half-depth terminal will have epitaxial regions where the electric field varies significantly per unit distance. Therefore, the maximum reverse voltage that the half-depth terminal can withstand will be lower than that that that the full-depth terminal can withstand.

[0094] Illustrative embodiments have been provided herein, wherein one or more floating field rings and deep trenches are disposed around the active region of a semiconductor device to form a high-voltage termination. The high-voltage termination may further include a field plate disposed on part or all of the one or more field rings, on the deep trench, or both. The field plate may be floating or "grounded." Such a high-voltage termination can provide a high reverse blocking voltage without consuming as much die area as conventional high-voltage terminations, thereby reducing the cost of semiconductor devices including such high-voltage terminations.

[0095] Various aspects of the invention have been described in conjunction with specific embodiments as illustrative examples, but the embodiments are not limited to those shown in the drawings or mentioned in the specification. Many substitutions, modifications, and variations can be made to the disclosed embodiments without departing from the scope of the following claims. The embodiments disclosed herein are not intended to be limiting.

[0096] 100: Semiconductor components 102:Substrate 104: Lei Jing 106: Doped region 108: Deep Ditch 108S: Deep Ditch 108V: Deep Ditch 116: Floating Field Ring 116A: First Floating Field Ring 116B: Second Floating Field Ring 116C: Third Floating Field Ring 116D: Fourth Floating Field Ring 118: Dielectric 126: First electrode 126B: First electrode 126D: First electrode 127A: Field board 127C: Field Plate 128: Passivation layer 130: Second electrode 200A: Semiconductor Components 200B: Semiconductor Components 200C: Semiconductor Components 200D: Semiconductor Components 200E: Semiconductor Components 402:Substrate 404: Leijing 408: Deep Ditch 416A: First Floating Field Ring 416B: Second Floating Field Ring 416C: Third Floating Field Ring 416D: Fourth Floating Field Ring 416: Floating Field Ring 417: Oxide layer 418: Dielectric layer 522: Thin conductive layer 526: First electrode 528: Passivation layer 530: Second electrode 602:Substrate 604: Leijing 606: Doped region 608S: Deep Ditch 616B: Second Floating Field Ring 616C: Third Floating Field Ring 616D: Fourth Floating Field Ring 616: Floating Field Ring 617: Thin oxide layer 618: Dielectric layer 722: Thin conductive layer 726: First electrode 727: Floating Field Plate 728: Passivation layer 730: Second electrode 826: Doped source pole region 832: Opening 834: Dielectric layer 836: Dielectric layer 838: Gate electrode 840: Thin conductive layer 842: Source Electrode 844: Gate contact 846: Passivation layer 848: Drain Electrode

Claims

1. A semiconductor device comprising: a substrate; a semiconductor layer formed on the substrate; an active element in or on a region of the semiconductor layer; and a high-voltage terminal comprising: a plurality of floating field rings formed on the semiconductor layer, the plurality of floating field rings being disposed around the region of the semiconductor layer; a deep trench formed on the semiconductor layer, the deep trench being concentrically disposed around the outermost floating field ring of the plurality of floating field rings and having a bottom deeper than a doped region of the active element; and a dielectric material disposed within the deep trench.

2. The semiconductor element of claim 1, wherein the high-voltage termination includes a field plate.

3. The semiconductor device of claim 2, wherein the field plate is disposed on at least one of the floating field rings.

4. The semiconductor element of claim 2, wherein the field plate is disposed on at least a portion of the deep trench.

5. The semiconductor device of claim 2, wherein the field plate is a floating field plate.

6. The semiconductor device of claim 2, wherein the field plate is electrically connected to the doped region.

7. The semiconductor device of claim 1, wherein the plurality of floating field rings each include a doped region of the semiconductor layer.

8. The semiconductor device of claim 7, wherein a bottom of the deep trench is deeper than the metallurgical interface between the outermost floating field ring of the plurality of floating field rings and the semiconductor layer, and the deep trench does not extend through the entire thickness of the semiconductor layer.

9. The semiconductor device of claim 1, wherein the deep trench extends into the substrate.

10. The semiconductor device of claim 1, wherein at least one sidewall of the deep trench is inclined.

11. The semiconductor device of claim 1, wherein the semiconductor layer includes an epitaxial layer grown on the substrate, and the epitaxial layer comprises silicon, silicon carbide or gallium nitride.

12. The semiconductor device of claim 1, wherein the deep trench is disposed adjacent to the outermost floating field ring.

13. The semiconductor element of claim 1, wherein the dielectric material disposed within the deep trench comprises silicon dioxide, polyimide, benzocyclobutene, spin-coated glass, or a combination thereof.

14. A method for manufacturing a semiconductor device, the method comprising: An epitaxial layer is formed on a semiconductor substrate; An active element is formed in or on one region of the semiconductor layer; Multiple floating field rings are formed, which are concentrically disposed around the region in the epitaxial layer; a deep trench is formed in the epitaxial layer, which surrounds the outermost floating field ring of the multiple floating field rings and has a bottom that is deeper than a doped region of the active element; and a dielectric material is formed in the deep trench.

15. The method of manufacturing a semiconductor device as claimed in claim 14, further comprising: After filling the deep trench with the dielectric material, the semiconductor device is processed at a temperature exceeding 600 degrees Celsius.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein forming the dielectric material within the deep trench comprises: An oxide layer forms on the surface of the deep trench; After the oxide layer is formed, the dielectric material is deposited in the deep trench.

17. The method of manufacturing a semiconductor device as claimed in claim 14, further comprising: A dielectric layer is formed on the epitaxial layer; A field plate is formed on the dielectric layer and on at least one of the plurality of floating field rings, at least a portion of the deep trench, or both.

18. The method of manufacturing a semiconductor device as claimed in claim 17, further comprising: An electrical connection is formed between the field plate and the doped region of the active element.

19. The method of manufacturing a semiconductor device as claimed in claim 14, wherein each of the plurality of floating field rings includes a doped region of the epitaxial layer, and wherein a bottom of the deep trench is deeper than the metallurgical interface between the outermost floating field ring and the epitaxial layer.

20. The method of manufacturing a semiconductor device as claimed in claim 19, wherein the deep trench extends into the substrate.

21. The method of manufacturing a semiconductor device as claimed in claim 14, wherein forming the deep trench includes removing a portion of the outermost floating field ring.

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