Semiconductor memory structure

Abstract

A semiconductor memory structure includes a substrate having a transistor formation region and a capacitor formation region adjacent to the transistor formation region; a transistor disposed on the substrate within the transistor formation region; a capacitor disposed within the capacitor formation region and electrically connected to the transistor; a first interlayer dielectric layer covering the transistor formation region and the capacitor formation region, wherein the first interlayer dielectric layer surrounds the metal gate of the transistor and the lower electrode plate of the capacitor; and a capping layer located on the first interlayer dielectric layer, wherein the capping layer has a first thickness within the transistor formation region and a second thickness within the capacitor formation region, wherein the first thickness is greater than the second thickness, and the capping layer acts as the capacitor dielectric layer of the capacitor within the capacitor formation region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to one-time programmable (OTP) memory cells and their manufacturing methods. Prior Technology

[0002] With the increasing use of solid-state non-volatile memory (NVM) in consumer, industrial, and automotive electronics for storing configuration settings, program code, application parameters, and data, the market demand for embedded NVM is growing rapidly.

[0003] Recently, anti-fuse variable one-time programmable (OTP) memory cells have been continuously developed due to their non-volatile strength and logic process compatibility. Figure 1 illustrates a cross-sectional schematic diagram of an OTP memory cell MC of a single transistor and a single capacitor (1T1C). As shown in Figure 1, the OTP memory cell MC of the single transistor and single capacitor includes a transistor T and a capacitor C. The transistor T includes doped regions 102 and 104 located on a substrate 100, a channel region CH between the doped regions 102 and 104, a gate MG on the channel region CH, and a gate dielectric layer GD between the gate MG and the channel region CH. The doped region 104 is electrically connected to an upper electrode plate TP of the capacitor C through an interconnect structure. The capacitor C includes an upper electrode plate TP, a lower electrode plate BP, and a capacitor dielectric layer CD between the lower electrode plate BP and the upper electrode plate TP. The lower electrode plate BP of capacitor C and the gate MG of transistor T are fabricated simultaneously, and the lower electrode plate BP of capacitor C is set on the trench insulation structure TI.

[0004] In the aforementioned OTP memory cell structure, the capacitor dielectric layer CD of capacitor C also serves as a capping layer for transistor T, protecting the underlying metal gate MG during high-resistivity metal etching processes. This means that the capacitor dielectric layer CD needs to have sufficient thickness. However, because the thickness of the capacitor dielectric layer CD cannot be further reduced, the breakdown voltage of capacitor C cannot decrease. Summary of the Invention

[0005] The main objective of this invention is to provide an improved semiconductor memory structure and its manufacturing method to overcome the shortcomings and disadvantages of the prior art.

[0006] The present invention provides a semiconductor memory structure comprising: a substrate having a transistor forming region and a capacitor forming region adjacent to the transistor forming region; a transistor disposed on the substrate within the transistor forming region; a capacitor disposed on the substrate within the capacitor forming region and electrically connected to a terminal of the transistor; a first interlayer dielectric layer covering the transistor forming region and the capacitor forming region, wherein the first interlayer dielectric layer surrounds a metal gate of the transistor and a lower electrode plate of the capacitor; and a capping layer located on the first interlayer dielectric layer, wherein the capping layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region, wherein the first thickness is greater than the second thickness, and wherein the capping layer serves as a capacitor dielectric layer of the capacitor within the capacitor forming region.

[0007] According to an embodiment of the present invention, the capacitor further includes: an upper electrode plate disposed on the cover layer within the capacitor forming region.

[0008] According to an embodiment of the present invention, the semiconductor memory structure further includes: a second interlayer dielectric layer covering the capping layer and the upper electrode plate.

[0009] According to an embodiment of the present invention, the lower electrode plate is a metal gate lower electrode plate.

[0010] According to an embodiment of the present invention, the lower electrode plate and the metal gate of the transistor are coplanar.

[0011] According to an embodiment of the present invention, the upper electrode plate comprises titanium nitride or tantalum nitride.

[0012] According to an embodiment of the present invention, the first thickness is 200-300 angstroms and the second thickness is 20-50 angstroms.

[0013] According to an embodiment of the present invention, the capping layer is a silicon oxide layer.

[0014] According to an embodiment of the present invention, the composition of the capping layer in the transistor formation region is different from the composition of the capping layer in the capacitor formation region.

[0015] According to an embodiment of the present invention, the semiconductor memory structure further includes: a trench isolation structure located in the substrate within the capacitor formation region, wherein the lower electrode plate is directly disposed on the trench isolation structure.

[0016] Another aspect of the present invention provides a method for forming a semiconductor memory structure. First, a substrate is provided having a transistor forming region and a capacitor forming region adjacent to the transistor forming region; a transistor is formed on the substrate within the transistor forming region; a capacitor is formed on the substrate within the capacitor forming region and electrically connected to a terminal of the transistor; a first interlayer dielectric layer is formed, covering the transistor forming region and the capacitor forming region, wherein the first interlayer dielectric layer surrounds a metal gate of the transistor and a lower electrode plate of the capacitor; and a capping layer is formed on the first interlayer dielectric layer, wherein the capping layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region, wherein the first thickness is greater than the second thickness, and wherein the capping layer serves as a capacitor dielectric layer of the capacitor within the capacitor forming region.

[0017] According to an embodiment of the present invention, forming the capacitor further includes: forming an upper electrode plate on the capping layer within the capacitor forming region.

[0018] According to an embodiment of the present invention, the method further includes: forming a second interlayer dielectric layer covering the capping layer and the upper electrode plate.

[0019] According to an embodiment of the present invention, the lower electrode plate is a metal gate lower electrode plate.

[0020] According to an embodiment of the present invention, the lower electrode plate and the metal gate of the transistor are coplanar.

[0021] According to an embodiment of the present invention, the upper electrode plate comprises titanium nitride or tantalum nitride.

[0022] According to an embodiment of the present invention, the first thickness is 200-300 angstroms and the second thickness is 20-50 angstroms.

[0023] According to an embodiment of the present invention, the capping layer is a silicon oxide layer.

[0024] According to an embodiment of the present invention, the composition of the capping layer in the transistor formation region is different from the composition of the capping layer in the capacitor formation region.

[0025] According to an embodiment of the present invention, the method further includes: forming a trench isolation structure in the substrate within the capacitor forming region, wherein the lower electrode plate is directly disposed on the trench isolation structure.

[0026] The main technical feature of this invention is that the capping layer has a thicker first part and a thicker third part, located within the transistor formation region and the resistor formation region, respectively, and a thinner second part, located within the capacitor formation region. This effectively reduces the capacitor's breakdown voltage while protecting the transistor's metal gate. Simple Explanation of the Diagram

[0027] Figure 1 illustrates a cross-sectional schematic diagram of an OTP memory cell of a single-electro-transistor single-capacitor. Figure 2 is a cross-sectional schematic diagram of a semiconductor memory structure according to an embodiment of the present invention. Figures 3 to 8 are schematic cross-sectional views illustrating a method for forming a semiconductor memory structure according to an embodiment of the present invention. Figures 9 to 12 are schematic cross-sectional views illustrating a method for forming a semiconductor memory structure according to another embodiment of the present invention. Implementation

[0028] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0029] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0030] Please refer to Figure 2, which is a schematic cross-sectional view of a semiconductor memory structure 1 according to an embodiment of the present invention. The semiconductor memory structure 1 may be, for example, a one-time programmable (OTP) memory cell. As shown in Figure 2, the semiconductor memory structure 1 includes a substrate 200, for example, a silicon substrate. According to an embodiment of the present invention, the substrate 200 may have a first conductivity type, for example, P-type. According to an embodiment of the present invention, the substrate 200 may include a resistance forming region HIR, a transistor forming region TR, and a capacitor forming region CAP adjacent to the transistor forming region TR.

[0031] According to an embodiment of the present invention, a semiconductor memory structure 1 includes a transistor 20 disposed on a substrate 200 within a transistor formation region TR. According to an embodiment of the present invention, the transistor 20 is formed within an active region AA surrounded by trench isolation structures 201a and 201b. According to an embodiment of the present invention, trench isolation structure 201a is located within a resistor formation region HIR, while trench isolation structure 201b is located within a capacitor formation region CAP.

[0032] According to an embodiment of the present invention, the semiconductor memory structure 1 further includes a capacitor 30, which is directly disposed on the trench isolation structure 201b within the capacitor formation region CAP and electrically connected to a terminal of the transistor 20, such as the doped region 204.

[0033] According to an embodiment of the present invention, the transistor 20 may be an NMOS transistor. According to an embodiment of the present invention, the transistor 20 includes a doped region 202 located in a substrate 200 and having a second conductivity type (e.g., N-type), a doped region 204 located in the substrate 200 and having the second conductivity type (e.g., N-type), a channel region 206 located in the substrate 200 and between the doped regions 202 and 204, and a metal gate 208 on the channel region 206.

[0034] According to an embodiment of the present invention, the transistor 20 further includes a gate dielectric layer 207 located between the channel region 206 and the metal gate 208. According to an embodiment of the present invention, the gate dielectric layer 207 may include a silicon oxide layer and a high dielectric constant film. According to an embodiment of the present invention, the silicon oxide layer is below the high dielectric constant film and directly contacts the surface of the substrate 200. According to an embodiment of the present invention, the metal gate 208 may contain, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, aluminum, or any combination thereof, but is not limited thereto. According to an embodiment of the present invention, sidewalls (not shown) may be additionally formed on the metal gate 208.

[0035] According to an embodiment of the present invention, a first interlayer dielectric layer 210 is provided on the substrate 200, covering the transistor formation region TR, the capacitor formation region CAP, and the resistor formation region HIR. The first interlayer dielectric layer 210 surrounds the metal gate 208 of the transistor 20 and the lower electrode plate 310 of the capacitor 30. According to an embodiment of the present invention, the lower electrode plate 310 is a metal gate electrode plate, formed together with the metal gate 208, so the lower electrode plate 310 and the metal gate 208 have the same structure. According to an embodiment of the present invention, the lower electrode plate 310 and the metal gate 208 of the transistor 20 are coplanar. According to an embodiment of the present invention, the lower electrode plate 310 directly contacts the trench isolation structure 201b.

[0036] According to an embodiment of the present invention, the semiconductor memory structure 1 further includes a capping layer 220 located on the first interlayer dielectric layer 210. The capping layer 220 has a first thickness t1 within the transistor formation region TR and a second thickness t2 within the capacitor formation region CAP, wherein the first thickness t1 is greater than the second thickness t2. According to an embodiment of the present invention, the first thickness t1 is approximately 200-300 angstroms, and the second thickness t2 is approximately 20-50 angstroms. According to an embodiment of the present invention, the capping layer 220 may be a silicon oxide layer.

[0037] In other words, the capping layer 220 has a thicker first portion 220a and a third portion 220c, located within the transistor formation region TR and the resistor formation region HIR, respectively, and a thinner second portion 220b, located within the capacitor formation region CAP. There is a step difference between the first portion 220a and the second portion 220b. According to an embodiment of the present invention, the composition of the capping layer 220 in the transistor formation region TR may be different from the composition of the capping layer 220 in the capacitor formation region CAP. For example, the first portion 220a may be a silicon oxide layer, and the second portion 220b may contain a high dielectric constant dielectric layer, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc.

[0038] According to an embodiment of the present invention, the capacitor 30 further includes an upper electrode plate 330 disposed on a second portion 220b of the capping layer 220 within the capacitor forming region CAP. According to an embodiment of the present invention, the second portion 220b of the capping layer 220 is located between the upper electrode plate 330 and the lower electrode plate 310, and serves as the dielectric layer of the capacitor 30 within the capacitor forming region CAP.

[0039] According to an embodiment of the present invention, a resistor 40 is disposed on the third portion 220c of the capping layer 220 within the resistor formation region HIR. The resistor 40 is composed of a high-resistivity metal layer 430 and has two terminals 430a and 430b, which are the cathode and anode, respectively. According to an embodiment of the present invention, the high-resistivity metal layer 430 of the resistor 40 and the upper electrode plate 330 of the capacitor 30 are formed together. For example, the upper electrode plate 330 and the high-resistivity metal layer 430 may contain titanium nitride or tantalum nitride. According to an embodiment of the present invention, a dummy gate 410 is disposed below the third portion 220c of the capping layer 220 within the resistor formation region HIR to increase the yield and reliability during the formation of the resistor 40. According to an embodiment of the present invention, the dummy gate 410, the lower electrode plate 310, and the metal gate 208 are formed together, and therefore have the same structure.

[0040] According to an embodiment of the present invention, the semiconductor memory structure 1 further includes a second interlayer dielectric layer 230, covering the capping layer 220, the upper electrode plate 330, and the high-resistivity metal layer 430. An intermetallic dielectric layer 240, such as a low-dielectric-constant dielectric layer or an ultra-low-dielectric-constant dielectric layer, is disposed on the second interlayer dielectric layer 230.

[0041] According to an embodiment of the present invention, a plurality of plugs CT1 to CT5 are provided in the second interlayer dielectric layer 230. Plugs CT1 and CT2 penetrate downwards through the first portion 220a of the cap layer 220 and the first interlayer dielectric layer 210, respectively, and are electrically connected to the doped regions 202 and 204 of the transistor 20. Plug CT1 is electrically connected to the internal interconnect ML1 located within the intermetallic dielectric layer 240, while plug CT2 is electrically connected to the internal interconnect ML2 located within the intermetallic dielectric layer 240, and then electrically connected to the upper electrode plate 330 via plug CT3. The internal interconnects ML4 and ML5 located within the intermetallic dielectric layer 240 are electrically connected to the two terminals 430a and 430b of the resistor 40 via plugs CT4 and CT5, respectively.

[0042] The main technical feature of this invention is that the capping layer has a thicker first part and a thicker third part, located within the transistor formation region and the resistor formation region, respectively, and a thinner second part, located within the capacitor formation region. This effectively reduces the capacitor's breakdown voltage while protecting the transistor's metal gate.

[0043] Please refer to Figures 3 to 8, which are cross-sectional schematic diagrams illustrating a method for forming a semiconductor memory structure according to an embodiment of the present invention, wherein the same regions, layers, or materials are still represented by the same symbols. As shown in Figure 3, a substrate 200 is provided, for example, a silicon substrate. According to an embodiment of the present invention, the substrate 200 may have a first conductivity type, for example, P-type. According to an embodiment of the present invention, the substrate 200 may include a resistor formation region HIR, a transistor formation region TR, and a capacitor formation region CAP adjacent to the transistor formation region TR.

[0044] A transistor 20 is formed on a substrate 200 within a transistor formation region TR. According to an embodiment of the invention, the transistor 20 is formed within an active region AA surrounded by trench isolation structures 201a and 201b. According to an embodiment of the invention, trench isolation structure 201a is located within a resistance formation region HIR, while trench isolation structure 201b is located within a capacitance formation region CAP.

[0045] According to an embodiment of the present invention, the transistor 20 may be an NMOS transistor. According to an embodiment of the present invention, the transistor 20 includes a doped region 202 located in a substrate 200 and having a second conductivity type (e.g., N-type), a doped region 204 located in the substrate 200 and having the second conductivity type (e.g., N-type), a channel region 206 located in the substrate 200 and between the doped regions 202 and 204, and a metal gate 208 on the channel region 206.

[0046] According to an embodiment of the present invention, the transistor 20 further includes a gate dielectric layer 207 located between the channel region 206 and the metal gate 208. According to an embodiment of the present invention, the gate dielectric layer 207 may include a silicon oxide layer and a high dielectric constant film. According to an embodiment of the present invention, the silicon oxide layer is below the high dielectric constant film and directly contacts the surface of the substrate 200. According to an embodiment of the present invention, the metal gate 208 may contain, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, aluminum, or any combination thereof, but is not limited thereto. According to an embodiment of the present invention, sidewalls (not shown) may be additionally formed on the metal gate 208.

[0047] According to an embodiment of the present invention, a dummy gate 410 and a lower electrode plate 310 of a capacitor 30 are respectively formed on trench isolation structures 201a and 201b within the resistor formation region HIR and the capacitor formation region CAP. According to an embodiment of the present invention, a first interlayer dielectric layer 210 is provided on the substrate 200, covering the transistor formation region TR, the capacitor formation region CAP, and the resistor formation region HIR, wherein the first interlayer dielectric layer 210 surrounds the metal gate 208 of the transistor 20, the dummy gate 410, and the lower electrode plate 310 of the capacitor 30. According to an embodiment of the present invention, the dummy gate 410, the lower electrode plate 310, and the metal gate 208 are formed together using a replacement metal gate (RMG) process, and therefore have the same structure. Through a chemical mechanical polishing process, the top surfaces of the dummy gate 410, the lower electrode plate 310, and the metal gate 208 are flush with the top surface of the first interlayer dielectric layer 210.

[0048] As shown in Figure 4, a capping layer 220 is then deposited over the entire substrate 200, covering the transistor formation region TR, the capacitor formation region CAP, and the resistor formation region HIR. According to an embodiment of the invention, the capping layer 220 has a first thickness t1, for example, approximately 200-300 angstroms. According to an embodiment of the invention, the capping layer 220 may be a silicon oxide layer.

[0049] As shown in Figure 5, next, using lithography and etching processes, the capping layer 220 located within the capacitor formation region CAP is etched, reducing the thickness of the capping layer 220 within the capacitor formation region CAP from a first thickness t1 to a second thickness t2, for example, the second thickness t2 is approximately 20-50 angstroms. The capping layer 220 has a thicker first portion 220a and a third portion 220c, located within the transistor formation region TR and the resistor formation region HIR, respectively, and a thinner second portion 220b, located within the capacitor formation region CAP. There is a stepped drop between the first portion 220a and the second portion 220b.

[0050] As shown in Figure 6, a high-resistivity metal layer 430, such as titanium nitride or tantalum nitride, is then deposited over the substrate 200 to cover the transistor formation region TR, the capacitor formation region CAP, and the resistance formation region HIR.

[0051] As shown in Figure 7, next, using photolithography and etching processes, the high-resistivity metal layer 430 is patterned into the upper electrode plates 330 of the resistor 40 and capacitor 30 in the resistor formation region HIR and capacitor formation region CAP, respectively. The resistor 40 has two terminals 430a and 430b, which are the cathode and anode, respectively.

[0052] As shown in Figure 8, the interconnect fabrication process is then performed. First, a second interlayer dielectric layer 230 is formed on the substrate 200, covering the transistor formation region TR, the capacitor formation region CAP, and the resistor formation region HIR. Then, a plurality of plugs CT1 to CT5 are formed within the second interlayer dielectric layer 230. Next, an intermetallic dielectric layer 240, for example, a low-dielectric-constant dielectric layer or an ultra-low-dielectric-constant dielectric layer, is deposited on the second interlayer dielectric layer 230. Then, interconnects ML1 to ML5 are formed within the intermetallic dielectric layer 240. Plugs CT1 and CT2 penetrate downwards through the first portion 220a of the capping layer 220 and the first interlayer dielectric layer 210, respectively, and are electrically connected to the doped regions 202 and 204 of the transistor 20. Plug CT1 is electrically connected to the internal interconnect ML1 located within the intermetallic dielectric layer 240, while plug CT2 is electrically connected to the internal interconnect ML2 located within the intermetallic dielectric layer 240, and then electrically connected to the upper electrode plate 330 via plug CT3. The internal interconnects ML4 and ML5 located within the intermetallic dielectric layer 240 are electrically connected to the two terminals 430a and 430b of resistor 40 via plugs CT4 and CT5, respectively.

[0053] Please refer to Figures 9 to 12, which are cross-sectional schematic diagrams illustrating a method for forming a semiconductor memory structure according to another embodiment of the present invention, wherein the same regions, layers, or materials are still represented by the same symbols. As shown in Figure 9, using photolithography and etching processes, the capping layer 220 located in the capacitor formation region CAP is completely removed, leaving only the first portion 220a and the third portion 220c of the capping layer 220, located in the transistor formation region TR and the resistor formation region HIR, respectively. At this time, the lower electrode plate 310 in the capacitor formation region CAP is exposed.

[0054] As shown in Figure 10, a capacitor dielectric layer 221 and a high-resistivity metal layer 430 are then sequentially deposited on the substrate 200 to cover the transistor formation region TR, the capacitor formation region CAP, and the resistance formation region HIR. According to an embodiment of the present invention, the capacitor dielectric layer 221 may comprise, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc., and the high-resistivity metal layer 430 may comprise, for example, titanium nitride or tantalum nitride, etc.

[0055] As shown in Figure 11, next, using photolithography and etching processes, the high-resistivity metal layer 430 is patterned into the upper electrode plates 330 of the resistor 40 and capacitor 30 in the resistor formation region HIR and capacitor formation region CAP, respectively. The resistor 40 has two terminals 430a and 430b, which are the cathode and anode, respectively.

[0056] As shown in Figure 12, the interconnect fabrication process is then performed. First, a second interlayer dielectric layer 230 is formed on the substrate 200, covering the transistor formation region TR, the capacitor formation region CAP, and the resistor formation region HIR. Then, a plurality of plugs CT1 to CT5 are formed within the second interlayer dielectric layer 230. Next, an intermetallic dielectric layer 240, for example, a low-dielectric-constant dielectric layer or an ultra-low-dielectric-constant dielectric layer, is deposited on the second interlayer dielectric layer 230. Then, interconnects ML1 to ML5 are formed within the intermetallic dielectric layer 240. Plugs CT1 and CT2 penetrate downwards through the capacitor dielectric layer 221, the first portion 220a of the capping layer 220, and the first interlayer dielectric layer 210, respectively, and are electrically connected to the doped regions 202 and 204 of the transistor 20. Plug CT1 is electrically connected to the internal interconnect ML1 located within the intermetallic dielectric layer 240, while plug CT2 is electrically connected to the internal interconnect ML2 located within the intermetallic dielectric layer 240, and then electrically connected to the upper electrode plate 330 via plug CT3. The internal interconnects ML4 and ML5 located within the intermetallic dielectric layer 240 are electrically connected to the two terminals 430a and 430b of resistor 40 via plugs CT4 and CT5, respectively. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0057] 1: Semiconductor memory structure 20: Transistor 30: Capacitor 40: Resistance 102, 104: Doped regions 100: Base 200: Base 201a, 201b: Ditch isolation structure 202, 204: Doped regions 206: Passage Area 207: Gate dielectric layer 208: Metal gate 210: First interlayer dielectric layer 220: Cap layer 220a: Part 1 220b: Part Two 220c: Part Three 221: Capacitor dielectric layer 230: Second interlayer dielectric layer 240: Intermetallic dielectric layer 310: Lower electrode plate 330: Upper electrode plate 410: Dummy gate 430: High-resistivity metal layer 430a, 430b: terminal AA: Active Zone BP: Lower electrode plate C: Capacitor CAP: Capacitor Formation Region CD: Capacitor dielectric layer CH: Passage Area CT1~CT5: Plugs GD: Gate Dielectric Layer HIR: Resistance Formation Region MC: OTP memory cell MG: Gate ML1~ML5: Internal connections T: Transistor TI: Trench Insulation Structure TP: Upper electrode plate TR: Transistor Formation Region t1: First thickness t2: Second thickness

Claims

1. A semiconductor memory structure, characterized in that it comprises: a substrate having a transistor formation region and a capacitor formation region adjacent to the transistor formation region; a transistor disposed on the substrate within the transistor formation region; a capacitor disposed on the substrate within the capacitor formation region and electrically connected to a terminal of the transistor; a first interlayer dielectric layer covering the transistor formation region and the capacitor formation region, wherein the first interlayer dielectric layer surrounds a metal gate of the transistor and a lower electrode plate of the capacitor; and a capping layer located on the first interlayer dielectric layer, wherein... The capping layer has a first thickness in the transistor forming region and a second thickness in the capacitor forming region, wherein the first thickness is greater than the second thickness, wherein the capping layer acts as a capacitor dielectric layer of the capacitor in the capacitor forming region, wherein the capacitor further includes an upper electrode plate disposed on the capping layer in the capacitor forming region, wherein the composition of the capping layer in the transistor forming region is different from the composition of the capping layer in the capacitor forming region.

2. The semiconductor memory structure according to claim 1, wherein, It also includes: a second interlayer dielectric layer covering the capping layer and the upper electrode plate.

3. The semiconductor memory structure according to claim 1, wherein, The lower electrode plate is a metal lower electrode plate.

4. The semiconductor memory structure according to claim 1, wherein, The lower electrode plate is coplanar with the metal gate of the transistor.

5. The semiconductor memory structure according to claim 1, wherein, The upper electrode plate contains titanium nitride or tantalum nitride.

6. The semiconductor memory structure according to claim 1, wherein, The first thickness is 200-300 angstroms, and the second thickness is 20-50 angstroms.

7. The semiconductor memory structure according to claim 1, wherein, The capping layer is a silicon oxide layer.

8. The semiconductor memory structure according to claim 1, wherein, It also includes: a trench isolation structure located in the substrate within the capacitor forming region, wherein the lower electrode plate is directly disposed on the trench isolation structure.

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