Unit specific variable or adaptive metal fill and system and method for the same

Abstract

A method of forming a semiconductor device may include a first shift region disposed therein for determining a first displacement. A second shift region disposed therein for determining a second displacement. A unique conductive structure including traces may be formed to accommodate the first displacement and the second displacement. The conductive structure may include traces, the traces comprising a first portion within the first shift region and a second portion of traces laterally offset from the first portion of the traces in the second shift region. A third portion of the traces may be disposed in a wiring region between the first shift region and the second shift region. A unique variable metal fill may be formed in the fill region. The variable metal fill may be electrically isolated from the unique conductive structure.

Description

Technical Field Cross-referencing of related applications

[0001] This disclosure claims the benefit of U.S. Provisional Patent No. 63 / 232,949, filed on August 13, 2021, entitled “Unit Specific Adaptive Metal Fill and System and Method for the Same,” the entire disclosure of which is incorporated herein by reference.

[0002] This disclosure relates to unit-specific variable metal fill, also known under the Deca Technologies trade names and trademarks "Unit Specific Adaptive Metal Fill," "Adaptive Metal Fill"™, and "AMF"™. This disclosure relates to semiconductor devices, substrates, and packages, including systems and methods for unit-specific variable metal fill. Prior Technology

[0003] Semiconductor components, packages, substrates, and interposers are commonly found in modern electronic products. Substrates and interposers provide structural support and electrical interconnection for semiconductor components, packages, wafers, passive components, and other components, modules, and units. Substrates include circuit boards and printed circuit boards (PCBs). As is known in the art, PCBs can be configured or arranged in several ways, including single-layer, double-layer, multi-layer, high-density interconnect (HDI), high-frequency, formed with or without a core (coreless), with or without mesh or glass braid reinforcement, rigid, flexible, rigid-flexible, laminate, interposer, or any other substrate or support material.

[0004] Semiconductor components vary in number and density within electronic assemblies. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual projections for television displays. Semiconductor components are found in entertainment, communications, power conversion, networking, computers, and consumer products. They are also used in military applications, aerospace, automotive, industrial controllers, office equipment, and other fields and applications.

[0005] Semiconductor devices are typically manufactured using both front-end and back-end manufacturing. Front-end manufacturing involves forming multiple semiconductor dies on the surface of a semiconductor wafer. Each semiconductor die can be identical and may contain circuitry formed by electrically connecting active and passive components. Back-end manufacturing involves dicing individual semiconductor dies from one or more finished wafers and packaging the dies to provide structural support, electrical interconnections from the die to the next level (such as a printed circuit board), electrical interconnections between multiple dies or between dies and other components (such as passive components), and finally, environmental protection. Summary of the Invention

[0006] There are opportunities to improve semiconductor manufacturing. Therefore, in one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: providing a temporary carrier; disposing of a first element including a first interconnect on the carrier; disposing of a second element including a second interconnect on the carrier at a lateral offset from the first element; disposing of an encapsulant on and around the first element and the second element to form a first embedded element including a first displacement region and a second embedded element including a second displacement region; measuring the displacement of the first embedded element within the first displacement region to determine a first displacement; measuring the displacement of the second embedded element within the second displacement region to determine a second displacement; forming a variable region between the first displacement region and the second displacement region and extending the variable region to both the first displacement region and the second displacement region. The variable region further includes a wiring region, a buffer region, and a filling region; a unique conductive structure containing traces is formed to accommodate the first displacement and the second displacement, the traces being a first portion within the first displacement region and a second portion of a trace laterally offset from the first portion of the trace in the second displacement region, and a third portion of the traces located in the wiring region between the first displacement region and the second displacement region; a unique non-conductive variable metal filler is formed in the filling region, wherein the non-conductive variable metal filler is electrically isolated from the unique conductive structure; and an insulating layer is formed on the unique conductive structure containing the traces and on the non-conductive variable metal filler laterally disposed between the first portion and the second portion of the trace.

[0007] The insulating layer may further include: a lower surface that contacts the unique conductive structure containing the trace and is located above the non-conductive variable metal filler; and an upper surface opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar, such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than one thickness of the insulating layer. The non-conductive variable metal filler is formed of a solid continuous material. The non-conductive variable metal filler may be formed of a patterned discontinuous material containing the metal filler and the gaps between the blocks. The filler region extends beyond the variable region into the first shift region, the second shift region, or both. The size, shape, or both of the size and shape of a structure selected from one or more of the conductive patterned trace and the non-conductive variable metal filler are adjusted in the design space by: reducing the space between the initial outer edge of the structure and the center of the structure by a fixed distance to form a reduced outer edge of the structure; and increasing the space between the reduced outer edge of the structure and the center of the structure by the fixed distance to form a new outer edge of the structure.

[0008] According to another aspect of this disclosure, a method of manufacturing a semiconductor device may include: providing a first displacement region therein for determining a first displacement; providing a second displacement region therein for determining a second displacement; forming a unique conductive structure including traces to accommodate the first displacement and the second displacement, the conductive structure including traces, the traces including a first portion within the first displacement region and a second portion of traces laterally offset from the first portion of the traces in the second displacement region, and a third portion of the traces located in a wiring region between the first displacement region and the second displacement region; and forming a unique variable metal fill in the fill region, wherein the variable metal fill is electrically isolated from the unique conductive structure.

[0009] The method of manufacturing a semiconductor device may further include forming an insulating layer on the unique conductive structure containing the trace and on a variable metal fill laterally disposed between the first portion and the second portion of the trace. A lower surface may contact the unique conductive structure containing the trace and lie on the variable metal fill; and the upper surface of the insulating layer is opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar, such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than the thickness of the insulating layer. The variable metal fill may be formed of a solid continuous material. The variable metal fill may be formed of a patterned discontinuous material containing the metal fill and the gaps between the blocks. The unique conductive structure containing the trace may be electrically coupled to vias, under-bump metallization (UBM) pads, or other conductive structures. The size, shape, or both of the size and shape of a structure selected from one or more of the conductive patterned trace and the variable metal filler are adjusted in the design space by: reducing the space between the initial outer edge of the structure and the center of the structure by a fixed distance to form a reduced outer edge of the structure; and increasing the space between the reduced outer edge of the structure and the center of the structure by the fixed distance to form a new outer edge of the structure.

[0010] According to another aspect of this disclosure, a method of manufacturing a semiconductor element may include: forming a semiconductor element including a first displacement region disposed therein for determining a first displacement; forming a unique conductive structure extending to the first displacement region to accommodate the first displacement; and forming a unique variable metal fill, wherein the variable metal fill is electrically isolated from the unique conductive structure.

[0011] The method of manufacturing a semiconductor device may further include forming an insulating layer over the unique conductive structure containing traces and over the variable metal filler. The insulating layer may further include: a lower surface that contacts the unique conductive structure containing traces and is located over the variable metal filler; and an upper surface opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar, such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than the thickness of the insulating layer. The variable metal filler may be formed as a solid continuous material extending to the first and second shift regions to form a conductive feature. The variable metal filler may be formed from a patterned discontinuous material containing the metal filler and the gaps between the blocks. The unique conductive structure may include traces electrically coupled to vias or vertical conductive interconnects, under-bump metallization (UBM) pads, or other conductive structures. A method may also include adjusting the size, shape, or both of the size and shape of a structure selected from one or more of the conductive structure and the variable metal filler in a design space by: reducing the space between the initial outer edge of the structure and the center of the structure by a fixed distance to form a reduced outer edge of the structure; and increasing the space between the reduced outer edge of the structure and the center of the structure by the fixed distance to form a new outer edge of the structure.

[0012] Based on the specification, drawings, and claims, the foregoing and other features, applications, and advantages will be obvious to those skilled in the art. Unless explicitly stated otherwise, it is intended that the words and phrases in the specification and claims be given simple, common, and conventional meanings to those skilled in the art. The inventors fully recognize that they may become their own lexicographers if desired. As their own lexicographers, the inventors explicitly choose to use only the simple and common meanings of the terms in the specification and claims, unless otherwise stated, further explicitly defining the "specific" meaning of the term and explaining its difference from the simple and common meaning. In the absence of such explicit statement of intent to apply the "specific" meaning, the inventors intend and expect that the concise, simple, and common meanings of the terms be applied to the interpretation of the specification and claims.

[0013] The inventors also understand normal English grammar rules. Therefore, if a noun, term, or phrase is intended to further characterize, specify, or narrow its scope in some way, then such a noun, term, or phrase will explicitly include additional adjectives, descriptive terms, or other modifiers that conform to normal English grammar rules. Without using such adjectives, descriptive terms, or modifiers, it is intended to give such nouns, terms, or phrases a simple and common English meaning to those skilled in the art described above.

[0014] Furthermore, the inventors are fully aware of the standards and applications of the specific provisions of the Patent Act. Therefore, the use of the terms "function," "means," or "step" in the simple description of the embodiments or drawings or in the claims is not intended to indicate, in any respect, an intention to invoke the specific provisions of the Patent Act to define the invention. On the contrary, if an attempt were made to invoke the provisions of the Patent Act to define the invention, the claims would specifically and clearly state the exact phrases "means for..." or "steps for..." and would also list the term "function" (i.e., "means for performing the [insertion function]"), without listing any structure, material, or action supporting that function. Therefore, even when the claims list "means for performing the function" or "steps for performing the function," if the claims also list any structure, material, or action supporting that means or step or performing the listed function, the inventors' explicit intention is not to invoke the provisions of the Patent Act. Furthermore, even when the provisions of patent law are invoked to define the claimed features, it is intended that such features are not limited to the specific structures, materials, or actions described in the preferred embodiments, but also include any and all structures, materials, or actions that perform the claimed functions as described in the alternative embodiments or forms disclosed herein, or well-known existing or subsequently developed equivalent structures, materials, or actions for performing the claimed functions.

[0015] Based on the specification, drawings and the scope of the patent application, the foregoing and other features and advantages will be obvious to those skilled in the art. Simple Explanation of the Diagram

[0016] Figures 1A to 1E illustrate the formation of embedded components.

[0017] Figures 2A to 2C illustrate elements or fully molded semiconductor packages that include a variable region, a first shift region, and a second shift region.

[0018] Figures 3A and 3B illustrate a substrate or molded substrate including a variable region, a first shift region, and a second shift region.

[0019] Figures 4A through 4C illustrate various views of conductive interconnects with and without metal filler for support.

[0020] Figures 5A to 5C illustrate further views of conductive material (e.g., traces) formed in the variable region, the first shift region, and the second shift region.

[0021] Figures 6A through 6C illustrate additional views of the variable metal fill (VMF) formed in the variable region, the first shift region, and the second shift region.

[0022] Figures 7A through 7D illustrate additional enlarged views of the variable metal fill.

[0023] Figures 8A to 8H illustrate the various states of variable metal filling.

[0024] Figures 9A and 9B illustrate flowcharts of a method for forming a variable metal filler. Implementation

[0025] This disclosure includes one or more embodiments or configurations in the following description with reference to the accompanying drawings, wherein like numerals denote like or similar elements. Those skilled in the art will understand that this description is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of this disclosure as defined by the appended claims and their equivalents, supported by the following disclosure and the accompanying drawings. Numerous specific details, such as specific configurations, components, and processes, are set forth in the description to provide a thorough understanding of this disclosure. In other instances, well-known processes and manufacturing techniques have not been described in particular detail to avoid unnecessarily obscuring this disclosure. Furthermore, the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0026] This disclosure, its morphology, and embodiments are not limited to the specific equipment, material types, or other system component examples or methods disclosed herein. Many other components, manufacturing and assembly procedures known in the art and conforming to manufacturing and packaging are contemplated for use with specific embodiments derived from this disclosure. Therefore, for example, while specific embodiments are disclosed, such embodiments and implementing components may include any components, models, types, materials, versions, quantities, and / or similarities known in the art for use in such systems and implementing components that conform to intended operation.

[0027] The terms “exemplary,” “example,” or any of their various forms are used herein to mean something that serves as an example, illustration, or illustration. Any form or design described herein as “exemplary” or “example” is not necessarily to be construed as superior or advantageous over other forms or designs. Furthermore, examples are provided solely for clarity and understanding and are not intended to limit or constrain the subject matter disclosed or any part of this disclosure in any way. It should be understood that numerous other or alternative examples of different categories may have been presented, but such examples have been omitted for the sake of brevity.

[0028] In the examples, embodiments, and implementations described below, it will be understood by those skilled in the art that other manufacturing elements and examples may be combined with or substituted for those provided. Where specific embodiments are referenced in the foregoing description, it should be apparent that many modifications may be made without departing from the spirit of this disclosure, and that such embodiments and implementations may also be applied to other technologies. Therefore, the subject matter disclosed is intended to encompass all such changes, modifications, and variations falling within the spirit and scope of this disclosure and the knowledge of those skilled in the art.

[0029] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electronic components that are electrically connected to form a functional circuit. Active electronic components, such as transistors and diodes, have the ability to control the flow of current. Passive electronic components, such as capacitors, inductors, resistors, and transformers, create the voltage and current relationship required to perform the circuit's function.

[0030] Passive and active components are formed on the surface of a semiconductor wafer through a series of process steps including doping, deposition, lithography, etching, and planarization. Doping introduces impurities into the semiconductor material using techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active component, thereby transforming the semiconductor material into an insulator, a conductor, or dynamically changing its conductivity in response to an electric field or base current. Transistors contain different types and degrees of doping regions configured as needed to enable the transistor to promote or confine current flow when an electric field or base current is applied.

[0031] Active and passive components are formed from layers of materials with different electrical properties. These layers can be formed using a variety of deposition techniques, which depend in part on the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. The layers are typically patterned to form portions of active components, passive components, or electrical connections between components.

[0032] These layers can be patterned using lithography, which involves depositing a photosensitive material, such as a photoresist, onto the layer to be patterned. Light is used to transfer the pattern from a photomask to the photoresist. In one embodiment, a solvent is used to remove the light-exposed portions of the photoresist pattern, thereby exposing the underlying layer to be patterned. In another embodiment, a solvent is used to remove the unexposed portions of the photoresist pattern (negative photoresist), thereby exposing the underlying layer to be patterned. The remaining portion of the photoresist can be removed, for example, by a stripping process, leaving a patterned layer. Alternatively, some types of materials can be patterned by directly depositing the material into areas or voids created by a previous deposition / etching process using techniques such as electroless plating and electrolytic plating.

[0033] Patterning is a basic operation that partially removes photoresist to provide patterns or plating templates for subsequent structure formation, such as patterned redistribution layers (RDLs), under-bump metallization (UBM), copper terminals, vertical interconnects, or other desired structures. Parts of a semiconductor wafer can be removed using lithography, photomasks, masks, oxide or metal removal, photolithography and lithography, and microlithography. Lithography involves forming a pattern in a mask or photomask and transferring the pattern to a surface layer of the semiconductor wafer. Lithography forms the horizontal dimensions of active and passive components on the surface of a semiconductor wafer in a two-step process. First, the pattern, mask, or direct-write imaging design file on the mask is transferred to a photoresist layer. Photoresist is a photosensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs in the form of negative or positive photoresist. Second, the photoresist layer is transferred to the wafer surface. The transfer occurs when etching removes or electroplating adds a layer to the top layer of a semiconductor wafer that is not covered by photoresist. The chemical properties of the photoresist allow it to remain substantially intact and resistant to removal by chemical etching solutions, while the top layer of the semiconductor wafer, not covered by photoresist, is removed by etching or a layer is added by electroplating. The processes for forming, exposing, and removing the photoresist, as well as the processes for removing or adding a portion of the semiconductor wafer, can be modified depending on the specific photoresist used and the desired result. Negative or positive photoresists can be designed for use with solvent or alkaline developing solutions.

[0034] In negative photoresists, the photoresist is exposed to light and changes from a soluble to an insoluble state during a process called polymerization. In polymerization, the unpolymerized material is exposed to light or energy, and the polymer forms an etch-resistant cross-linked material. In most negative photoresists, the polymer is polyisoprene. Removing the soluble portion (i.e., the portion not exposed to light) with a chemical solvent or alkaline developer leaves a hole in the photoresist layer, corresponding to an opaque pattern on the photomask. A mask with a pattern in the opaque area is called a bright-field mask.

[0035] In positive photoresist, the photoresist is exposed to light and changes from a relatively insoluble state to a more soluble state in a process called photodissolution. In photodissolution, the relatively insoluble resist is exposed to appropriate light energy and converted to a more soluble state. The photodissolved portion of the resist can be removed during the development process using solvents or alkalis. Alkaline positive photoresist polymers are phenol-formaldehyde polymers, also known as phenol-formaldehyde varnish resins. Removing the soluble portion (i.e., the portion exposed to light) with chemical solvents or alkaline developers leaves a hole in the resist layer, corresponding to a transparent pattern on the photomask. A mask with a pattern in the transparent area is called a dark-field mask.

[0036] After removing the top portion of the semiconductor wafer not covered by photoresist, the remaining portion of the photoresist is removed, leaving a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material onto areas or voids formed by previous deposition / etching processes using techniques such as electroless plating and electrolytic plating.

[0037] Depositing a thin film of material over an existing pattern can expand the underlying pattern and produce an unevenly flat surface. A uniformly flat surface can be beneficial for producing smaller and denser-packed active and passive components, or is necessary for producing such active and passive components. Planarization can be used to remove material from the surface of a wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. During the polishing process, abrasive materials and corrosive chemicals are added to the surface of the wafer. Alternatively, mechanical abrasion without the use of corrosive chemicals is used for planarization. In some embodiments, purely mechanical abrasion is achieved by using a belt grinder, a standard wafer back grinder, or other similar machines. The combined mechanical action of abrasion and the corrosive effect of chemicals removes any irregular morphology, thereby producing a uniformly flat surface.

[0038] Back-end manufacturing refers to the process of dicing or partitioning finished wafers into individual semiconductor dies, and then encapsulating these dies to achieve structural support and environmental isolation. To partition semiconductor dies, the wafer is cut along non-functional areas called serrations or scribing lines. Dividing the wafer can be done using laser cutting tools, laser silicon lattice breaking processes, dry etching plasma slicing processes, or saw blades. After partitioning, individual semiconductor dies are mounted onto a packaging substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made using solder bumps, stud bumps, conductive paste, redistribution layers, or wire bonds. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, enabling the functionality of the semiconductor element to be used in other system components.

[0039] As revealed in this paper back-end manufacturing also does not simply encapsulate embedded components or semiconductor grains to achieve structural support and environmental isolation. The package described herein further provides non-single-chip electrical interconnection of the grains to achieve increased functionality and performance. Previously, almost all advanced semiconductor wafers were single-chip single-chip systems (SoCs), in which during front-end processing, all electrical interconnections occurred on silicon wafers. However, now, work traditionally belonging to the front-end domain can be carried or moved to back-end manufacturing, thereby allowing many semiconductor wafers (small wafers) to be linked together with packaging techniques to form wafer-based SoCs (which are non-monolithic) and provide composite packages with greater functionality. The small-chip approach also reduces waste due to defects and improves production efficiency, reliability and performance. The chiplet approach also allows for heterogeneous integration, where components constructed from different front-end processes can be integrated into a composite package.

[0040] Electrical Systems may be separate systems that use semiconductor components to perform one or more electrical functions. Alternatively, the electrical system may be a subcomponent of a larger system. For example, the electrical system may be part of a cellular telephone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication devices. Alternatively, the electrical system may be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. Semiconductor packages may include microprocessors, memory, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete components, or other semiconductor chips or electronic components. Miniaturization and weight reduction can be beneficial or indispensable for market acceptance of the product. The distance between semiconductor components must be reduced to achieve higher density.

[0041] Figures 1A to 1E illustrate the placement and configuration of a semiconductor die 14 , which may further be configured as an encapsulant or an embedded element 50 within a molding compound 42 . The embedded components may be semiconductor wafers 14 split from the native semiconductor wafer 10 . The embedded element 14 may be placed on a temporary carrier or substrate provided around it with an encapsulant or molding compound 42 .

[0042] Embedded elements include active elements, semiconductor dies including active surfaces formed on a first surface, semiconductor wafers or wafers, bridging wafers containing only wiring layers and no active elements, integrated passive devices (IPDs), and passive elements. When any of the exemplary embedded elements listed above are referenced in the description, it should be understood that any other embedded element may be used. Therefore, references to semiconductor die 14 include any embedded element as defined above.

[0043] Figure 1A illustrates a semiconductor wafer or semiconductor substrate 10 having a substrate material 12 (such as, but not limited to, silicon, glass, ceramic, germanium, gallium arsenide, indium phosphide, silicon carbide, or other materials) for structural support. A plurality of semiconductor grains or components 14 are formed on the wafer 10, separated by non-active inter-grain wafer regions or sawtooth 16 as described above. The sawtooth 16 provides dicing areas to divide the semiconductor wafer 10 into individual semiconductor grains 14.

[0044] Figure 1B illustrates a cross-sectional view of a portion of a semiconductor wafer 10. Each semiconductor die 14 has a back surface or back surface 18 and an active surface 20 opposite to the back surface. The active surface 20 contains analog or digital circuitry, including active elements, passive elements, conductive layers, and dielectric layers, which are formed within the die and electronically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 20 to implement analog or digital circuitry, such as DSPs, ASICs, memory, or other signal processing circuitry. The semiconductor die 14 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0045] The conductive layer or contact pad 22 is formed on the active surface 20 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 22 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), palladium (Pd), silver (Ag), or other suitable conductive materials. The conductive layer 22 operates as a contact pad or bonding pad for electrically coupling or connecting to circuits on the active surface 20. The conductive layer 22 can be formed as contact pads arranged side-by-side at a first distance from the edge of the semiconductor die 14, as shown in Figure 1B. Alternatively, the conductive layer 22 can be formed as contact pads offset in multiple rows, such that a first row of contact pads is located at a first distance from the die edge, and a second row of contact pads alternating with the first row is located at a second distance from the die edge.

[0046] Figure 1B also illustrates that the semiconductor substrate 10 and semiconductor die 14 can undergo optional polishing operations performed by a polishing machine 29 to planarize the back surface 18 and reduce the thickness of the semiconductor substrate 10 and semiconductor die 14.

[0047] Figure 1C illustrates an optional insulating or passivation layer 26 conformally applied over the active surface 20 and the conductive layer 22. The insulating layer 26 may comprise one or more layers applied using PVD, CVD, screen printing, spin coating, spraying, sintering, thermal oxidation, or other suitable processes. The insulating layer 26 may contain, but is not limited to, one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polymers, polyimide, phenylcyclobutene (BCB), polybenzo[a]benzene, etc. PBO (polyoxohydrin) or other materials with similar insulating and structural properties. Alternatively, the semiconductor die 14 is packaged without using any PBO layer, and the insulating layer 26 may be formed of different materials or omitted entirely. In another embodiment, the insulating layer 26 includes a passivation layer formed on the active surface 20 but not on the conductive layer 22. When the insulating layer 26 is present and formed on the conductive layer 22, an opening is formed to completely penetrate the insulating layer 26 to expose at least a portion of the conductive layer 22 for subsequent mechanical and electrical interconnection. Alternatively, when the insulating layer 26 is omitted, the conductive layer 22 is exposed for subsequent electrical interconnection without forming an opening.

[0048] Figure 1C shows that the electrical interconnect structure 28 can be formed as copper pillars, copper struts, or copper terminals and disposed on and coupled to or connected to the contact pad 22. The interconnect structure 28 can be formed directly on the contact pad 22 using patterning and metal deposition processes (such as printing, PVD, CVD, sputtering, electroplating, electroless plating, metal evaporation, metal sputtering) or other suitable metal deposition processes. The interconnect structure 28 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd) or other suitable conductive materials, and may include one or more UBM layers. In one embodiment, a photoresist layer can be deposited on the semiconductor die 14 and the contact pad 22. A portion of the photoresist layer can be exposed and removed by an etching and developing process. Then, a selective electroplating process can be used to form the electrical interconnect structure 28 as copper struts in the portion of the photoresist removed and on the contact pad 22. The photoresist layer can be removed, leaving interconnect structures 28 that provide subsequent mechanical and electrical interconnections and a support relative to the active surface 20 and the insulating layer 26 (if present). Preferably, the interconnect structures 28 include a height H1 in the range of 10 micrometers (μm) to 100 μm, 5 μm to 50 μm, or approximately 25 μm.

[0049] Figure 1C further illustrates that an optional die attach film (DAF) 30 may be attached to the back surface 18 of the semiconductor die 14, such as for subsequent mounting on a carrier. Figure 1C also shows that before or after subsequent processing of the semiconductor dies 10 and 14, the wafer 10 may be diced into individual semiconductor dies 14 by a saw or wafer dicing tool 32 through the saw path 16.

[0050] Figure 1D illustrates a semiconductor die 14 disposed within and forming a portion thereof within a panel or embedded die panel 50. An adhesive 41 may optionally be disposed on the back surface 18 of the semiconductor die 14. The adhesive 41 may be a thermoplastic epoxy, epoxy resin, a B-stage epoxy film, an ultraviolet (UV) B-stage film having an optional acrylic polymer, or other suitable material. In one embodiment, the adhesive 41 may be disposed on the back surface 18 before or after the semiconductor die 14 is mounted onto a temporary carrier, which may be used for the formation of the embedded die panel 50. In some examples, the adhesive 41 may be the same as DAF 30. In some examples, the adhesive 41 may extend over the entire surface (or a large portion of the entire surface) of the embedded die panel 50, and in other examples may be disposed over the semiconductor die 14 rather than over the embedded die panel 50.

[0051] Semiconductor dies 14 may be separated by spaces or gaps 40, which may serve as variable regions, wiring regions, or custom routing regions ("Custom Routing Regions," CRRs) 80 (including CRRs trademarked or service-marked as "Adaptive Routing Region"™ or "ARR"™). Spaces 40 may provide areas for subsequently formed fan-out interconnect structures and variable metal fill 110, which will be described in more detail below. The size of gaps 40 includes areas sufficient for optionally mounting semiconductor elements or assemblies to be included within a final semiconductor element or package (such as a FOWLP). A portion of space 40 may be held and filled with encapsulant 42 between semiconductor dies 14, which may be deposited using paste printing, compression molding, transfer molding, liquid encapsulation molding, lamination, vacuum lamination, spin coating, or other suitable application devices. Encapsulant 42 may be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. The encapsulant 42 can be formed as a single material disposed on and around the semiconductor die 14 and the electrical interconnect structure 28. The encapsulant 42 can contact the sidewalls 39 of the electrical interconnect structure 28 and is also disposed between the interconnect structures 28.

[0052] Panel 50 may optionally undergo a curing process to cure encapsulant 42. Panel 50 may include any shape and size of footprint or form factor. In some examples, panel 50 may include a form factor similar to that of substrate 10 (such as a 300 mm semiconductor wafer) and include a circular footprint with a diameter of 300 mm. Like substrate 10, panel 50 may have any desired size or shape that can be formed from any desired size, such as circular, square (such as 600 mm × 600 mm), or rectangular.

[0053] Figure 1D also shows that panel 50 can undergo optional polishing operations performed with polisher 34 to planarize the surface and reduce the thickness of the panel. Chemical etching can also be used to remove any potential metal contamination on the encapsulant and create slight indentations in the interconnects 28 relative to the planarized encapsulant 42 in panel 50. Thus, the surface of interconnect structure 28 can be exposed relative to encapsulant 42 on the outer surface or periphery of panel 50 to provide electrical connections between semiconductor die 14 and subsequently formed interconnect structures (such as fan-out interconnect structures).

[0054] Figure 1E shows a cross-sectional view of a portion of panel 50, wherein a conductive layer 68 is patterned and deposited on encapsulant 42, interconnect 28, and seed layer 62 to form an RDL as part of an interconnect structure. The conductive layer 68 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The deposition or formation of the conductive layer 68 may use a wafer-like process that uses the seed layer 28 as part of an additive process (such as PVD, CVD, electroplating, electroless plating, or other suitable processes) performed on the molded panel. In one embodiment, the conductive layer 68 is formed on the seed layer 62 by an electroplating process using the conductive layer 62 as the plating surface. The conductive layer 68 provides electrical interconnection between the electrical interconnect structure 28 and subsequently formed bump or package interconnect structures, which provide electrical signal transmission between the semiconductor die 14 and other semiconductor dies, other components, and points outside the final semiconductor package. Conductive layer 68 further includes unique conductive patterns, traces, redistribution layers (RDLs), various shapes or features across multiple layers, including box-shaped shielding (for shielding interference and unwanted RF or EM signals), stacked interconnects of inductors with or without wiring or RDLs, conductive interconnects or studs for antennas, and power delivery and heat dissipation structures. Conductive layer 130 may also be formed on an insulating layer such as insulating layer 77 shown in Figure 4B and coupled to vias 74 (including polymer vias) formed through the insulating layer.

[0055] Figure 1E also illustrates a first shift region 90, a second shift region 100, and a variable region 80 disposed between the first shift region and the second shift region 100. Shift regions 90 and 100 may reflect shifts arising from process variations, inaccuracies, or accidental or unforeseen movements such as when placing the die 14 during pick-and-place operations, from molding or placement of the encapsulant 42, or from any other process, procedure, or factor of the die 14.

[0056] Figures 2A through 2C illustrate the following plan views, which may be plans of the semiconductor device or package 69 from Figure 1E, or of the substrate or interposer 70 as shown in Figures 3A and 3B. Figure 2A further illustrates a first shift region 90, a second shift region 100, and a variable region 80 disposed between the first and second shift regions 100. The variable region 80 may further include a wiring region 82 and a fill region 84. The wiring region 82 may be reserved for or contain traces, conductive materials, patterning materials, or unique conductive structures 68, 130. The fill region 84 may receive VMF or AMFTM 110. In some examples, the routing relief area (RRA) 86 may be an area equal to or smaller than the area of ​​the wiring region 82, such as a subset of the wiring region 82, to accommodate different amounts of shifting or rewiring, as shown, for example, in Figures 5A through 6C. In some examples, the routing relief area (RRA) 86 may be generated by grouped traces between multiple rows of positioning pads or other vertical interconnects (e.g., traces on the left 134 and right 138 in Figure 5A). The routing relief area 86 between traces 68 and 130 may become a fill area 84 and may receive a variable metal fill VMF 110. Shift areas 90 and 100 may correspond to embedded components, such as the left and right semiconductor dies 14 shown in Figure 1E and 130 shown in Figures 5A to 8H.

[0057] Figure 2B shows a close-up view or enlarged plan view of the portion of Figure 2A indicated by section line 2B.

[0058] Figure 2C illustrates a close-up view or enlarged plan view of a portion of Figure 2A indicated by section line 2C. Figure 2C also illustrates an example of VMF 110 formed by discrete portions or islands 110a separated by gaps or spaces 110b. In such examples, VMF may be non-conductive and provide, for example, structural support or filling for subsequently formed layers or other features. In other examples, VMF 110 may be formed as a solid continuous material 110c extending to a first shift region and a second shift region to form a conductive feature, the solid continuous material being connected at each end and including, for example, a power plane, a ground plane, or another desired structure.

[0059] Figure 3A illustrates a substrate or interposer 70, which may include a molded substrate 70a. This molded substrate includes top-side pads 71a and bottom-side bumps 71b, which are used for subsequent interconnections such as with other semiconductor elements, packages, semiconductor dies 14, and the substrate. Figure 3A illustrates a molded substrate 70a having a flip-chip element 14. The molded substrate 70a may have been formed or built onto a temporary carrier that is subsequently removed. Figure 3A also illustrates that the substrate 70 or molded substrate 70a may include vias 74 in the case of known construction structures and, in the case of the molded substrate 70a, vertical conductive interconnects 74a that can be coupled to a unique conductive structure 130. The substrate 70 or molded substrate 70a may include under-bump metallization (UBM) pads 75.

[0060] Figure 3B illustrates how a molded substrate 70a may be formed on or on another conventional substrate 70, such as a PCB 72, or other laminated material that may or may not contain polyimide, which will remain (permanently) attached to achieve structural support and additional connectivity to form a hybrid substrate 73.

[0061] As illustrated in Figures 3A and 3B, substrate 70, PCB 72, and hybrid substrate 73 may include a first shift region 90, a second shift region 100, and a variable region 80 disposed between the first and second shift regions 100. The variable region 80 may further include a wiring region 82 and a fill region 84. The wiring region 82 may be reserved for or contain traces, conductive materials, patterning materials, or unique conductive structures 68, 130. The fill region 84 may receive VMF or AMFTM 110. In some examples, a routing relief area (RRA) 86 may be an area equal to or smaller than the area of ​​the wiring region 82, such as a subset of the wiring region 82, to accommodate different amounts of shifting or rerouting, as shown, for example, in Figures 5A to 6C. The routing relief area 86 between traces 68, 130 may become the fill region 84 and may receive VMF 110. Multiple layers of AMF 110 (such as vertically offset or separate layers) may be formed within substrate 70, PCB 72, hybrid substrate 73, and semiconductor element or package 69, or such layers may be used for stacked or layered wiring or other packaging designs, structures, or interconnects.

[0062] Figures 4A to 4C illustrate various views of a conductive structure 130 formed as a trace or RDL, with and without metal fill 110 for structural support. Figure 4A illustrates a plan view of a first shift region 90, a second shift region 100, and a variable region 80 disposed adjacent to and between the first and second shift regions 90 and 100. The metal fill and RDL extend between the first and second shift regions. Figure 4A illustrates how the first shift region 90, the second shift region 100, and the variable region 80 can interact to facilitate the variable metal fill 110 for both the semiconductor element 69 and the substrate 70, as well as other elements such as those shown in Figures 1E to 3B.

[0063] Figure 4B shows a cross-sectional side view or section view taken from Figure 4A along section line 4B, in which the variable metal filler 110 is present. Figure 4B shows an insulating or passivating layer 77 disposed on and around the variable metal filler 110 and the conductive material 130. The insulating layer 77 may comprise one or more layers applied using PVD, CVD, screen printing, spin coating, spraying, sintering, thermal oxidation, or other suitable processes. The insulating layer 77 may contain, but is not limited to, one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymers, polyimides, BCB, PBO, molding compounds, polymer composites such as filled epoxy resins, filled epoxy acrylates, or polymers with appropriate fillers, any suitable dielectric, or other materials with similar insulating and structural properties. An insulating layer 77 may be disposed or formed over or within the first shift region 90 and the second shift region 100, and over or within the variable region 80, wherein a planar layer of conductive material or RDL 130 is formed on the insulating layer 77 and does not have valleys, grooves, ripples, or inclined upper surface profiles 78 as shown in Figure 4C, and the conductive material 130 is supported and formed on the metal filler. The lower surface of the insulating layer may contact the unique conductive pattern 130 and is located on the variable metal filler 110. The upper surface of the insulating layer 77, opposite to the lower surface of the insulating layer 77, is substantially planar, thereby minimizing morphology effects, such as for the upper RDL 130. For example, the variation in height of the upper surface of the insulating layer 77 may be less than a typical range such as 1 μm to 10 μm or less than the thickness of the insulating layer.

[0064] Figure 4C illustrates a cross-sectional side view or section view similar to Figure 4B. The difference between Figure 4C and Figure 4B is the omission of the variable metal fill 110. Due to the omission of the metal fill 110, the insulating layer 77 can be disposed or formed over the first shift region 90 and the second shift region 100, and within the variable region 80 forming valleys, grooves, or inclined upper surface profiles 78. An upper layer or RDL 130 of conductive material is shown after the valleys 78 of the insulating layer 77.

[0065] As noted above, and as shown, for example, in Figure 4C, spaces, gaps, or offsets between the variable metal fillers 110 can create uneven surfaces such as an insulating layer 77, which may include a photosensitive material, a polymeric material, or a polymeric layer "PM". Uneven surfaces can lead to breakage of the insulating layer 77, the variable metal fillers 110, and the conductive material (including RDL) 130, which can result in losses during manufacturing. Contrary to the goal of improving production yield, such defects reduce production yield. In other words, building the conductive material 130 (such as traces or RDL 130) on an uneven material layer (such as the insulating layer 77) increases the chance of RDL defects. Gaps in copper or other conductive materials or features, including gaps between traces, typically result in valleys 78 in the PM layer. More generally, uneven metal density leads to ripples 78 in the PM layer, which in turn leads to defects in the overlying layers, thereby affecting the final production yield.

[0066] The use of variable metal fill 110 solves the aforementioned problems and facilitates other design rules such as planarization or plating. Designers also use metal fill to achieve connections between dies with custom geometries. Metal fill can be used for power connections or other connections with specific geometric rules. Connections between dies are not always traces, and some connections can be filled polygons. Die displacement can occur in and around the area where the designer needs variable metal fill 110. When the designer determines the metal fill, the final location of the routing can be, and is often, unknown.

[0067] As described in more detail herein, the conductive material 130, such as the gaps between unique traces, can advantageously be filled with a unique variable metal filler 110 (including a copper plane). See, for example, Figures 5A through 6C. Certain manufacturing processes may recommend or require the variable metal filler 110 to meet metal density rules (e.g., planarization or plating). The variable metal filler 110 may contain unique or custom shapes that connect to other metal geometries. According to known process and design rules, a unique or custom shape defined in real-time or in response to displacement, labeled "Custom Shape, CS" (also known by the trademarks or service marks "Adaptive Shapes"™, "ASTM"™), will not be connected to any metal to which it is not explicitly connected. Conventionally, the variable metal filler 110 is unknown or intended for connection to unique traces, or custom traces or custom wiring (e.g., "Adaptive Routing"™ metal).

[0068] Figures 5A through 5C illustrate further views of conductive material 130 (e.g., traces) formed in variable region 80, first shift region 90, and second shift region 100. Figure 5A illustrates conductive material 130 comprising a first portion 134, a second portion, and a third portion 142. The first portion 134 is disposed in the first shift region 90, the second portion 138 is disposed in the second shift region 100, and the third portion 142 extends to and couples with the first portion 134 and the second portion 138. Figure 5A illustrates cases where there is little or no significant displacement in the first shift region 90 and the second shift region 100, allowing conductive material 130 to be formed without any changes, customizations, or adjustments compared to the original design. Figure 5A illustrates examples where any displacement is within tolerances of the design used to form subsequent features (such as conductive material 130).

[0069] Similar to Figure 5A, Figure 5B illustrates a view of conductive material 130 (e.g., traces) formed in the variable region 80, the first shift region 90, and the second shift region 100. The conductive material 130 includes a first portion 134 disposed in the first shift region 90, a second portion 138 disposed in the second shift region 100, and a third portion 142 extending to and coupled to the first and second portions 134 and 138. Figure 5B illustrates a design and structure in which significant shifts exist in the first shift region 90, the second shift region 100, or both, resulting in a third portion 142 formed with variations, customizations, or adjustments 142a compared to the original design to account for the shifts.

[0070] Similar to Figure 5B, Figure 5C illustrates a view of conductive material 130 (e.g., traces) formed in the variable region 80, the first shift region 90, and the second shift region 100. The conductive material 130 includes a first portion 134 disposed in the first shift region 90, a second portion 138 disposed in the second shift region 100, and a third portion 142 extending to and coupled to the first and second portions 134 and 138. Figure 5C illustrates a situation with even more significant displacement than shown in Figure 5B, leading to greater changes in the design and structure of the third portion 142 to include variations, customizations, or adjustments 142a compared to the original design to account for the displacement.

[0071] Figures 6A through 6C correspond to Figures 5A through 5C, respectively, and show the same structure, but with the addition of variable metal fill 110, which reduces unwanted valleys 78. Variable metal fill 110 is shown as solid 114, or without fill pattern 118, but in other examples, variable metal fill 110 may be formed with fill pattern 118, as discussed below with respect to other figures. Variable metal fill 110 may be formed in fill region 84 and wiring buffer region 86. Wiring buffer region 86 may be formed to provide space for larger or smaller variations 142a in conductive material 130. The wiring buffer region may coexist with fill region 84 when there is no displacement or before displacement occurs. The wiring buffer region filled with variation 142 may be a smaller subset of wiring region 82, which then makes room for fill region 84, in which variable metal fill 110 is deposited. In some examples, wiring buffer region 86 between traces or conductive material 130 may become fill region 84. As shown in Figure 6A, the variable metal fill 110 can be continuous, or it can be separated into individual portions or islands as shown in Figures 6B and 6C.

[0072] Figure 7A shows a plan view of a portion of the semiconductor element 69 or substrate 70. Figure 7B shows a close-up view of the portion of the semiconductor element 69 or substrate 70 shown by section line 7B in Figure 7A. Figure 7B shows an example of a filled region 84, in which a variable metal filler 110 may subsequently be formed. Figures 7C and 7D show filled regions 84 filled with variable metal filler 110. The filled region 84 may be defined by one or more regions defined by four corners or other shapes. Multiple filled regions 84 may exist, specified across the surface or horizontal plane of the semiconductor element 69 or substrate 70.

[0073] The profile of the adaptive metal-filled region 84 may be formed by one or more corners, points, curves, arcs, line segments, or any other suitable geometric or organic form. For a batch of 30 or more semiconductor elements 69 (or other similar suitable or statistically significant number), the difference between the profiles of the unique variable metal-filled regions 110 will be greater than typical manufacturer tolerances, such as greater than 30% (or other similar suitable or statistically significant number, percentage, or number or portion of standard deviation).

[0074] Figure 8A shows a plan view of a portion of the semiconductor element 69 or substrate 70. Figure 8B shows a close-up view of the portion of the semiconductor element 69 or substrate 70 shown by section line 8B in Figure 8A. Figure 8B shows an example of variable metal filler 110 formed at the edge of the semiconductor element 69 or substrate 70. Figures 8C and 8D show a fill region 84 filled with variable metal filler 110.

[0075] Figure 8C illustrates a plan view of a portion of the semiconductor element 69 or substrate 70. Figure 8D illustrates a close-up view of the portion of the semiconductor element 69 or substrate 70 shown by section line 8D in Figure 8C. Figure 8D illustrates an example of a variable metal fill 110 as pattern 118, which includes a plurality of shapes, objects, or blocks 119 formed within a fill area 84 on or above the semiconductor element 69 or substrate 70. Blocks 119, 119a, and 119b may be defined by any shape such as a square, rectangle, or any regular or irregular polygon or geometry. In some examples, the lateral offset between the conductive pattern of trace 130 and the unique variable metal fill 110 is less than 1%-50%, 10%-20%, 30%, or one standard deviation of the offset between one side of the first embedded element 14 and one side of the semiconductor element or package 69.

[0076] Figure 8E illustrates a plan view of a portion of semiconductor element 69 or substrate 70. Figure 8F illustrates a close-up view of the portion of semiconductor element 69 or substrate 70 shown by section line 8F in Figure 8E. Figure 8F illustrates an example of variable metal fill 110 as pattern 118. Pattern 118 may include a plurality of shapes, objects, or blocks 119 formed on, above, or within a fill region 84 of a layer of semiconductor element 69 or substrate 70. The pattern 118 in Figure 8F differs from the pattern in Figure 8D in that it includes shapes, objects, or blocks 119a and 119b of different sizes. Figure 8F illustrates how the fill region can be defined by placing larger shapes 119a and smaller shapes 119b adjacent to those larger shapes 119a. Although two different sizes are shown, any number of shapes or blocks 119 of different sizes can be used.

[0077] Figure 8G shows a plan view of a portion of semiconductor element 69 or substrate 70. Figure 8F shows a close-up view of the portion of semiconductor element 69 or substrate 70 shown by section line 8F in Figure 8G. Figure 8F shows an example of a variable metal fill 110 formed or as pattern 118. Pattern 118 may include multiple shapes, objects, or blocks 119 formed on, above, or within a fill region 84 of semiconductor element 69 or substrate 70. Pattern 118 further includes blocks 119 that can be defined by shape trimming, which includes starting with a block 119 having any initial shape and then modifying, adjusting, or trimming (removing a portion of it) the shape to fit the outline, shape, or profile being filled. Thus, in design space, an entire shape (such as a complete octagon containing a diameter of 50 μm) can be modified, trimmed, or cut in physical space before being formed as a trimmed element 124.

[0078] Therefore, the variable region 80 may include a unique variable metal fill 110, wherein the unique variable metal fill 110 is electrically isolated from the unique conductive pattern 130. In other examples, portions of the conductive material 130 may also include either a solid fill 114 or a patterned fill 118, which include the patterns 119, 119a, 119b, and 124 as described above. In some examples, a portion of the variable region 80 may be filled with the variable metal fill 110 using "stitching" or multiple "lines" or "sutures," connecting two objects or regions with lines or sutures of standard length, much like conventional traces of standard thickness. Stitching can create open or empty areas without metal fill placed within the metal fill region 110.

[0079] The boundary of the adaptive metal-fill region 84 may also serve as the profile of the unique non-conductive metal-fill region 110. In other examples, the total perimeter or profile (i.e., the entire metal-fill region 84) may encompass the profile of the adaptive metal-fill region. The profile may be formed by one or more corners, points, curves, arcs, line segments, or any other suitable geometric or organic form. For a batch of 30 or more semiconductor elements (or other similar suitable or statistically significant number), the variation between the profiles of the unique variable metal-fill 110 (adaptive metal-fill region / area) will be greater than typical manufacturer tolerances, such as greater than 30% (or other similar suitable or statistically significant number, percentage, or standard deviation).

[0080] Figures 9A and 9B illustrate flowcharts or wireframes of various methods that can be used to implement the cell-specific variable metal fill as described herein. The flowchart or wireframe 200 of Figure 9A includes element 202 for providing a first shift region 90 in which a first displacement is determined. Element 204 is used to provide a second shift region 100 in which a second displacement is determined. Element 206 is used to form a unique conductive structure 130 including traces to accommodate the first and second displacements, the traces including a first portion 134 within the first shift region 90 and a second portion 138 of a trace laterally offset from the first portion 134 in the second shift region 100, and a third portion 142 of the trace located in a wiring region 82 between the first and second shift regions 90 and 100. Element 208 is used to form a unique non-conductive variable metal fill 110 within the fill region 84, wherein the non-conductive metal fill 110 is electrically isolated from the unique conductive structure 130.

[0081] The method 200 for cell-specific metal fill may include forming a unique conductive pattern of trace 130 and a unique non-conductive metal fill 110, which is not electrically coupled to current and provides structural support to prevent valleys 78. Firstly, at the design stage, the designer can create a variable region 80 for the conductive material 130 (including custom or unique RDLs, traces, or wiring). The variable region 80 can handle wide traces and traces with varying widths without requiring active changes from the designer.

[0082] The custom patterning studio "CP Studio" electronic design automation (EDA) software (such as CP Studio trademarked as "AP Studio") can be used to cut all metal in the variable region 80. CP Studio can calculate or allow engineers to create custom routing regions (CCRs) for traces traversing the variable region, as well as a list of connections for the traces within them. If the ends of features do not have the same width, or if the width exceeds the threshold of a normal trace, CP Studio can create connected variable metal fill regions 110. CP Studio can pass the list of custom routing region (CRR) connections and the variable metal fill regions 110 for adjustment by the custom patterning engine "CP Engine" (including CP Engine trademarked or service-marked as "AP EngineTM"). The ends of the variable metal fills 110 can move with the shift regions 90, 100 in which they are located or associated. The points of the variable metal fills 110 between shift regions 90, 100 can remain fixed in place. Custom routing is possible. Connected fill regions 84 are filled to form variable metal fill regions 110. Unconnected fill regions 84 are filled to form variable metal fill regions 110.

[0083] The flowchart or wireframe diagram pertains to method 220 of Figure 9B, which includes element 222 for adjusting the size, shape, or both size and shape of a structure selected from one or more of conductive structure 130 and non-conductive variable metal filler 110 within the design space. Element 224 is used to reduce the space between the initial outer edge of the structure and the center of the structure by a fixed distance to form a reduced outer edge of the structure. Element 226 is used to increase the space between the reduced outer edge of the structure and the center of the structure by a fixed distance to form a new smooth or rounded outer edge of the structure.

[0084] Therefore, method 220 of Figure 9B is an example of adjusting the size, shape, or both size and shape of a structure selected from one or more of conductive material 130 (such as patterned traces) and variable metal filler 110 (which in some instances refers to the trademark or service mark "sandingTM") in the design space.

[0085] In some cases, two metal bodies, an upper body and a lower body, may be unintentionally connected in the design space by narrow strips or islets of material. In the design space, by reducing the distance between the outer edge and the center portion to more than half the total size or width of the narrow strip or islet, the size of the narrow strip or islet approaches zero, and therefore the narrow strip or islet is removed and no longer exists in the enlargement step. Thus, the upper and lower bodies may no longer be connected as intended in the design space, but can be created or constructed in real space.

[0086] In other examples, the rectangular feature can undergo a reduction step to move from an outer size to a nested inner size, which can be done by moving a point inward from the corner of the rectangular feature. In the case of an enlargement step, enlargement begins from a smaller corner to create a larger rounded corner. Thus, the new outer edge of the rectangle may be the same as the original outer edge along most of its length, but with rounded corners.

[0087] In other examples, small organic shape features with a width smaller than the reduction step cause the entire feature to be removed by approaching zero, without any points, regions, or edges to be enlarged or expanded. As the size of the reduction step has a larger magnitude, more features will be removed, erased, or "polished" away.

[0088] The advantages of the variable metal fill 110 compared to conventional custom wiring are improvements. Custom wiring is constrained by using a stitching implementation (connecting features of the same size) on the shapes in the variable region 80. Stitching limits flexibility because the ends of the shapes in the variable region 80 must be the same size, and the connections between them consist of many smaller traces (conventional custom wiring cannot route traces that do not terminate at the same width). By creating custom wiring regions, custom shapes and custom fills allow: (i) connections of features of different sizes, and (ii) structural support for lateral offset of non-conductive features (unique variable metal fill 110) and traces with a unique conductive pattern (CP), wherein the unique variable metal fill 110 is electrically isolated from the unique conductive pattern.

[0089] The variable metal fill 110 described herein can be detected in the final semiconductor device or package in a variety of ways; and these various ways include inspecting a single device or package as well as inspecting multiple semiconductor devices or packages from the same batch or group of devices. Detection can be based on: (i) observing or measuring embedded devices that are offset from the edge of the device or package but whose vias are still aligned with the interconnects of the embedded device; (ii) observing or measuring lithography misalignment that is unrelated to embedded device misalignment; and (iii) observing or measuring that the embedded device has been displaced, the pattern has been displaced accordingly, and the die displacement is greater than the gap or displacement between the inert metals between the displaced metal patterns (the unique variable metal fill 110 will be laterally offset from the unique conductive pattern of the trace), and the displacement is designed-specific and for 2μm coupling with the embedded device. The lines and 2μm pitch RDLs or traces may be on the order of approximately 2μm-100μm, 5μm-50μm, or approximately 30μm of grain shift; (iv) in a batch of 30 or more components, the fill metal pattern variation is greater than the typical manufacturer tolerance / variance, and the variation is greater than 1%-50%, 10%-20%, or 30%, and the manufacturer tolerance / variance is greater than 1 standard deviation; and (v) for a single batch and a single variable region 80 design, portions of the variable region 80 (such as the variable metal fill 110 and the conductive material 130) are present or absent (different).

[0090] Although this disclosure includes various embodiments in different forms, the specific embodiments presented should be understood as examples of the principles of the disclosed structures, elements, methods, and systems, and not as an attempt to limit the broad scope of the disclosed concepts to the illustrated embodiments. Furthermore, those skilled in the art will understand that other structures, manufacturing elements, and examples may be combined with or substituted for those provided. Where specific embodiments are referenced in the foregoing description, it should be apparent that many modifications can be made without departing from the spirit of this disclosure, and that such embodiments and implementations can also be applied to other technologies. Therefore, the subject matter of this disclosure is intended to cover all such alterations, modifications, and variations that fall within the spirit and scope of this disclosure and the knowledge of those skilled in the art. Thus, it will be apparent that various modifications and changes can be made to the invention without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0091] 10: Semiconductor wafers / semiconductor substrates

[0092] 12: Substrate Material

[0093] 14: Grain

[0094] 16: Saw track

[0095] 18: Back / Back Surface

[0096] 20: Active Surface

[0097] 22: Conductive layer or contact pad

[0098] 26: Insulation layer

[0099] 28: Interconnection Structure

[0100] 29: Grinding machine

[0101] 30: Grain attachment film or material / DAF

[0102] 32: Saw / Wafer Cutting Tool

[0103] 34: Grinding machine

[0104] 39: Sidewall

[0105] 40: Space / Gap

[0106] 41: Adhesive

[0107] 42: Encapsulating agent or molding compound

[0108] 50: Panel

[0109] 62: Seed layer

[0110] 68: Conductive layer / trace / conductive structure

[0111] 69: Semiconductor components / packages

[0112] 70: Substrate / Intermediate

[0113] 70a: Molded base plate

[0114] 71a: Top side pad of molded substrate

[0115] 71b: Bottom side protrusion of molded substrate

[0116] 72: Printed Circuit Board / PCB

[0117] 73: Hybrid substrate

[0118] 74: Through hole

[0119] 74a: Vertical conductive interconnect

[0120] 75: Under-bump metallization pad

[0121] 77: Insulation layer

[0122] 78: Valley / Trough / Sloping Upper Surface Profile

[0123] 80: Variable area

[0124] 82: Wiring Area

[0125] 84: Filled area

[0126] 86: Wiring buffer area

[0127] 90: First shift region

[0128] 100: Second shift region

[0129] 110: Variable Metal Fill / VMF

[0130] 110a: Separate part or island

[0131] 110b: gap or space

[0132] 110c: Solid Continuous Materials

[0133] 114: Solid

[0134] 118: Fill Pattern

[0135] 119, 119a, 119b: Shapes / Objects / Blocks

[0136] 130: Conductive layer / trace / conductive structure / conductive material / RDL

[0137] 134: Left side / First part

[0138] 138: Right side / Part 2

[0139] 142: Part Three

[0140] 142a: Changes, customizations, or adjustments

[0141] 200: Method

[0142] 220: Method

[0143] 202,204,206,208,222,224,226: Elements

[0144] 2B, 2C, 4B, 7B, 8B, 8D, 8F: Section lines

[0145] H1: Height of the interconnect structure

Claims

1. A method of forming an electronic product, comprising the steps of: measuring a displacement of a first embedded element in a first displacement region to determine a first displacement; measuring a displacement of a second embedded element in a second displacement region to determine a second displacement; forming a variable region between the first displacement region and the second displacement region and extending the variable region to the first displacement region and the second displacement region, the variable region further comprising a wiring region and a filling region; forming a unique conductive structure including traces to take into account the first displacement and the second displacement, the traces comprising a first portion in the first displacement region and a second portion of traces laterally offset from the first portion of the traces in the second displacement region, and a third portion of the traces located in the wiring region between the first displacement region and the second displacement region; A unique conductive variable metal filler is formed within the filling area, wherein the conductive variable metal filler includes one or more of a power plane, a ground plane, and a via, the via being electrically coupled to the unique conductive structure, and an insulating layer is formed on the unique conductive structure containing traces and on the unique conductive variable metal filler.

2. The method as claimed in claim 1, further comprising: forming a unique non-conductive variable metal filler in the filler region, wherein the unique non-conductive variable metal filler is laterally disposed between the first portion of the trace and the second portion of the trace and electrically isolated from the unique conductive structure; and forming the insulating layer on the unique non-conductive variable metal filler.

3. The method as claimed in claim 1, wherein the insulating layer further comprises: a lower surface that contacts the distinctive conductive structure containing the trace and is located above the conductive variable metal filler; and an upper surface that is opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than one thickness of the insulating layer.

4. The method as described in claim 2, wherein the non-conductive variable metal filler is formed of a patterned discontinuous material comprising the metal filler and the gaps between the blocks.

5. The method as described in claim 1, wherein the filling region extends beyond the variable region into the first shift region, the second shift region, or both.

6. The method as described in claim 2, wherein the insulating layer further comprises: a lower surface that contacts the distinctive conductive structure containing the trace and is located above the conductive variable metal filler; and an upper surface that is opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than one thickness of the insulating layer.

7. A method of forming an electronic product, comprising the steps of: setting a first displacement region therein for determining a first displacement; forming a unique conductive structure extending to the first displacement region to accommodate the first displacement; and forming a unique variable metal fill adjacent to the first displacement region, wherein the variable metal fill comprises one or more of a power plane, a ground plane, or a via.

8. The method as described in claim 7 further comprises the step of forming an insulating layer on the unique conductive structure and on the variable metal filler.

9. The method as described in claim 8, wherein the insulating layer further comprises: a lower surface that contacts the unique conductive structure and is located above the variable metal filler; and an upper surface that is opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than one thickness of the insulating layer.

10. The method as described in claim 7, wherein the variable metal filler is formed as a solid continuous material that extends to the first displacement region to form a conductive feature.

11. The method as described in claim 7, wherein the variable metal fill is formed of a patterned discontinuous material comprising the metal fill and the gaps between the blocks.

12. The method as described in claim 7, wherein the unique conductive structure is electrically coupled to a via or vertical conductive interconnect, under-bump metallization (UBM) pad, or other conductive structure.

13. The method of claim 7 further comprises the following steps: adjusting the size, shape, or both of the size and shape of one or more structures selected from the conductive structure and the variable metal filler in the design space by: reducing a space between an initial outer edge of the structure and a center of the structure by a fixed distance to form a reduced outer edge of the structure; and increasing the space between the reduced outer edge of the structure and the center of the structure by the fixed distance to form a new outer edge of the structure.

14. A method of forming an electronic product, comprising the steps of: setting a first displacement region therein in which a first displacement is to be determined; forming a unique conductive structure extending to the first displacement region to accommodate the first displacement; and forming a unique variable metal filler, wherein the variable metal filler is electrically isolated from the unique conductive structure.

15. The method as described in claim 14 further comprises the step of forming an insulating layer over the unique conductive structure and over the variable metal filler.

16. The method of claim 15, wherein the insulating layer further comprises: a lower surface that contacts the unique conductive structure and is located above the variable metal filler; and an upper surface that is opposite to the lower surface of the insulating layer, wherein the upper surface is substantially planar such that the height variation of the upper surface of the insulating layer is less than 10 μm or less than one thickness of the insulating layer.

17. The method as described in claim 14, wherein the variable metal filler is formed as a solid continuous material extending to the first displacement region to form a conductive feature.

18. The method as described in claim 14, wherein the variable metal fill is formed of a patterned discontinuous material comprising the metal fill and the gaps between the blocks.

19. The method as described in claim 14, wherein the unique conductive structure is electrically coupled to a via or vertical conductive interconnect, under-bump metallization (UBM) pad, or other conductive structure.

20. The method of claim 14 further comprises the steps of: adjusting the size, shape, or both of the size and shape of one or more structures selected from the unique conductive structure and the variable metal filler in a design space by: reducing a space between an initial outer edge of the structure and the center of the structure by a fixed distance to form a reduced outer edge of the structure; and increasing the space between the reduced outer edge of the structure and the center of the structure by the fixed distance to form a new outer edge of the structure.

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