Lateral diffused metal oxide semiconductor device

Abstract

This invention discloses a laterally diffused metal-oxide-semiconductor device, which mainly includes a first fin structure disposed on a substrate, a second fin structure disposed next to the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a vent disposed between the first gate structure and the second gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a laterally diffused metal oxide semiconductor (LDMOS) device. Prior Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in high-voltage operating environments, such as CPU power supply, power management system, DC / DC converter, and high-power or high-frequency power amplifiers, due to their high operating bandwidth and efficiency, as well as their planar structure that is easy to integrate with other integrated circuits.

[0003] Furthermore, as device dimensions continue to shrink, the development of conventional planar field-effect transistors has reached process limitations. To overcome these limitations, replacing planar transistors with non-planar transistors, such as fin field-effect transistors (FFETs), has become the mainstream development trend. Because the three-dimensional structure of fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Moreover, since fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Furthermore, the threshold voltage of the transistor can be controlled by adjusting the gate's work function.

[0004] However, with the continuous shrinking of device size, there are still many challenges in integrating existing laterally diffused metal-oxide-semiconductor devices with fin structures, such as controlling leakage current and breakdown voltage. Therefore, how to improve the existing high-voltage device architecture is an important issue today. Summary of the Invention

[0005] An embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, which mainly includes a first fin structure disposed on a substrate, a second fin structure disposed next to the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, and a vent disposed between the first gate structure and the second gate structure.

[0006] Another embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, which mainly includes a first fin structure disposed on a substrate, a second fin structure disposed next to the first fin structure, a third fin structure disposed between the first fin structure and the second fin structure, a first shallow trench isolation disposed between the first fin structure and the third fin structure, a second shallow trench isolation disposed between the second fin structure and the third fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, a third gate structure disposed on the third fin structure, and a first vent disposed between the first gate structure and the third gate structure.

[0007] Another embodiment of the present invention discloses a laterally diffused metal-oxide-semiconductor device, which mainly includes a first fin structure disposed on a substrate, a second fin structure disposed next to the first fin structure, a shallow trench isolation disposed between the first fin structure and the second fin structure, a first gate structure disposed on the first fin structure, a second gate structure disposed on the second fin structure, a third gate structure disposed on the shallow trench isolation, and a first vent disposed between the first gate structure and the third gate structure. Simple Explanation of the Diagram

[0008] Figures 1 to 4 are schematic diagrams illustrating a method for fabricating a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 5 is a top view of a laterally diffused metal-oxide-semiconductor element according to one embodiment of the present invention. Figure 6 is a top view of a laterally diffused metal-oxide-semiconductor element according to one embodiment of the present invention. Figure 7 is a cross-sectional view of a laterally diffused metal-oxide-semiconductor device fabricated along the tangent BB' in Figure 6. Figure 8 is a top view of a laterally diffused metal-oxide-semiconductor element according to one embodiment of the present invention. Figure 9 is a cross-sectional view of a laterally diffused metal-oxide-semiconductor device fabricated along the tangent CC' in Figure 8. Figure 10 is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to one embodiment of the present invention. Implementation

[0009] Please refer to Figures 1 to 4, which are schematic diagrams illustrating a method for fabricating a laterally diffused metal-oxide-semiconductor (MODS) device according to an embodiment of the present invention. Figure 1 is a top view of a laterally diffused MODS device according to an embodiment of the present invention, while Figures 2 to 4 are cross-sectional schematic diagrams illustrating the fabrication of the laterally diffused MODS device along tangent AA' in Figure 1. As shown in Figures 1 and 2, a substrate 12 is first provided, and then a plurality of fin-like structures, such as a first fin-like structure 14 and a second fin-like structure 16, are formed on the substrate 12. A first well region (e.g., P-well 18) and a second well region (e.g., N-well 20) are formed within the first fin-like structure 14 and the second fin-like structure 16. Next, a shallow trench isolation (STI) 22 is formed between the first fin-like structure 14 and the second fin-like structure 20, and the upper surface of the shallow trench isolation 22 is slightly lower than the upper surfaces of the first fin-like structure 14 and the second fin-like structure 16. The first well region (e.g., P well 18) is completely located within the first fin structure 14, while the second well region (e.g., N well 20) is located within the second fin structure 16 and the first fin structure 14. In addition, the contact shallow trench isolation 22 is completely located within the second well region (e.g., N well 20).

[0010] In this embodiment, the substrate 12 is preferably made of a semiconductor material, such as a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, and the shallow trench isolation 22 is preferably made of silicon oxide, but is not limited thereto. In addition, although the top view of Figure 1 in this embodiment shows seven first fin structures 14 and seven second fin structures 16 extending along the X direction on the substrate 12 as an example, the number of fin structures is not limited to this and can be adjusted according to process or product requirements.

[0011] According to a preferred embodiment of the present invention, the fin structure includes a first fin structure 14 and a second fin structure 16, preferably fabricated using techniques such as sidewall image transfer (SIT). The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on a substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form sidewalls on each sidewall of the patterned sacrificial layer. The patterned sacrificial layers are then removed, and an etching process is performed under the cover of the sidewalls, transferring the pattern formed by the sidewalls into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0012] In addition, the formation of the fin structure may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the first fin structure 14 and the second fin structure 16. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding first fin structure 14 and second fin structure 16. These embodiments of forming fin structures are all within the scope of this invention.

[0013] Next, a gate structure 24 is formed on the first fin structure 14, a gate structure 26 is formed on the first fin structure 14 to the left of the gate structure 24, and a gate structure 28 and a gate structure 30 are formed on the second fin structure 16. In this embodiment, the above-mentioned gate structure can be fabricated according to process requirements using a gate-first process, a gate-last process, a high-k first process, or a high-k last process after the gate process. Taking the high dielectric constant dielectric layer process in this embodiment as an example, a gate dielectric layer 32 or dielectric layer made of silicon oxide, a gate material layer 34 made of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer process. In a single etching or successive etching step, part of the gate material layer 34 and part of the gate dielectric layer 32 are removed. Then the patterned photoresist is stripped to form gate structures 24, 26, 28, and 30 on the substrate 12, which are composed of the patterned gate dielectric layer 32 and the patterned gate material layer 34.

[0014] Then, at least one sidewall 36 is formed on the sidewalls of each gate structure 24, 26, 28, and 30. A source region 38, composed of, for example, N+ regions, is formed within the first fin structure 14 on one side of the gate structure 24, and a drain region 40, composed of, for example, N+ regions, is formed within the second fin structure 16 on one side of the gate structure 28. In this embodiment, the sidewall 36 can be a single sidewall or a composite sidewall, for example, it may include a bias sidewall and a main sidewall. The bias sidewall and the main sidewall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The source region 38 and the drain region 40 may contain different dopants depending on the conductivity type of the transistor, for example, P-type dopants or N-type dopants.

[0015] As shown in Figure 3, an interlayer dielectric layer 42 is then formed on the gate structures 24, 26, 28, 30 and the shallow trench isolation 22, and a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42 and expose the gate material layer 34 made of polycrystalline silicon, so that the upper surface of each gate material layer 34 is flush with the upper surface of the interlayer dielectric layer 42. Subsequently, a metal gate replacement process is performed to convert the gate structures 24, 26, 28, 30 into metal gates. For example, a patterned mask (not shown) can be selectively formed to cover the interlayer dielectric layer 42, followed by a selective dry or wet etching process. For instance, an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) can be used to remove the gate material layer 34 and even the gate dielectric layer 32 in the gate structures 24, 26, 28, and 30 to form grooves (not shown) in the interlayer dielectric layer 42. Subsequently, a dielectric layer 44, a high dielectric constant dielectric layer 46, and a conductive layer containing at least a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in each groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 46, the U-shaped work function metal layer 48, and the low impedance metal layer 50 flush with the surface of the interlayer dielectric layer 42.

[0016] In this embodiment, the high dielectric constant dielectric layer 46 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO 4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2O 3), lanthanum oxide (La 2O 3), tantalum oxide (Ta 2O 5), yttrium oxide (Y 2O 3), zirconium oxide (ZrO 2), strontium titanate oxide (SrTiO 3), zirconium silicon oxide (ZrSiO 4), and hafnium zirconium oxide (HfZrO 4). 4) The group consisting of strontium bismuth tantalate (SrBi 2Ta 2O 9, SBT), lead zirconate titanate (PbZr xTi 1-xO 3, PZT), barium strontium titanate (Ba xSr 1-xTiO 3, BST), or combinations thereof.

[0017] The work function metal layer 48 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low impedance metal layer 50. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 50 may be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Since converting a dummy gate into a metal gate using a metal gate replacement process is a well-known technique in this field, it will not be elaborated upon here. Next, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low impedance metal layer 50 can be removed to form a groove (not shown in the figure). Then, a hard mask 52 is filled into the groove and made flush with the surface of the interlayer dielectric layer 42. The hard mask 52 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0018] Then, as shown in Figure 4, a photolithography and etching process is first performed to remove part of the interlayer dielectric layer 42 directly above the shallow trench isolation 22 to form a groove (not shown) to expose or not expose the surface of the shallow trench isolation 22. Then, one or more deposition processes are performed to form a pore 60 above the shallow trench isolation 22. More specifically, the formation of pores 60 in this stage can be achieved by first performing a flowable chemical vapor deposition (FCVD) process to conformally form a pad layer (not shown) in the groove but not filling the groove, selectively performing an etching process to remove part of the pad layer, and then performing a high-density plasma (HDP) process to form a dielectric layer such as another interlayer dielectric layer 54 to fill the groove between gate structures 24 and 28 on the pad layer and cover gate structures 24, 26, 28 and 30. By combining the FCVD process and the HDP process, the present invention can form pores 60 directly above the shallow trench isolation 22 while filling the above-mentioned grooves. In this embodiment, the interlayer dielectric layers 42 and 54 may contain the same or different materials, wherein both may contain silicon oxide such as tetraethyl orthosilicate (TES) or may contain an ultra-low dielectric constant dielectric layer, such as porous dielectric materials such as, but not limited to, silicon carbide (SiOC) or silicon hydrogen carbide (SiOCH).

[0019] A pattern transfer process is then performed, for example, by using a patterned mask to remove portions of the interlayer dielectric layers 42 and 54 adjacent to the gate structures 24, 26, 28, and 30 to form a plurality of contact holes (not shown) and expose the source region 38 and the drain region 40. Then, the desired conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization process is then performed, for example, by chemical mechanical polishing to remove some of the conductive material to form contact plugs 56 that contact and electrically connect the source region 38 and contact plugs 58 that contact and electrically connect the drain region 40. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0020] Please refer to Figures 1 and 4. Figures 1 and 4 are schematic diagrams of the structure of a laterally diffused metal-oxide-semiconductor device according to one embodiment of the present invention. Figure 1 is a top view of a laterally diffused metal-oxide-semiconductor device according to one embodiment of the present invention, while Figure 4 is a cross-sectional view of the laterally diffused metal-oxide-semiconductor device fabricated along the tangent AA' in Figure 1. As shown in Figure 4, the laterally diffused metal-oxide-semiconductor device mainly includes a first fin structure 14 and a second fin structure 16 disposed on a substrate 12, a shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, a gate structure 24 disposed on the first fin structure 14, a gate structure 28 disposed on the second fin structure 16, a source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, a drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, interlayer dielectric layers 42 and 54 surrounding the gate structure 24 and the gate structure 28, a contact plug 56 disposed on the source region 38, a contact plug 58 disposed on the drain region 40, and a vent 60 disposed directly above the shallow trench isolation 22 between the gate structure 24 and the gate structure 28. As shown in Figure 1, the first fin structure 14 and the second fin structure 16 preferably extend along a first direction, such as the X direction, to contact the plug 56, and the plug 56 and the vent 60 extend along a second direction, such as the Y direction, on the substrate 12.

[0021] In this embodiment, gate structures 24, 26, 28, and 30 are metal gates. Gate structures 26, 28, and 30 are preferably dummy gate structures, and their widths are preferably smaller than the width of gate structure 24. The vent 60 is disposed within the interlayer dielectric layer 54. It should be noted that although the top surface of the vent 60 in this embodiment is slightly lower than the top surfaces of the gate structures 24 and 28 on both sides, it is not limited to this. According to other embodiments of the present invention, the top surface of the vent 60 may be flush with or slightly higher than the top surfaces of the gate structures 24 and 28. These variations are all within the scope of the present invention.

[0022] Please refer to Figure 5, which is a top view of a laterally diffused metal-oxide-semiconductor device according to one embodiment of the present invention. As shown in Figure 5, compared to Figure 1 where the pores 60 extend along the Y direction directly above the shallow trench isolation 22 and are roughly elongated like the contact plugs 58 on both sides, the present invention can adjust the photomask pattern used in Figure 4 to first form a plurality of circular openings (not shown) when removing part of the interlayer dielectric layer 42 directly above the shallow trench isolation 22 using a photolithography and etching process. Then, the pad layer and interlayer dielectric layer 54 are filled into the openings using FCVD and HDP processes, and at the same time, pores 60, which are also roughly circular when viewed from the top, are formed directly above the shallow trench isolation 22 between the gate structures 24 and 28. In this embodiment, the position of each vent 60 in the cross-sectional direction, including parameters such as height and width, can be approximately equal to the position of each vent 60 disclosed in Figure 4. Since each vent 60 is approximately located in the middle of the fin-like structure, and even from a top-view perspective, each vent 60 can be aligned in a straight line with the fin-like structures 14 and 16 on both sides, the number of vents 60 is preferably approximately equal to the number of fin-like structures on both sides. In other words, if seven fin-like structures are provided on each side of the vent 60 in this embodiment, then seven vents 60 are preferably provided directly above the shallow trench isolation 22 between the gate structures 24 and 28.

[0023] Please refer to Figures 6 and 7. Figure 6 is a top view of a laterally diffused metal-oxide-semiconductor (MOS) element according to one embodiment of the present invention, and Figure 7 is a cross-sectional view of the MOS element fabricated along tangent BB' in Figure 6. As shown in Figures 6 and 7, compared to Figure 4 where the sidewall of the gate structure 24 or sidewall 36 on the left side of the shallow trench isolation 22 is flush with the sidewall of the first fin structure 14 below, and the sidewall of the gate structure 28 or sidewall 36 on the right side of the shallow trench isolation 22 is also flush with the sidewall of the second fin structure 16, in this embodiment, the sidewalls of the gate structures 24 and 28 on both sides of the shallow trench isolation 22 preferably are not flush with the edges of the fin structures on both sides. More specifically, the sidewall of the gate structure 24 on the left side of the shallow trench isolation 22 preferably extends slightly to the right and contacts the top surface of the shallow trench isolation 22, and similarly, the sidewall of the gate structure 28 on the right side of the shallow trench isolation 22 also extends slightly to the left and contacts the top surface of the shallow trench isolation 22.

[0024] Please refer to Figures 8 and 9. Figure 8 is a top view of a laterally diffused metal-oxide-semiconductor (MOS) element according to one embodiment of the present invention, and Figure 9 is a cross-sectional view of the MOS element fabricated along the tangent CC' in Figure 8. As shown in Figures 8 and 9, in this embodiment, another gate structure 62 can be provided between the gate structure 24 and the gate structure 28 on the third fin structure 64. A shallow trench isolation 22 is provided between the gate structure 24 and the gate structure 62, and a shallow trench isolation 22 is provided between the gate structure 28 and the gate structure 62. Vent holes 60 and 66 are respectively provided above the shallow trench isolation 22 on both sides of the gate structure 62.

[0025] In this embodiment, the gate structure 62 and the gate structures 24 and 28 on both sides are preferably manufactured in the same process and therefore preferably contain the same material, for example, all three contain metal gates. Furthermore, although the vents 60 and 66 on both sides of the gate structure 62 in this embodiment are slightly lower than the top surfaces of the gate structures 24 and 28, this is not a limitation. As in the aforementioned embodiments, the top surfaces of the vents 60 and 66 can be flush with or slightly higher than the top surfaces of the gate structures 24, 28, and 62. These variations are all within the scope of this invention. In addition, the vents 60 and 66 in Figure 8 extend along the Y direction directly above the shallow trench isolation 22 and are approximately elongated like the contact plugs 58 on both sides. However, this is not a limitation. The present invention can also form a plurality of approximately circular vents 60 and 66 on both sides of the gate structure 62 directly above the shallow trench isolation 22 from a top viewing angle, similar to the embodiment in Figure 5. These variations are all within the scope of this invention.

[0026] Please refer to Figure 10, which is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to one embodiment of the present invention. As shown in Figure 10, compared to Figures 8 and 9 where the gate structure 62 is disposed on the third fin structure 64, the present invention can also separately dispose of the gate structure 62 on the shallow trench isolation 22 when fabricating the gate structures 24, 26, 28, and 30 in Figure 2. Then, following the process of Figures 3 and 4, each gate structure 24, 26, 28, 30, and 62 is converted into a metal gate and vents 60 and 66 are formed on both sides of the gate structure 62. As in the aforementioned embodiments, although the vents 60 and 66 disposed on both sides of the gate structure 62 in this embodiment are slightly lower than the top surfaces of the gate structures 24 and 28 on both sides, it is not limited thereto. The top surfaces of each vent 60 and 66 can be flush with or slightly higher than the top surfaces of the gate structures 24, 28, and 62. These variations are all within the scope of the present invention. Furthermore, from a top view, the vents 60 and 66 on both sides of the gate structure 62 in Figure 10 can be roughly elongated or in the form of multiple circles, similar to the contact plugs 58 on both sides in the aforementioned embodiment. These variations are all within the scope of this invention.

[0027] In summary, the present invention mainly forms at least one vent directly above the shallow trench isolation between the active gate, such as the gate structure 24 in the aforementioned embodiment, and the dummy gate, such as the gate structure 28. The vent not only reduces the parasitic capacitance of the laterally diffused metal-oxide-semiconductor device, but also significantly improves the cut-off frequency (Ft) and maximum oscillation frequency (Fmax) of the device. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0028] 12: Base 14: First fin structure 16: Second fin structure 18:P Well 20:N well 22: Shallow trench isolation 24: Gate Structure 26: Gate structure 28: Gate Structure 30: Gate structure 32: Gate dielectric layer 34: Gate material layer 36: Side wall 38: Source Region 40: Dublin Region 42: Interlayer dielectric layer 44: Dielectric layer 46: High dielectric constant dielectric layer 48: Work function metal layer 50: Low-resistivity metal layer 52: Hard Mask 54: Interlayer dielectric layer 56: Contact plug 58: Contact plug 60: Stomata 62: Gate structure 64: Third fin structure 66: Stomata

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that it comprises: a first fin structure disposed on a substrate; a second fin structure disposed beside the first fin structure; a shallow trench isolation disposed between the first fin structure and the second fin structure; a first gate structure disposed on the first fin structure; a second gate structure disposed on the second fin structure; and a vent disposed between the first gate structure and the second gate structure, wherein the vent is disposed directly above the shallow trench isolation.

2. The laterally diffused metal-oxide-semiconductor device as described in claim 1, further comprising: a source region disposed on the first fin structure on one side of the first gate structure; a drain region disposed on the second fin structure on one side of the second gate structure; an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and a first contact plug disposed on the source region and a second contact plug disposed on the drain region.

3. The laterally diffused metal-oxide-semiconductor device as described in claim 2, wherein the pore is disposed within the interlayer dielectric layer.

4. The laterally diffused metal-oxide-semiconductor device as described in claim 1, wherein the width of the second gate structure is smaller than the width of the first gate structure.

5. The laterally diffused metal-oxide-semiconductor device as described in claim 1, wherein the first gate structure and the second gate structure comprise metal gates.

6. A laterally diffused metal-oxide-semiconductor device, characterized in that it comprises: a first fin structure disposed on a substrate; a second fin structure disposed beside the first fin structure; a third fin structure disposed between the first fin structure and the second fin structure; a first shallow trench isolation disposed between the first fin structure and the third fin structure; a second shallow trench isolation disposed between the second fin structure and the third fin structure; a first gate structure disposed on the first fin structure; a second gate structure disposed on the second fin structure; a third gate structure disposed on the third fin structure; and a first vent disposed between the first gate structure and the third gate structure, wherein the first vent is disposed directly above the first shallow trench isolation.

7. The laterally diffused metal-oxide-semiconductor device as described in claim 6, further comprising: a source region disposed on the first fin structure on one side of the first gate structure; a drain region disposed on the second fin structure on one side of the second gate structure; an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and a first contact plug disposed on the source region and a second contact plug disposed on the drain region.

8. The laterally diffused metal-oxide-semiconductor device as described in claim 7, wherein the first pore is disposed within the interlayer dielectric layer.

9. The laterally diffused metal-oxide-semiconductor device as described in claim 6, wherein the width of the second gate structure is smaller than the width of the first gate structure.

10. The laterally diffused metal-oxide-semiconductor device as described in claim 6, wherein the first gate structure and the second gate structure comprise metal gates.

11. The laterally diffused metal-oxide-semiconductor device as described in claim 6, further comprising a second vent disposed between the second gate structure and the third gate structure.

12. The laterally diffused metal-oxide-semiconductor device as described in claim 11, wherein the second pore is disposed directly above the second shallow trench isolation.

13. A laterally diffused metal-oxide-semiconductor device, characterized in that it comprises: a first fin structure disposed on a substrate; a second fin structure disposed beside the first fin structure; a shallow trench isolation disposed between the first fin structure and the second fin structure; a first gate structure disposed on the first fin structure; a second gate structure disposed on the second fin structure; a third gate structure disposed on the shallow trench isolation; and a first vent disposed between the first gate structure and the third gate structure, wherein the first vent is disposed directly above the shallow trench isolation.

14. The laterally diffused metal-oxide-semiconductor device as described in claim 13, further comprising: a source region disposed on the first fin structure on one side of the first gate structure; a drain region disposed on the second fin structure on one side of the second gate structure; an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and a first contact plug disposed on the source region and a second contact plug disposed on the drain region.

15. The laterally diffused metal-oxide-semiconductor device as described in claim 14, wherein the first pore is disposed within the interlayer dielectric layer.

16. The laterally diffused metal-oxide-semiconductor device as described in claim 13, wherein the width of the second gate structure is smaller than the width of the first gate structure.

17. The laterally diffused metal-oxide-semiconductor device as described in claim 13, wherein the first gate structure and the second gate structure comprise metal gates.

18. The laterally diffused metal-oxide-semiconductor device as described in claim 17 further includes a second vent disposed between the second gate structure and the third gate structure.

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