Random access memory

Abstract

A random access memory includes a write transistor whose gate is electrically connected to a write word line and whose drain is electrically connected to a write bit line; a first read transistor and a second read transistor whose gates are electrically connected to the source of the write transistor to form a storage node; their drains are electrically connected to a read bit line; their common source is electrically connected to a read word line, such that the first read transistor and the second read transistor are connected in parallel; and a capacitor is electrically connected to the storage node.

Description

Technical Field

[0001] The present invention is generally related to a random access memory (RAM), and more specifically, to a 3T1C (three transistors and one capacitor) random access memory having a metal bridging portion connecting adjacent gates and a read transistor connected in parallel. Prior Technology

[0002] Logic-compatible gain cell embedded dynamic random-access memory (eDRAM) arrays are considered an alternative to static random-access memory (SRAM) due to their advantages, including small size, non-proportional operation, low static leakage current, and dual-port functionality. However, traditional gated eDRAM implementations require increased control signals to write the full voltage level into the memory cells to reduce update frequency and access time. Therefore, their circuitry requires additional power supplies and onboard charge pumps to boost the control signals, as well as high-voltage level switching and fault tolerance. Furthermore, the sub-threshold swing (SS) of the MOSFETs used in typical eDRAMs is often above 60 mV / decade, limiting the potential for improvement in reducing the device operating voltage. This high operating voltage also results in considerable power consumption and increases the likelihood of leakage. Therefore, those skilled in the art urgently need to improve the existing gain cell embedded dynamic random-access memory architecture to overcome these shortcomings. Summary of the Invention

[0003] In view of the shortcomings of the aforementioned conventional gain cell embedded dynamic random access memory (eDRAM) designs, this invention proposes a novel circuit and layout structure for random access memory. Its key feature is the connection of two adjacent and parallel read transistors via a metal bridge, thereby increasing the read current. Furthermore, the invention uses a tunneling field-effect transistor (TFET) as the read transistor, which significantly reduces the required operating voltage, thereby reducing overall device power consumption and minimizing leakage current.

[0004] The present invention aims to provide a novel random access memory, comprising: a write transistor having a first gate, a first source, and a first drain, wherein the first gate is electrically connected to a write word line, and the first drain is electrically connected to a write bit line; a first read transistor having a second gate, a common source, and a second drain; a second read transistor having a third gate, the common source, and a third drain, wherein the third gate and the second gate are electrically connected to the first source of the write transistor, the connection point of the third gate, the second gate, and the first source is a storage node, the second drain and the third drain are electrically connected to a read bit line, and the common source is electrically connected to a read word line, such that the first read transistor and the second read transistor are connected in parallel; and a capacitor electrically connected to the storage node.

[0005] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Simple Explanation of the Diagram

[0006] This specification includes accompanying drawings, which form part of this specification, to provide the reader with a further understanding of the embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings: Figure 1 is a circuit diagram of a random access memory according to a preferred embodiment of the present invention; Figure 2 is a timing diagram of each line in the circuit of a random access memory during write and read operations according to a preferred embodiment of the present invention; Figure 3 is a circuit layout diagram of a random access memory according to an embodiment of the present invention; and Figure 4 is a circuit layout diagram of a random access memory according to another embodiment of the present invention. It should be noted that all illustrations in this specification are for illustrative purposes only. For clarity and ease of explanation, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments. Implementation

[0007] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0008] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly on" something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0009] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0010] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0011] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0012] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they explicitly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0013] First, please refer to Figure 1, which is a circuit diagram of a random access memory (RAM) according to a preferred embodiment of the present invention. The RAM of the present invention is preferably a dynamic random access memory (DRAM), such as an embedded dynamic random access memory (eDRAM), which consists of three main components: a write transistor WT, two read transistors RT1 and RT2, and a capacitor C. These constitute the 3T1C (three transistors and one memory cell) RAM architecture of the present invention. In terms of connection, the two read transistors RT1 and RT2 are connected in parallel, serving as the read device RT of the present invention. One end of each transistor has a common source SC connected to a read word line RWL, and the other end has a second drain D2 and a third drain D3 respectively connected to a read bit line RBL. The gates G2 and G3 of the read transistors RT1 and RT2 are interconnected through a bridging device. Due to the parallel design of the two read transistors RT1 and RT2, a higher read current can be generated during read operation, improving read performance. Furthermore, in this embodiment of the invention, the read transistors RT1 and RT2 are preferably tunneling field-effect transistors (TFETs), whose low sub-threshold swing (SS) characteristics result in a lower required gate operating voltage, faster switching speed, and can significantly reduce the overall energy consumption during device operation while also reducing leakage current.

[0014] Referring again to Figure 1, the write transistor WT of this invention can be a common MOSFET. Its first drain D1 is connected to a write bit line WBL, and its first source S1 is connected to the gates G2 and G3 of the read transistors RT1 and RT2. The connection point between the first source S1 and the gates G2 and G3 is the storage node SN of the random access memory of this invention, which is connected to a capacitor C. The gate G1 of the write transistor WT is connected to a write word line WWL. The write transistor WT, the first read transistor RT1, and the second read transistor RT2 together constitute a memory cell in the random access memory.

[0015] Please refer to Figure 2, which shows the timing diagram of each line in the circuit of a random access memory (RAM) during write and read operations according to a preferred embodiment of the present invention. The operation can also be understood by referring to the circuit diagram in Figure 1. In the operation of writing a high-order logic state "1" to the RAM of the present invention, a high-potential signal is applied from the write word line WWL to the gate G1 of the write transistor WT to open the channel of the write transistor WT (from the first drain D1 to the first source S1). Then, a write potential signal is applied from the write bit line WBL through the opened write transistor WT channel to the storage node SN, causing the storage state at the storage node SN (capacitor C) to become a high-order logic state "1". At this time, both the read word line RWL and the read bit line RBL maintain their pre-charge voltage levels unchanged. The low-order logic state "0" can also be written in the same way, the only difference being that the write potential signal applied to the write bit line WBL is at a negative level.

[0016] Referring again to Figure 2. After writing the high-order logic state, the register needs a holding period to stabilize its signal value to ensure that the temporary value passed to the next level is correct. After the signal stabilizes, during the read operation of the random access memory, an overdrive voltage (the precharge voltage becomes a low-level voltage) is applied from the read word line RWL to the read transistors RT1 and RT2. This causes the read bit line RBL to discharge and drop, thus determining the resistance value at the channel of transistors RT1 and RT2, and consequently the voltage level at the gate switches of read transistors RT1 and RT2, i.e., the storage state of the connected storage node SN. The low-order logic state "0" can also be read in the same way, except that when in the low-order logic state, the overdrive of the read word line RWL will cause the read bit line RBL to rise in reverse.

[0017] Please now refer to Figure 3, which is a circuit layout diagram of a random access memory (RAM) according to an embodiment of the present invention. The connection method can also be understood by referring to the circuit diagram in Figure 1. The layout structure of the RAM of the present invention includes a substrate (i.e., the blank area in the figure). The substrate material can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc., and is not limited thereto. Multiple doped regions, gates, contacts, and metal layers are generally formed on the substrate. The doped regions can be conductive regions formed by doping impurities into the semiconductor substrate through an ion-doping process. These regions can serve as the source and drain of devices. These doped regions can also be formed in fin structures pre-formed on the substrate to fabricate fin field-effect transistors (FinFETs). The gates can be polycrystalline silicon strip structures formed on the substrate. Generally, all gates extend towards a first direction D1 and are equally spaced along a second direction D2 orthogonal to the first direction D1. They can serve as the gates of devices and connect different devices. Contacts can be vertical pillars made of metals such as tungsten or titanium nitride, and are mostly located on doped regions or gates to connect these parts to the upper metal layer. The metal layer can be a metal pattern formed by copper wires, which constitutes the semiconductor back-end interconnect structure and connects various components on the substrate.

[0018] Referring again to Figure 3. The following component description will use a memory cell (bit cell) BC of the present invention as an example. In a preferred embodiment of the present invention, a first gate G1 is located on the substrate and extends in a first direction D1. A first source S1 and a first drain D1 are respectively located in the substrate on both sides of the first gate G1, such that the first gate G1, the first source S1, and the first drain D1 constitute a write transistor WT, wherein the first gate G1 serves as the gate of the write transistor WT, and its upper part is connected to a write word line (i.e., the write word line WWL shown in Figure 1) through a contact CWWL, and the upper part of the first drain D1 is connected to a write bit line (i.e., the write bit line WBL shown in Figure 1) through a contact CWBL. A second gate G2 is located on the substrate, preferably adjacent to the first gate G1 and aligned with the first gate G1 in the first direction D1. A common source SC and a second drain D2 are located in the substrate on both sides of the second gate G2. Thus, the second gate G2, the common source SC and the second drain D2 constitute a first read transistor RT1, wherein the second gate G2 serves as the gate of the first read transistor RT1. The second drain D2 is connected to a read bit line (i.e., the read bit line RBL shown in Figure 1) through a contact CRBL above it, and the common source SC is connected to a read word line (i.e., the read word line RWL shown in Figure 1) through a contact CRWL above it.

[0019] Referring again to Figure 3, a third gate G3 is located on the substrate, preferably adjacent to the first gate G1 and the second gate G2 in the second direction D2. The third gate G3 has a third drain D3 on one side and a common source SC shared with the first read transistor RT1 on the other. Thus, the third gate G3, the common source SC, and the third drain D3 constitute a second read transistor RT2, where the third gate G3 serves as the gate of the second read transistor RT2. The third drain D3 is connected to a read bit line (i.e., the read bit line RBL shown in Figure 1) via a contact CRBL. The second drain D2 and the third drain D3 are connected to the same read bit line. The common source SC is connected to a read word line (i.e., the read word line RWL shown in Figure 1) via a contact CRWL. Thus, the first read transistor RT1 and the second read transistor RT2 are connected in parallel, jointly serving as the read device RT of this invention, which can improve read current and performance. Furthermore, in the design where the first read transistor RT1 and the second read transistor RT2 are tunneling transistors (TFETs), the common source SC is preferably a heavily P-type doped (P+) region, and the second drain D2 and the third drain D3 are preferably heavily N-type doped (N+) regions.

[0020] Referring again to Figure 3, it should be noted that in this embodiment of the invention, the third gate G3 of the second read transistor RT2 extends along the first direction D1 to the first source S1 of the write transistor WT and is connected thereto. The connection point between the first source S1 and the third gate G3 is the storage node SN of the random access memory of this invention. Above the third gate G3, a capacitor (i.e., the capacitor C shown in Figure 1) is connected via a contact CC. Thus, the voltage applied from the first drain D1 determines the storage state of the storage node SN and affects the channel resistance of the first read transistor RT1 and the second read transistor RT2. Furthermore, in this embodiment of the invention, the second gate G2 and the third gate G3 are electrically connected to each other through a metal bridge 100. Preferably, the metal bridge 100 is located at one end of the second gate G2 and the third gate G3 along the first direction D1 and extends along the second direction D2 to connect the second gate G2 and the third gate G3. Thus, as shown in the figure, the second gate G2, the third gate G3, and the metal bridging portion 100 form a J-shaped layout pattern on the base plane when viewed from the top.

[0021] Please refer to Figure 4, which is a circuit layout diagram of a random access memory according to another embodiment of the present invention. The circuit layout of this embodiment is similar to that shown in Figure 3, except that the metal bridging portion 100 connects the middle section of the third gate G3 and the other end of the second gate G2 in the first direction D1, and is preferably located between the first gate G1 and the second gate G2. Thus, from a top view, the second gate G2, the third gate G3, and the metal bridging portion 100 form an h-shaped layout pattern on the base plane from a top view. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0022] 100: Metal bridging section C: Capacitor CC: Contact CRBL: Contact element CRWL: Contact element CWBL: Contact element CWWL: Contact D1: First Direction D2: Second Direction D1: First Drain D2: Second Absorption Pole D3: Third Water Pole G1: First gate G2: Second gate G3: Third gate RBL: Read Bit Line RWL: Read character lines RT1: (First) Reading transistor RT2: (Second) Reading transistor S1: First Source SC: Common Source SN: Storage Node WBL: Write Bit Line WT: Written Transistor WWL: Write character line

Claims

1. A random access memory (RAM) comprising: a write transistor having a first gate, a first source, and a first drain, wherein the first gate is electrically connected to a write word line, and the first drain is electrically connected to a write bit line; a first read transistor having a second gate, a common source, and a second drain; a second read transistor having a third gate, the common source, and a third drain, wherein the third gate and the second gate are electrically connected to the first source of the write transistor, the junction of the third gate, the second gate, and the first source constitutes a storage node, the second drain and the third drain are electrically connected to a read bit line, and the common source is electrically connected to a read word line, such that the first read transistor and the second read transistor are connected in parallel; and a capacitor electrically connected to the storage node.

2. The random access memory as described in claim 1 further includes a substrate, wherein the first gate, the second gate, and the third gate are located on the substrate and extend in a first direction, the first gate, the second gate, and the third gate are adjacent to each other, and a metal bridge electrically connects the second gate and the third gate, the first source and the first drain are respectively located in the substrate on both sides of the first gate, the common source and the second drain are respectively located in the substrate on both sides of the second gate, and the common source and the third drain are respectively located in the substrate on both sides of the third gate.

3. The random access memory as described in claim 1, wherein the write operation of the random access memory comprises: applying a high potential signal from the write word line to enable the write transistor; applying a write potential signal from the write bit line through the enabled write transistor to the storage node, such that the storage state of the storage node becomes a high state.

4. The random access memory as described in claim 1, wherein the read operation of the random access memory includes: applying a low-level overdrive voltage to the read word line to discharge and reduce voltage at one end of the read word line; and determining the storage state of the storage node by detecting the voltage drop at one end of the read word line.

5. The random access memory as described in claim 2, wherein the second gate is adjacent to and aligned with the first gate in the first direction.

6. The random access memory as described in claim 2, wherein the third gate is adjacent to the first gate and the second gate in a second direction, and the third gate extends in the first direction to overlap with the first gate and the second gate, the second direction being orthogonal to the first direction.

7. The random access memory as described in claim 6, wherein the metal bridging portion extends in the second direction above the second gate and the third gate to electrically connect the second gate and the third gate.

8. The random access memory as described in claim 7, wherein the second gate and the third gate are aligned at one end in the first direction, and the metal bridge is electrically connected to the second gate and the third gate at that end, such that the second gate, the third gate and the metal bridge appear J-shaped when viewed from a top view.

9. The random access memory as described in claim 7, wherein the second gate and the third gate are aligned at one end in the first direction, and the metal bridge is electrically connected to the other end of the second gate and the middle section of the third gate, such that the second gate, the third gate and the metal bridge form an h-shape when viewed from a top view.

10. The random access memory as described in claim 2, wherein the third gate extends in the first direction to the first source of the write transistor.

11. The random access memory as described in claim 2, wherein the first drain of the write transistor and the second drain of the first read transistor are aligned in a first direction, and the first source of the write transistor is aligned in the first direction with the common source of the first read transistor and the second read transistor.

12. The random access memory as described in claim 1, wherein the write transistor, the first read transistor, and the second read transistor constitute a memory cell.

13. The random access memory as described in claim 1, wherein the write transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET), and the first read transistor and the second read transistor are tunneling transistors (TFETs).

14. The random access memory as described in claim 13, wherein the common source is a P-type doped region and the second drain and the third drain are N-type doped regions.

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