Precision multi-axis photolithography alignment correction using stressor film

Abstract

Embodiments of this disclosure provide a method for improving the overlay alignment of patterned wafers by correcting wafer shape. For example, the method may include receiving a wafer having a working surface and a back surface, the working surface having at least partially processed semiconductor devices, the back surface being relative to the working surface. The method may also include forming a first stress source film on the back surface. The first stress source film can correct the overlay alignment of the working surface in a first direction traversing the working surface of the wafer. The method may also include forming one or more first semiconductor structures on the working surface of the wafer. These first semiconductor structures are aligned in the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor processing, and in particular to wafer bending, warping, and overall wafer shape. [References merged]

[0002] This disclosure claims priority to U.S. Provisional Application No. 63 / 281,431, "Precision Multi-Axis Photolithography Alignment Correction Using Stressor Film" (filed November 19, 2021) and U.S. Non-Provisional Application No. 17 / 888,553, "Precision Multi-Axis Photolithography Alignment Correction Using Stressor Film" (filed August 16, 2022), the entire contents of which are incorporated herein by reference. Prior Technology

[0003] The prior art description provided herein is for the purpose of providing a general overview of the background of this disclosure. Descriptions of the work of currently listed inventors in this prior art section, and descriptions of embodiments that cannot otherwise be considered prior art at the time of application, are not expressly or impliedly acknowledged as prior art to this disclosure.

[0004] Semiconductor fabrication involves a wide variety of steps and procedures. A typical process is called photolithography (also known as microlithography). In semiconductor device design, photolithography uses radiation such as ultraviolet or visible light to create fine patterns. Semiconductor fabrication techniques, including photolithography, etching, film deposition, surface cleaning, metallization, and more, can be used to manufacture many types of semiconductor devices, such as diodes, transistors, and integrated circuits.

[0005] An exposure system (also known as a tool) is used to implement photolithography. An exposure system generally includes: an illumination system; a reticle (also known as a photomask) or spatial light modulator (SLM) for generating a circuit pattern; a projection system; and a wafer alignment stage for aligning a semiconductor wafer already coated with photosensitive photoresist. The illumination system illuminates an area of ​​the reticle or SLM with a (preferably) rectangular trench illumination field. The projection system projects an image of the illuminated area of ​​the reticle pattern onto the wafer. For accurate projection, it is important to expose the photolithography pattern on a relatively flat or planar wafer (preferably with a height deviation of less than 10 micrometers). Summary of the Invention

[0006] Embodiments of this disclosure provide a method for improving the overlay alignment of patterned wafers by correcting wafer shape. For example, the method may include receiving a wafer having a working surface and a back surface, the working surface having at least partially processed semiconductor devices, the back surface being relative to the working surface. The method may also include forming a first stress source film on the back surface. The first stress source film corrects the overlay alignment of the working surface in a first direction traversing the working surface of the wafer, but not in a second direction traversing the working surface of the wafer. The second direction is different from the first direction. The method may also include forming one or more first semiconductor structures on the working surface of the wafer. These first semiconductor structures are aligned in the first direction.

[0007] In one embodiment, the second direction may be rotated at least 15 degrees relative to the first direction. For example, the second direction may be rotated 45 degrees relative to the first direction. As another example, the second direction may be orthogonal to the first direction.

[0008] In one embodiment, the method may further include, after forming the first semiconductor structures on the working surface of the wafer, forming a second stress source film on the back side surface, the second stress source film correcting the superposition alignment of the working surfaces in the second direction across the working surface of the wafer; and forming one or more second semiconductor structures on the working surface of the wafer, the second semiconductor structures being aligned in the second direction. In another embodiment, the method may further include, after forming the first semiconductor structures on the working surface of the wafer, forming a second stress source film on the back side surface, the second stress source film correcting the superposition alignment of the working surfaces in the second direction across the working surface of the wafer; and correcting the first semiconductor structures on the working surface of the wafer, the corrected first semiconductor structures being aligned in the second direction. In yet another embodiment, the method may further include forming a second stress source film on the back surface before forming the first semiconductor structures on the working surface of the wafer, the second stress source film correcting the superposition alignment of the working surfaces in the second direction traversing the working surface of the wafer; and correcting the first semiconductor structures on the working surface of the wafer after forming the first semiconductor structures, the corrected first semiconductor structures being aligned in the second direction. For example, the first stress source film and the second stress source film are formed in a litho-etch-litho-etch (LELE) process or a litho-freeze-litho-etch (LFLE) process.

[0009] In one embodiment, the first stress source film may be patterned based on a warpage measurement of the wafer in the first direction. For example, the first stress source film may be patterned using direct-write patterning.

[0010] Embodiments of this disclosure also provide another method for improving the overlay alignment of patterned wafers by correcting wafer shape. For example, the method may include receiving a wafer having a working surface and a back surface, the working surface having at least partially processed semiconductor devices, the back surface being relative to the working surface. The method may also include forming a stress-source film on the back surface. The stress-source film can correct the overlay alignment of the working surface in first and second directions traversing the working surface of the wafer. The method may also include forming one or more semiconductor structures on the working surface of the wafer. These semiconductor structures are aligned in the first and second directions.

[0011] In one embodiment, the stress source film may be patterned based on warpage measurements of the wafer in the first and second directions. In another embodiment, the stress source film may be patterned based on α times the warpage measurement of the wafer in the first direction and (1-α) times the warpage measurement of the wafer in the second direction, where 0 ≤ α ≤ 1. For example, α is ½.

[0012] We note that this summary paragraph does not specifically describe every embodiment of the present disclosure or the claimed invention and / or any additional novel embodiments. Rather, this summary provides only a preliminary discussion of different embodiments and corresponding novelty over the prior art. For additional details and / or feasible embodiments of the present disclosure and its embodiments, the reader may turn their attention to the implementation paragraphs of the present disclosure and the corresponding figures, as further discussed below. Simple Explanation of the Diagram

[0013] Various embodiments of the disclosure presented as examples will be described in detail with reference to the following figures, wherein similar symbols refer to similar elements, and wherein:

[0014] Figure 1 shows the alignment tree prepared before creating the photomask;

[0015] Figures 2A to 2D show an example of superimposed patterning error;

[0016] Figure 3A illustrates the alignment of two layers without wafer stress correction;

[0017] According to certain embodiments of this disclosure, FIG3B illustrates the alignment of two layers having wafer stress correction in the X direction;

[0018] According to certain embodiments of this disclosure, FIG3C illustrates further alignment of the layers shown in FIG3B with wafer stress correction in the Y direction;

[0019] According to certain embodiments of this disclosure, Figure 4 is a flowchart illustrating an exemplary method for improving the overlay alignment of patterned wafers by correcting wafer shapes in two directions;

[0020] According to certain embodiments of this disclosure, Figures 5A to 5D illustrate the correction of the superposition alignment of the working surfaces of the wafer in the first direction;

[0021] According to certain embodiments of this disclosure, Figures 6A to 6D illustrate a modified superposition alignment of the working surfaces of the wafers shown in Figures 5A to 5D in a second direction;

[0022] According to certain embodiments of this disclosure, Figures 7A to 7D illustrate the litho-etch-litho-etch (LELE) process used;

[0023] According to certain embodiments of this disclosure, Figures 8A to 8D illustrate the litho-freeze-litho-etch (LFLE) procedure used;

[0024] According to certain embodiments of this disclosure, Figures 9A to 9C illustrate the correction of wafer warpage and bending only in the X direction;

[0025] According to certain embodiments of this disclosure, Figures 10A to 10C illustrate the correction of wafer warpage and bending only in the Y direction;

[0026] According to certain embodiments of this disclosure, FIG11 is a flowchart illustrating an exemplary method for improving the overlay alignment of patterned wafers by correcting the wafer shape on a single axis;

[0027] According to certain embodiments of this disclosure, Figures 12A to 12D illustrate exemplary results of average X and Y correction; and

[0028] According to certain embodiments of this disclosure, FIG13 is a flowchart illustrating an exemplary method for improving the overlay alignment of patterned wafers by correcting wafer shape. Implementation

[0029] Semiconductor fabrication advancements currently incorporate technologies such as advanced patterning and 3D device structures to reduce feature size and increase device density. However, the implementation of these technologies has presented new challenges to successful micromachining. These new processing methods involve creating multiple layers of various materials on the wafer surface. However, each layer adds additional stress to the wafer surface. As the layers accumulate, the resulting stress distorts the wafer's flatness. This distortion has been shown to reduce the dimensional uniformity of critical features across the wafer surface.

[0030] This distortion can also cause overlay errors and challenges. Various processing steps can cause the substrate to expand and / or contract, resulting in a distorted or warped substrate. For example, during exposure, the substrate is locally heated due to the energy transferred from the exposure beam. The substrate is also heated during the annealing process. This heating causes the substrate to expand. If the expansion is not contained, it will exceed the overlay error tolerance. Furthermore, if the clamping force between the substrate and the substrate chuck is insufficient to prevent expansion, the substrate may slide on the chuck, resulting in greater expansion and larger overlay errors. In some processes, such as in extreme ultraviolet (EUV) systems, sliding may be more pronounced because the environment surrounding the substrate during exposure is a vacuum. Therefore, vacuum clamping is not always feasible, and a weaker electrostatic clamp must be used instead.

[0031] Other processing steps can also cause substrate expansion and contraction. For example, the deposited film may cause substrate shrinkage. Furthermore, various annealing and doping steps can introduce significant warpage within a given substrate. Annealing, in particular, can pose stacking challenges. The result of these various processing steps is a non-planar or non-flat substrate. For example, the back side of the substrate may have z-height variation (i.e., variation in vertical height), with both high and low points. This z-height variation caused by warpage can range from approximately one micrometer to approximately 100 micrometers. Since semiconductor devices or structures being exposed using various exposure tools are being exposed on a scale of tens to hundreds of nanometers, this fluctuation is significant. Therefore, warpage variations ranging from thousands to 10,000 nanometers can drastically reduce yield.

[0032] Figure 1 shows an alignment tree 100 prepared before photomask fabrication. In the alignment tree 100, layer L7 is aligned using the alignment marks of layer L1, and layers L11 and L12 are aligned using the alignment marks of layer L7. Layer L7 is directly aligned with layer L1, while layers L11 and L12 are indirectly aligned with layer L1. Layers L1, L7, L11, and L12 can be transistors, fins, metal layers, masks, or any other sacrificial or final structures formed on the wafer during micromachining. Walkouts of successive layers may occur. Due to unavoidable stresses induced on the layers during the micromachining process, successive layers may gradually become misaligned with each other and with the starting layer.

[0033] Microfabrication causes stress on the wafer due to various material deposition, removal, annealing, etching, etc. Because of the processing stress on the wafer, some possible wafer warpages exhibit Zernike polynomials, including vertical tile, horizontal tilt, oblique astigmatism, defocus, etc. Figures 2A to 2D show an example of superimposed patterning errors. Many different forms of wafer warpage and bending exist. This particular example shows oblique astigmatism, resulting in varying degrees of misalignment of layer L11 in both the X and Y directions (dashed lines indicate where layer L11 is intended to be placed, and solid lines indicate where layer L11 is actually placed due to wafer warpage).

[0034] Conventional techniques for addressing substrate warpage and non-flat bending on partially treated substrates focus on clamping (or gripping / adhesive) the substrate to a substrate holder to flatten the bending. However, for relatively significant warpage, it may be extremely difficult or impossible to accurately flatten the substrate solely through clamping. Therefore, a substrate warpage correction technique is desired to correct substrate warpage and improve overlay before transfer or return to the scanner for additional exposure.

[0035] To more accurately print patterns on wafers, the present technique includes methods for improving the overlay alignment of patterning by correcting wafer shape or wafer warpage and bending. The technique includes single-axis or single-direction alignment or correction, followed by secondary alignment or correction along different axes or directions. This progressive multi-axis correction provides higher accuracy compared to simultaneously correcting warpage in all directions. Therefore, the technique progressively or continuously corrects alignment in individual directions. The technique also includes correction in one direction without correction in another direction (generally orthogonal).

[0036] The technique disclosed herein involves using stress source films on the back surface of a wafer. Some embodiments use direct-write laser processing only to correct stress values ​​for optimal wafer shape using wafer shape correction tools. These stress correction tools are used to correct wafer shape (wafer warpage, wafer bending) and improve overlay. One technique involves depositing one or more stress source films on the back surface of a wafer. These stress source films may have different initial internal stresses. The stress source films can be patterned and then etched to selectively increase / decrease stress at predetermined points across the back surface, thereby correcting the wafer shape and improving overlay values. Patterning can be performed using direct-write laser exposure. Direct-write patterning is advantageous because patterns can be generated based on wafer shape characteristics or wafer warpage measurements using software and laser intensity control at various coordinate locations on the wafer. Therefore, the exposure pattern can be easily changed between wafers. Mask-based exposure is also considered. As an option, a predetermined stress source film can be removed from a selected area on the back surface. The stress source film can be reset and held in place or removed. The stress source film can be a single layer or N layers. The stress source film can be corrected between the X and Y directions, or subjected to multi-axis optical lithography alignment correction.

[0037] Figure 3A illustrates the alignment of layer L2 and layer L1 without wafer stress correction. Note that misalignment exists in the X and Y directions. This is a problem to be solved. Figure 3B illustrates the alignment of layer L2 and layer L1 with wafer stress correction in the X direction according to this disclosure. Note that layer L2 is correctly aligned with layer L1 in the X direction, but is still misaligned with layer L1 in the Y direction. Figure 3C illustrates a further alignment of layer L2 and layer L1 with wafer stress correction in the Y direction according to this disclosure. Note that layer L2 is also aligned with layer L1 in the Y direction. The X and Y directions extend across the working surface of the wafer and are orthogonal to each other. Therefore, wafer stress is corrected and layer L2 and layer L1 are aligned in two stages.

[0038] The technology disclosed here uses back-side membrane stress correction and novel lithography integration.

[0039] According to certain embodiments of this disclosure, Figure 4 is a flowchart illustrating an exemplary method 400 for improving the overlay alignment of patterned wafers by correcting wafer shapes on two different axes. For example, method 400 can correct wafer warpage and bending in two or more independent directions to more accurately print patterns on the wafer. Therefore, two masks can be used. However, an additional masking layer can be integrated with a back-side stress source film using a wafer shape correction tool. In one embodiment, the two or more independent directions may include the X and Y directions. In another embodiment, the two or more independent directions may include a first direction and a second direction rotated at least 15 degrees (e.g., 45 degrees) relative to the first direction.

[0040] Generally, one or more stress source films can be deposited on the back surface of a wafer, which is relative to the working surface where active components are disposed. A photoresist film can then be deposited on the back surface and patterned. Patterning can be performed via a photomask and a scanner, but it is preferable to perform patterning using direct-write laser exposure. Direct-write is preferred because the exposure pattern can be modified or customized for each individual wafer. For example, the shape of each wafer can be measured to generate wafer warpage measurements. Wafer warpage measurements can be, for example, a graph of relative z-height variation across the wafer or other superimposed misalignment measurements. After patterning and developing the photoresist formed on the back surface, one or more stress source films can be etched. This corrects the internal stress of the wafer, thereby producing a modified wafer shape, which, for example, improves superposition or flattens the wafer. The stress source films can have initial internal stresses that can be tensile or compressive. Selectively removing material from coordinate locations correspondingly corrects the internal stress of the wafer.

[0041] Additional back-side film correction techniques are employed to induce / correct stress, such as epoxy films having internal stresses that change in response to a light pattern corresponding to a specific location on the epoxy film. Therefore, stress correction can be performed without etching. Thus, the stress source film referred to herein is any film formed on the back surface of a wafer and processed to induce stress correction on the wafer. This may include depositing one (or more) stress source films (e.g., silicon oxide or silicon nitride films), coating the stress source film with a photoresist layer, exposing (e.g., direct writing) and developing the photoresist layer, etching the stress source film, and removing the photoresist layer. Patterning on the working surface of the wafer can then proceed. Progressive overlay correction has been found to offer significant advantages in this technique. One finding is that correcting alignment in one direction at a time provides higher accuracy compared to correcting warp in all directions simultaneously. Therefore, this technique progressively or continuously corrects alignment in individual directions. The technique also includes correcting in one direction without correcting in another direction (generally orthogonal).

[0042] Method 400 begins at step S410, in which a wafer is received having a back surface and a working surface relative to the back surface. The working surface may have at least partially processed means, one or more of which may cause a certain degree of wafer warping. For example, as shown in Figures 5A and 5B, layers L1 and L7 are formed on the working surface of the wafer. It is desirable to add layer L11 at a specified location (shown by dashed lines), which is spaced apart from layers L1 and L7 or aligned regardless of the alignment of layers L1 and L7.

[0043] In step S420, a first stress source film 510, as shown in Figures 5A and 5B, is deposited and formed on the back surface of the wafer. In one embodiment, the first stress source film 510 is used to correct the superposition alignment of the wafer's working surfaces in a first direction (e.g., the X direction) across the working surfaces of the wafer, while having no stress correction in the Y direction. Therefore, the first stress source film 510 targets superposition alignment correction in one direction (e.g., the X direction) and not in another direction (e.g., the Y direction). For example, a wafer having layers L1 and L7 formed on its working surfaces can be measured to identify the wafer's X-direction warpage measurement, and the first stress source film 510 can have an X-direction internal stress corrected based on the X-direction warpage measurement. In one embodiment, a photoresist layer is coated onto the first stress source film 510. The photoresist layer is patterned to correspond to the X-direction warpage measurement and developed. The first stress source film 510 is etched using dry or wet etching, and then the photoresist layer is removed. This corrects the internal stress of the first stress source film 510 to correspond to the X-direction warpage measurement of the wafer, thus making the wafer nearly flat or considered flat in the X-direction. In another embodiment, the first stress source film 510 is thermally responsive, causing the applied heat to alter its internal stress. A thermal pattern can be applied to the first stress source film 510, the thermal pattern corresponding to the X-direction warpage measurement. In some other embodiments, the first stress source film 510 is responsive to a first light wavelength, wherein exposure to the first light wavelength alters its internal stress, and a pattern of the first light wavelength can be generated to expose the first stress source film 510, the pattern of the first light wavelength corresponding to the X-direction warpage measurement. The first stress source film 510 thus formed is used to correct the superposition alignment in the first direction (i.e., the X direction) and does not include substantial or significant superposition alignment in the second direction (e.g., the Y direction), which is different from or orthogonal to the first direction.

[0044] Next, a photoresist layer L11x can be formed on the working surface of the wafer and aligned with layer L1 in the X direction. The photoresist layer L11x can be patterned, exposed, and developed in a lithography process to form a hard mask L11x1, as shown in Figures 5C and 5D, and the wafer can be etched accordingly. Note that the hard mask L11x1 is formed and placed between layers L1, and no alignment correction is performed in the Y direction. Therefore, the hard mask L11x1 covers a portion of layer L7. This may be acceptable depending on the etching selectivity and patterning target. The hard mask L11x1 is aligned in the X direction, i.e., it does not overlap with layer L1.

[0045] In step S430, a second stress source film 610, as shown in Figures 6A and 6B, is deposited and formed on the back surface of the wafer. In one embodiment, the second stress source film 610 is used to correct the superposition alignment of the wafer's working surfaces in a second direction (e.g., the Y direction) across the working surfaces of the wafer, without any stress correction in the X direction. Therefore, the second stress source film 610 also targets superposition alignment correction in one direction (e.g., the Y direction) and not in the other direction (e.g., the X direction). For example, a wafer having layers L1 and L7 formed on its working surface and a first stress source film 510 formed on its back surface can be measured to identify the wafer's Y-direction warpage measurement, and the second stress source film 610 may have Y-direction internal stress corrected based on the Y-direction warpage measurement. In one embodiment, a photoresist layer is coated onto the second stress source film 610. The photoresist layer is patterned to correspond to the warpage measurement in the Y direction and developed. The second stress source film 610 is etched using dry or wet etching, and then the photoresist layer is removed. This corrects the internal stress of the second stress source film 610 to correspond to the warpage measurement in the Y direction of the wafer, where the wafer is approximately flat or considered flat in the Y direction. In another embodiment, the second stress source film 610 may react to heat so that the applied heat changes its internal stress, or it may react to a second light wavelength, wherein exposure to the second light wavelength changes its internal stress. A thermal pattern is applied to the second stress source film 610 or a pattern of the second light wavelength is generated to expose the second stress source film 610. The thermal pattern and the pattern of the second light wavelength correspond to the warpage measurement in the Y direction. The second stress source film 610 thus formed is used to correct the superposition alignment in the second direction (i.e., the Y direction) and does not include substantial or significant superposition alignment in the first direction (e.g., the X direction), which is different from or orthogonal to the second direction.

[0046] Next, a photoresist layer L11y can be formed on the working surface of the wafer and aligned with layer L7 in the Y direction. The photoresist layer L11y can be patterned, exposed, and developed in a lithography process to form a hard mask L11y1, as shown in Figures 6C and 6D, and the wafer can be etched accordingly. Note that the hard mask L11y1 is formed and placed between layers L1 and between layers L7, and aligned in the X and Y directions without overlapping layers L1 and L7.

[0047] In one embodiment, the first stress source film 510 may be removed from a selected area on the back surface of the wafer before the second stress source film 610 is formed. Stress memorization may also be used here. In some embodiments, the semiconductor lattice still has a memory effect even after the first stress source film 510 is removed because the stress of the first stress source film 510 has been transferred to the silicon lattice of the wafer.

[0048] In some embodiments, the second stress source film 610 and the first stress source film 510 can be formed in a dual-patterning lithography process. For example, in a lithography-etch-lithography-etch (LELE) process, as shown in FIG7A, the second stress source film 610 and the first stress source film 510 are formed on the back surface of the wafer 710, and a first photoresist layer 720 is coated on the first stress source film 510 and patterned to correspond to the warp measurement value in the X direction. As shown in FIG7B, the first stress source film 510 is etched. As shown in FIG7C, the first photoresist layer 720 is removed, and a second photoresist layer 730 is coated on the second stress source film 610 and patterned to correspond to the warp measurement value in the Y direction. As shown in FIG7D, the second stress source film 610 is etched, and the second photoresist layer 730 is removed. In the LELE process, two lithography steps and two etching steps are performed. As another example, in the lithography-freeze-lithography-etch (LFLE) process, as shown in Figure 8A, a first photoresist layer 720 is coated onto the second stress source film 610 and patterned to correspond to the warp measurement value in the X direction. As shown in Figure 8B, the patterned first photoresist layer 720 is frozen using a chemical treatment. As shown in Figure 8C, a second photoresist layer 730 is coated onto the second stress source film 610 and patterned to correspond to the warp measurement value in the Y direction. As shown in Figure 8D, the second stress source film 610, having corrected internal stresses corresponding to the warp measurements in both the X and Y directions, is etched, and the first photoresist layer 720 and the second photoresist layer 730 are removed. In the LFLE process, two lithography steps and only one etching step are performed. The first stress source film 510 and the second stress source film 610 can also be formed in a litho-curing-litho-etch (LCLE) process, in which the patterned first photoresist layer 720 is baked instead of being frozen by chemical treatment.

[0049] In step S440, one or more semiconductor devices, such as layer L11, may be formed on the working surface of the wafer. Because the wafer warpage in the first and second directions is corrected and the wafer is nearly flat or considered flat in the X and Y directions, the semiconductor devices can be aligned in the X and Y directions.

[0050] This embodiment also includes single-axis or single-direction correction. Some embodiments include alignment correction in only one direction when sufficient for the desired micromachining application. For example, in some micromachining steps, certain features may exist that have only X-direction alignment dependency or Y-direction alignment dependency. These features will not require a cutting masking method and can be separated on the X-mask and Y-mask respectively. An example with a through-hole 900 is shown in FIG. 9A, illustrating that a layer L2 with a through-hole configured in the Y direction is formed on a layer L1 having metal signal lines. As shown in FIG. 9B and 9C, the X-direction key through-hole of layer L2 may be located on a hard mask L2x. Another example with a through-hole 1000 is shown in FIG. 10A, illustrating that a layer L2 with a through-hole configured in the X direction is formed on a layer L1 having metal signal lines. As shown in FIG. 10B and 10C, the Y-direction key through-hole of layer L2 may be located on a hard mask L2y.

[0051] According to certain embodiments of this disclosure, FIG11 illustrates a flowchart of an exemplary method 1100 for improving the overlay alignment of patterned wafers by correcting wafer shape on a single axis. For example, as described with reference to FIGS. 9A to 9C and FIGS. 10A to 10C, method 1100 can correct wafer warpage and bending on a single axis. Method 1100 begins at step S410, followed by step S420, in which a first stress source film 510 is formed and patterned on the back surface of the wafer to correct the overlay alignment of the working surfaces of the wafer in a first direction (e.g., the X direction). In step S1130, one or more first semiconductor devices, such as vias 900 or layers L2x, can be formed on the working surface of the wafer. Because wafer warpage in the first direction is corrected and the wafer is nearly flat or considered flat in the X direction, the first semiconductor devices can be aligned in the X direction. Method 1100 may then proceed to step S430, wherein the second stress source film 610 is formed and patterned on the back surface of the wafer to correct the superposition alignment of the wafer's working surfaces in the second direction (e.g., the Y direction). In step S1150, one or more second semiconductor devices, such as vias 1000 or layers L2y, may be formed on the working surface of the wafer. Because wafer warpage in the second direction is corrected and the wafer is nearly flat or considered flat in the Y direction, the second semiconductor devices can be aligned in the Y direction.

[0052] Some embodiments may include average X and Y correction. Layers may be L1 to Ln (n is 1 to 300). For example, an alignment tree is prepared: L1 --> L7 --> L11, and layers L1 and L7 have been patterned. Ideally, the wafer shape of hard mask L11x1 is L1, and the wafer shape of hard mask L11y1 is L7. In one embodiment, the wafer shape of L11 = αL1 + (1-α)L7, where 0 ≤ α ≤ 1. For example, α = ½, and L11 = (L1 + L7) / 2. The advantage is that this procedure is less expensive and involves fewer processes (one stress source film). Figures 12A to 12D illustrate an exemplary result. Note that layer L11 is aligned within layers L1 and L7, but it has lower accuracy compared to progressive correction and placement. This alignment correction is still better than not using a stress source film.

[0053] According to certain embodiments of this disclosure, FIG13 illustrates a flowchart of an exemplary method 1300 for improving the overlay alignment of patterned wafers by correcting wafer shape. For example, as described in FIGS. 12A to 12D, method 1300 may include average X and Y correction of wafer warpage and bending. Method 1300 begins at step S410. In step S1320, a stress source film is deposited and formed on the back surface of the wafer. In one embodiment, the stress source film is used to correct the overlay alignment of the wafer's working surface on average in a first and second direction (e.g., the X and Y directions) across the working surface of the wafer. For example, a wafer having layers L1 and L7 formed on its working surface may be measured to identify X and Y direction warpage measurements of the wafer, and the stress source film may have X and Y direction internal stresses corrected based on the X and Y direction warpage measurements. For example, the stress source film may have internal stresses in the X and Y directions corrected based on an α-fold X-direction warpage measurement and a (1-α)-fold Y-direction warpage measurement, where 0 ≤ α ≤ 1, for example, α = ½. Method 1300 may also include step S440, in which one or more semiconductor devices, such as layer L11, may be formed on the working surface of the wafer. Compared to a wafer without a stress source film formed on its backside surface, the semiconductor devices can be aligned in the X and Y directions because the wafer warpage in the first and second directions is corrected and the wafer becomes flatter in the X and Y directions.

[0054] In another exemplary embodiment, in the A, H, Z example, another way to address the ZxZy challenge is to pre-ensure the shape of A and H to match. Assuming H has a relatively large overlay budget, this allows for the simple application of wafer shape correction tools to manipulate the wafer shape to match A. Thus, when fabricating layer Z, there exists an optimal Zx --> A and Zy --> H overlay. Even if H does not have a large overlay budget, co-optimization can still be performed to match A while remaining within the budget, making wafer tool correction at Z easier. In the above process, A and H are interchangeable. If A has greater flexibility, feedback from previous lot runs can be used to pre-shape it to resemble H.

[0055] To some extent, the multi-axis nature of precision revealed here can be understood from the practice of photolithography. When exposure is performed at the resolution limit of a given photolithography system, the shape is usually easier to print when exposed as lines. Therefore, multiple exposures can be performed to print lines in different directions. Of course, photolithography is different from stress correction, but stress correction can be improved by dividing directional stress correction into multiple components. For example, Y-direction correction and application can be performed after X-direction correction and application. Some transistor designs may have a 45-degree feature offset, so a third alignment correction can be performed, and a fourth, fifth, and so on. Therefore, by dividing the back-side alignment correction into multiple directional components, the precision and accuracy of alignment patterning are achieved.

[0056] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and procedures used herein, have been set forth. However, it should be understood that the technology herein may be implemented in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific numbers, materials, and configurations have been presented to provide a complete understanding. Nevertheless, embodiments may be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and therefore any lengthy description may be omitted.

[0057] Of course, the order in which the different steps are described herein is for the purpose of brevity. Generally speaking, these steps can be performed in any suitable order. Furthermore, although the different features, techniques, configurations, etc., may be discussed in different places within this disclosure, we intend to implement each concept either independently or in combination with each other. Therefore, this disclosure can be embodied and viewed in many different ways.

[0058] Various techniques have been described as multiple separate operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations must depend on that order. These operations do not necessarily need to be performed in the presented order. The operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations may be omitted in additional embodiments.

[0059] As used herein, "substrate" or "target substrate" generally refers to the object being processed. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a substrate structure such as a semiconductor wafer, a preform mask, or a layer (e.g., a thin film) on or covering a substrate structure. Therefore, a substrate is not limited to any particular substrate structure, underlying layer, or overlay, whether patterned or unpatterned, but is considered to include any such layer or substrate structure, and any combination of layers and / or substrate structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0060] Those skilled in the art will also understand that many variations can be made to the operation of the techniques explained above while still achieving the same purpose of this disclosure. Such variations are intended to be covered by the scope of this disclosure. Therefore, the above description of the embodiments of this disclosure is not intended to be limiting. Any limitations on the embodiments of this disclosure are instead presented in the following claims.

[0061] 100: Aiming at the tree L1: Layer L2: Layer L2x: Hard mask (layer) L2y: Hard mask (layer) L7: Layer L11: Layer L11x: Photoresist layer L11x1: Hard mask L11y: Photoresist layer L11y1: Hard mask L12: Layer 400: Method S410: Steps S420: Steps S430: Steps S440: Steps 510: First stress source membrane 610: Second stress source membrane 710: Wafer 720: First photoresist layer 730: Second photoresist layer 900: Perforation 1000: Perforation 1100: Method S1130: Steps S1150: Steps 1300: Method S1320: Steps

Claims

1. A method for improving the superposition alignment of patterned wafers by correcting wafer shape, comprising: receiving a wafer having a working surface and a back surface, the working surface having a first layer and a second layer formed thereon, the back surface being relative to the working surface; measuring the relative z-height variation of the wafer having the first layer and the second layer formed on the working surface to generate a first warpage measurement in a first direction; forming a first stress source film on the back surface, and correcting the internal stress of the first stress source film in the first direction based on the first warpage measurement, the first stress source film correcting the superposition alignment of the working surface in the first direction across the working surface of the wafer, and excluding superposition alignment in a second direction across the working surface of the wafer, the second direction being different from the first direction; forming a first photoresist layer on the working surface, the first photoresist layer being aligned with the first layer in the first direction; and performing a first lithography process on the first photoresist layer to form an intermediate hard mask; The method involves measuring the relative z-height variation across a wafer having a first layer, a second layer, and an intermediate hard mask formed on the working surface, and a first stress source film formed on the back surface, to generate a second warpage measurement in the second direction; forming a second stress source film on the back surface, and correcting the internal stress of the second stress source film in the second direction based on the second warpage measurement, the second stress source film correcting the superposition alignment of the working surface in the second direction across the working surface of the wafer, but excluding the superposition alignment in the first direction across the working surface of the wafer; forming a second photoresist layer on the working surface, the second photoresist layer being aligned with the second layer in the second direction and covering the intermediate hard mask; performing a second lithography process on the second photoresist layer and the intermediate hard mask to form a target hard mask; and performing a target lithography process on the working surface to form a target layer, the target layer being aligned with the first layer in the first direction and with the second layer in the second direction.

2. The method for improving the overlay alignment of patterned wafers by correcting wafer shape as described in claim 1, wherein the second direction is rotated at least 15 degrees relative to the first direction.

3. The method for improving the overlay alignment of patterned wafers by correcting wafer shape as described in claim 2, wherein the second direction is rotated 45 degrees relative to the first direction.

4. The method for improving the overlay alignment of patterned wafers by correcting wafer shape as described in claim 2, wherein the second direction is orthogonal to the first direction.

5. The method for improving the superimposed alignment of patterned wafers by correcting wafer shape as described in claim 1, further comprising: after performing the first lithography process on the first photoresist layer to form the intermediate hard mask, forming one or more first semiconductor structures on the working surface of the wafer, the first semiconductor structures being aligned in the first direction.

6. The method for improving the overlay alignment of patterned wafers by correcting wafer shape as described in claim 5, wherein the first stress source film and the second stress source film are formed in a lithography-etch-lithography-etch (LELE) process or a lithography-freeze-lithography-etch (LFLE) process.

7. The method for improving the superposition alignment of patterned wafers by correcting wafer shape as described in claim 1, wherein the first stress source film is formed using direct-write patterning.

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