Dual depth junction structures and process methods

Abstract

A transistor, an electronic device, and a method are provided. The transistor includes: a gate trench formed in a semiconductor substrate and extending to a depth of the gate trench; and a source and a drain formed as doped regions in the semiconductor substrate and having a first conductivity type. The source and the drain are respectively formed along a channel length direction of the transistor at a first end and a second end of a gate trench, and each of the source and drain includes a first doped region and a second doped region extending away from the first doped region. The second doped region extends in the semiconductor substrate to a depth greater than that of the first doped region relative to a surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates generally to image sensors, and more particularly, but not exclusively, to transistors used in image sensors. Prior Technology

[0002] Image sensors are ubiquitous. They are widely used in digital cameras, cell phones, security cameras, and in medical, automotive, and other applications. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices. These trends have also led to an increase in pixel count.

[0003] Increasing channel width is one way to improve transistor performance in image sensors. Non-planar (3D) gate structures are one way to achieve a larger effective channel width. In these transistors, channel performance depends in part on the depth of the source and drain junctions in the semiconductor substrate. Deeper junctions improve the charge carrier mobility through the channel, but may also cause current leakage, particularly from neighboring transistors. Therefore, improved transistors are needed. Simple Explanation of the Diagram

[0004] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the accompanying drawings, wherein similar element symbols refer to similar parts throughout the various views unless otherwise specified.

[0005] Figure 1 is a block diagram of one embodiment of an image sensor according to the teachings of the present invention.

[0006] Figure 2 illustrates an embodiment of a pixel layout according to the teachings of the present invention.

[0007] Figure 3A shows a cross-section of one embodiment of a pixel in a channel length plane according to the teachings of the present invention.

[0008] Figure 3B shows a cross-section of another portion of the pixel in Figure 3A in a channel width plane.

[0009] Figure 4 shows a cross-section of one embodiment of another pixel in a portion of a channel length plane according to the teachings of the present invention.

[0010] Figure 5 shows a cross-section of one embodiment of another pixel in a portion of a channel length plane according to the teachings of the present invention.

[0011] Figure 6A shows a schematic top view of a portion of another transistor according to the teachings of the present invention.

[0012] Figure 6B shows a schematic perspective view of one of the transistors in Figure 6A.

[0013] Figure 7 illustrates a method for forming a transistor according to the present invention. Implementation

[0014] This invention provides transistors, pixels, image sensors, electronic devices, and methods for manufacturing the same. In the following description, numerous specific details are set forth to provide a thorough understanding of one example. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring specific aspects.

[0015] Throughout this specification, the references to "an embodiment" or "some embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in some embodiments," "in one embodiment," or "in any embodiment" appearing throughout this specification do not necessarily all refer to the same instance. Furthermore, any particular feature, structure, and / or characteristic of any embodiment may be combined in any suitable manner in one or more instances.

[0016] For ease of description, spatially relative terms such as “below,” “under,” “lower,” “below,” “above,” “above,” and similar terms may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It will be understood that spatially relative terms are intended to cover not only the orientation described in the figures but also different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “under” can cover both orientations of above and below. The device may be oriented in other ways (rotated ninety degrees or otherwise) and the spatially relative descriptive terms used herein shall be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” the layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0017] This invention also provides transistors for image sensors, such as source follower transistors, reset transistors, and column select transistors. To facilitate understanding, these transistors are described in the context of complementary metal-oxide-semiconductor (“CMOS”) image sensors. However, it should be understood that this invention is not limited to transistors for CMOS image sensors, but can also be applied to non-CMOS image sensors and other transistor types. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring specific aspects.

[0018] In this invention, the term "semiconductor substrate" or "substrate" refers to any type of substrate on which an electronic device is formed, including single-crystal substrates, semiconductor-on-insulator (SOI) substrates, doped silicon bulk substrates, and epitaxial-on-semiconductor (EPI) substrates, and the like. Furthermore, although embodiments are described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), the technology is not limited in this respect. Rather, embodiments can be implemented using any type of semiconductor material.

[0019] This invention relates to several terms relating to different embodiments (including apparatus and methods). Terms with similar names have similar meanings in relation to different embodiments, unless explicitly stated otherwise. For clarification, similar elements are numbered similarly between figures and should be understood to be capable of having any one or more features of other similar elements, except for the relevant differences described. Similarly, this invention utilizes several technical terms. These terms will take their ordinary meaning in the art to which they belong, unless specifically defined herein or otherwise clearly implied in their use. It should be noted that throughout this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0020] This application may also refer to quantities and numbers. Unless specifically stated otherwise, such quantities and numbers should not be considered limiting, but rather represent possible quantities or numbers associated with this application. Furthermore, in this regard, this application may use the term "plural" to refer to a quantity or number. In this regard, the term "plural" means any number greater than one, such as two, three, four, five, etc. The terms "about," "approximately," "close to," etc., mean plus or minus 5% of the stated value. For the purposes of this invention, the phrase "at least one of A, B, and C" may, for example, mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), and when more than three elements are listed, all further possible permutations are included.

[0021] Figure 1 is a diagram illustrating one example of a representative image sensor 100 having a pixel array 102 with one pixel 104. As shown, the pixel array 102 is coupled to a control circuit system 106 and a readout circuit system 108, which is coupled to a functional logic 110.

[0022] Pixel array 102 is a two-dimensional ("2D") array of pixels 104 (e.g., pixels P1, P2, ..., Pn). In one embodiment, each pixel 104 is a complementary metal-oxide-semiconductor ("CMOS") imaging pixel. Pixel array 102 may be implemented as a front-illuminated image sensor array or a back-illuminated image sensor array. In some embodiments, pixel 104 includes one or more transistors as described below, including source follower transistors, column select transistors, and / or reset transistors. In an embodiment, at least one of these transistors has at least one vertical gate structure. As illustrated, pixels 104 are configured in columns (e.g., columns R1 to Ry) and rows (e.g., rows C1 to Cx) to acquire image data of a person, place, or object, which can then be used to present a 2D image of the person, place, or object.

[0023] After a pixel 104 has acquired its image data or image charge, the image data is read out by the readout circuitry system 108 and transferred to the functional logic 110. The readout circuitry system 108 may include an amplification circuitry system, such as a differential amplifier circuitry system, an analog-to-digital ("ADC") conversion circuitry system, or other circuitry systems. In some embodiments, the readout circuitry system 108 may read out a line of image data at a time along a readout row (shown) or may use a variety of other techniques (not shown) to read out the image data, such as simultaneous serial readout or fully parallel readout of all pixels.

[0024] Control circuitry 106 is coupled to pixels 104 of pixel array 102 and includes logic and memory for controlling the operational characteristics of pixels 104. For example, control circuitry 106 may generate a shutter signal for controlling image acquisition. In some embodiments, the shutter signal is a global shutter signal that enables all pixels 104 to simultaneously capture their respective image data during a single acquisition window. In some embodiments, the shutter signal is a rolling shutter signal that sequentially enables columns, rows, or groups of pixels 104 during consecutive acquisition windows.

[0025] Functional logic 110 includes logic and memory for storing image data or even manipulating image data by applying image post-effects (e.g., cropping, rotating, removing red-eye, adjusting brightness, adjusting contrast, or other methods).

[0026] In any embodiment, one or more of the image sensor 100, pixel array 102, or pixel 104 may be embedded in an electronic device 112, such as a smartphone, a camera, an endoscope, a biometric sensing device, a light-based proximity sensor, and the like.

[0027] Figure 2 illustrates a representative example of a simplified pixel 204 layout, which can be used in an image sensor such as the image sensor 100 of Figure 1, and can be integrated into an electronic device such as a smartphone. The pixel layout shown in Figure 2 is representative, and the teachings of the present invention can be embodied in many other pixel layouts.

[0028] Pixel 204 includes a semiconductor substrate 214 in which a plurality of photodiodes 216a to 216d are formed and the plurality of photodiodes are arranged in a "quad-shared" configuration. Each of the transfer transistors 218a to 218d may have the ability to transfer charge from one of the corresponding photodiodes 216a to 216d to a vertical transfer gate 220a to 220d of a floating diffusion region 222 when turned on (e.g., receiving a transfer signal). The floating diffusion region 222 is coupled to a source follower transistor 250 (e.g., via a metal interconnect as shown in FIG. 2) and a reset transistor 224, and the source follower transistor 250 is coupled to a row of select transistors 226.

[0029] The floating diffusion region 222 is coupled to the planar transfer gate of the transfer transistors 218a to 218d and the gate of the source follower transistor 250, and operates to gather charge carriers from the photodiodes 216a to 216d (via one or more transfer transistors 218a to 218d) and output a corresponding voltage to the gate of the source follower transistor 250 for signal amplification and readout.

[0030] Photodiodes 216a to 216d are each configured to generate and accumulate charge in response to incoming light received during an integration cycle of the image sensor. For example, charge (e.g., photoelectrons) accumulated in a charge accumulation region (e.g., a source of transfer transistors 218a to 218d) of photodiodes 216a to 216d during an integration cycle of the image sensor can be selectively transferred to a floating diffusion region 222 (e.g., a drain of transfer transistors 218a to 218d) during a charge transfer cycle of the image sensor, depending on the voltage applied to the planar gate of the transfer transistors 218a to 218d. In some embodiments, photodiodes 216a to 216d have a pinned photodiode configuration.

[0031] The reset transistor 224 is configured to, under the control of a reset signal received at the gate RST of the reset transistor 224 during a reset cycle, reset (e.g., discharge or charge) the photodiodes 216a to 216d coupled via transfer transistors 218a to 218d and floating diffusion region 222 to a preset voltage, such as a supply voltage VDD.

[0032] A source follower transistor 250 is coupled between an electric field line and a column select transistor 226, and modulates an image signal output based on the voltage output from a floating diffusion region 222. This image signal corresponds to the amount of photoelectrons accumulated in the charge accumulation regions of the coupled photodiodes 216a to 216d during the integration period at their gates. The source follower transistor 250 amplifies the image signal based on the voltage received at its gate. Both the source follower transistor 250 and the reset transistor 224 can be coupled to the same electric field line receiving the supply voltage VDD. For example, one drain of the source follower transistor 250 and one drain of the reset transistor 224 are coupled to the supply voltage VDD.

[0033] In this invention, the terms "channel width plane," "channel width direction," "channel length plane," and "channel length direction" are used to describe the characteristics of transistors and pixels. For clarity, a "channel width plane" is a plane extending across a channel through which charge carriers flow between a source and a drain of a transistor (e.g., the source 236 and drain 240 of a source follower transistor 250). In other words, a channel width plane or channel width direction is perpendicular to the direction of current flow. In contrast, a channel length plane or channel length direction is perpendicular to all channel width planes and oriented parallel to the direction of current flow.

[0034] The column select transistor 226 selectively couples the output (e.g., an image signal) of the source follower transistor 250 to the readout line under the control of a column select signal received at its gate RS.

[0035] The region where the source follower transistor 250, reset transistor 224, and column select transistor 226 are located can be referred to as a transistor region of pixel 204. In contrast, the region where photodiodes 216a to 216d, transfer transistors 218a to 218d, and floating diffusion region 222 are located can be referred to as the active region. An isolation structure 228a (e.g., a shallow channel isolation trench structure having a depth of about 150 nm to about 400 nm relative to one side of the semiconductor substrate 214) is disposed between the active region and the transistor region and extends along a channel length direction. In some embodiments, isolation structures 228a to 228b form portions of the transistors of the present invention described below. Some embodiments include a plurality of isolation structures 228a to 228b, i.e., one on each side of the transistor region.

[0036] In some embodiments, pixel 204 may include additional elements not described in detail herein, such as one or more additional transistors, capacitors, floating diffusion regions, or the like. In some embodiments, the transfer gates of transfer transistors 218a to 218d utilize a planar transfer gate instead of vertical transfer gates 220a to 220d.

[0037] During operation, during the integration cycle (also known as the exposure or accumulation cycle) of the image sensor, photodiodes 216a to 216d absorb incident light on their respective charge accumulation regions. The photogenerated charge accumulated in the charge accumulation regions indicates the amount of light incident on the charge accumulation regions. After the integration cycle, a transfer signal (e.g., a positive bias voltage) is applied, for example from the control circuit system 106 of FIG1, to the vertical transfer gates 220a to 220d of the transfer transistors 218a to 218d, thereby causing the transfer transistors 218a to 218d to turn on and transfer the photogenerated charge from the corresponding photodiodes 216a to 216d to the floating diffusion region 222 during the charge transfer cycle. The source follower transistor 250 operably generates an image signal based on the voltage output from the coupled floating diffusion region 222. The column select transistor 226 is coupled to the source follower transistor 250, and then selectively couples the image signal to a row bit line for subsequent image processing when a column select signal is received during a readout cycle.

[0038] Figures 3A and 3B show different views of a portion of pixel 304 having the same features as pixel 204 in Figure 2. Specifically, the illustrated portion of pixel 304 includes a source follower transistor 350 operatively coupled to a series of select transistors 326. A gate 352 of the source follower transistor 350 is operatively coupled to a floating diffusion region (not shown) of pixel 304. It should be noted that the use of a source follower transistor and a series of select transistors in this example is representative and not limiting. For example, in any embodiment, the transistor 326 adjacent to the source follower transistor 350 is a reset transistor or another transistor, rather than a series of select transistors. As another example, transistor 350 may be a vertical gate transistor.

[0039] The viewpoint of Figure 3A is in a channel length plane, that is, the plane of Figure 3A is parallel to the direction in which the charge carriers move from the column selector transistor 326 to the source follower transistor 350 (e.g., along channels 380 and 382). In contrast, Figure 3B shows a cross-section of the source follower transistor 350 in a channel width plane, which is perpendicular to the channel length plane shown in Figure 3A.

[0040] As can be seen from Figures 3A and 3B, gate 352 is a non-planar gate, that is, gate 352 has: a planar gate portion 356, which is parallel to one surface 330 of the semiconductor substrate 314 and extends along the channel length direction between one source 336 and one drain 340 of the source follower transistor 350; and at least one fin-shaped or finger-shaped vertical gate portion 354a to 354c, which extends into the semiconductor substrate 314 away from the planar gate portion 356. Figure 3B specifically shows that gate 352 includes a plurality of parallel fin-shaped vertical gate portions 354a to 354c, which are spaced apart from each other in the channel width direction, thus producing a wave-like shape, which increases the effective channel width of one source follower transistor 350. It should be noted that the number and shape of the fin-shaped vertical gate portions shown in Figure 3B are representative and not limiting.

[0041] Figure 3B also highlights channel isolation structures 328a and 328b disposed in the semiconductor substrate 314 on opposite sides of the source follower transistor 350 along the channel width direction. Each channel isolation structure 328a and 328b may extend in the channel length direction and isolate the transistor region from the active region of the pixel 304. See isolation structures 228a and 228b in Figure 2. In any embodiment, the channel isolation structures 328a and 328b are filled with oxide material and / or are shallow isolation trench structures with a depth of about 150 nm to about 400 nm relative to the surface 330 of the semiconductor substrate 314. As shown in Figure 3B, in any embodiment, the planar gate portion 356 of the gate 352 may extend at least partially over the channel isolation structures 328a and 328b. In any embodiment, a portion of the outer vertical gate portions 354a and 354c may extend over the corresponding channel isolation structures 328a and 328b.

[0042] To enable the vertical gate portions 354a to 354c to extend into the semiconductor substrate 314, for example by an etching process, such as a dry or wet etching process or a combination of wet and dry etching, at least one gate trench 358 is first formed in the semiconductor substrate along the channel width direction. See Figure 3B (showing gate trenches 358a to 358c). Specifically, each of the gate trenches 358a to 358c is formed as a groove extending into the semiconductor substrate 314 relative to the front surface 330 to a gate trench depth DT. In any embodiment, the gate trench depth DT is about 50 nm to about 600 nm, about 100 nm to about 150 nm, about 100 nm to about 140 nm, about 100 nm to about 130 nm, about 100 nm to about 120 nm, about 100 nm to about 110 nm, about 110 nm to about 150 nm, about 120 nm to about 150 nm, about 130 nm to about 150 nm, or about 140 nm to about 150 nm. In some embodiments, the gate trench depth DT is greater than the depth of each vertical transfer gate in the corresponding active pixel region (e.g., deeper than the vertical transfer gates 220a to 220d of transfer transistors 218a to 218d). In embodiments where gate 352 has a plurality of vertical gate portions (e.g., 354a to 354c), gate trench 358 defines an equal number of parallel grooves (e.g., gate trenches 358a to 358c) across a channel width plane, each of which extends in the channel length direction. Furthermore, referring to FIG. 3B, the parallel grooves of gate trenches 358a to 358c define non-planar substrate structures 362a and 362b in a semiconductor substrate 314. Each non-planar substrate structure has a plurality of sidewall portions, and each of the non-planar substrate structures 362a and 362b may have a width W of approximately 5 nm to approximately 20 nm in the channel width direction. For example, non-planar substrate structure 362a has sidewall portions 364a and 364b, and non-planar substrate structure 362b has sidewall portions 364c and 364d.

[0043] Referring to Figure 3B, after forming the gate trench 358, an isolation layer 360 (i.e., a gate isolation layer) is deposited in the gate trench, such that the isolation layer 360 has a thickness of about 5 nm to about 10 nm. The isolation layer 360 includes a dielectric material, such as an oxide or a high-k material, for example, a material having a dielectric constant greater than about 3.9 (e.g., Al₂O₃ or HfO₂). In any embodiment, the dielectric material may be deposited into the gate trench 358 to a thickness of about 50 nm to about 75 nm to prevent the formation of a channel at the bottom of the gate trench 358.

[0044] After depositing the isolation layer 360, a gate material such as polycrystalline silicon or a metal is deposited on the isolation layer 360, thereby forming a gate 352. An optional spacer 376 is formed around the gate 352, for example, in a configuration that modifies the current and voltage parameters of the source follower transistor 350. In some embodiments, the spacer 376 surrounds the gate 352. In some embodiments, the spacer 376 is formed of a dielectric material similar to the isolation layer 360. In some embodiments, the spacer 376 is a single-layer or multi-layer stacked structure formed of an oxide, nitride, or a combination thereof.

[0045] Before proceeding with the description of the pixels and transistors of the present invention, the following paragraphs provide some background. A transistor typically comprises a source and a drain for charge carriers, disposed on opposite sides of a gate along the channel length direction. These sources and drains can be formed from doped portions of an underlying semiconductor substrate. To date, these source and drain doped regions have a substantially uniform junction depth. As an example, the source and drain may each nominally extend into the underlying semiconductor substrate. One disadvantage of this configuration is that in transistors having a non-planar gate (i.e., having a finned vertical gate portion) extending to a greater depth in the semiconductor substrate than the source and drain, the charge carrier channel is not effectively formed around the non-planar finned vertical gate portion—particularly around the bottom or farthest region of one of these vertical gate portions. As another example, the source and drain may each have a uniform junction depth extending to approximately the same depth as one of the non-planar finned junction portions. However, this configuration leads to undesirable current leakage between adjacent transistors (e.g., between the source follower transistor and the column select transistor). For these reasons, the aforementioned transistor structure does not provide satisfactory performance.

[0046] Returning to pixel 304 of Figure 3A, the source follower transistor 350 has a double-depth source 336 and a double-depth drain 340 formed along the channel length direction on opposite sides of the gate 352. The source 336 can also serve as a drain of the column select transistor 326, but for consistency, it is referred to herein as a source. As explained below, the double-depth source and drain junction facilitates the formation of a complete charge carrier channel while preventing current leakage between adjacent transistors (e.g., between the source follower transistor 350 and the column select transistor 326). The drain 340 is coupled to an electric field line via contact 342 to receive a supply voltage VDD.

[0047] Source 336 and drain 340 are formed as doped regions in a semiconductor substrate 314 at a first end and a second end of a gate trench 358 (or gate 352), respectively, along the channel length direction. Specifically, each of the source 336 and drain 340 is doped with a common first dopant (e.g., As) having a first conductivity type (e.g., N-type), which is opposite to the lower semiconductor substrate 314 having a second conductivity type. In some embodiments, the source 336 and drain 340 may be formed in a well region of the second conductivity type embedded in the semiconductor substrate 314. The well region having the source 336 and drain 340 may have a higher concentration than that of the semiconductor substrate 314. In some embodiments, each of the source 336 and drain 340 is implanted in alignment with the gate 352 (e.g., implanted in alignment with the edge of the gate).

[0048] Each of the source 336 and drain 340 includes a first doped region or a shallow doped region (having a shallow junction depth) and a second doped region or a deep doped region extending away from the first doped region relative to the front surface 330 (having a junction depth deeper than the first region). More specifically, the source 336 includes a first doped region 366 having a shallow junction depth and a second doped region 368 extending away from the first doped region 366 having a deep junction depth. Similarly, the drain 340 includes a first doped region 370 having a shallow junction depth and a second doped region 372 having a deep junction depth. For simplicity, the first doped region and the second doped region will be referred to as the first region and the second region, respectively, hereinafter.

[0049] As used herein, the terms "shallow" and "deep" are relative terms, meaning that the second region extends in the semiconductor substrate 314 to a depth greater than that of the first region (relative to surface 330). Accordingly, the second region (also referred to as the deep-doped region) has a junction depth greater than that of the first region (also referred to as the shallow-doped region). Given the similarity between the source 336 and the drain 340, both the first and second doped regions should be described without distinguishing between the source 336 and the drain 340, unless relevant differences require description.

[0050] Regions 366 and 370 and regions 368 and 372 have similar material properties and therefore may be indistinguishable from each other in a material sense. That is, regions 366 and 370 are all portions of semiconductor substrate 314 doped with a first dopant (e.g., As) having a first conductivity type (e.g., N-type).

[0051] Shallow doped regions 366 and 370 originate from or are adjacent to the opposite ends of gate 352 and extend outward from therein along the channel length direction. Each shallow doped region 366 and 370 has a uniform first depth D1 relative to the surface 330 of semiconductor substrate 314, which is approximately 50 nm to approximately 200 nm, approximately 50 nm to approximately 150 nm, approximately 50 nm to approximately 100 nm, approximately 50 nm to approximately 90 nm, approximately 50 nm to approximately 80 nm, approximately 50 nm to approximately 70 nm, approximately 50 nm to approximately 60 nm, approximately 100 nm to approximately 200 nm, approximately 150 nm to approximately 200 nm, approximately 160 nm to approximately 200 nm, approximately 170 nm to approximately 200 nm, approximately 180 nm to approximately 200 nm, approximately 190 nm to approximately 200 nm, or approximately 100 nm to approximately 150 nm. Typically, shallow doped regions 366 and 370 do not extend into semiconductor substrate 314 to the gate trench depth DT. In any embodiment, it may be illustrated that each shallowly doped region 366, 370 extends only to the first depth D1, or does not extend deeper than the first depth D1.

[0052] The source 336 (which also serves as a drain of one of the column select transistors 326) extends along the channel length direction from the gate 352 of the source follower transistor 350 toward the planar gate 374 of the column select transistor 326. In some embodiments, a lightly doped region 366 of the source 336 extends from below the planar gate portion 356 of the gate 352 to below the planar gate 374 of the column select transistor 326. For example, when the column select transistor 326 is turned on, a first channel 380 of the column select transistor 326 may be formed in the semiconductor substrate 314, located below the planar gate 374 of the column select transistor 326 between the lightly doped region 366 and the source 378 of the column select transistor 326. As described above, the source 378 of the selector transistor 326 is coupled to the power line via contact 390 (e.g., the same power line as contact 342 coupled to the drain 340 of the source follower transistor 350) to receive the supply voltage VDD.

[0053] Returning attention to the source follower transistor 350, the deeply doped regions facilitate the movement of charge carriers around the entire depth of the vertical gate portions of the gate 352 (e.g., each of the vertical gate portions 354a to 354c shown in FIG. 3B). A characteristic of one of the deeply doped regions 368 and 372 is that each extends further into the semiconductor substrate 314 to a second depth D2 deeper than the corresponding first depth D1 of the shallowly doped regions 366 and 370 (relative to the surface 330 of the semiconductor substrate 314). Specifically, each deep region 368 and 372 extends to the second depth D2 away from the lower portion of the corresponding shallowly doped region 366 and 370. In any embodiment, the sum of the first depth D1 and the second depth D2 may be approximately equal to the gate trench depth DT, i.e., the same as or greater than the depth of the vertical gate portions 354a to 354c of the gate 352. Therefore, the deeply doped regions 368 and 372 may each further extend to a second depth D2 of approximately 50 nm to approximately 500 nm, approximately 50 nm to approximately 400 nm, approximately 50 nm to approximately 300 nm, approximately 50 nm to approximately 200 nm, approximately 50 nm to approximately 100 nm, approximately 100 nm to approximately 500 nm, approximately 200 nm to approximately 500 nm, approximately 300 nm to approximately 500 nm, and approximately 400 nm to approximately 500 nm. That is, in the embodiment, the interface depth of each deeply doped region 368 and 372 relative to the surface 330 of the semiconductor substrate 314 is the sum of one of the first depth D1 and the second depth D2.

[0054] As shown, for each of the source 336 and drain 340, the shallowly doped region may extend away from the corresponding deeply doped region in the channel length direction, for example, in a vertical orientation (i.e., a direction perpendicular to a substrate depth direction or a surface 330 of the semiconductor substrate 314). Accordingly, in any embodiment, each dual-depth source 336 and drain 340 may have an angled profile, which may include an L-shape (specifically, a lateral L-shape in which the deeply doped region extends away from the shallowly doped region in a vertical orientation). In some embodiments, the source 336 and drain 340 may have a shape or profile that conforms to the shape or profile of the gate 352 in the channel width dimension. For example, if the vertical gate portions 354a to 354c have different depths (e.g., if the central vertical gate portion 354b has a deeper gate depth), then the source 336 and drain 340 have different junction depths in the channel width direction depending on the depth of the gate 352.

[0055] Advantageously, the aforementioned dual-depth source and drain facilitate the movement of charge carriers throughout the entire depth of the vertical gate portion (e.g., through the second channel 382), while preventing the formation of a charge carrier path 384 from the deeply doped region 368 of the source 336 of the source follower transistor 350 to the source 378 of the column select transistor 326 (which would otherwise cause current leakage). Specifically, the deeply doped regions 368, 372 extend vertically along the vertical gate portions 354a to 354c and provide free charge carriers by means of the first dopant. This allows a channel (e.g., the second channel 382) to be formed along the sidewall portions 364a to 364d of the non-planar substrate structures 362a to 362b in the channel length direction when the source follower transistor 350 is turned on, increasing the effective channel width of the source follower transistor 350, thereby increasing the Gm of the source follower transistor 350 to improve device performance. Meanwhile, the distance between the deep doped region 368 of the source transistor 336 of the source follower transistor 350 and the source 378 of the column select transistor 326 is relatively large, thereby suppressing the junction leakage between the two adjacent transistors 350 and 326.

[0056] Referring again to FIG. 3A, pixel 304 includes optional isolation regions formed as doped regions embedded in semiconductor substrate 314 adjacent to shallow and deep doped regions. These isolation regions further prevent current leakage from the shallow and deep doped regions by forming a barrier layer along the exterior of one of the dual-depth source / drain regions, the barrier layer interfacing with the isolation regions. Specifically, source follower transistor 350 includes a source isolation region 386 and a drain isolation region 388, each formed in a region of semiconductor substrate 314 partially defined by its respective shallow and deep doped regions (i.e., an inner region defined on one side by a deep doped region 368 or 372 and on an upper side by a corresponding shallow region 366 or 370). To create the barrier layer, source isolation regions 386 and 388 are doped with a second dopant (e.g., boron) having a second conductivity type opposite to that of the first conductivity type of source 336 and drain 340. In any embodiment, source isolation region 386, drain isolation region 388, and / or other isolation regions such as the channel isolation region of FIG. 5 may have a dopant concentration greater than that of the surrounding semiconductor substrate 314. As a representative example, the region of semiconductor substrate 314 shown in FIG. 3A may include a P-type doped well region with a dopant concentration of about E16 / cm3, and source isolation region 386 and drain isolation region 388 may each have a P-type dopant concentration greater than about E16 / cm3, for example, about E17 / cm3 to about E18 / cm3.

[0057] In any embodiment, each of the source isolation region 386 and the drain isolation region 388 extends from the lower portion of one of the corresponding shallowly doped regions 366 and 370 into the semiconductor substrate 314 to the lower portion of one of the corresponding deeply doped regions 368 and 372, and / or extends at least as deep as the gate trench depth DT. To reiterate, each of the source isolation region 386 and the drain isolation region 388 may extend from a first depth D1 to at least a second depth D2. In some embodiments, such as those described below with reference to FIG4, each of the source isolation region 386 and the drain isolation region 388 extends deeper than the gate trench depth DT or the second depth D2 to enhance channel isolation.

[0058] Additional variations of the isolation zone are described below with reference to Figures 4 and 5.

[0059] Figure 4 shows a portion of a pixel 404 that has the same features as pixels 304 in Figures 3A to 3B (except where described below). Accordingly, similar element symbols have similar meanings to those described above (e.g., 460 corresponds to an isolation layer as defined above with respect to isolation layer 360), and only the relevant differences are described herein.

[0060] Although the dual-depth source and drain of pixel 404 are the same as those of pixel 304, the source isolation region 486 and drain isolation region 488 are each larger to more effectively isolate channel 482 and prevent current leakage between source follower transistor 450 and column select transistor 426. Specifically, each of the source isolation region 486 and drain isolation region 488 extends into the semiconductor substrate 414 from below one of the corresponding shallowly doped regions 466 and 470 to a third depth D3 relative to the front surface 430 of the semiconductor substrate 414. This third depth D3 is deeper than the gate trench depth DT or the depth of the deep doped regions 468 and 472. In any embodiment, the third depth D3 is about 50 nm to about 300 nm deeper than the gate trench depth DT or the depth of the deep doped regions 468 and 472 relative to the front surface 430 of the semiconductor substrate 414. Accordingly, in any embodiment, the source isolation regions 486, 488 may be approximately 50 nm to approximately 300 nm deeper than either the depth DT or the second depth D2 identified above with respect to FIG2. Alternatively or additionally, each of the source isolation region 486 and the drain isolation region 488 extends at least along the entire length L1, L2 of one of the corresponding shallowly doped regions 466, 470 in the channel length direction. Accordingly, in these embodiments, each of the source isolation region 486 and the drain isolation region 488 extends below the lower portion of one of the corresponding shallowly doped regions 466, 470 and the deeply doped region 468, 472. In embodiments, each of the source isolation region 486 and the drain isolation region 488 is adjacent to or adjacent to the corresponding shallowly doped region 466, 470 and the deeply doped region 468.

[0061] In any embodiment, one of the isolation zones 486 and 488 may have the configuration shown in FIG4, while the other of the isolation zones may have the configuration shown in FIG3A.

[0062] Figure 5 shows a portion of another pixel 504 having the same features as pixels 304 in Figures 3A to 3B and pixel 404 in Figure 4 (except where described below). Accordingly, similar element symbols have similar meanings as described above (e.g., 560 corresponds to an isolation layer as defined above with respect to isolation layer 360), and only the relevant differences are described herein. The embodiment of Figure 5 may be advantageous in a pixel in which at least a portion of at least one photodiode is directly disposed below the transistor region of the pixel.

[0063] Although the dual-depth source 536 and drain 540 of pixel 504 are the same as those of the aforementioned pixel, channel 582 is isolated from photodiode 516 by a single channel isolation region 586 extending continuously below source 536, gate 552 of source follower transistor 550, and drain 540. Similar to gate 352 of source follower transistor 350, gate 552 includes a planar gate and at least one vertical gate. Specifically, channel isolation region 586 is disposed between photodiode 516 and source 536 and drain 540, and extends along the channel length direction from a distal portion of one of the shallowly doped regions 570 (of drain 540) to a relatively distal portion of one of the shallowly doped regions 566 (of source 536). At least one central portion of the channel isolation region 586 disposed under the gate 552 extends in the semiconductor substrate 514 to a depth deeper than the gate depth of the vertical gate portion of the gate 552, for example, about 50 nm to about 300 nm deeper than the gate 552 or the gate trench depth DT. Similar to the isolation regions of Figures 3A to 4, the channel isolation region 586 is formed as a doped region in the semiconductor substrate 514 having a second dopant and a second conductivity type opposite to the first conductivity type of the source 436 and the drain 440. The channel isolation region 586 may have a concentration higher than that of the semiconductor substrate 514.

[0064] Similar to the isolation regions of Figures 3A to 4, an optional channel isolation region 590 is formed as a doped region below the source 578 of the column select transistor 526, and may have any of the same material properties as the channel isolation region 586. The channel isolation region 590 is a feature that can be utilized in any of the embodiments described herein, for example, to facilitate the isolation of the column select transistor 526 from the photodiode 516.

[0065] Figure 6A shows a schematic top view of a portion of a transistor 650 having a non-planar source and drain. Figure 6B shows a schematic perspective view of a transistor 650 having one of the optional drain contacts described below. Transistor 650 has the same features as the aforementioned transistors 350, 450 and 550, except for the relevant differences described below. It should be understood that transistor 650 is not limited to a source follower transistor and can be any transistor having a vertical gate electrode.

[0066] Similar to the aforementioned transistor, transistor 650 includes a dual deep source 636 and a dual deep drain 640 (see shallow doped regions 670, 674 and deep doped regions 672, 676). A plurality of gate trenches are formed in a semiconductor substrate 614, thereby defining a plurality of non-planar substrate structures 662a, 662b. The plurality of gate trenches are located between and adjacent to the non-planar substrate structures 662a, 662b. This configuration is similar to the configuration shown in FIG. 3B (the number of non-planar substrate structures shown is representative and not limiting). Accordingly, a gate 652 is disposed on the non-planar substrate structures 662a, 662b and includes a planar gate portion 656 disposed on a top surface of one of the semiconductor substrates 614, and a plurality of vertical gate portions 654a to 654c each of the planar gate portion extending into one of the gate trenches.

[0067] Unlike the aforementioned transistors, transistor 650 has the unique feature that its source 636 and drain 640 each comprise a portion of one of the non-planar substrate structures 662a and 662b. To reiterate, a portion of each end of the non-planar substrate structures 662a and 662b is doped with a dopant having a first conductivity type opposite to that of the underlying semiconductor substrate 614, for example, through a surface plasma implantation process, a low-energy tilt implantation process, or a similar process. Because the source 636 and drain 640 can be formed at both the shallower and deeper depths of the dual-depth structure using a surface plasma implantation process or a similar process, the manufacturing process avoids the need for one or two implantation steps. Therefore, as best shown in FIG6B, the non-planar substrate structures 662a and 662b form portions of two deeply doped regions (see deep doped region 672). Therefore, the source 636 and drain 640 benefit from the dual-depth structure described above, and also improve channel performance by means of the non-planar substrate structures 662a and 662b integrally formed therein.

[0068] As shown in Figure 6B, an optional drain contact 690 is operatively connected to a current source. The drain contact 690 is formed of a metal or other conductive material and includes a body portion 692 from which a plurality of fingers 694a, 694b extend. Each finger 694a, 694b extends into a corresponding gate trench adjacent to a drain 640 formed in the semiconductor substrate 614. Accordingly, in any embodiment, the number of vertical gate portions may be equal to the number of gate trenches. In any embodiment, the transistor 650 may additionally or alternatively include a source contact having the same structure as the drain contact 690, but with fingers extending into the gate trench and coupled to the source 636.

[0069] Figure 7 illustrates a method 700 for forming the transistor of the present invention. The terminology used below has similar meanings to those used above to describe the structure of the present invention. In any embodiment of method 700, the steps may be performed in the order described below.

[0070] In step 702, a semiconductor substrate in which at least one gate trench is formed is provided. The at least one gate trench is formed to a gate trench depth, such as about 50 nm to about 600 nm, about 50 nm to about 500 nm, about 50 nm to about 400 nm, about 50 nm to about 300 nm, about 50 nm to about 200 nm, about 50 nm to about 100 nm, about 100 nm to about 600 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, or about 500 nm to about 600 nm, by etching the semiconductor substrate using dry etching, wet etching, or a combination thereof. In any embodiment, the at least one gate trench comprises a plurality of parallel gate trenches that define one or more non-planar substrate structures in the semiconductor substrate.

[0071] In step 704, a shallowly doped region (first doped region) of a source and a drain is formed in the semiconductor substrate by doping a region to a first depth at opposite ends of at least one gate trench with a first dopant (e.g., As) having a first conductivity type (opposite to the semiconductor substrate) through a first mask. In any embodiment, the first depth is approximately 50 nm to approximately 200 nm, approximately 10 nm to approximately 40 nm, approximately 10 nm to approximately 30 nm, approximately 10 nm to approximately 20 nm, approximately 20 nm to approximately 50 nm, approximately 30 nm to approximately 50 nm, or approximately 40 nm to approximately 50 nm. In any embodiment, ion implantation, plasma implantation, tilting implantation, or similar processes through at least one gate trench can be used. In any embodiment, forming the shallowly doped region may include doping at least a portion of a non-planar substrate structure of the semiconductor substrate to at least a first depth with the first dopant.

[0072] In step 706, a deep-doped region (second doped region) of the source and drain is formed in the semiconductor substrate by doping a region of the semiconductor substrate below the shallow doped region and at the opposite end of the gate trench to at least the gate trench depth using a first dopant through a second mask. In an embodiment using ion implantation, the same process as in step 704 can be used, for example, with a higher implantation energy. For example, the shallow-doped regions of the source and drain are formed by implanting the first dopant into the semiconductor substrate with a first implantation energy, and the deep-doped regions of the source and drain are formed by implanting the first dopant into the semiconductor substrate with a second implantation energy greater than the first implantation energy, such that each of the deep-doped regions extends from its respective shallow-doped region and has a junction depth formed at a depth deeper than its respective shallow-doped region. In any embodiment, the deep region can be formed using an ion implantation, plasma implantation, tilt implantation, or similar process through at least one gate trench; in these embodiments, this step can be performed substantially simultaneously with the formation of the shallow region in step 704. In any embodiment, forming a deep doped region may include, for example, using a plasma implantation or tilt implantation process through one of the gate trenches, doping a portion of at least one non-planar substrate structure of a semiconductor substrate with a first dopant to at least the gate trench depth.

[0073] In optional step 708, at least one isolation region is formed beneath the shallow and / or deep doped regions by masking and implanting a second dopant (e.g., boron) having a second conductivity type opposite to the first conductivity type into the semiconductor substrate. In any embodiment, at least one isolation region is formed through a third mask. In any embodiment, at least one isolation region extends from a lower portion of a shallow junction to at least the depth of a gate trench. In any embodiment, at least one isolation structure extends to a depth deeper than the depth of the gate trench, for example, about 50 nm to about 300 nm deeper than the depth of the gate trench. In any embodiment, the isolation region has a dopant concentration greater than the dopant concentration of a semiconductor substrate. In some embodiments, the isolation region extends continuously along the channel length direction beneath at least one gate trench and / or gate from a distal portion of a shallow doped region of the drain to a relatively distal portion of a shallow doped region of the drain, as illustrated in FIG5. In any embodiment, the isolation region extends at least along the entire length L1, L2 of the corresponding shallow doped region in the channel length direction.

[0074] In step 710, an isolation layer of dielectric material is deposited in the gate trench, and a gate material comprising a metal, polycrystalline silicon, or a similar material is deposited on the isolation layer and in the gate trench. In any embodiment, the isolation layer may be deposited with a thickness of about 3 nm to about 10 nm.

[0075] Advantageously, the transistors, pixels, and devices with dual-depth source and drain as described herein facilitate the movement of charge carriers around the entire depth of the non-planar gate, thus increasing Gm, while preventing current leakage between adjacent transistors.

[0076] 100: Image Sensor 102: Pixel Array 104 pixels 106: Control Circuit System 108: Readout Circuit System 110: Functional Logic 112: Electronic devices 204: pixels 214: Semiconductor substrate 216a: Photodiode 216b: Photodiode 216c: Photodiode 216d: Photodiode 218a: Transfer transistor 218b: Transfer Transistor 218c: Transfer Transistor 218d: Transfer transistor 220a: Vertical Transfer Gate 220b: Vertical Transfer Gate 220c: Vertical Transfer Gate 220d: Vertical Transfer Gate 222: Floating diffusion zone 224: Reset Transistor 226: Column Select Transistor 228a: Isolation structure 228b: Isolation Structure 236: Source 240: Jiji 250: Source follower transistor 304: pixels 314: Semiconductor substrate 326: Column Select Transistor 328a: Channel isolation structure 328b: Channel isolation structure 330: Surface 336: Source 340: Jiji 342: Contact element 350: Source follower transistor 352: Gate 354a: Vertical gate section 354b: Vertical gate portion 354c: Vertical gate portion 356: Planar gate section 358a: Gate trench 358b: Gate trench 358c: Gate trench 360: Isolation Layer 362a: Non-planar substrate structure 362b: Non-planar substrate structure 364a: Sidewall portion 364b: Sidewall portion 364c: Sidewall portion 364d: Sidewall portion 366: First doped region / shallow doped region 368: Second doped region / deep doped region 370: First doped region / shallow doped region 372: Second doped region / deep doped region 374: Planar Gate 376: Spacer 378: Source 380: First Channel 382: Second Channel 384: Charge Carrier Path 386: Source Isolation Zone 388: Dublin Isolation Zone 390: Contact element 404: pixels 414: Semiconductor substrate 426: Column Select Transistor 430: Front surface 436: Source 440: Jiji 450: Source follower transistor 460: Isolation layer 466: Shallow doped region 468: Deeply doped region 470: Shallow doped region 472: Deeply Doped Region 482: Channel 486: Source Isolation Zone 488: Source Isolation Zone 504: pixels 514: Semiconductor substrate 516: Photodiode 526: Column Select Transistor 536: Source 540: Jiji 550: Source Follower Transistor 552: Gate 560: Isolation Layer 566: Shallow doped region 570: Shallow doped region 578: Source Extreme 582: Channel 586: Passage Isolation Zone 590: Passage Isolation Zone 614: Semiconductor substrate 636: Source 640: Jiji 650: Transistor 652: Gate 654a: Vertical gate section 654b: Vertical gate section 654c: Vertical gate section 656: Planar gate section 662a: Non-planar substrate structure 662b: Non-planar substrate structure 670: Shallow doped region 672: Deeply Doped Region 674: Shallow doped region 676: Deeply Doped Region 690: Drain contact 692: Main body 694a: Finger part 694b: Finger part 700: Method 702: Steps 704: Steps 706: Steps 708: Steps 710: Steps C1 to Cx: rows D1: First Depth D2: Second Depth D3: Third Depth DT: Gate Trench Depth L1: Length L2: Length P1 to Pn: pixels R1 to Ry: Columns W: Width

Claims

1. A transistor formed in a semiconductor substrate, comprising: A gate trench formed in the semiconductor substrate and extending to a gate trench depth; a source and a drain, which are formed as doped regions in the semiconductor substrate and have a first conductivity type, wherein the source and the drain are formed along a channel length direction of the transistor at a first end and a second end of the gate trench, respectively, wherein each of the source and the drain includes a first doped region and a second doped region extending away from the first doped region, wherein the second doped region extends in the semiconductor substrate to a depth greater than the first doped region relative to a surface of the semiconductor substrate; and an isolation layer disposed in the gate trench. A gate electrode disposed on the isolation layer and extending into the gate trench; and a source isolation region and a drain isolation region, the source isolation region and the drain isolation region being formed as doped regions in the semiconductor substrate adjacent to the first doped region and the second doped region of the source and the drain, respectively, wherein the source isolation region and the drain isolation region have a second conductivity type opposite to the first conductivity type.

2. The transistor of claim 1, wherein the first doped region forms a shallow junction with a uniform first junction depth in the semiconductor substrate, and wherein the second doped region forms a deep junction with a second junction depth in the semiconductor substrate, wherein the second junction depth is greater than the first junction depth relative to the surface of the semiconductor substrate.

3. The transistor of claim 1, wherein the gate trench comprises a plurality of gate trenches, the gate trenches being defined in the semiconductor substrate in at least one nonplanar substrate structure having a plurality of sidewall portions in a channel width plane perpendicular to the channel length direction of the transistor.

4. The transistor of claim 3, wherein the source and the drain are formed along the length of the channel at a first end and a opposite second end of one of the at least one nonplanar substrate structures.

5. The transistor of claim 1, wherein for each of the source and the drain, the second doped region extends into the semiconductor substrate at least to the depth of the gate trench.

6. The transistor of claim 1, wherein for each of the source and the drain, the first doped region does not extend into the semiconductor substrate to the depth of the gate trench.

7. The transistor of claim 3, wherein the source and the drain are partially formed in the at least one non-planar substrate structure, and wherein the gate is coupled to the source and the drain.

8. The transistor of claim 7, wherein the at least one non-planar substrate structure forms a portion of the second doped region of each of the source and the drain.

9. The transistor of claim 1, wherein the source and the drain each have an angled shape.

10. The transistor of claim 9, wherein for each of the source and the drain, the first doped region extends away from the second doped region in a vertical orientation along the channel length direction.

11. The transistor of claim 1, wherein the lower portion of each of the first doped regions of the source isolation region and the drain isolation region extends into the semiconductor substrate to the lower portion of the second doped region.

12. The transistor of claim 1, wherein the source isolation region and the drain isolation region each extend into the semiconductor substrate to at least the gate trench depth.

13. The transistor of claim 1, wherein the source isolation region and the drain isolation region extend into the semiconductor substrate deeper than the gate trench depth.

14. The transistor of claim 1, wherein each of the source isolation region and the drain isolation region has a dopant concentration greater than that of one of the semiconductor substrates.

15. The transistor of claim 1, further comprising a channel isolation region formed as a doped region in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, wherein the channel isolation region extends continuously beneath the source, the gate and the drain.

16. An image sensor comprising: Such as the transistor in request item 1; A photodiode is formed in the semiconductor substrate; A floating diffusion region coupled to the gate of the transistor; a transfer transistor coupled to the photodiode to the floating diffusion region, wherein the transfer transistor operates to transfer image charge from the photodiode to the floating diffusion region, wherein the transistor system is a source follower transistor.

17. The image sensor of claim 16, further comprising a second transistor having a drain of the first doped region comprising the source of the source follower transistor, wherein the second transistor includes: A planar gate, adjacent to the source of the source follower transistor, is disposed on the surface of the semiconductor substrate; A source electrode is disposed in the semiconductor substrate on the side of the planar gate opposite to the drain electrode of the second transistor along a channel length direction, wherein the source electrode of the second transistor extends from the surface of the semiconductor substrate to the same junction depth as the first doped region of the drain electrode of the second transistor.

18. The image sensor of claim 17, further comprising: A source isolation region and a drain isolation region are formed in the semiconductor substrate as doped regions adjacent to the first doped region and the second doped region of the source and drain of the source follower transistor, respectively, wherein the source isolation region and the drain isolation region have a second conductivity type opposite to the first conductivity type; and a second channel isolation region is formed in the semiconductor substrate as a doped region adjacent to the drain of the second transistor, wherein the second channel isolation region has the second conductivity type.

19. The image sensor of claim 16, further comprising a channel isolation region formed as a doped region in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, wherein the channel isolation region extends below the source, gate trench and drain of the source follower transistor, wherein a portion of the photodiode extends below the source, gate trench and drain of the source follower transistor, wherein the channel isolation region is disposed between the photodiode and the gate trench.

20. A method for forming a transistor in a semiconductor substrate, comprising: A semiconductor substrate is provided having a gate trench formed therein up to a gate trench depth; a source and a drain of the transistor are formed, the source and the drain each having a double junction depth relative to a surface of the semiconductor substrate including a first junction depth and a second junction depth greater than the first junction depth, wherein the source and the drain of the transistor further include: doping the semiconductor substrate to the first junction depth at opposite ends of the gate trench by using a first implantation energy and through a first mask with a first dopant having a first conductivity type, thereby forming a first doped region in the semiconductor substrate; By using a second implantation energy greater than the first implantation energy, and through a second masking, using the first dopant to dope the region of the semiconductor substrate below the first doped region and on the opposite end of the gate trench to at least the gate trench depth, a second doped region extending from the corresponding first doped region is formed in the semiconductor substrate; and by using a second dopant having a second conductivity type opposite to the first conductivity type to dope the semiconductor substrate to at least the gate trench depth below the first doped region and the second doped region, at least one isolation region is formed, wherein the gate trench depth is deeper than the first junction depth.

21. The method of claim 20, wherein forming the source and drain of the transistor includes doping the opposite ends of the gate trench using a plasma implantation or tilt implantation process.

22. The method of claim 20, further comprising: An isolation layer is deposited in the gate trench; And a gate material is deposited on the isolation layer and in the gate trench.

Images