Integrated circuit device

Abstract

An integrated circuit element is provided, the integrated circuit element comprising: a substrate having a first active region and a second active region spaced apart from the first active region; and a plurality of cell patterns having a column shape, wherein the plurality of cell patterns comprises: a plurality of first cell patterns extending in a first horizontal direction and including a plurality of first cell groups; and a plurality of second cell patterns spaced apart from the plurality of first cell groups, extending in the first horizontal direction and including a plurality of second cell groups, wherein a corresponding side surface of the plurality of second cell patterns has a corresponding concave portion, the corresponding concave portion being recessed inward along a corresponding side surface of the plurality of first cell patterns adjacent to a corresponding second cell pattern in the plurality of second cell patterns.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2022-0094023, filed with the Korean Intellectual Property Office on July 28, 2022, the entire disclosure of which is incorporated herein by reference.

[0003] The present invention relates to integrated circuit elements, and more specifically to integrated circuit elements comprising conductive lines and contact plugs adjacent to said conductive lines. Prior Technology

[0004] Recently, with the rapid miniaturization of integrated circuit components, the gaps between multiple conductive lines have decreased, and consequently, the separation distance between these conductive lines and the contact structures arranged in the relatively narrow space between them has also gradually decreased. Therefore, there is a need to develop a technique to implement a structure that can maintain the electrical reliability of the contact structures arranged in the relatively narrow space between the multiple conductive lines. Summary of the Invention

[0005] The present invention provides an integrated circuit element that can maintain electrical reliability even when the area of ​​the element region decreases as the integration density of the semiconductor element increases.

[0006] According to the present invention, an integrated circuit element is provided, the integrated circuit element comprising: a substrate having a first active region and a second active region spaced apart from the first active region; a component isolation layer located between the first active region and the second active region; a direct contact electrically connected to the first active region in a direct contact opening extending through a portion of the first active region and a portion of the component isolation layer; a plurality of cell patterns having a columnar shape and extending from the lower surface of the direct contact opening on the second active region; and a buried contact plug extending through a portion of the plurality of cell patterns and electrically connected to the second active region, wherein the plurality of cell patterns The method includes: a plurality of first unit groups arranged along a first horizontal direction, each of the plurality of first unit groups including a plurality of first unit patterns arranged in a row along a second horizontal direction perpendicular to the first direction; and a plurality of second unit groups spaced apart from the plurality of first unit groups and arranged along the first horizontal direction, each of the plurality of second unit groups including a plurality of second unit patterns arranged in a row along the second horizontal direction, wherein a corresponding side surface of the plurality of second unit patterns has a corresponding concave portion, the corresponding concave portion being recessed inward along a corresponding side surface of the plurality of first unit patterns adjacent to the corresponding second unit pattern of the plurality of second unit patterns.

[0007] According to another embodiment of the present invention, an integrated circuit element is provided, the integrated circuit element comprising: a substrate having a plurality of first active regions and a plurality of second active regions; a plurality of cell patterns defining direct contact openings in one or more of the second active regions, including a plurality of first cell patterns arranged in a first horizontal direction and a second horizontal direction perpendicular to the first direction, and a plurality of second cell patterns arranged in the first horizontal direction and the second horizontal direction and spaced apart from the first cell patterns; a direct contact extending through a gap-filled insulating pattern in the direct contact opening and electrically connected to one or more of the first active regions; a bit line electrically connected to the direct contact on the substrate; and a buried contact plug extending through portions of the plurality of cell patterns and electrically connected to one or more of the second active regions, wherein the plurality of second cell patterns are spaced apart from the plurality of first cell patterns adjacent to the plurality of second cell patterns by at least a first separation distance, and wherein the planar area of ​​each of the plurality of second cell patterns is smaller than the planar area of ​​each of the plurality of first cell patterns.

[0008] According to another embodiment of the present invention, an integrated circuit element is provided, the integrated circuit element comprising: a substrate having a first active region and a second active region spaced apart from the first active region; a component isolation layer located between the first active region and the second active region; a direct contact electrically connected to the first active region in a direct contact opening extending through a portion of the first active region and a portion of the component isolation layer; a character line extending on the substrate in a first horizontal direction and intersecting the first active region and the second active region; a bit line extending on the substrate in a second horizontal direction perpendicular to the first direction and electrically connected to the direct contact; a capacitor located on the bit line and configured to store data; a plurality of cell patterns having a column shape and extending from the lower surface of the direct contact opening on the second active region and defining the direct contact opening; and a buried contact plug extending through the plurality of cells. The plurality of unit patterns include portions thereof, electrically connected to the second active region; and conductive overlap pads extending vertically over the buried contact plug and electrically connecting the buried contact plug to the capacitor, wherein the plurality of unit patterns comprise: a plurality of first unit groups arranged along the first horizontal direction, each of the plurality of first unit groups comprising a plurality of first unit patterns arranged in a column along the second horizontal direction; and a plurality of second unit groups spaced apart from the plurality of first unit groups and arranged along the first horizontal direction, each of the plurality of second unit groups comprising a plurality of second unit patterns arranged in a column along the second horizontal direction, wherein the planar area of ​​each of the plurality of second unit patterns is smaller than the planar area of ​​each of the plurality of first unit patterns, and wherein the plurality of second unit patterns are spaced apart from the plurality of first unit patterns adjacent to the plurality of second unit patterns by at least a first separation distance. Simple Explanation of the Diagram

[0009] The exemplary embodiments disclosed herein will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: Figure 1A is a layout diagram illustrating integrated circuit elements according to some exemplary embodiments. Figure 1B is a cross-sectional view taken along line B-B' of Figure 1A. Figure 1C is a cross-sectional view taken along line C-C' of Figure 1A. Figure 1D is an enlarged view illustrating the area indicated by P in Figure 1A. Figure 1E is an enlarged view of a portion of the layout diagram of integrated circuit elements according to some exemplary embodiments, that is, an enlarged view illustrating the area corresponding to the area indicated by P in Figure 1A. Figures 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9, 10A, and 10B are plan views and cross-sectional views illustrating the process sequence of manufacturing an integrated circuit element according to some exemplary embodiments. Specifically, Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 10A are plan views illustrating a method of manufacturing a cell pattern of an integrated circuit element according to some exemplary embodiments, and Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9, and 10B are cross-sectional views taken along lines A-A', B-B', and C-C' of Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 10A, respectively. Figures 11A to 11C are cross-sectional views taken along line B-B' of Figure 1A to illustrate a method of manufacturing an integrated circuit element according to some exemplary embodiments. Implementation

[0010] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Similar reference numerals in the drawings represent similar components, and therefore their descriptions will be omitted.

[0011] Figure 1A is a layout diagram illustrating an integrated circuit element 100 according to some exemplary embodiments. Figure 1B is a cross-sectional view taken along line B-B' of Figure 1A. Figure 1C is a cross-sectional view taken along line C-C' of Figure 1A. Figure 1D is an enlarged view illustrating the area indicated by P in Figure 1A.

[0012] Referring to Figures 1A, 1B, 1C, and 1D, the integrated circuit element 100 may include a substrate 102, in which a plurality of active regions ACT are defined. The active regions ACT may include a first active region 106a and a second active region 106b. The plurality of active regions ACT may be spaced apart from each other by a component isolation layer 104.

[0013] According to some embodiments, substrate 102 may comprise silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. According to some embodiments, substrate 102 may comprise at least one selected from Ge, SiGe, SiC, GaAs, InAs, and / or InP. According to some embodiments, substrate 102 may include conductive regions, such as impurity-doped wells or impurity-doped structures. The device isolation layer 104 may comprise an oxide layer, a nitride layer, or a combination thereof.

[0014] According to some embodiments, the plurality of active regions ACT may be arranged on a diagonal direction D1 relative to a first horizontal direction (X direction) and a second horizontal direction perpendicular to the first horizontal direction (Y direction).

[0015] According to some embodiments, a character line trench 112 extending in a first horizontal direction (X direction) may be formed in a substrate 102, and a gate dielectric layer 114, a character line 116, and a first top cover insulating layer 118 may be disposed in the character line trench 112. The character line 116 in FIG1C may correspond to the character line WL in FIG1A.

[0016] According to some embodiments, the gate dielectric layer 114 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO) layers, and / or a high-dielectric layer (e.g., high-k) with a dielectric constant higher than that of the silicon oxide layer. The high-dielectric layer may comprise HfO₂, Al₂O₃, HfAlO₃, Ta₂O₃, TiO₂, or combinations thereof. The word line 116 may comprise Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof. The first top cover insulating layer 118 may comprise a silicon oxide layer, silicon nitride, silicon oxynitride, or combinations thereof.

[0017] According to some embodiments, the character lines WL can be arranged to intersect or cross the active region ACT. According to some embodiments, a first active region 106a can be arranged between a pair of character lines WL that intersect with the active region ACT, and a second active region 106b can be arranged at the edge of the active region ACT.

[0018] According to some embodiments, a first buffer layer 122 and a first conductive layer 124 may be sequentially disposed on a substrate 102. According to some embodiments, the first buffer layer 122 may cover the upper surface of the active region ACT and the upper surface of the element isolation layer 104.

[0019] According to some embodiments, the first buffer layer 122 may include a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer sequentially formed on the substrate 102, but is not limited thereto. According to some embodiments, the first conductive layer 124 may include a doped polycrystalline silicon layer.

[0020] According to some embodiments, a direct contact opening 184 may be formed to expose the first active region 106a. According to some embodiments, the direct contact opening 184 may pass through or extend through the first buffer layer 122 and the first conductive layer 124, and may pass through or extend through portions of the plurality of active regions ACT and portions of the element isolation layer 104.

[0021] According to some embodiments, the direct contact opening 184 may be defined by a plurality of unit patterns CP. According to some embodiments, the plurality of unit patterns CP may have a column shape that protrudes in the vertical direction or extends from the lower surface 184L of the direct contact opening 184 on the second active region 106b.

[0022] According to some embodiments, the plurality of unit patterns CP may include a second active region 106b. For example, the plurality of unit patterns CP may simultaneously include the second active region 106b of each of two adjacent active regions ACT among the plurality of active regions ACT. For example, the plurality of unit patterns CP may overlap with the second active region 106b of each of two adjacent active regions ACT among the plurality of active regions ACT.

[0023] According to some embodiments, the direct contact opening 184 may be a space between the plurality of unit patterns CP, and may be a recessed space in the vertical direction (Z direction). According to some embodiments, from a horizontal viewpoint or a plan viewpoint, the direct contact opening 184 may be defined by the side surfaces CPW of the plurality of unit patterns CP.

[0024] According to some embodiments, the plurality of unit patterns CP may have isolated island shapes when viewed from a horizontal or planar perspective. Figure 1 illustrates that, when viewed from a planar perspective, the plurality of unit patterns CP have an elliptical shape or an elliptical shape with deformed portions, but the plurality of unit patterns CP are not limited to this. For example, when viewed from a planar perspective, the plurality of unit patterns CP may have shapes such as rectangles or circles.

[0025] According to some embodiments, the side surface CPW of the plurality of unit patterns CP may include the side surface of the first conductive layer 124, the side surface of the first buffer layer 122, the side surface of the element isolation layer 104 and the side surface of the first top cover insulation layer 118, and the direct contact opening 184 passes through or extends through the first conductive layer 124, the first buffer layer 122, the element isolation layer 104 and the first top cover insulation layer 118.

[0026] The multiple embedded contacts BC and multiple bit line spacers 216, which will be described later, can pass through or extend through portions of the multiple unit patterns CP in the vertical direction (Z direction). The boundaries of the multiple unit patterns CP illustrated in Figure 1 can indicate the boundaries of the side surfaces CPW of the unpenetrated portions of the multiple unit patterns CP.

[0027] According to some embodiments, the plurality of unit patterns CP may include a plurality of first unit groups CPG1 and a plurality of second unit groups CPG2. The plurality of first unit groups CPG1 are arranged along a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). Each of the plurality of first unit groups includes a plurality of first unit patterns CP1 arranged in a column along the second horizontal direction (Y direction). The plurality of second unit groups CPG2 are spaced apart from the plurality of first unit groups CPG1, arranged along the first horizontal direction (X direction), and extend in the second horizontal direction (Y direction). Each of the plurality of second unit groups includes a plurality of second unit patterns CP2 arranged in a column along the second horizontal direction (Y direction). According to some embodiments, the first unit groups CPG1 and the second unit groups CPG2 may be spaced apart from each other in the first direction (X direction) and the second direction (Y direction). The plurality of first unit patterns CP1 and the plurality of second unit patterns CP2 are spaced apart from each other in the first direction (X direction) and the second direction (Y direction).

[0028] According to some embodiments, multiple first unit groups CPG1 and multiple second unit groups CPG2 may intersect or cross each other. For example, the multiple first unit patterns CP1 and the multiple second unit patterns CP2 may not be arranged in a straight line in the first direction (X direction). For example, the multiple first unit patterns CP1 and the multiple second unit patterns CP2 may not be arranged in a straight line in the second direction (Y direction). For example, the multiple first unit patterns CP1 and the multiple second unit patterns CP2 may be offset from each other.

[0029] According to some embodiments, from a plan view perspective, the plurality of first unit patterns CP1 and the plurality of second unit patterns CP2 can be arranged to surround each other. For example, a first unit pattern CP1 may be surrounded by a plurality of second unit patterns CP2. For example, a second unit pattern CP2 may be surrounded by a plurality of first unit patterns CP1.

[0030] According to some embodiments, a first unit matrix CPM1 in which a plurality of first unit groups CPG1 are arranged in a first horizontal direction (X direction) can be defined. According to some embodiments, a plurality of first unit patterns CP1 in the first unit group CPG1 can be arranged in a straight line with a plurality of first unit patterns CP1 in another adjacent first unit group CPG1 in the first horizontal direction (X direction).

[0031] According to some embodiments, a second unit matrix CPM2 in which a plurality of second unit groups CPG2 are arranged in a first horizontal direction (X direction) can be defined. According to some embodiments, a plurality of second unit patterns CP2 in the second unit group CPG2 can be arranged in a straight line with a plurality of second unit patterns CP2 in another adjacent second unit group CPG2 in the first horizontal direction (X direction).

[0032] According to some embodiments, each of the first unit matrix CPM1 and the second unit matrix CPM2 may have a rectangular arrangement. According to some embodiments, each of the first unit matrix CPM1 and the second unit matrix CPM2 may have a parallelogram arrangement.

[0033] According to some embodiments, a plurality of first unit patterns CP1 may be arranged to be spaced apart from each other by a first unit distance a1 in the second horizontal direction (Y direction) and by a second unit distance a2 in the first horizontal direction (X direction). According to some embodiments, a plurality of second unit patterns CP2 may be arranged to be spaced apart from each other by a third unit distance b1 in the second horizontal direction (Y direction) and by a fourth unit distance b2 in the first horizontal direction (X direction). According to some embodiments, the first unit distance a1 and the third unit distance b1 may be substantially the same as each other, and the second unit distance a2 and the fourth unit distance b2 may be substantially the same as each other. Here, each of the first unit distance a1, the second unit distance a2, the third unit distance b1, and the fourth unit distance b2 may refer to the distance between the centers of the plurality of unit patterns CP. The quantitative relationship obtained by comparing the first unit distance a1, the second unit distance a2, the third unit distance b1, and the fourth unit distance b2 may be substantially the same as the quantitative relationship determined by the distance between the side surfaces CPW of each of the plurality of unit patterns CP.

[0034] According to some embodiments, the distances a1 and a2 of the first unit may be the same, and the distances b1 and b2 of the third unit may be the same. In this case, each of the first unit matrix CPM1 and the second unit matrix CPM2 may have a square arrangement. According to some embodiments, each of the first unit matrix CPM1 and the second unit matrix CPM2 may also have a rhomboid arrangement.

[0035] According to some embodiments, from a horizontal viewpoint or a plan viewpoint, a second unit pattern CP2 can be arranged within a rectangular arrangement R1 of a first unit matrix CPM1, and a first unit pattern CP1 can be arranged within a rectangular arrangement R2 of a second unit matrix CPM2.

[0036] According to some embodiments, a virtual third unit pattern CPS can be defined, which is arranged at the center of each of the rectangular arrangements R1 and R2 of the first unit matrix CPM1 and the second unit matrix CPM2. For example, the center CPSC of the third unit pattern CPS can be the center of a rectangle formed by connecting the centers CC1 of the four first unit patterns CP1 surrounding the third unit pattern CPS.

[0037] According to some embodiments, the center CC2 of the second unit pattern CP2 may not match the center CPSC of the third unit pattern CPS. For example, the first unit pattern CP1 may not be arranged at the center of the rectangular arrangement R2 of the second unit matrix CPM2. For example, the first unit pattern CP1 may be offset from the center of the rectangular arrangement R2. For example, the second unit pattern CP2 may not be arranged at the center of the rectangular arrangement R1 of the first unit matrix CPM1. For example, from a horizontal viewpoint or a plan viewpoint, the center CC2 of the second unit pattern CP2 may be arranged at a position moved from the center CPSC of the third unit pattern CPS in the second horizontal direction (Y direction) and / or the first horizontal direction (X direction). For example, the center CC2 of the second unit pattern CP2 may be offset from the center of the rectangular arrangement R1 (e.g., offset from the center CPSC of the third unit pattern CPS).

[0038] According to some embodiments, at least two first unit patterns CP1 surrounding a second unit pattern CP2 among a plurality of first unit patterns CP1 may be at different distances from the second unit pattern CP2. For example, the distances DAB1 and DAB2 from the center CC2 of the second unit pattern CP2 to the center CC1 of the plurality of first unit patterns CP1 may be different from each other.

[0039] According to some embodiments, from a horizontal or plan view, a plurality of second unit patterns CP2 surrounding a first unit pattern CP1 may be arranged asymmetrically relative to the first unit pattern CP1. According to some embodiments, from a horizontal or plan view, the first unit pattern CP1 surrounding the second unit pattern CP2 may be arranged asymmetrically relative to the second unit pattern CP2.

[0040] According to some embodiments, viewed from a horizontal or planar perspective, the shape of the cross-section of the first unit pattern CP1 may differ from the shape of the cross-section of the second unit pattern CP2. According to some embodiments, the horizontal area (e.g., planar area) of the second unit pattern CP2 may be smaller than the horizontal area (e.g., planar area) of the first unit pattern CP1. According to some embodiments, viewed from a horizontal or planar perspective, the cross-section of the second unit pattern CP2 may be spaced apart from the first unit pattern CP1 adjacent to the second unit pattern CP2 by a first separation distance t1, and may have a shape cut along the boundary of the first unit pattern CP1 adjacent to the second unit pattern CP2.

[0041] According to some embodiments, the side surface CPW of the second unit pattern CP2 may have a concave portion CA, which is concavely recessed inward along the side surface CPW of the first unit pattern CP1 adjacent to the second unit pattern CP2. In this case, the second unit pattern CP2 may be arranged such that the concave portion CA is spaced apart from the first unit pattern CP1 by a first separation distance t1.

[0042] According to some embodiments, the first separation distance t1 may refer to the minimum separation distance between the first unit pattern CP1 and the second unit pattern CP2. According to some embodiments, multiple first unit patterns CP1 and multiple second unit patterns CP2 may be spaced apart from each other by a spacing or distance greater than or equal to the first separation distance t1. Therefore, the minimum spacing distance between multiple unit patterns CP can be ensured, and the electrical reliability of integrated circuit elements can be improved.

[0043] Figure 1E is an enlarged view of a portion of the layout diagram of an integrated circuit element 100a according to some exemplary embodiments, that is, an enlarged view illustrating the area corresponding to the area indicated by P in Figure 1A.

[0044] Referring to Figure 1E, the second unit pattern CP2 may have multiple concave portions CA. For example, the second unit pattern CP2 may be arranged such that two first unit patterns CP1 adjacent to the second unit pattern CP2 are spaced apart by a first separation distance t1, and may have two concave portions CA.

[0045] Referring back to Figures 1A, 1B, 1C, and 1D, multiple bit lines BL can extend parallel to each other on multiple character lines WL in a second horizontal direction (Y direction). According to some embodiments, portions of the multiple character lines WL can overlap with multiple unit patterns CP in the vertical direction (Z direction).

[0046] According to some embodiments, the plurality of bit lines BL may be disposed on the first buffer layer 122. According to some embodiments, the plurality of bit lines BL may include a first conductive layer 124 and a second conductive layer 204 located on the first conductive layer 124. Although FIG. 1B illustrates that the bit lines BL have two conductive layers, the bit lines BL may include multiple conductive layers, including three or more layers. Each of the plurality of bit lines BL may be covered by a second top cover insulating layer 206.

[0047] According to some embodiments, the second conductive layer 204 may include a layer comprising Ti, TiN, TiSiN, tungsten (W), WN, tungsten silicon (WSi x), tungsten silicon nitride (WSi xN y), ruthenium (Ru), or combinations thereof. According to some embodiments, the second top cover insulating layer 206 may include a silicon nitride layer.

[0048] According to some embodiments, the multiple bit lines BL can be connected to multiple active regions ACT via direct contacts DC. According to some embodiments, the direct contacts DC can be connected to a first active region 106a exposed via a direct contact opening 184. According to some embodiments, the direct contacts DC can comprise Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof. In some embodiments, the direct contacts DC can comprise a doped polycrystalline silicon layer.

[0049] According to some embodiments, the direct contact DC may face the side surface CPW of a plurality of unit patterns CP in a first direction (X direction). According to some embodiments, the direct contact DC may face the side surface CPW of the plurality of unit patterns CP in a second direction (Y direction), wherein an insulating spacer 214 is disposed between the direct contact DC and the plurality of unit patterns CP. According to some embodiments, the direct contact DC may be surrounded by unit patterns CP, with the insulating spacer 214 disposed between the direct contact DC and the unit patterns CP. According to some embodiments, at least two of the plurality of unit patterns CP surrounding the direct contact DC may be at different distances from the direct contact DC. For example, the horizontal thickness of the insulating spacer 214 between the plurality of unit patterns CP surrounding the direct contact DC may be different from the horizontal thickness of the direct contact DC.

[0050] According to some embodiments, the insulating spacer 214 may fill the space defined by a plurality of unit patterns CP and direct contacts DC. According to some embodiments, the insulating spacer 214 may be formed as at least a single layer or multiple layers selected from the group including silicon oxide layers, silicon nitride layers and / or silicon oxynitride layers.

[0051] According to some embodiments, multiple buried contacts BC may be formed between two adjacent bit lines BL among multiple bit lines BL. According to some embodiments, multiple bit line spacers 216 may be respectively arranged between the multiple bit lines BL and the multiple buried contacts BC. According to some embodiments, the sidewalls of the multiple bit lines BL may respectively face the multiple buried contacts BC, wherein the multiple bit line spacers 216 are arranged between the multiple bit lines BL and the multiple buried contacts BC.

[0052] According to some embodiments, the plurality of buried contacts BC can be arranged in a line in the second horizontal direction (Y direction) and the first horizontal direction (X direction). A plurality of conductive overlap pads 222 can be formed on the plurality of buried contacts BC. The plurality of bit line spacers 216 can also be respectively arranged between the plurality of conductive overlap pads 222 and the plurality of second top cover insulating layers 206.

[0053] According to some embodiments, the plurality of buried contacts BC and the plurality of conductive overlap pads 222 may be configured to connect the lower electrode (not shown) of a capacitor 232 formed above or on the plurality of bit lines BL to the active region ACT. According to some embodiments, the plurality of conductive overlap pads 222 may be connected to the plurality of capacitors 232 via a plurality of through-hole plugs 228. According to some embodiments, at least a portion of each of the plurality of conductive overlap pads 222 may overlap with the buried contact BC in the vertical direction.

[0054] According to some embodiments, the overlap pad isolation pattern 224 may be arranged between the plurality of conductive overlap pads 222. According to some embodiments, the plurality of conductive overlap pads 222 may be isolated from each other by the overlap pad isolation pattern 224.

[0055] According to some embodiments, the bit line spacer 216 may comprise at least one material selected from silicon nitride, silicon oxide, and / or silicon oxide. According to some embodiments, the overlap pad isolation pattern 224 may comprise at least one material selected from silicon nitride, silicon oxide, and / or silicon oxide.

[0056] Figures 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9, 10A and 10B are plan views and cross-sectional views illustrating the process sequence of a method for manufacturing an integrated circuit element 100 according to some exemplary embodiments. In detail, Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A and 10A are plan views illustrating a method of manufacturing a unit pattern CP of an integrated circuit element 100 according to some exemplary embodiments, and Figures 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9 and 10B are cross-sectional views taken along lines A-A', B-B' and C-C' of Figures 2A, 3A, 4A, 5A, 6A, 7A, 8A and 10A, respectively.

[0057] Referring to Figures 2A and 2B, a first buffer layer 122 can be formed on the substrate 102. The first buffer layer 122 can cover the upper surface of the active region ACT and the upper surface of the component isolation layer 104.

[0058] According to some embodiments, a first conductive layer 124, a second buffer layer 132, an interlayer insulating layer 134, a first masking layer 136 and a second masking layer 138 may be sequentially formed (e.g., stacked) on the first buffer layer 122.

[0059] According to some embodiments, the second buffer layer 132 may comprise amorphous carbon. The second buffer layer 132 may comprise a single layer or multiple layers. For example, the second buffer layer 132 may comprise a layer comprising at least one material selected from silicon nitride, silicon oxide, and / or silicon nitride oxide. For example, the second buffer layer 132 may be a bilayer consisting of a layer of amorphous carbon and a layer of silicon oxynitride sequentially stacked.

[0060] According to some embodiments, the interlayer insulating layer 134 may comprise at least one material selected from silicon nitride, silicon oxide, and / or silicon oxide nitride. For example, the interlayer insulating layer 134 may be a single layer or multiple layers comprising at least one material selected from silicon nitride, silicon oxide, and / or silicon oxide nitride.

[0061] According to some embodiments, the first masking layer 136 may be a bilayer consisting of a spin-coated hard mask and at least one material selected from silicon nitride, silicon oxide, and / or silicon oxynitride. According to some embodiments, the second masking layer 138 may be a bilayer consisting of a spin-coated hard mask and at least one material selected from silicon nitride, silicon oxide, and / or silicon oxynitride.

[0062] According to some embodiments, the interlayer insulating layer 134 may include silicon oxide, the first masking layer 136 may be a double layer of spin-coated hard mask and silicon oxynitride stacked sequentially, and the second masking layer 138 may be a double layer of spin-coated hard mask and silicon oxynitride stacked sequentially.

[0063] Referring to Figures 3A and 3B, a first pattern opening 142 can be formed by providing a first unit pattern mask (not shown) on a second masking layer 138 and removing a portion of the second masking layer 138. According to some embodiments, the first pattern opening 142 may be formed above or on the second active region 106b. For example, the first pattern opening 142 may overlap vertically with a second active region 106b located at one end of one of two adjacent active regions ACT and a second active region 106b located at one end of the other of two adjacent active regions ACT.

[0064] Subsequently, a first patterned insulating layer 144 may be filled into the first patterned opening 142. According to some embodiments, the first patterned insulating layer 144 may comprise silicon oxide. For example, the first patterned insulating layer 144 may simultaneously cover two adjacent second active regions 106b located at the ends of some of the active regions ACT in a plurality of active regions.

[0065] Referring to Figures 4A and 4B, a portion of the second mask layer 138 can be removed by using the first patterned insulating layer 144 as an etching mask, thereby forming a second mask opening 146. In this case, a portion of the upper surface of the interlayer insulating layer 134 can be exposed.

[0066] Referring to Figures 5A and 5B, a unit isolation layer 152 can be conformally coated on the first patterned insulating layer 144 and the interlayer insulating layer 134. For example, the unit isolation layer 152 may have a thickness of a first separation distance t1 (shown in Figure 6B) and may cover the upper surface of the first patterned insulating layer 144, the side surfaces of the first patterned insulating layer 144, the side surfaces of the first masking layer 136, and the upper surface of the interlayer insulating layer 134. According to some embodiments, the unit isolation layer 152 may comprise silicon oxide.

[0067] Subsequently, a third masking layer 154 and a fourth masking layer 156 may be sequentially formed on the unit isolation layer 152. According to some embodiments, the third masking layer 154 may include a double layer. For example, the third masking layer 154 may be a double layer consisting of a spin-coated hard mask and silicon oxynitride sequentially stacked. In this case, the upper surface of the layer including the spin-coated hard mask may be formed at a horizontal height in the vertical direction above the upper surface of the unit isolation layer 152 covering the first patterned insulating layer 144. For example, a layer comprising silicon oxynitride may be formed on the upper surface of the spin-coated hard mask. According to some embodiments, the fourth masking layer 156 may include a spin-coated hard mask.

[0068] Referring to Figures 6A and 6B, a second pattern opening 162 can be formed by providing a second unit pattern mask (not shown) on a fourth mask layer 156 and removing a portion of the fourth mask layer 156. Subsequently, a second pattern insulating layer 164 can be filled into the second pattern opening 162. According to some embodiments, the second pattern insulating layer 164 may comprise silicon oxide.

[0069] According to some embodiments, a second patterned opening 162 may be formed above or on a plurality of second active regions 106b not covered by the first patterned insulating layer 144. According to some embodiments, the second patterned insulating layer 164 may cover two adjacent second active regions 106b that are not covered by the first patterned insulating layer 144 among the plurality of second active regions 106b.

[0070] According to some embodiments, when the first patterned insulating layer 144 and the second patterned insulating layer 164 are projected onto the same plane, the patterned insulating layer distance da1 between the first patterned insulating layer 144 and the second patterned insulating layer 164 can be less than the first separation distance t1. Although FIG6B illustrates that the first patterned insulating layer 144 and the second patterned insulating layer 164 do not overlap each other in the vertical direction, the first patterned insulating layer 144 and the second patterned insulating layer 164 can also overlap each other in the vertical direction.

[0071] Referring to Figures 6A, 6B, 7A, and 7B, the first pattern insulating layer 144 and the second pattern insulating layer 164 can be removed via an etching process. In this case, at least some portions of the fourth masking layer 156, at least some portions of the third masking layer 154, at least some portions of the unit isolation layer 152, at least some portions of the first masking layer 136, and at least some portions of the interlayer insulating layer 134 can be removed simultaneously, and a second masking opening 172 can be formed. Therefore, the first masking layer 136, the third masking layer 154, the interlayer insulating layer 134, and the unit isolation layer 152 can be exposed.

[0072] According to some embodiments, from a plan view, a unit isolation layer 152 extending in the vertical direction (Z direction) can be arranged to surround a first masking layer 136 having a certain thickness (e.g., a first separation distance t1). According to some embodiments, a third masking layer 154 can be spaced apart from the first masking layer 136, wherein the unit isolation layer 152 is arranged between the third masking layer 154 and the first masking layer 136. For example, the first masking layer 136 and the third masking layer 154 can be spaced apart from each other by a first separation distance t1, the first separation distance t1 being the thickness of the unit isolation layer 152. According to some embodiments, from a plan view, the boundary of the third masking layer 154 can have a shape in which a portion of the third masking layer 154 is cut along the boundary of the first masking layer 136. For example, the boundary of the third masking layer 154 can have a shape that is recessed inward along the boundary of the first masking layer 136.

[0073] According to some embodiments, the second shielding opening 172 may pass through, penetrate, or extend through a portion of the interlayer insulation layer 134 in a vertical direction. For example, the upper surface of the second buffer layer 132 may not be exposed.

[0074] Referring to Figures 8A and 8B, the third shielding opening 182 can be formed by removing the cell isolation layer 152 exposed through the second shielding opening 172. In this case, the interlayer insulation layer 134 can be removed simultaneously, and thus a portion of the second buffer layer 132 can be exposed.

[0075] Referring also to Figures 8A, 8B and 9, some portions of the second buffer layer 132, some portions of the first conductive layer 124 and some portions of the first buffer layer 122 can be removed by using the first interlayer insulating layer 134, the unit isolation layer 152, the first mask layer 136 and the third mask layer 154 that define the third mask opening 182 as an etching mask to form a spare direct contact opening p184.

[0076] According to some embodiments, the spare direct contact opening p184 may pass through, penetrate, or extend through portions of the first top cover insulation layer 118, portions of the first active region 106a, and portions of the component isolation layer 104. According to some embodiments, the first active region 106a may be exposed via the spare direct contact opening p184.

[0077] Referring also to Figures 9, 10A, and 10B, the first interlayer insulating layer 134, unit isolation layer 152, first masking layer 136, third masking layer 154, and second buffer layer 132 can be removed to expose the upper surface of the first conductive layer 124 and form a direct contact opening 184. Therefore, a plurality of unit patterns CP can be defined, which define the direct contact opening 184 and have a column shape protruding from the lower surface 184L of the direct contact opening 184. For example, the plurality of unit patterns CP can be unetched portions covered by etch masks (e.g., the first interlayer insulating layer 134, unit isolation layer 152, first masking layer 136, and third masking layer 154) during the operation of forming the alternative direct contact opening p184 as described with reference to Figure 9. For example, the plurality of unit patterns CP can be the portion remaining after the first interlayer insulating layer 134, unit isolation layer 152, first mask layer 136, third mask layer 154 and second buffer layer 132 are removed from the self-etched mask (first interlayer insulating layer 134, unit isolation layer 152, first mask layer 136, third mask layer 154 and second buffer layer 132).

[0078] According to some embodiments, the first unit pattern CP1 and the second unit pattern CP2 may be spaced apart from each other by a first separation distance t1.

[0079] Figures 11A to 11C are cross-sectional views taken along line B-B' of Figure 1A to illustrate the manufacturing sequence of the integrated circuit element (100) following the manufacturing method described with reference to Figures 10A and 10B.

[0080] Referring to Figure 11A, a spare conductive layer 202 can be filled into the direct contact opening 184. Subsequently, a second conductive layer 204 and a second top cover insulating layer 206 can be formed sequentially. A direct contact shield 208 for forming the direct contact DC can be provided on the second top cover insulating layer 206.

[0081] Referring to Figure 11B, direct contacts DC and buried contact openings 212 can be formed by removing portions of the spare conductive layer 202, the first conductive layer 124, the second conductive layer 204, and the second top cover insulating layer 206 using a direct contact mask 208 as an etching mask. The buried contact opening 212 may include: a second sub-opening 212b, which is a space defined within the direct contact opening 184 by a plurality of unit patterns CP and direct contacts DC; and a first sub-opening 212a, which is a space defined on the first buffer layer 122 by the first conductive layer 124, the second conductive layer 204, and the second top cover insulating layer 206.

[0082] Referring to Figure 11C, after the insulating spacer 214 is filled into the second sub-opening 212b, the components for forming the bit line spacers are conformally coated on the exposed upper surface of the second top cover insulating layer 206, the upper surface of the insulating spacer 214, the side surface of the direct contact DC, and the side surfaces of the first conductive layer 124 and the second conductive layer 204. Subsequently, a recessed portion 218 exposing the upper surface of the second active region 106b can be formed by recessing the spaces between the multiple bit lines BL, thereby forming a portion covering the side surfaces of the bit lines BL and the side surfaces of the bit line spacers 216 of the second top cover insulating layer 206. Then, a conductive material can be used to fill the recessed spaces to form the buried contact BC.

[0083] Referring also to Figures 11C and 1B, according to some embodiments, conductive overlap pads 222 can be formed on the buried contact BC and the second top cover insulating layer 206, and then a plurality of overlap pad isolation patterns 224 can be formed between the plurality of adjacent conductive overlap pads 222. According to some embodiments, an overlap pad insulating layer 226 can be formed on the plurality of conductive overlap pads 222 and the plurality of overlap pad isolation patterns 224, and a through-hole plug 228 can be formed through, penetrating through, or extending through the overlap pad insulating layer 226. Subsequently, a capacitor 232 can be formed on the overlap pad insulating layer 226, and the capacitor 232 can be connected to the conductive overlap pad 222 via the through-hole plug 228.

[0084] As described above, exemplary embodiments have been shown in the drawings and description. Although specific terms have been used to describe embodiments herein, these terms are for illustrative purposes only and are not intended to limit the meaning or scope of the inventive concept as defined in the appended claims. While embodiments of the inventive concept have been specifically shown and illustrated with reference to them, it will be understood that various changes in form and detail may be made without departing from the scope of the following claims.

[0085] 100, 100a: Integrated circuit elements 102:Substrate 104: Component isolation layer 106a: First Active Region 106b: Second Active Region 112: Character line groove 114: Gate dielectric layer 116: Character Line 118: First Top Cover Insulation Layer 122: First Buffer Layer 124: First conductive layer 132: Second Buffer Layer 134: Interlayer insulation layer 136: First mask layer 138: Second masking layer 142: First pattern opening 144: First Pattern Insulating Layer 146: Second mask opening 152: Unit isolation layer 154: Third masking layer 156: Fourth masking layer 162: Second pattern opening 164: Second Pattern Insulating Layer 172: Second mask opening 182: Third mask opening 184: Opening of direct contact component 184L: Lower surface 202: Spare conductive layer 204: Second conductive layer 206: Second top cover insulation layer 208: Direct contact component shield 212: Opening of concealed contact component 212a: First child opens 212b: Second child opens 214: Insulating spacers 216: Bit line spacer 218: concave part 222: Conductive lap joint pad 224: Overlap joint pad isolation pattern 226: Overlap joint insulation layer 228: Through-hole plug 232: Capacitor a1: Distance of the first unit a2: Second unit distance A-A', B-B', C-C': lines ACT: Active Zone b2: Fourth unit distance BC: Concealed Contacts BL: Bitline CA: Concave portion CC1, CC2, CPSC: Center CP: Unit Pattern CP1: First unit pattern CP2: Second Unit Pattern CPG1: First Unit Group CPG2: Second Unit Group CPM1: First Unit Matrix CPM2: Second Unit Matrix CPS: Virtual Third Unit Pattern / Third Unit Pattern CPW: Side surface D1: Diagonal direction da1: Pattern insulation layer distance DAB1, DAB2: Distance DC: Direct contact component P: Area p184: Spare direct contact opening R1, R2: Rectangular layout t1: First separation distance WL: Character Line X, Y, Z: Direction

Claims

1. An integrated circuit element, comprising: The substrate has a first active region and a second active region spaced apart from the first active region; A component isolation layer is located between the first active region and the second active region; a direct contact is electrically connected to the first active region in a direct contact opening that extends through a portion of the first active region and a portion of the component isolation layer; a plurality of unit patterns having a column shape and extending from the lower surface of the direct contact opening on the second active region. And a concealed contact plug, extending through some portions of the plurality of unit patterns and electrically connected to the second active area, wherein the plurality of unit patterns include: a plurality of first unit groups arranged along a first horizontal direction and each of the plurality of first unit groups includes a plurality of first unit patterns arranged in a column along a second horizontal direction perpendicular to the first horizontal direction; And a plurality of second unit groups, spaced apart from the plurality of first unit groups and arranged along the first horizontal direction, and each of the plurality of second unit groups includes a plurality of second unit patterns arranged in a column along the second horizontal direction, wherein a corresponding side surface of the plurality of second unit patterns has a corresponding concave portion, the corresponding concave portion being recessed inward along a corresponding side surface of a plurality of first unit patterns adjacent to the corresponding second unit pattern of the plurality of second unit patterns, wherein the concave portion of the corresponding side surface of the plurality of second unit patterns is spaced apart from the plurality of first unit patterns adjacent to the plurality of second unit patterns by a first separation distance, and the plurality of first unit patterns and the plurality of second unit patterns are spaced apart from each other by at least the first separation distance.

2. The integrated circuit element as claimed in claim 1, wherein each of the side surfaces of the plurality of second unit patterns has two concave portions.

3. The integrated circuit element as claimed in claim 1, wherein in a plan view the plurality of first unit patterns and the plurality of second unit patterns surround each other, and at least two of the plurality of first unit patterns surrounding one of the plurality of second unit patterns are at different distances from the second unit pattern.

4. The integrated circuit element as claimed in claim 1, wherein the plurality of first cell patterns are equidistant from each other in the first horizontal direction and in the second horizontal direction to form a first cell matrix, wherein the plurality of second cell patterns are equidistant from each other in the first horizontal direction and in the second horizontal direction to form a second cell matrix intersecting the first cell matrix.

5. The integrated circuit element as claimed in claim 4, wherein, in a plan view, four of the plurality of second unit patterns surround one of the plurality of first unit patterns and are asymmetrical relative to the first unit pattern.

6. The integrated circuit element as claimed in claim 4, wherein the distance between adjacent first unit patterns in the plurality of first unit patterns is equal to the distance between adjacent second unit patterns in the plurality of second unit patterns.

7. The integrated circuit element as claimed in claim 1, wherein the planar area of ​​each of the plurality of second unit patterns is smaller than the planar area of ​​each of the plurality of first unit patterns.

8. The integrated circuit element as claimed in claim 1, wherein the plurality of unit patterns in a plan view surround the direct contact, and at least two of the plurality of unit patterns surrounding the direct contact are at different distances from the direct contact.

9. The integrated circuit element as described in claim 1, further comprising: Multiple character lines are located on the substrate and in multiple character line trenches extending in the first horizontal direction, wherein the multiple unit patterns overlap with some portions of the multiple character lines in the vertical direction.

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