Methods for fabricating diode wafers and wafers to be processed

Abstract

A method for fabricating a diode wafer and a wafer to be processed involves processing multiple raw wafers diced from a crystal ingot. First, it is determined whether the multiple raw wafers conform to a fabrication specification. If the raw wafers conform to the fabrication specification, they are designated as high-order raw wafers. If the raw wafers do not conform to the fabrication specification, they are designated as low-order raw wafers. Next, the proportion of low-order raw wafers with lattice orientation pit issues is calculated relative to the total number of low-order raw wafers, and it is determined whether this proportion is greater than a preset value. If the proportion is not greater than the preset value, a portion of the structure of each low-order raw wafer is removed, and the surface of each low-order raw wafer is smoothed. Finally, a diode structure is formed in the smoothed low-order raw wafers to obtain the diode wafer.

Description

Technical Field

[0001] This invention relates to a method for fabricating a wafer, and more particularly to a method for fabricating a diode wafer and a wafer to be processed. Prior Technology

[0002] In semiconductor manufacturing, wafers are made from ingots. First, a suitable material is selected to make the ingot. Common materials include silicon and gallium arsenide. The selected material is placed in a high-temperature furnace and melted. The temperature and gas conditions in the furnace need to be properly controlled to ensure that the material melts uniformly and reaches the required purity. A crystal called a "seed crystal" (usually single-crystal silicon) is gently placed into the molten material and slowly lifted. During the lifting process, the crystal grasps a seed from the molten material, forming a growing ingot. The ingot gradually cools during the ingot pulling process, forming a single-crystal structure. The cooling rate and temperature control during the process are crucial to the quality of the ingot, ensuring its purity and integrity. After the ingot cools, it is cut to form wafers of the desired diameter. This is usually done using a diamond blade or other cutting tools. The cut wafers undergo chemical or mechanical treatment to remove surface residues, contaminants, and defects, making the surface smooth and clean. Next, the wafer is polished to further improve surface smoothness and optical quality. Finally, the fabricated wafer is cleaned to remove any residue and contaminants. The wafer is then inspected and tested to ensure it meets specific quality standards.

[0003] In the semiconductor manufacturing industry, A-grade wafers and B-grade wafers define wafer quality and specifications. These definitions are typically agreed upon through negotiations between semiconductor manufacturers, international standards organizations, and customers. Generally, A-grade wafers have higher quality standards, such as surface flatness, wafer thickness uniformity, and lattice integrity. B-grade wafers have relatively lower quality standards and are typically used for general applications, not requiring very high performance and reliability. A-grade wafers have a lower defect density, meaning fewer defects on the wafer surface or within its volume. B-grade wafers may have a higher defect density, meaning more defects may exist on the wafer surface or within its volume. A-grade wafers have strict specification controls in terms of size, wafer thickness, wafer flatness, and lattice orientation to ensure process consistency and repeatability. B-grade wafers have relatively looser specification controls in terms of size, flatness, and lattice orientation, unlike A-grade wafers. Wafers to be processed generally include low-grade, mid-grade, and high-grade wafers. However, the price of higher-grade wafers often cannot be reduced in the market. For example, diode wafers include low-end, mid-end, and high-end diode wafers. Due to wafer pricing factors, many low-end diode wafers use inferior Grade A wafers, resulting in poor quality. Conversely, many mid-end diode wafers use superior Grade A wafers, but cannot compete with low-end and mid-end diode wafers due to substrate cost differences.

[0004] Therefore, the present invention addresses the aforementioned problems by proposing a method for fabricating a diode wafer and a wafer to be processed, thereby resolving the issues arising from conventional methods. Summary of the Invention

[0005] This invention provides a method for manufacturing diode wafers and wafers to be processed, which produces diode wafers and wafers to be processed of better quality at a lower cost.

[0006] In one embodiment of the present invention, a method for fabricating a diode wafer is provided, which processes multiple raw wafers obtained by slicing from a crystal ingot. The method for fabricating a diode wafer includes the following steps: determining whether the multiple raw wafers meet a fabrication specification; if yes, the raw wafers are designated as high-order raw wafers; and if no, the raw wafers are designated as low-order raw wafers, wherein there are multiple low-order raw wafers; calculating the proportion of the number of low-order raw wafers with crystal oriented pits (COP) related problems to the total number of low-order raw wafers, and determining whether this proportion is greater than a preset value; if yes, the process ends; and if no, removing a portion of the structure of each low-order raw wafer, wherein the portion of the structure has a fixed thickness; smoothing the surface of each low-order raw wafer whose structure has been removed; and forming multiple diode structures in each smoothed low-order raw wafer to obtain a diode wafer.

[0007] In one embodiment of the present invention, the manufacturing specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual concentration of metal particles, total thickness deviation, total indicator reading, wafer warpage, local total indicator reading and dust count.

[0008] In one embodiment of the present invention, defects include chipping, cracking, redundant laser markings, scratches, stains, and lattice cracks.

[0009] In one embodiment of the present invention, in the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer with a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

[0010] In one embodiment of the present invention, the surface of each low-order original wafer to which the structure is removed is sequentially etched and polished to smooth the surface of each low-order original wafer to which the structure is removed.

[0011] In one embodiment of the present invention, the surface of each low-order original wafer with the structure removed is sequentially subjected to grinding and polishing processes to smooth the surface of each low-order original wafer with the structure removed.

[0012] In one embodiment of the present invention, the method for fabricating a diode wafer further includes a step of roughening the surface of each low-order raw wafer that has been smoothed. In the step of forming a plurality of diode structures in each smoothed low-order raw wafer to obtain a diode wafer, a plurality of diode structures are formed in each roughened low-order raw wafer to obtain a diode wafer.

[0013] In one embodiment of the present invention, the surface of each low-order raw wafer that is smoothed is roughened by bench etching or spin etching.

[0014] In one embodiment of the present invention, the method for fabricating a diode wafer further includes the step of forming a metal conductive layer on the surface of the diode wafer.

[0015] In one embodiment of the present invention, the diode structure includes a doped well region, a first heavily doped region, and a second heavily doped region. The doped well region and the first heavily doped region have a first conductivity type, wherein the doped well region is located in a smoothed low-order original wafer. The first heavily doped region is located in the doped well region. The second heavily doped region has a second conductivity type opposite to the first conductivity type, wherein the second heavily doped region is located in the doped well region.

[0016] In one embodiment of the present invention, a method for fabricating a wafer to be processed includes processing multiple raw wafers obtained by slicing from a crystal ingot. The method for fabricating the wafer to be processed includes the following steps: determining whether the multiple raw wafers meet a fabrication specification; if yes, the raw wafers are designated as high-order raw wafers; and if no, the raw wafers are designated as low-order raw wafers, wherein there are multiple low-order raw wafers; calculating the proportion of the number of low-order raw wafers with crystal oriented pits (COP) related problems to the total number of low-order raw wafers, and determining whether this proportion is greater than a preset value; if yes, the process ends; and if no, removing a portion of the structure of each low-order raw wafer, wherein the portion of the structure has a fixed thickness; and smoothing the surface of each low-order raw wafer from which the structure has been removed to obtain the wafer to be processed.

[0017] In one embodiment of the present invention, the manufacturing specifications include resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual concentration of metal particles, total thickness deviation, total indicator reading, wafer warpage, local total indicator reading and dust count.

[0018] In one embodiment of the present invention, defects include chipping, cracking, redundant laser markings, scratches, stains, and lattice cracks.

[0019] In one embodiment of the present invention, in the step of removing a portion of the structure of each low-order original wafer, a low-order original wafer with a thickness greater than a preset value is selected, and a portion of the structure of each selected low-order original wafer is removed.

[0020] In one embodiment of the present invention, the surface of each low-order original wafer to which the structure is removed is sequentially etched and polished to smooth the surface of each low-order original wafer to which the structure is removed.

[0021] In one embodiment of the present invention, the surface of each low-order original wafer with the structure removed is sequentially subjected to grinding and polishing processes to smooth the surface of each low-order original wafer with the structure removed.

[0022] In one embodiment of the present invention, the method for manufacturing a wafer to be processed further includes the step of roughening the surface of each low-order raw wafer that has been smoothed.

[0023] In one embodiment of the present invention, the surface of each low-order raw wafer that is smoothed is roughened by bench etching or spin etching.

[0024] Based on the above, the method for fabricating diode wafers and wafers to be processed selects lower-quality raw wafers based on the presence of crystal oriented pits (COPs), thereby producing higher-quality diode wafers and wafers to be processed at a lower cost.

[0025] To enable your review committee to gain a better understanding of the structural features and effects achieved by the present invention, preferred embodiment diagrams and detailed descriptions are provided below: Simple Explanation of the Diagram

[0026] Figure 1 is a flowchart of one embodiment of the method for fabricating a diode wafer according to the present invention. Figure 2 is a structural cross-sectional view of one embodiment of the diode wafer of the present invention. Figure 3 is a flowchart of one embodiment of the method for manufacturing the wafer to be processed according to the present invention. Implementation

[0027] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0028] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0029] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0030] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element through other elements or connection means.

[0031] The disclosure is specifically described with reference to the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “the” include statements containing “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes statements of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0032] In the specification and claims, if the first element is described as being located on, above, connected to, joined to, coupled to, or connected to the second element, it indicates that the first element can be directly located on, directly connected to, directly joined to, or directly coupled to the second element, or that there are other elements between the first and second elements. Conversely, if the first element is described as being directly located on, directly connected to, directly joined to, directly coupled to, or directly connected to the second element, it indicates that there are no other elements between the first and second elements.

[0033] The following description provides a method for fabricating diode wafers and wafers to be processed, which selects lower-quality raw wafers based on crystal oriented pits (COP) related issues, thereby producing higher-quality diode wafers and wafers to be processed at a lower cost.

[0034] Figure 1 is a flowchart of one embodiment of the diode wafer fabrication method of the present invention. Referring to Figure 1, the following describes a diode wafer fabrication method that processes multiple raw wafers obtained by slicing from a crystal ingot. These wafers have undergone grinding, etching, and polishing processes to smooth their surfaces. Silicon wafers are used as an example of raw wafers, but the present invention is not limited thereto. First, as shown in step S10, it is determined whether the multiple raw wafers meet a fabrication specification. When the raw wafers meet the fabrication specification, as shown in step S12, the raw wafers are designated as high-order raw wafers. When the raw wafers do not meet the fabrication specification, as shown in step S14, the raw wafers are designated as low-order raw wafers. For example, the fabrication specification items may include, but are not limited to, resistance, defects, black film, color film, wafer thickness, wafer growth method, wafer size, wafer surface, residual metal particle concentration, total thickness deviation, total indicator reading, wafer warpage, local total indicator reading, and dust count. Defects may include chipping, cracks, redundant laser markings, scratches, stains, and lattice fractures, but this invention is not limited thereto. Total thickness deviation is defined as the difference between the maximum and minimum thickness of the wafer from the reference plane when the wafer is clamped tightly; it is generally expressed in micrometers (μm), typically in the form of ≤15μm. Total indication reading is defined as the difference between the maximum and minimum distances between the wafer surface and the reference plane when the wafer is clamped tightly, using the smallest surface formed by the sum of the intercepts of all points within the acceptable quality area of ​​the wafer surface as the reference plane. Wafer warpage is defined as the difference between the minimum and maximum distances between the wafer surface and the reference plane when the wafer is not clamped tightly, typically using the back side of the wafer as the reference plane. Wafer warpage includes concave and convex cases; concave warpage is negative, and convex warpage is positive; it is generally expressed in micrometers, typically in the form of ≤30μm. The local total indication reading is defined as the difference between the maximum and minimum distances between the wafer surface and the reference plane, measured when the wafer is clamped tightly, using the smallest plane formed by the sum of the intercepts of all points within a specified local area on the wafer surface as the reference plane. Table 1 provides a manufacturing specification. A raw wafer that does not meet one condition in the manufacturing specification is considered a low-order raw wafer. A raw wafer that meets all conditions in the manufacturing specification is considered a high-order raw wafer. Furthermore, a raw wafer with observed defects, black films, or color films is also considered a low-order raw wafer. A raw wafer without observed defects, black films, or color films is considered a high-order raw wafer. 6-inch wafer 8-inch wafer 12-inch wafer Wafer growth method Czochralski method wafer thickness 625±15 micrometers 725±25 micrometers 750±25 micrometers Wafer size – expressed in diameter 150 mm 200 mm 300 mm wafer surface Single-sided polishing (gloss finish) Single-sided roughening (matte finish) Single-sided polishing (gloss finish) Single-sided roughening (matte finish) Double-sided polishing (double gloss) Sodium metal particle residual concentration <5 10 / cm² Residual concentration of aluminum metal particles <5 10 / cm 2 Iron metal particle residual concentration <5 10 / cm 2 Residual concentration of nickel metal particles <5 10 / cm 2 Chromium metal particle residual concentration <5 10 / cm 2 Copper metal particle residual concentration <5 10 / cm 2 Zinc metal particle residual concentration <5 10 / cm 2 Residual concentration of calcium metal particles <5 10 / cm 2 Total thickness deviation Maximum 7 micrometers Total indicator reading ≤4 micrometers wafer warpage Maximum 50 micrometers Local total indication reading <1.5 micrometers Dust count ≥0.3 um ≥0.2 um <20 <30 resistance 10⁻⁴ to 10⁻³ ohms per centimeter Table 1

[0035] Generally, there are multiple low-order raw wafers obtained from cutting a crystal ingot. After step S14, step S18 is performed. In step S18, the proportion of low-order raw wafers with crystal oriented pits (COP) related problems to the total number of low-order raw wafers is calculated, and it is determined whether this proportion is greater than a preset value. Crystal oriented pits are not easily removed by etching, grinding, or polishing processes, and can be observed using tools such as optical microscopes or electron microscopes. A crystal oriented pit related problem is defined as the corresponding low-order raw wafer failing the COP specification test set by the inspection machine. For example, when the number of crystal oriented pits in a low-order raw wafer is greater than a preset value, this low-order raw wafer cannot pass the COP specification test set by the inspection machine. If the number of selected low-order raw wafers with crystal oriented pit related problems is 64, and the total number of selected low-order raw wafers is 100, the proportion is 0.64. The appearance of lattice orientation pits indicates the presence of unwanted holes during diode manufacturing and wafer etching. Diode fabrication requires processing on silicon wafers. During this process, the silicon wafer is used as a substrate for processes such as ion implantation and diffusion. Where there are holes, there is no silicon wafer present. Therefore, it cannot support the required processes, causing the diode's electrical properties to drift, resulting in defects and a decrease in yield. Furthermore, diode manufacturing sometimes requires drilling and filling with the necessary materials. Poor COP (Coefficient of Occurrence) can lead to excessive dust accumulation after drilling, causing problems in subsequent processes, further resulting in electrical property drift in the diode and defects, again leading to a decrease in yield. Therefore, a good silicon wafer substrate can help prevent material issues from lowering the overall process yield of the diode. In other words, when the proportion of selected low-order original wafers with lattice orientation pit problems exceeds a preset value, it indicates that the yield of diode wafers manufactured from this batch of low-order original wafers will decrease significantly, so the process proceeds to step S20, ending the entire process. When the proportion of selected low-order original wafers with lattice orientation pit problems does not exceed a preset value, it indicates that the yield of diode wafers manufactured from this batch of low-order original wafers will increase significantly, and the low-order original wafers are inexpensive and very valuable in the market. That is, if the judgment result in step S18 is negative, the process proceeds to step S22. In step S22, low-order original wafers with a thickness greater than a preset value are selected, and a portion of the structure of each selected low-order original wafer is removed, wherein this portion of the structure has a fixed thickness, thereby removing the observed lattice orientation pits. This fixed thickness depends on the depth of the observed lattice orientation pits.For example, if the observed lattice orientation pit is located at a depth of 7 micrometers from the surface, it means that the fixed thickness can be 7 micrometers.

[0036] Following step S22, step S24 is performed. In step S24, the surface of each low-order original wafer from which the structure is removed is smoothed to remove surface contaminants, chemical films, or scratches, achieving the desired surface smoothness and dust level. In some embodiments of the present invention, the surface of each low-order original wafer from which the structure is removed is sequentially etched and polished to smooth the surface. Alternatively, the surface of each low-order original wafer from which the structure is removed is sequentially ground and polished to smooth the surface.

[0037] After step S24, step S26 is performed. In step S26, the surface of each smoothed low-order raw wafer is roughened to improve the stability of the bonding metal layer. The surface of each smoothed low-order raw wafer can be roughened by bench etching or spin etching. Then, in step S28, a plurality of diode structures are formed in each roughened low-order raw wafer to obtain a diode wafer. Finally, as shown in step S30, a metal conductive layer is formed on the surface of the diode wafer, and the metal conductive layer serves as the electrode of the diode. After step S30, step S20 is performed. If substantially the same result can be obtained, these steps do not necessarily have to be performed in the order shown in Figure 1. Figure 2 is a structural cross-sectional view of an embodiment of the diode wafer 1 of the present invention. As shown in Figure 2, each diode structure 10 may include a doped well region 100, a first heavily doped region 102, and a second heavily doped region 104. The doped well region 100 and the first heavily doped region 102 have a first conductivity type, and the second heavily doped region 104 has a second conductivity type opposite to the first conductivity type. For example, when the first conductivity type is N-type, the second conductivity type is P-type. When the first conductivity type is P-type, the second conductivity type is N-type. The doped well region 100 is located in the roughened low-order raw wafer 11. The first heavily doped region 102 is located in the doped well region 100, and the second heavily doped region 104 is located in the doped well region 100. A metal conductive layer 12 is located on the surface of the roughened low-order raw wafer 11.

[0038] In the flowchart of Figure 1, the step of selecting low-order raw wafers with a thickness greater than a preset value can be omitted, so that step S22 removes a portion of the structure from each low-order raw wafer. Furthermore, step S26 can also be omitted. When step S26 is omitted, step S28 forms multiple diode structures in each smoothed low-order raw wafer to obtain a diode wafer. Step S30 can also be performed or omitted as needed. When step S30 is omitted, step S20 will proceed directly after step S28.

[0039] Figure 3 is a flowchart of one embodiment of the method for fabricating the wafer to be processed according to the present invention. Referring to Figure 3, the method for fabricating the wafer to be processed is described below, which involves processing multiple raw wafers obtained by slicing from a crystal ingot. These wafers have undergone grinding, etching, and polishing processes to smooth their surfaces. The raw wafers are silicon wafers as an example, but the present invention is not limited thereto. Steps S32, S34, S36, S40, S42, and S44 in Figure 3 are the same as steps S10, S12, S14, S18, S20, and S22 in Figure 1, and will not be repeated here. After step S44, step S46 is performed. In step S46, the surface of each low-order raw wafer where the smoothing structure has been removed is removed to obtain the wafer to be processed. Any semiconductor device, such as a diode or a microelectromechanical system (MEMS) device, can be formed on the wafer to be processed. In step S46, the surface of each low-order original wafer with the structure removed is sequentially etched and polished to smooth the surface of each low-order original wafer with the structure removed. Alternatively, the surface of each low-order original wafer with the structure removed is sequentially ground and polished to smooth the surface of each low-order original wafer with the structure removed. Next, step S48 is performed to roughen the smoothed surface of each low-order original wafer to improve the stability of the bonding metal layer. The smoothed surface of each low-order original wafer can be roughened using bench etching or spin etching. After step S48 is completed, step S42 is performed.

[0040] In the flowchart of Figure 3, the step of selecting low-order raw wafers with a thickness greater than a preset value can be omitted, so that step S44 removes a portion of the structure from each low-order raw wafer. Furthermore, step S48 can also be performed or omitted as needed. When step S48 is omitted, step S42 will proceed directly after step S46.

[0041] According to the above embodiments, the method for fabricating diode wafers and wafers to be processed selects lower-grade raw wafers of better quality based on lattice orientation pit related issues, thereby producing diode wafers and wafers to be processed of better quality at a lower cost.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

[0043] 1: Diode wafer 10: Diode Structure 100: Doped Well Zone 102: First doped region 104: Second doped region 11: Low-end raw wafers 12: Metal conductive layer S10, S12, S14, S18, S20, S22, S24, S26, S28, S30, S32, S34, S36, S40, S42: Steps

Claims

1. A method for fabricating a diode wafer, comprising processing multiple raw wafers obtained by slicing from a crystal ingot, the method comprising the following steps: determining whether the multiple raw wafers conform to a fabrication specification, wherein the fabrication specification includes at least one of defects, black film, color film, wafer thickness, wafer surface, total thickness deviation, and wafer warpage; if yes, classifying the raw wafer as a high-order raw wafer; and if no, classifying the raw wafer as a low-order raw wafer, wherein the number of the low-order raw wafers is multiple; calculating the proportion of the number of low-order raw wafers with crystal oriented pits (COP) related problems to the total number of the low-order raw wafers, and determining whether the proportion is greater than a preset value: If yes, end; and if no, select the low-order original wafer with a thickness greater than a preset value, and remove the portion of the structure with lattice orientation pit related problems in each of the selected low-order original wafers, wherein the portion of the structure has a fixed thickness, and the fixed thickness depends on the depth of the lattice orientation pit from the surface of the low-order original wafer; smooth the surface of each low-order original wafer from which the structure has been removed; and form a plurality of diode structures in each smoothed low-order original wafer to obtain a diode wafer.

2. The method for fabricating a diode wafer as described in claim 1, wherein the fabrication specifications further include resistance, wafer growth method, wafer size, residual metal particle concentration, total indicator reading, local total indicator reading, and dust count.

3. The method for fabricating a diode wafer as described in claim 2, wherein the defect includes chipping, cracking, excess laser markings, scratches, stains, and lattice cracks.

4. The method for fabricating a diode wafer as described in claim 1, wherein in the step of smoothing the surface of each low-order original wafer in which the structure is removed, the surface of each low-order original wafer in which the structure is removed is sequentially subjected to an etching process and a polishing process to smooth the surface of each low-order original wafer in which the structure is removed.

5. The method for fabricating a diode wafer as described in claim 1, wherein in the step of smoothing the surface of each low-order original wafer in which the structure is removed, a grinding process and a polishing process are sequentially performed on the surface of each low-order original wafer in which the structure is removed, so as to smooth the surface of each low-order original wafer in which the structure is removed.

6. The method for fabricating a diode wafer as described in claim 1 further includes the step of roughening the surface of each of the smoothed low-order original wafers, and in the step of forming the plurality of diode structures in each of the smoothed low-order original wafers to obtain the diode wafer, the plurality of diode structures are formed in each of the roughened low-order original wafers to obtain the diode wafer.

7. A method for fabricating a diode wafer as described in claim 6, wherein the surface of each of the smoothed low-order raw wafers is roughened by bench etching or spin etching.

8. The method for fabricating a diode wafer as described in claim 6 further includes the step of forming a metal conductive layer on the surface of the diode wafer.

9. A method for fabricating a diode wafer as claimed in claim 1, wherein the diode structure comprises: a doped well region having a first conductivity type, wherein the doped well region is located in the smoothed low-order original wafer; a first heavily doped region having the first conductivity type, wherein the first heavily doped region is located in the doped well region; and a second heavily doped region having a second conductivity type opposite to the first conductivity type, wherein the second heavily doped region is located in the doped well region.

10. A method for fabricating a wafer to be processed, comprising processing multiple raw wafers obtained by slicing from a crystal ingot, the method comprising the following steps: determining whether the multiple raw wafers conform to a fabrication specification, wherein the fabrication specification includes at least one of defects, black film, color film, wafer thickness, wafer surface, total thickness deviation, and wafer warpage; if yes, classifying the raw wafer as a high-order raw wafer; and if no, classifying the raw wafer as a low-order raw wafer, wherein the number of the low-order raw wafers is multiple; calculating the proportion of the number of low-order raw wafers with crystal oriented pits (COP) related problems to the total number of the low-order raw wafers, and determining whether the proportion is greater than a preset value: If yes, end; and if no, select the low-order raw wafer with a thickness greater than a preset value, and remove the portion of the structure with lattice orientation pit related problems in each of the selected low-order raw wafers, wherein the portion of the structure has a fixed thickness, and the fixed thickness depends on the depth of the lattice orientation pit from the surface of the low-order raw wafer; and smooth the surface of each low-order raw wafer from which the structure is removed, to obtain the wafer to be processed.

11. The method for fabricating a wafer as described in claim 10, wherein the fabrication specifications include resistance, wafer growth method, wafer size, residual metal particle concentration, total indicator reading, local total indicator reading, and dust count.

12. A method for manufacturing a wafer as described in claim 11, wherein the defect includes chipping, cracking, excess laser markings, scratches, stains, and lattice cracks.

13. The method for fabricating a wafer as described in claim 10, wherein in the step of smoothing the surface of each low-order original wafer from which the structure is removed, an etching process and a polishing process are sequentially performed on the surface of each low-order original wafer from which the structure is removed, so as to smooth the surface of each low-order original wafer from which the structure is removed.

14. The method for manufacturing a wafer to be processed as described in claim 10, wherein in the step of smoothing the surface of each low-order original wafer in which the structure is removed, a grinding process and a polishing process are sequentially performed on the surface of each low-order original wafer in which the structure is removed, so as to smooth the surface of each low-order original wafer in which the structure is removed.

15. The method for fabricating a wafer as described in claim 10 further includes a step of roughening the surface of each of the smoothed low-order raw wafers.

16. A method for fabricating a wafer as described in claim 15, wherein the surface of each of the smoothed low-order raw wafers is roughened by bench etching or spin etching.

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