Semiconductor device structure with air gap and method for preparing the same

Abstract

This disclosure provides a semiconductor device structure including a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is disposed above the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact is disposed above the first source / drain structure. The bit line contact includes a barrier layer in contact with the first source / drain structure and a conductive layer disposed above the barrier layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 241,057 (i.e., priority date "August 31, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device structure and a method for fabricating the semiconductor device structure. In particular, it relates to a semiconductor device structure having an air gap between adjacent source / drain structures and a method for fabricating the semiconductor device structure. Prior Technology

[0003] Due to its simple structure, Dynamic Random Access Memory (DRAM) can provide more memory cells per unit die area than other types of memory (such as Static Random Access Memory (SRAM)). DRAM consists of multiple DRAM cells, each including a capacitor for storing information and a transistor coupled to the capacitor to regulate when it charges or discharges. During a read operation, the word line (WL) is established to turn on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via the bit line (BL). During a write operation, the data to be written is provided on the BL, and the WL is established.

[0004] To meet the demand for larger memory storage, the size of DRAM memory cells has been continuously reduced, leading to a significant increase in the packaging density of DRAM. However, as the size requirements for DRAM memory cells continue to shrink, capacitive coupling is becoming an increasingly important problem leading to an increase in parasitic capacitance. This undesirably reduces the speed of the DRAM memory cells, thus negatively impacting the overall device performance.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is disposed above the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact is disposed above the first source / drain structure. The bit line contact includes a barrier layer in contact with the first source / drain structure and a conductive layer disposed above the barrier layer.

[0007] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first fin structure, a first source / drain structure, a second source / drain structure, a third source / drain structure, a first word line, and a second word line. The first fin structure is disposed on a semiconductor substrate and includes a first channel region, a second channel region, and other regions. The first source / drain structure, the second source / drain structure, and the third source / drain structure are disposed above the first fin structure. The first word line is disposed between the first source / drain structure and the second source / drain structure, and spans the first channel region of the first fin structure from a top view of the semiconductor device structure. The second word line is disposed between the second source / drain structure and the third source / drain structure, and spans the second channel region of the first fin structure from the top view. A width of the first channel region is equal to a width of the second channel region, and the width of the first channel region is smaller than a width of the other region of the first fin structure.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate; forming an isolation structure over the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; partially removing the first fin structure and the second fin structure to form a first recess of the first fin structure and a second recess of the second fin structure; epitaxially growing a first source / drain structure over the first recess and epitaxially growing a second source / drain structure over the second recess, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; partially removing the isolation structure through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; and forming a contact etching. A terminating layer is formed above the first source / drain structure and the second source / drain structure to form and seal an air gap in the first opening and the second opening; an interlayer dielectric structure is formed above the contact etch terminating layer; a portion of the interlayer dielectric structure above the first source / drain structure and a portion of the contact etch terminating layer above the first source / drain structure are removed to form a third opening, wherein the third opening exposes the first source / drain structure; an anisotropic deposition process is performed to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion in contact with the first source / drain structure and a side portion in contact with the dielectric structure of the layer; and a conductive layer is formed above the barrier layer, wherein the barrier layer and the conductive layer are configured to form a bit line contact point.

[0009] Embodiments of a semiconductor device structure are provided according to some embodiments disclosed herein. The semiconductor device structure includes a first word line spanning a first fin structure and a second fin structure, a first source / drain structure located above the first fin structure, and a second source / drain structure located above the second fin structure. The first source / drain structure and the second source / drain structure are formed adjacent to the first word line, and an air gap is formed between the first and second source / drain structures. Therefore, the capacitance between adjacent source / drain structures (i.e., the first and second source / drain structures) can be reduced. As a result, the operating speed of the semiconductor device structure can be improved, and the overall device performance can be improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be understood that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0012] Figure 1 is a top view schematic diagram illustrating the semiconductor element structure of some embodiments disclosed herein.

[0013] Figure 2 is a cross-sectional schematic diagram illustrating the semiconductor device structure along section line I-I' in Figure 1 of some embodiments of this disclosure.

[0014] Figure 3 is a flowchart illustrating a method for fabricating semiconductor device structures according to some embodiments of this disclosure.

[0015] Figure 4 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0016] Figure 5 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0017] Figure 6 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0018] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0019] Figure 8 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0020] Figure 9 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0021] Figure 10 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0022] Figure 11 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0023] Figure 12 is a cross-sectional schematic diagram illustrating the semiconductor device structure of some other embodiments of this disclosure.

[0024] Figure 13 is a top view schematic diagram illustrating the semiconductor element structure of some different embodiments disclosed herein. Implementation

[0025] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0026] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0027] Figure 1 is a top view schematic diagram illustrating a semiconductor device structure 100 according to some embodiments of the present disclosure. As shown in Figure 1, according to some embodiments, the semiconductor device structure 100 includes a plurality of fin structures 111a, 111b, and 111c, which are active regions of the semiconductor device structure 100. The fin structures 111a, 111b, and 111c are parallel to each other and extend along the X direction. It should be understood that in this embodiment, the semiconductor device structure 100 is a dynamic random access memory (DRAM).

[0028] Furthermore, according to some embodiments, as shown in FIG1, the semiconductor device structure 100 also includes a plurality of word lines 161a, 161b, 161c and 161d. The word lines 161a to 161d are parallel to each other and extend along the Y direction. In some embodiments, the word line 161a is a gate structure extending across the fin structures 111a to 111c.

[0029] Additionally, in some embodiments, fin structures 111a to 111c include multiple recesses exposed (i.e., uncovered) by character lines 161a to 161d. As shown in FIG1, source / drain (S / D) structures 121a, 121b, 121c, 121d, and 121e are disposed above the recesses of fin structure 111a, source / drain structures 121f, 121g, 121h, 121i, and 121j are disposed above the recesses of fin structure 111b, and source / drain structures 121k, 121l, 121m, 121n, and 121o are disposed above the recesses of fin structure 111c. It should be understood that, for the sake of simplicity, FIG1 only shows some of the recesses of fin structures 111a, 111b, and 111c. For example, the source / drain structure 121c is disposed above the recess 111a' of the fin structure 111a, the source / drain structure 121g is disposed above the recess 111b' of the fin structure 111b, and the source / drain structure 121m is disposed above the recess 111c' of the fin structure 111c.

[0030] The semiconductor device structure 100 also includes bit line contacts 151a, 151b, 151c, and 151d respectively disposed above source / drain structures 121c, 121f, 121j, and 121m, and deep trench capacitors 171a, 171b, 171c, 171d, 171e, and 171f are covered by word lines 161a to 161d. In some embodiments, each of the bit line contacts 151a, 151b, 151c, and 151d has a circular outline when viewed from a top view. In some embodiments, the bit line contacts 151a to 151d are used to electrically connect the underlying source / drain structures 121c, 121f, 121j, and 121m to the bit lines above, which are not shown in FIG1 for simplicity and clarity.

[0031] In some embodiments, deep trench capacitor 171a is located at the intersection of word line 161a and fin structure 111a, deep trench capacitor 171b is located at the intersection of word line 161d and fin structure 111a, deep trench capacitor 171c is located at the intersection of word line 161b and fin structure 111b, deep trench capacitor 171d is located at the intersection of word line 161c and fin structure 111b, deep trench capacitor 171e is located at the intersection of word line 161a and fin structure 111c, and deep trench capacitor 171f is located at the intersection of word line 161d and fin structure 111c. In some embodiments, each of the deep trench capacitors 171a and 171f is embedded in one of the fin structures 111a to 111c. Furthermore, deep trench capacitors 171a to 171f may extend to the semiconductor substrate 101 beneath the fin structures 111a to 111c (as shown in FIG. 2).

[0032] It should be understood that, according to some embodiments, referring to the source / drain structures 121a to 121e above the recess of fin structure 111a in FIG1, source / drain structures 121a and 121e are virtual source / drain structures and are not electrically connected to other elements or components, source / drain structure 121b is electrically connected to deep trench capacitor 171a, source / drain structure 121c is electrically connected to the upper bit line via bit line contact point 151a, and source / drain structure 121d is electrically connected to deep trench capacitor 171b.

[0033] Furthermore, according to some embodiments, referring to the source / drain structures 121f to 121j above the recess of the fin structure 111b in FIG1, the source / drain structure 121f is electrically connected to the upper bit line via bit line contact point 151b, the source / drain structure 121g is electrically connected to the deep trench capacitor 171c, the source / drain structure 121h is a virtual source / drain structure and is not electrically connected to other elements or components, the source / drain structure 121i is electrically connected to the deep trench capacitor 171d, and the source / drain structure 121j is electrically connected to the upper bit line via bit line contact point 151c.

[0034] Furthermore, the arrangement of source / drain structures 121k to 121o above the recess of fin structure 111c is similar to the arrangement of source / drain structures 121a to 121e. According to some embodiments, as shown in FIG1, source / drain structures 121k and 121o are virtual source / drain structures and are not electrically connected to other elements or components, source / drain structure 121l is electrically connected to deep trench capacitor 171e, source / drain structure 121m is electrically connected to the upper bit line via bit line contact point 151d, and source / drain structure 121n is electrically connected to deep trench capacitor 171f.

[0035] Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor element structure 100 along section line I-I' in Figure 1 according to some embodiments of the present disclosure. According to some embodiments, as shown in Figure 2, an isolation structure 113” is disposed above the semiconductor substrate 101, and recesses 111a', 111b' and 111c' of fin structures 111a, 111b and 111c protrude from the isolation structure 113”.

[0036] In some embodiments, source / drain structures 121c, 121h, and 121m are disposed above recesses 111a', 111b', and 111c', forming a contact etch stop layer (CESL) 131 to cover source / drain structures 121c, 121h, and 121m and isolation structure 113", and multiple air gaps are formed between adjacent source / drain structures. For example, as shown in Figures 1 and 2, according to some embodiments, air gap 134a is formed between source / drain structures 121c and 121h, and air gap 134b is formed between source / drain structures 121h and 121m.

[0037] Although only the three source / drain structures 121c, 121h, 121m of the semiconductor element structure 100 and the three recesses 111a', 111b', 111c' of the fin structures 111a, 111b, 111c are shown, it should be understood that the structure and configuration of the other source / drain structures and other recesses of the fin structures may be similar to or the same as the source / drain structures 121c, 121h, 121m and the recesses 111a', 111b', 111c'.

[0038] In some embodiments, each air gap 134a and 134b is surrounded by a contact etch-stop layer 131 and is pentagonal in the cross-sectional view of FIG2, and the air gaps 134a and 134b are partially covered by source / drain structures 121c, 121h and 121m. In some embodiments, the air gap 134a has a highest point P, and the source / drain structure 121c has a maximum width Wm1, wherein the portion of the source / drain structure 121c with the maximum width Wm1 is located above the highest point P of the air gap 134a. In some embodiments, the recess 111a' of the fin structure 111a has an upper surface S1 and an interface S2. The upper surface S1 is positioned above a portion of the air gap 134a having a maximum width Wm2. The interface S2 is located at the interface S2 between the isolation structure 113” and the source / drain structure 121c and is positioned above that portion of the air gap 134a having a maximum width Wm2. The details of the air gap 134b may be similar to or the same as the details of the air gap 134a, and will not be described again here.

[0039] Additionally, an interlayer dielectric (ILD) structure 141 is disposed on the semiconductor substrate 101. The ILD structure 141 is disposed above the contact etch-stop layer 131 and forms bit line contact points 151a and 151d to penetrate the ILD structure 141 and the contact etch-stop layer 131 to directly contact the source / drain structures 121c and 121m, respectively. Although only two air gaps 134a and 134b are shown in Figures 1 and 2, the semiconductor device structure 100 may include more than two air gaps. For example, a gap may exist between the source / drain structures 121b and 121g (refer to Figure 1). It should be understood that the air gap may be arranged along the Y direction between adjacent source / drain structures, and the Y direction is parallel to the longitudinal direction of word lines 161a to 161d.

[0040] Figure 3 is a flowchart illustrating a method 10 for fabricating a semiconductor device structure 100 according to some embodiments of this disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, and S21. Steps S11 to S21 of Figure 3 will be described in detail with reference to Figures 4 to 10.

[0041] Figure 4 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0042] As shown in Figure 4, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0043] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a block of semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using oxygen implantation separation (SIMOX), wafer bonding, and / or other suitable methods.

[0044] In some embodiments, a dielectric layer (not shown) is disposed above a semiconductor substrate 101, a mask layer (not shown) is disposed above the dielectric layer, and a patterned photoresist layer (not shown) is disposed above the mask layer. The fabrication technique for the patterned photoresist layer may include a deposition process and a patterning process.

[0045] The deposition process for forming a patterned photoresist layer may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, a sputtering process, or other suitable processes. The patterning process for forming the patterned photoresist layer may include a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0046] Furthermore, the dielectric layer may be a buffer layer between the semiconductor substrate 101 and the mask layer. In some embodiments, the dielectric layer is used as a termination layer when the mask layer is removed. The dielectric layer may include silicon oxide. The mask layer may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The fabrication techniques for the dielectric layer and the mask layer may include multiple deposition processes, which may include a CVD process, an HDPCVD process, a spin coating process, a sputtering process, or other suitable processes.

[0047] As shown in Figure 4, according to some embodiments, after forming a patterned photoresist layer, the patterned photoresist layer is used as a mask to pattern the dielectric layer and the mask layer. Thus, a patterned dielectric layer 103 and a patterned mask layer 105 are obtained. Next, the patterned photoresist layer is removed.

[0048] Next, an etching process is performed on the semiconductor substrate 101 using a patterned dielectric layer 103 and a patterned mask layer 105 as a mask to form fin structures 111a, 111b, and 111c. The corresponding step is shown as step S11 in fabrication method 10 shown in FIG3. The etching process can be a dry etching process or a wet etching process. After the etching process used to form fin structures 111a to 111c, the fin structures 111a to 111c are separated by openings 108a and 108b.

[0049] In some embodiments, the semiconductor substrate 101 is etched using a dry etching process. The dry etching process includes using a fluorine-based etching gas, such as SF6, CxFy, NF3, or a combination thereof. The etching process can be a time-controlled process and can continue until the fin structures 111a to 111c reach a predetermined height. In some embodiments, each of the fin structures 111a to 111c has a width that gradually increases from top to bottom.

[0050] Figure 5 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure along section line I-I' in Figure 1, according to some embodiments of this disclosure.

[0051] According to some embodiments, after forming fin structures 111a to 111c, an insulating material (not shown) is formed to cover the fin structures 111a to 111c, the patterned dielectric layer 103, and the patterned masking layer 105 above the semiconductor substrate 101. In other words, according to some embodiments, openings 108a and 108b are filled with the insulating material. In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), or other low-k dielectric materials. The insulating material can be deposited by a CVD process, a spin-coating glass process, or other suitable processes.

[0052] Next, the insulating material is thinned or planarized to expose the upper surface of the patterned mask layer 105. In some embodiments, the insulating material is thinned by a chemical mechanical polishing (CMP) process. Next, the patterned dielectric layer 103 and the patterned mask layer 105 are removed.

[0053] As shown in Figure 5, according to some embodiments, after removing the patterned dielectric layer 103 and the patterned masking layer 105, an upper portion of the insulating material is removed to form an isolation structure 113. The corresponding step is shown as step S13 in the fabrication method 10 shown in Figure 3. The isolation structure 113 may be a shallow trench isolation (STI) structure surrounding the fin structures 111a to 111c. In some embodiments, the lower portions of openings 108a and 108b are each filled by the isolation structure 113, and openings 114a and 114b are disposed above the isolation structure 113 and between adjacent fin structures 111a, 111b, and 111c.

[0054] In some embodiments, portions of fin structures 111a to 111c are embedded in isolation structure 113. In some embodiments, the lower portions of each of fin structures 111a to 111c are surrounded by isolation structure 113, while the upper portions of each of fin structures 111a to 111c protrude from isolation structure 113. Isolation structure 113 is used to prevent electrical interference or crosstalk.

[0055] Figure 6 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0056] According to some embodiments, as shown in FIG6, after the isolation structure 113 is formed, character lines 161a to 161d (refer to FIG1) are provided across fin structures 111a to 111c and extend above the isolation structure 113. Multiple portions of fin structures 111a to 111c exposed (i.e., not covered) by character lines 161a to 161d are partially removed to form recesses in the fin structures, such as recess 111a' of fin structure 111a, recess 111b' of fin structure 111b, and recess 111c' of fin structure 111c. The corresponding step is shown as step S15 in the preparation method 10 shown in FIG3.

[0057] In some embodiments, word lines 161a to 161d are multiple gate structures disposed across fin structures 111a to 111c. During this step, multiple dummy gate structures are formed on word lines 161a to 161d. After the contact etch stop layer 131 and the interlayer dielectric structure 141 are formed in subsequent processes, these dummy gate structures will be replaced by gate structures (i.e., metal gate structures).

[0058] In some embodiments, multiple portions of the adjacent character lines 161a to 161d of the recessed fin structures 111a, 111b, and 111c are used to form recesses (e.g., recesses 111a', 111b', and 111c') on both sides of the fin structures 111a, 111b, and 111c. In some embodiments, the upper portions of the isolation structures 113 are removed during the recessed fin structures 111a, 111b, and 111c, such that the recesses 111a', 111b', and 111c' protrude from a recessed isolation structure 113'.

[0059] In some embodiments, the recessed isolation structure 113' has a protrusion 113p1 adjacent to the recesses 111a', 111b', and 111c' of the fin structures 111a, 111b, and 111c, and the protrusion 113p1 has a concave surface. In some embodiments, the recesses 111a', 111b', and 111c' have an upper surface Sl exposed (i.e., uncovered) by the recessed isolation structure 113' and a sidewall SWl.

[0060] Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0061] Next, source / drain structures 121a to 121o are epitaxially grown above the recesses of fin structures 111a, 111b, and 111c. For example, according to some embodiments, as shown in FIG7, source / drain structures 121c, 121h, and 121m are disposed above the recesses 111a', 111b', and 111c' of fin structures 111a to 111c. The corresponding step is shown as step S17 in preparation method 10 shown in FIG3. It should be understood that in some embodiments, source / drain structures 121a to 121o are separated from each other. That is, source / drain structures 121a to 121o are not connected to each other or are not merged together.

[0062] In some embodiments, as shown in FIG7, according to some embodiments, the source / drain structure 121c is separated from the source / drain structure 121h by a first opening 124a1, and the source / drain structure 121h is separated from the source / drain structure 121m by another first opening 124b1. In some embodiments, the upper boundaries of the first openings 124a1 and 124b1 are defined as being aligned with the position of the maximum width of the adjacent source / drain structure, for example, the maximum value of Wm1 of the source / drain structure 121c, and the width of each of the first openings 124a1 and 124b1 increases from the upper part to the lower part. Furthermore, a dashed line extending from the upper boundaries of the first openings 124a1 and 124b1 also divides the source / drain structure 121c into an upper part and a lower part. The lower part 121c of the source / drain structure covers a portion of the upper surface S1 and the sidewall SW1. The upper part of the source / drain structure 121c has a triangular profile, namely a main side as shown by the dashed line in Figure 7, and two sub-sides. The main side is coupled to the lower part of the source / drain structure 121c, and the sub-sides have the same length.

[0063] In some embodiments, a strained material is grown over the recesses of fin structures 111a, 111b, and 111c via an epitaxial (epiped) process to form source / drain structures 121a to 121o. Furthermore, the lattice constant of the strained material may differ from the lattice constant of the semiconductor substrate 101. In some embodiments, the material of the source / drain structures 121a to 121o includes Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like.

[0064] Figure 8 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0065] As shown in Figure 8, according to some embodiments, after the epitaxial growth of the source / drain structures 121a to 121o, the upper portion of the recessed isolation structure 113' is removed to form an isolation structure 113" which is a remainder of the recessed isolation structure 113'. In some embodiments, the recessed isolation structure 113' is partially removed via first openings 124a1 and 124b1 to form second openings 124a2 and 124b2 in the isolation structure 113". The corresponding step is shown as step S19 in the fabrication method 10 shown in Figure 3.

[0066] In some embodiments, partial removal of the recessed isolation structure 113' includes a wet etching process, a dry etching process, or a combination thereof. Following the etching process, second openings 124a2 and 124b2 are formed below the first openings 124a1 and 124b1 and between the protrusions 113p2 of the isolation structure 113', wherein the protrusions 113p2 are located below the protrusions 113p1. In some embodiments, the width of each of the second openings 124a2 and 124b2 decreases from top to bottom. Furthermore, the protrusions 113p2 of the isolation structure 113' have sidewalls SW2 exposed through the second openings 124a2 and 124b2.

[0067] Figure 9 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0068] Next, a contact etch termination layer 131 is disposed over the source / drain structures 121a to 121o to form and seal multiple air gaps in the first and second openings. For example, according to some embodiments, air gaps 134a and 134b are formed as shown in FIG9. The corresponding step is shown as step S21 in the fabrication method 10 shown in FIG3.

[0069] In some embodiments, a contact etch-stop layer 131 is formed to cover the sidewalls SW2 of the isolation structure 113”, wherein the sidewalls SW2 are exposed through the second openings 124a2 and 124b2, and the contact etch-stop layer 131 also covers the sidewalls of the source / drain structures 121a to 121o. As a result, in the cross-sectional view of FIG9, the air gaps 134a and 134b are surrounded by the contact etch-stop layer 131. In some embodiments, the contact etch-stop layer 131 comprises silicon nitride, silicon oxynitride, and / or other suitable materials. Furthermore, according to some embodiments, the fabrication techniques of the contact etch-stop layer 131 include plasma-enhanced CVD, low-pressure CVD, atomic layer deposition (ALD), or other suitable processes.

[0070] In some embodiments, each of the air gaps 134a and 134b has a highest point P, a leftmost point, and a rightmost point. The highest point P is below the upper part of the source / drain structure 121c and above the upper surface S1 of the fin structure 111a. The leftmost and rightmost points are flush. Furthermore, the leftmost and rightmost points are below the highest point of the protrusion 113p1 of the upper surface S1 and the isolation structure 113".

[0071] After the contact etch stop layer 131 is formed, an interlayer dielectric structure 141 is disposed above the contact etch stop layer 131. The interlayer dielectric structure 141 is disposed on the semiconductor substrate 101. It should be understood that in this embodiment, since the air gaps 134a and 134b are sealed by the contact etch stop layer 131, the interlayer dielectric structure 141 is not deposited into the air gaps 134a and 134b. In some embodiments, the interlayer dielectric structure 141 comprises a multilayer made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), and polyimide. Furthermore, the fabrication techniques for the interlayer dielectric structure 141 may include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0072] Figure 10 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element structure 100 along the cross-section I-I' in Figure 1, according to some embodiments of this disclosure.

[0073] After forming the interlayer dielectric structure 141, the interlayer dielectric structure 141 and the contact etch stop layer 131 are partially removed to form a plurality of contact openings exposing the underlying source / drain structures. These structures are designed to be electrically connected to subsequently formed bit lines. For example, as shown in FIG10, according to some embodiments, contact openings 148a and 148b are formed to expose source / drain structures 121c and 121m, respectively. In some embodiments, the interlayer dielectric structure 141 and the contact etch stop layer 131 are partially removed by an etch process, such as a dry etch process.

[0074] Next, bit line contacts 151a to 151d are formed in a plurality of contact openings surrounded by the contact etch-stop layer 131 and the interlayer dielectric structure 141, for example, according to some embodiments, bit line contacts 151a to 151d as shown in the cross-sectional view of FIG2.

[0075] In some embodiments, each of the bit line contacts 151a to 151d comprises a multilayer. In some embodiments, the material of the bit line contacts 151a to 151d includes polycrystalline silicon, tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), cobalt (Co), cobalt silicon, titanium silicon, tantalum silicon, nickel silicon, copper silicon, tungsten silicon, molybdenum silicon, other suitable conductive materials, or combinations thereof.

[0076] Additionally, in some embodiments, deep trench capacitors 171a to 171f are formed after the fin structures 111a to 111c are formed. In some embodiments, the deep trench capacitors 171a to 171f are formed before the formation of the dummy gate structure, which is used to form word lines 161a to 161d. In some embodiments, the semiconductor device structure 100 is a DRAM, and the bit line contacts 151a to 151d are used to form a vertical electrical connection between the underlying source / drain structure and the upper bit lines.

[0077] Embodiments of a semiconductor device structure and a method for fabricating the same are provided. The semiconductor device structure 100 includes word lines 161a to 161d spanning fin structures 111a to 111c, source / drain structures 121a to 121o disposed above and adjacent to the recesses (e.g., recesses 111a', 111b', and 111c') of the fin structures 111a to 111c, and source / drain structures 121a to 121o. Air gaps (e.g., air gaps 134a and 134b) are formed between adjacent source / drain structures (e.g., source / drain structures 121c, 121h, and 121m) along a direction parallel to the longitudinal direction of the word lines 161a to 161d. Because the air gaps are formed between adjacent source / drain structures and extend into the adjacent recesses of the fin structures 111a to 111c, the capacitance between adjacent source / drain structures can be reduced. As a result, the operating speed of the semiconductor device structure 100 can be increased, and the overall device efficiency can be improved.

[0078] The semiconductor device structure 100 described above is provided for illustrative purposes, and this disclosure is not limited thereto. For example, in other embodiments, the bit line contacts 151a to 151d of the semiconductor device structure 100 may be replaced by other structures, such as the semiconductor device structure 200 shown in FIG. 12.

[0079] Please refer to Figures 11 and 12. Figure 11 is a cross-sectional schematic diagram illustrating an intermediate stage in forming a semiconductor device structure 200 according to some other embodiments of this disclosure. Figure 12 is a cross-sectional schematic diagram illustrating a semiconductor device structure 200 according to some other embodiments of this disclosure.

[0080] In some embodiments, the semiconductor device structure 200 can be formed using the formation shown in Figures 4 to 10 prior to the formation of the bit line contacts. Therefore, for simplicity, the formation details prior to the bit line contacts of the semiconductor device structure 200 are omitted.

[0081] In Figure 11, a barrier layer 251a and a barrier layer 251d are formed in contact openings 148a and 148d, respectively. Although only barrier layers 251a and 251d are described, it should be understood that barrier layers 251b and 251c are also formed in contact openings 148b and 148c, respectively.

[0082] Barrier layer 251a and barrier layer 251d are identical; therefore, for simplicity, only barrier layer 251 will be discussed below. In some embodiments, barrier layer 251a is formed to cover the sidewalls of contact opening 148a and the exposed surface of source / drain structure 121c. In other words, a portion of contact opening 148a is filled by barrier layer 251a, thus shrinking contact opening 148a into opening 149a. Similarly, after forming barrier layer 251d, contact opening 148d shrinks into opening 149d.

[0083] The barrier layer 251a includes a lower portion and two side portions (e.g., a left side portion and a right side portion), with the lower portion connecting the left side portion to the right side portion. The lower portion contacts the source / drain structure 121c and the contact etch stop layer 131, and the left and right side portions each contact the interlayer dielectric structure 141. In some embodiments, a thickness W1 of the lower portion differs from a thickness W2 of the side portions. In some embodiments, the thickness W1 is greater than the thickness W2.

[0084] In some embodiments, the barrier layer 251a includes titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0085] In some embodiments, the fabrication technique for the barrier layer 251a includes an anisotropic deposition process, such that the thickness W1 is greater than the thickness W2. In some embodiments, the anisotropic deposition process for forming the barrier layer 251a includes a physical vapor deposition (PVD) process.

[0086] After forming barrier layers 251a to 251d, conductive layers 252a to 252d are formed in openings 149a to 149d, respectively.

[0087] As shown in Figure 12, openings 149a and 149d are completely filled by conductive layers 252a and 252d, respectively. Conductive layer 252a is separated from source / drain structure 121c and interlayer dielectric structure 141, and conductive layer 252d is separated from source / drain structure 121d and interlayer dielectric structure 141.

[0088] In some embodiments, conductive layer 252a and conductive layer 252d comprise tungsten (W).

[0089] The barrier layer 251a and the conductive layer 252b together form a bit line contact 252. In some embodiments, the bit line contact 252 is a hole-free contact. In some embodiments, the hole-free contact has better conductivity than the porous contact. Therefore, when the semiconductor device structure 200 has a hole-free contact for transmitting electronic signals, the semiconductor device structure 200 can have better performance.

[0090] Please refer to Figure 13. Figure 13 is a top view schematic diagram illustrating a semiconductor element structure 300 of some different embodiments of this disclosure.

[0091] Except for the configuration of the fin structures, the semiconductor element structure 300 is similar to the semiconductor element structure 100 shown in FIG. 1. As shown in FIG. 13, the semiconductor element structure 300 includes fin structures 311a, 311b, and 311c that are different from the fin structures 111a, 111b, and 111c of the semiconductor element structure 100. It should be understood that the other elements of the semiconductor element structure 300 are the same as those of the semiconductor element structure 100.

[0092] In different embodiments, each channel region of fin structures 311a, 311b and 311c has a narrower width than other regions of fin structures 311a, 311b and 311c.

[0093] In some embodiments, from a top view of the semiconductor element structure 300, the channel regions CH1 and CH2 of the fin structure 311a are narrower than other regions of the fin structure 311a; therefore, the channel regions CH1 and CH2 of the fin structure 311a are narrower than other regions of the fin structure 311a; the channel regions CH3 and CH4 of the fin structure 311b are narrower than other regions of the fin structure 311b; and the channel regions CH5 and CH6 of the fin structure 311c are narrower than other regions of the fin structure 311c.

[0094] Although the semiconductor device structures 200 and 300 described above have their own different features, semiconductor device structure 200 may include the features of semiconductor device structure 300, and semiconductor device structure 300 may include the characteristics of semiconductor device structure 200.

[0095] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a first fin structure, a first source / drain structure, and a bit line contact. The first fin structure protrudes from the semiconductor substrate and has a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall. The first source / drain structure is disposed above the first fin structure and covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall. The bit line contact is disposed above the first source / drain structure. The bit line contact includes a barrier layer in contact with the first source / drain structure and a conductive layer disposed above the barrier layer.

[0096] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a first fin structure, a first source / drain structure, a second source / drain structure, a third source / drain structure, a first word line, and a second word line. The first fin structure is disposed on a semiconductor substrate and includes a first channel region, a second channel region, and other regions. The first source / drain structure, the second source / drain structure, and the third source / drain structure are disposed above the first fin structure. The first word line is disposed between the first source / drain structure and the second source / drain structure, and spans the first channel region of the first fin structure from a top view of the semiconductor device structure. The second word line is disposed between the second source / drain structure and the third source / drain structure, and spans the second channel region of the first fin structure from the top view. A width of the first channel region is equal to a width of the second channel region, and the width of the first channel region is smaller than a width of the other region of the first fin structure.

[0097] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate; forming an isolation structure over the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; partially removing the first fin structure and the second fin structure to form a first recess of the first fin structure and a second recess of the second fin structure; epitaxially growing a first source / drain structure over the first recess and epitaxially growing a second source / drain structure over the second recess, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; partially removing the isolation structure through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; and forming a contact etching. A terminating layer is formed above the first source / drain structure and the second source / drain structure to form and seal an air gap in the first opening and the second opening; an interlayer dielectric structure is formed above the contact etch terminating layer; a portion of the interlayer dielectric structure above the first source / drain structure and a portion of the contact etch terminating layer above the first source / drain structure are removed to form a third opening, wherein the third opening exposes the first source / drain structure; an anisotropic deposition process is performed to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion in contact with the first source / drain structure and a side portion in contact with the dielectric structure of the layer; and a conductive layer is formed above the barrier layer, wherein the barrier layer and the conductive layer are configured to form a bit line contact point.

[0098] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0099] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0100] 10: Preparation method

[0101] 100: Semiconductor Component Structure

[0102] 101: Semiconductor substrate

[0103] 103: Patterned dielectric layer

[0104] 105: Patterned mask layer

[0105] 108a: Opening

[0106] 108b: Opening

[0107] 111a~111c: Fin structure

[0108] 111a'~111c': Depression

[0109] 113: Isolation Structure

[0110] 113': Recessed isolation structure

[0111] 113”: Isolation structure

[0112] 113p1: Protrusion

[0113] 113p2: Protrusion

[0114] 121a~121o: Source / Drain Structure

[0115] 124a1: First opening

[0116] 124b1: First opening

[0117] 124a2: Second opening

[0118] 124b2: Second opening

[0119] 131: Contact Etching Termination Layer

[0120] 134a~134b: Air gap

[0121] 141: Interlayer dielectric structure

[0122] 148a: Contact opening

[0123] 148b: Contact opening

[0124] 149a: Opening

[0125] 149d: Opening

[0126] 151a~151d: Bit line contact points

[0127] 161a~161d: Character lines

[0128] 171a~171f: Deep trench capacitors

[0129] 200: Semiconductor Component Structure

[0130] 251: Barrier Layer

[0131] 251a~251d: Barrier layer

[0132] 252: Bit line contact point

[0133] 252a: Conductive layer

[0134] 252b: Conductive layer

[0135] 252d: Conductive layer

[0136] 300: Semiconductor Component Structure

[0137] 311a: Fin structure

[0138] 311b: Fin structure

[0139] 311c: Fin structure

[0140] CH1~CH6: Passage region

[0141] P: Highest point

[0142] S1: Upper surface

[0143] S2: Interface

[0144] S11: Steps

[0145] S13: Steps

[0146] S15: Steps

[0147] S17: Steps

[0148] S19: Steps

[0149] S21: Steps

[0150] SW1: Sidewall

[0151] SW2: Sidewall

[0152] W1: Thickness

[0153] W2: Thickness

[0154] Wm1: Maximum width

[0155] Wm2: Maximum width

Claims

1. A semiconductor device structure, comprising: A semiconductor substrate; A first fin structure protruding from the semiconductor substrate and having a first sidewall, a second sidewall, and an upper surface connecting the first sidewall to the second sidewall; a second fin structure protruding from the semiconductor substrate, wherein the second fin structure is disposed parallel to the first fin structure; a first source / drain structure disposed above the first fin structure, wherein the first source / drain structure includes: a lower portion; and an upper portion disposed above the lower portion of the first source / drain structure, wherein the lower portion of the first source / drain structure covers the upper surface of the first fin structure, a portion of the first sidewall, and a portion of the second sidewall, wherein the upper portion of the first source / drain structure has a triangular profile, wherein the upper portion of the first source / drain structure has a main side coupled to the lower portion of the first source / drain structure and two sub-sides surrounding the triangular profile having the main side, wherein the two sub-sides have the same length; a second source / drain structure disposed above the second fin structure; An isolation structure is formed between the first fin structure and the second fin structure, wherein the isolation structure includes a plurality of protrusions that contact the first source / drain structure and the second source / drain structure; an interlayer dielectric structure is disposed above the semiconductor substrate; a bit line contact point is disposed above the first source / drain structure and includes: a barrier layer that contacts the first source / drain structure; and a conductive layer disposed above the barrier layer, wherein the bit line contact point is a hole-free contact point, wherein the barrier layer includes a lower portion that contacts the first source / drain structure and a first side portion and a second side portion that contacts the interlayer dielectric structure, wherein the thickness of the lower portion of the barrier layer is greater than the respective thicknesses of the first side portion and the second side portion of the barrier layer; A contact etch-stop layer contacts the two sub-sides of the upper part of the first source / drain structure, the lower part of the first source / drain structure, the isolation structure, the second source / drain structure, and the barrier layer, wherein the interlayer dielectric structure is disposed above the contact etch-stop layer; and an air gap is disposed between the first fin structure and the second fin structure, wherein the air gap is surrounded by and sealed by the contact etch-stop layer.

2. The semiconductor device structure as described in claim 1, wherein the barrier layer is in contact with the two sub-sides.

3. The semiconductor device structure as described in claim 1, wherein the first source / drain structure has a maximum width equal to a length of the main side.

4. The semiconductor device structure as described in claim 1, wherein the air gap has a pentagonal profile.

5. The semiconductor device structure as claimed in claim 1, wherein a highest point of the air gap is lower than the upper portion of the first source / drain structure, and the highest point of the air gap is higher than the upper surface of the first fin structure.

6. The semiconductor device structure as claimed in claim 1, wherein the air gap has a leftmost point and a rightmost point flush with the leftmost point, wherein the leftmost point and the rightmost point are lower than the upper surface of the first fin structure.

7. The semiconductor device structure as described in claim 6, wherein the highest point of the protrusions of the isolation structure is higher than the leftmost and rightmost points of the air gap.

8. The semiconductor device structure as claimed in claim 1, wherein the interlayer dielectric structure is disposed above the contact etch-stop layer, and the second source / drain structure is separated from the interlayer dielectric structure.

9. The semiconductor device structure as described in claim 1, further comprising: A first character line, viewed from a top view of the semiconductor device structure, crosses the first fin structure and the second fin structure; And a second character line, which, from the top view of the semiconductor element structure, spans the first fin structure and the second fin structure; wherein the first character line is parallel to the second character line; wherein, from the top view, the first source / drain structure, the second source / drain structure and the air gap are disposed between the first character line and the second character line.

10. The semiconductor device structure as claimed in claim 1, wherein the lower portion of the barrier layer connects the first side of the barrier layer to the second side of the barrier layer.

11. A method for fabricating a semiconductor device structure, comprising: A first fin structure and a second fin structure are formed on a semiconductor substrate; An isolation structure is formed above the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure; the first fin structure and the second fin structure are partially removed to form a first recess of the first fin structure and a second recess of the second fin structure; a first source / drain structure is epitaxially grown above the first recess and a second source / drain structure is epitaxially grown above the second recess, wherein the first source / drain structure is separated from the second source / drain structure by a first opening; the isolation structure is partially removed through the first opening to form a second opening, wherein the first opening and the second opening are a continuous space; a contact etch stop layer is formed above the first source / drain structure and the second source / drain structure to form and seal an air gap in the first opening and the second opening; an interlayer dielectric structure is formed above the contact etch stop layer. A portion of the interlayer dielectric structure above the first source / drain structure and a portion of the contact etch stop layer above the first source / drain structure are removed to form a third opening, wherein the third opening exposes the first source / drain structure; an anisotropic deposition process is performed to deposit a barrier layer in the third opening, wherein the barrier layer includes a lower portion in contact with the first source / drain structure and a side portion in contact with the dielectric structure of the layer, wherein the thickness of the lower portion of the barrier layer is greater than the thickness of the side portion of the barrier layer; and a conductive layer is formed above the barrier layer, wherein the barrier layer and the conductive layer are configured to form a bit line contact point, wherein the bit line contact point is a hole-free contact point.

12. A method for fabricating a semiconductor device structure as claimed in claim 11, wherein, prior to epitaxial growth of the first source / drain structure, an upper surface and a sidewall of the first recess protrude from the isolation structure.

13. A method for fabricating a semiconductor device structure as claimed in claim 11, wherein the width of the first opening increases from an upper portion of the first opening to a lower portion of the first opening, and the width of the second opening decreases from an upper portion of the second opening to a lower portion of the second opening.

14. A method for fabricating a semiconductor device structure as claimed in claim 11, wherein one sidewall of the isolation structure is exposed in the second opening.

15. A method for fabricating a semiconductor device structure as claimed in claim 14, wherein the contact etch-stop layer extends into the first opening and the second opening, and the sidewall of the isolation structure is covered by the contact etch-stop layer.

16. The method for fabricating the semiconductor device structure as described in claim 11 further includes: A first character line and a second character line are formed across the first fin structure and the second fin structure, wherein the first source / drain structure, the second source / drain structure and the air gap are located between the first character line and the second character line.

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