Optoelectronic device and method of manufacturing thereof

Abstract

Some embodiments described in this disclosure include complementary metal-oxide-semiconductor (CMOS) image sensor devices and techniques for forming CMOS image sensor devices. The CMOS image sensor device includes a first array of multiple photodiodes stacked above a second photodiode array. A polarization structure is located between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., a signal corresponding to an unpolarized light wave) can be multiplexed with signaling generated by the second array of photodiodes (e.g., a signal corresponding to a polarized light wave). The CMOS image sensor device also includes a filter structure that filters out visible and near-infrared light waves between the first and second arrays of photodiodes.

Description

Technical Field

[0001] This disclosure relates to an optoelectronic device and a method for manufacturing the same. Prior Technology

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include multiple pixel sensors. Each pixel sensor in a CMOS image sensor may include a photodiode region for converting photons of incident light into electrons of photocurrent, a transfer gate for controlling the flow of photocurrent between the photodiode region and a floating diffusion region, and a drain region in the floating diffusion region for receiving the photocurrent, allowing the photocurrent to be measured and / or transferred to other regions of the CMOS image sensor. Summary of the Invention

[0003] According to some embodiments disclosed herein, an optoelectronic device includes an optical filter structure, a first photodiode, a second photodiode, and a polarization shield structure. The first photodiode is located in a first device region below the optical filter structure. The second photodiode is located in a second device region below the first photodiode. The polarization shield structure is located between the photodiode and the second photodiode.

[0004] According to some embodiments disclosed herein, an optoelectronic device includes an optical filter structure, a red visible light photodiode, a near-infrared light photodiode, and a polarizing shield structure. The optical filter structure has a transmittance that allows multiple red visible light waves and multiple near-infrared light waves to pass through it. The red visible light photodiode is located in a first device region below the optical filter structure. The near-infrared light photodiode is located in a second device region below the red visible light photodiode. The polarizing shield structure is located between the red visible light photodiode and the near-infrared light photodiode.

[0005] According to some embodiments of this disclosure, a method of manufacturing an optoelectronic device includes the following operations: forming a first photodiode in a layer of semiconductor material; forming a first portion of a dielectric region above the first photodiode; forming a polarizing shield structure above the first portion of the dielectric region, wherein the polarizing shield structure above the first portion of the dielectric region includes a vertically aligned polarizing shield structure and the first photodiode; forming a second portion of the dielectric region above the first portion of the dielectric region and above the polarizing shield structure; and connecting the dielectric region and a portion of the device containing a second photodiode, wherein the portion connecting the dielectric region and the device containing the second photodiode includes a vertically aligned second photodiode and the polarizing shield structure. Simple Explanation of the Diagram

[0006] This disclosure is best understood when read in conjunction with the accompanying figures, and is described in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic diagram of an exemplary environment in which the systems and / or methods described in this disclosure can be implemented. Figure 2 is a schematic diagram of an exemplary pixel sensor array described in this disclosure. Figure 3 is a schematic diagram of an exemplary optoelectronic device including the polarization shield structure described in this disclosure. Figures 4A through 4D are schematic diagrams of exemplary embodiments of the polarization mask structure described in this disclosure. Figures 5A to 5S are schematic diagrams of exemplary embodiments of the optoelectronic device that forms Figure 3. Figure 6 is a schematic diagram of an exemplary optoelectronic device including the polarization shield structure described in this disclosure. Figure 7 is a schematic diagram of exemplary components of one or more devices described in Figure 1 in this disclosure. Figure 8 is a flowchart of an exemplary process related to forming an optoelectronic device including a polarizing shield structure. Implementation

[0007] The following disclosure provides many different implementations or embodiments to achieve different features of the provided object. Specific embodiments of components and configurations are described below to simplify this disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, in the following description, forming a first feature above or above a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, thus the first and second features may not be in direct contact. Furthermore, numbers and / or letters may be repeatedly designated in various embodiments. Such repetition is for simplification and clarity and is not intended to indicate a relationship between the various implementations and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0009] In some cases, complementary metal-oxide-semiconductor (CMOS) image sensors utilize photosensitive CMOS circuitry to convert light energy into electrical energy. The photosensitive CMOS circuitry may include photodiodes formed in a silicon substrate. When the photodiode is exposed to light, a charge (called photocurrent) is induced in it. The photodiode may be coupled to a switching transistor, which samples the charge in the photodiode. Color can be determined by placing filters above the photosensitive CMOS circuitry.

[0010] In some low-lighting applications, the image processing system uses signaling corresponding to unpolarized visible (VIS) light waves (e.g., VIS light waves reflected from the target object) detected by the photodiode of a first discrete CIS device. The image processing system may also use signaling corresponding to unpolarized near-infrared (NIR) light waves (e.g., NIR light waves reflected from the target object) detected by the photodiode of a second discrete CIS device. Combining the signaling corresponding to the unpolarized VIS light waves with the signaling corresponding to the unpolarized NIR light waves may be insufficient to generate an accurate optical image representing the target object. Furthermore, the separation of the first and second discrete CIS devices may cause timing asynchrony between the signaling corresponding to the unpolarized VIS and NIR light waves. This lack of synchronization may reduce the image processing system's ability to generate the precision multiplexed signal required to accurately represent the target object.

[0011] Some embodiments described in this disclosure include a CIS device and techniques for forming a CIS device. The CIS device includes a first array of multiple photodiodes stacked above a second array of multiple photodiodes. A polarization structure is located between the first array of multiple photodiodes and the second array of multiple photodiodes. Signaling generated by the first array of multiple photodiodes (e.g., signaling corresponding to unpolarized light waves) can be multiplexed with signaling generated by the second array of multiple photodiodes (e.g., signaling corresponding to polarized light waves). The CIS device also includes a filter structure that distributes visible light waves and near-infrared light waves between the first array of multiple photodiodes and the second array of multiple photodiodes.

[0012] In this manner, reflected light waves (including unpolarized VIS light waves, polarized VIS light waves, unpolarized NIR light waves, and / or polarized NIR light waves) from the target object are simultaneously captured by a single CIS device. Thus, compared to another image processing system that multiplexes simultaneously captured unpolarized VIS light waves and unpolarized NIR light waves, which can be captured by separate and discrete devices with timing offsets, the performance of an image processing system that multiplexes unpolarized VIS light waves and unpolarized NIR light waves can be improved. This improved performance leads to a reduction in the amount of computational resources required for the image processing system. Furthermore, by combining unpolarized visible light detection capabilities, polarized visible light detection capabilities, unpolarized near-infrared light detection capabilities, and polarized near-infrared light detection capabilities into a single CIS device, the amount of semiconductor manufacturing resources (e.g., semiconductor manufacturing tools, raw materials, manpower, and / or computational resources) required to manufacture the image processing system is reduced.

[0013] Figure 1 is a schematic diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. As shown in Figure 1, environment 100 may include a plurality of semiconductor processing tools 102-116 and a wafer / wafer transfer tool 118. The plurality of semiconductor processing tools 102-116 may include a deposition tool 102, an exposure tool 104, a developing tool 106, an etching tool 108, a planarization tool 110, an electroplating tool 112, an ion implantation tool 114, a bonding / separation / disconnection tool 116, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be found in examples such as semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities.

[0014] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0015] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., deep ultraviolet light source, extreme ultraviolet (EUV) source, etc.), an X-ray source, an electron beam source, and / or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, exposure tool 104 includes a scanner, stepper, or similar type of exposure tool.

[0016] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve either the exposed or unexposed portions of the photoresist layer.

[0017] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, etc. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific time period to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to isotropically or directionally etch the one or more portions.

[0018] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or electroplated material. Planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free-grinding polishing) to polish or planarize the surface of the semiconductor device. Planarization tool 110 may be used in conjunction with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) using abrasives and corrosive chemical slurries. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and plan any irregularities in the semiconductor device, making the semiconductor device flat or planar.

[0019] Electroplating tool 112 is a semiconductor processing tool capable of electroplating substrates (e.g., wafers, semiconductor devices, etc.) or portions thereof with one or more metals. For example, electroplating tool 112 may include copper electroplating apparatus, aluminum electroplating apparatus, nickel electroplating apparatus, tin electroplating apparatus, compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating apparatus, and / or electroplating apparatus for one or more other types of conductive materials, metals and / or similar types of materials.

[0020] Ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. Ion implantation tool 114 can generate ions from a source material, such as a gas or solid, in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions from the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate, such that ions are implanted below the surface of the substrate.

[0021] Bonding / Separating / Decoupling Tool 116 is a semiconductor processing tool capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, bonding / separating / decoupling tool 116 may include a eutectic bonding tool capable of forming a eutectic bond between two or more wafers. In these examples, the bonding tool may heat two or more wafers to form a eutectic system between the materials of the two or more wafers. As another example, bonding / separating tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or another type of bonding tool. In some embodiments, bonding / separating / decoupling tool 116 may separate and / or transfer layers or material stacks from one substrate to another.

[0022] The wafer / wafer transfer tool 118 may be included in a cluster tool or another type of tool that includes multiple processing chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, to transfer substrates and / or semiconductor devices between processing chambers and buffer areas, to transfer substrates and / or semiconductor devices between processing chambers and an interface tool such as an equipment front end module (EFEM), and / or to transfer substrates and / or semiconductor devices between processing chambers and transfer carriers (e.g., front opening unified pods, FOUPs), etc. In some embodiments, the wafer / wafer transfer tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidants and / or other types of contaminants or byproducts from the substrate and / or semiconductor device) and various types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0023] As described in more detail elsewhere in this disclosure in conjunction with Figures 5A through 5S, one or more of the semiconductor processing tools 102-116 and / or wafer / wafer transfer tool 118 can perform a series of one or more semiconductor processing operations. In some embodiments, and as an example, the series of one or more semiconductor processing operations includes forming a first photodiode in a layer of semiconductor material. The series of one or more semiconductor processing operations includes forming a first portion of a dielectric region over the first photodiode. The series of one or more semiconductor processing operations includes forming a polarizing mask structure over the first portion of the dielectric region, wherein forming the polarizing mask structure over the first portion of the dielectric region includes vertically aligning the polarizing mask structure and the first photodiode. The series of one or more semiconductor processing operations includes forming a second portion of the dielectric region over the first portion of the dielectric region and over the polarizing mask structure. The series of one or more semiconductor processing operations includes bonding the dielectric region and a portion of a means including a second photodiode, wherein said portion of bonding the dielectric region and the means including the second photodiode includes vertically aligning the second photodiode and the polarizing mask structure.

[0024] The number and arrangement of devices shown in Figure 1 are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or devices with different arrangements compared to those shown in Figure 1. Furthermore, two or more devices shown in Figure 1 may be implemented within a single device, or the single device shown in Figure 1 may be implemented as multiple distributed devices. Alternatively or additionally, a group of devices (e.g., one or more devices) in exemplary environment 100 may perform one or more functions described as being performed by another group of devices in exemplary environment 100.

[0025] Figure 2 is a schematic diagram of an exemplary pixel array 200 (or a portion thereof) described in this disclosure. The pixel array 200 may be included in an image sensor, such as a complementary metal-oxide-semiconductor (CMOS) image sensor, a back-side illuminated (BSI) CMOS image sensor, or other types of image sensors.

[0026] Figure 2 illustrates a top view of pixel array 200. As shown in Figure 2, pixel array 200 may include a plurality of pixel sensors 202. As further shown in Figure 2, pixel sensors 202 may be arranged in a grid. In some embodiments, pixel sensors 202 are square (as shown in the example in Figure 2). In some embodiments, pixel sensors 202 include other shapes, such as circles, octagons, rhombuses, and / or other shapes.

[0027] Pixel sensor 202 can be configured to sense and / or accumulate incident light (e.g., light directed to pixel array 200). For example, pixel sensor 202 can absorb photons of the incident light and accumulate them in a photodiode. The accumulation of photons in the photodiode can generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge can correspond to a larger intensity or brightness, and a smaller amount of charge can correspond to a smaller intensity or brightness).

[0028] The pixel array 200 can be electrically connected to the back-end-of-line (BEOL) metallization stack (not shown) of the image sensor. The BEOL metallization stack can electrically connect the pixel array 200 to a control circuit that can be used to measure the accumulation of incident light in the pixel sensor 202 and convert the measurement result into an electrical signal.

[0029] As described in more detail elsewhere in this disclosure in conjunction with Figures 3 through 6, pixel sensor 202 may include a combination of a light wave filter (e.g., a light wave filter for filtering light of a target wavelength) and a polarization structure (e.g., a polarization structure that polarizes the target wavelength of light). For example, using the combination of the light wave filter and the polarization structure, pixel sensor 202a may include a photodiode that senses unpolarized red VIS light waves and polarized red VIS light waves (having unpolarized and polarized electromagnetic waves with wavelengths ranging from about 620 nanometers to about 750 nanometers). Alternatively or additionally, pixel sensor 202b may include a photodiode that senses unpolarized blue VIS light waves and polarized blue VIS light waves (e.g., having unpolarized and polarized electromagnetic waves with wavelengths ranging from about 450 nanometers to about 495 nanometers). Alternatively, pixel sensor 202c may include a photodiode for sensing unpolarized green VIS light waves and polarized green VIS light waves (e.g., unpolarized and polarized electromagnetic waves with wavelengths ranging from about 495 nanometers to about 570 nanometers). Alternatively, pixel sensor 202d may include a photodiode for sensing unpolarized NIR light waves and polarized NIR light waves (e.g., unpolarized and polarized electromagnetic waves with wavelengths ranging from about 750 nanometers to about 2500 nanometers).

[0030] As mentioned above, Figure 2 is provided as an example. Other examples may differ from those described regarding Figure 2.

[0031] Figure 3 is a schematic diagram of an exemplary optoelectronic device 300 described in this disclosure. As shown in Figure 3, the optoelectronic device 300 includes a combination of optoelectronic devices 302a and 302b connected via a bonding interface 304. In some embodiments, the optoelectronic device 300 may correspond to a three-dimensional complementary metal-oxide-semiconductor image sensor (3D CIS) device, wherein optoelectronic devices 302a and 302b are stacked and / or vertically arranged.

[0032] As further shown in Figure 3, device 302a may include dielectric region 306a. In some embodiments, dielectric region 306a corresponds to a first dielectric region of optoelectronic device 300. Dielectric region 306a (e.g., intermetallic dielectric region) may include one or more layers of dielectric material (e.g., silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), phosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, or other dielectric materials). One or more metallization layers 308a may be formed in and / or between the layers of dielectric region 306a. The metallization layer 308a may include bonding pads, wires, and / or other types of conductive structures, which electrically connect various regions of the electrical connection means 302a and / or electrically connect various regions of the optoelectronic device 300 to one or more external devices, and / or external packages. In some embodiments, the metallization layer 308a may be referred to as a BEOL metallization stack and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof.

[0033] Device 302a may also include a semiconductor material layer 310a. In some embodiments, the semiconductor material layer 310a corresponds to a first device region of the optoelectronic device 300. The semiconductor material layer 310a may include a semiconductor material such as silicon, a III-V compound such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) layer, or another type of semiconductor material capable of generating charge from photons of incident light.

[0034] A photodiode 312a for sensing light (e.g., light waves) may be contained within a layer 310a of a semiconductor material. The photodiode 312a may include various types of ions to form a pn junction or pin junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, the semiconductor material layer 310a may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 312a and a p-type dopant to form a second portion (e.g., a p-type portion) of the second photodiode 312a. The photodiode 312a may include a visible light photodiode and / or a near-infrared light photodiode.

[0035] Furthermore, in some embodiments of device 302a, a shallow trench isolation (STI) region 314 may be located above dielectric region 306a. STI region 314 can electrically isolate photodiode 312a from other regions of device 302a.

[0036] As shown in Figure 3, oxide layer 316a may be located above semiconductor material layer 310a. Oxide layer 316a can serve as a passivation layer between semiconductor material layer 310a and the upper layer of pixel sensor 202. In some embodiments, oxide layer 316a comprises an oxide material such as silicon oxide (SiO x). In some embodiments, silicon nitride (SiN x), silicon carbide (SiC x), or mixtures thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or other dielectric materials, are used instead of oxide layer 316a as the passivation layer.

[0037] The oxide layer 316a may fill a deep trench isolation (DTI) structure 318a included in the semiconductor material layer 310a. Specifically, the DTI structure 318a may be formed between each photodiode 312a. The DTI structure 318a may include trenches (e.g., deep trenches) extending downwards in the semiconductor material layer 310a between the photodiodes 312a. The DTI structure 318a may provide optical isolation between the photodiodes 312a to reduce the amount of optical crosstalk between adjacent photodiodes.

[0038] One or more high absorption (HA) regions 320 may be located above one or more photodiodes 312a. Each HA region 320 may be defined by a shallow trench. Multiple adjacent HA regions 320 may form a periodic or zigzag structure in the semiconductor material layer 310a and / or the photodiode 312a layer. One or more HA regions 320 may be formed on the same side of the semiconductor material layer 310a as the DTI structure 318a.

[0039] Region HA 320 can increase the absorption of incident light by photodiode 312a by modifying or changing the orientation of the refractive interface between the photodiode and the semiconductor material layer 310a (thereby increasing the quantum efficiency of photodiode 312a). The inclined walls of region HA 320 change the orientation of the interface between photodiode 312a and semiconductor material layer 310a relative to the top surface of semiconductor material layer 310a. For the same incident light angle, this change in orientation can result in a smaller angle of refraction relative to the flat surface of the top surface of semiconductor material layer 310a. As a result, compared to the case where photoelectric device 300 does not include region HA 320, region HA 320 can guide incident light at a wider angle toward the center of photodiode 312a.

[0040] In some embodiments, the top surface of the semiconductor material layer 310a, the surface of the DTI structure 318a, and the surface of the HA region 320 may be coated with an antireflective coating (ARC) to reduce the reflection of incident light away from the photodiode 312a, thereby increasing the transmission of incident light into the semiconductor material layer 310a and the photodiode 312a.

[0041] As further shown in Figure 3, one or more passivation layers may be formed over oxide layer 316a and / or oxide layer 316a. For example, backside illumination (BSI) oxide layer 322 may be located over and / or over a portion of oxide layer 316a. As another example, buffer oxide layer 324 may be located over and / or over BSI oxide layer 322. In some embodiments, BSI oxide layer 322 and / or buffer oxide layer 324 comprises an oxide material such as silicon oxide (SiO x). In some embodiments, silicon nitride (SiN x), silicon carbide (SiC x), or mixtures thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material, are used instead of BSI oxide layer 322 and / or buffer oxide layer 324 as passivation layers.

[0042] Bonding pads 326 may be located above STI region 314 and / or above and / or above buffer oxide layer 324. Bonding pads 326 may extend through buffer oxide layer 324, through STI region 314 and to dielectric region 306a, and may contact one or more metallization layers 308a in dielectric region 306a. Bonding pads 326 may include conductive materials such as gold, silver, aluminum, copper, aluminum-copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, metal alloys, other metals or combinations thereof. Bonding pads 326 may provide electrical connections between metallization layer 308a of optoelectronic device 300 and external devices and / or external packages.

[0043] A filter layer 328 (e.g., a light filter structure including portions of a color filter array and / or a near-infrared filter array) is included on and / or on a buffer oxide layer 324 of one or more pixel sensors 202. The filter layer 328 may include one or more visible light filter regions configured to filter visible light of a specific wavelength or wavelength range (e.g., allowing visible light of a specific wavelength or wavelength range to pass through the filter layer 328), one or more near-infrared (NIR) filter regions (e.g., NIR bandpass filter regions) configured to allow wavelengths associated with NIR light to pass through the filter layer 328 and block light of other wavelengths, one or more NIR cutoff filter regions and / or other types of filter regions configured to block NIR light from passing through the filter layer 328.

[0044] In some embodiments, one or more pixel sensors 202 are each configured with a filtering region of the filter layer 328. In some embodiments, a microlens layer 330 is included on and / or on the filter layer 328. The microlens layer 330 may include a plurality of microlenses. Specifically, the microlens layer 330 may include a corresponding microlens for each pixel sensor in the pixel sensor array (e.g., each pixel sensor 202 included in the pixel array 200).

[0045] As shown in Figure 3, device 302b includes a dielectric region 306b. In some embodiments, dielectric region 306b corresponds to a second dielectric region of optoelectronic device 300. Dielectric region 306b (e.g., an intermetallic dielectric region) may include one or more layers of dielectric material (e.g., silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, or another dielectric material). Metallization layer 308b may be formed in and / or between layers of dielectric region 306b. Metallization layer 308b may include bonding pads, wires, and / or other types of conductive structures, electrically connecting various regions of the electrical connection means 302b and / or electrically connecting various regions of the optoelectronic device 300 to one or more external devices, and / or providing an external package. Metallization layer 308a may be referred to as a BEOL metallization stack and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof.

[0046] Device 302b may also include a layer 310b of semiconductor material (e.g., a second device region including layer 310b of semiconductor material). Layer 310b of semiconductor material may include a semiconductor material such as silicon, a III-V compound such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) layer, or a layer of another type of semiconductor material capable of generating charge from photons of incident light.

[0047] In some embodiments, semiconductor material layers 310a and 310b comprise the same material. Optionally, and in some embodiments, semiconductor material layer 310b comprises a material different from that comprised in semiconductor material layer 310a. For example, semiconductor material layer 310b may comprise a material having a “narrow” bandgap suitable for detecting NIR light waves (e.g., a material having a bandgap ranging from about 0.6 eV to about 1.7 eV, such as indium gallium arsenide (InGaAs), lead sulfide (PbS), or lead selenide (PbSe)), while semiconductor material layer 310a comprises a material having a wider bandgap suitable for detecting VIS light waves (e.g., a material with a bandgap ranging from about 1.1 eV to about 1.4 eV, such as silicon (Si) or gallium arsenide (GaAs)).

[0048] A photodiode 312b for sensing light (e.g., light waves) may be included within a layer 310b of a semiconductor material. The photodiode 312b may include various types of ions to form a pn junction or pin junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, the semiconductor material layer 310b may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 312b and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 312b. Furthermore, the photodiode 312b may include a visible light photodiode and / or a near-infrared light photodiode.

[0049] In some embodiments, the dopants included in photodiodes 312a and 312b are the same dopants. Alternatively, in embodiments, the dopants included in one or more photodiodes 312b are different from the dopants included in one or more photodiodes 312a. For example, photodiode 312b may include dopants suitable for detecting NIR light waves (e.g., silicon (Si) or tellurium (Te)), while one or more photodiodes 312a may include dopants suitable for detecting VIS light waves (e.g., boron (B), aluminum (Al), phosphorus (P), or arsenic (As)).

[0050] As shown in Figure 3, oxide layer 316b may be located above semiconductor material layer 310b. Oxide layer 316b can serve as a passivation layer between semiconductor material layer 310b and the upper layer of pixel sensor 202. In some embodiments, oxide layer 316b comprises an oxide material such as silicon oxide (SiO x). In some embodiments, silicon nitride (SiN x), silicon carbide (SiC x), or mixtures thereof, such as silicon carbonitride (SiCN), silicon oxynitride (SiON), or another dielectric material, are used instead of oxide layer 316b as the passivation layer.

[0051] The oxide layer 316b can fill a deep trench isolation (DTI) structure 318b included in the semiconductor material layer 310b. Specifically, the DTI structure 318b can be formed between each photodiode 312b. The DTI structure 318b can include trenches (e.g., deep trenches) extending downwards in the semiconductor material 2 layer 310b between the photodiodes 312b. The DTI structure 318b can provide optical isolation between the photodiodes 312b to reduce the amount of optical crosstalk between adjacent photodiodes.

[0052] As shown in Figure 3, and as described in more detail elsewhere in this disclosure in conjunction with Figures 4A through 4D, one or more polarization mask structures 332 may be included in a dielectric region 306b between one or more pairs of corresponding photodiodes 312a and 312b. Furthermore, as shown in Figure 3, dielectric regions 306a and 306b include penetration regions 334a and 334b, which allow light waves 336 (which may be filtered by filter layer 328) to pass from photodiode 312a through the metallization layers 308a and 308b and reach the polarization mask structure 332. The light waves 336 may be polarized by the polarization mask structure 332 before being sensed by the photodiode 312b.

[0053] Based on the arrangement and / or configuration of the filter layer 328, photodiode 312a, polarization mask structure 332, and photodiode 312b, the optoelectronic device 300 can simultaneously capture reflected light waves including combinations of: unpolarized visible light waves, polarized visible light waves, unpolarized near-infrared light waves, and / or polarized near-infrared light waves. In this way, an image processing system including the optoelectronic device 300 can multiplex the simultaneously captured unpolarized VIS light waves, polarized VIS light waves, unpolarized NIR light waves, and / or polarized NIR light waves to present the image of the target more accurately than another image processing system that is limited to multiplexing unpolarized VIS light waves and unpolarized NIR light waves captured by separate and discrete devices. This performance improvement results in a reduction in the amount of computational resources required by the image processing system. Furthermore, by combining unpolarized visible light detection capability, polarized visible light detection capability, unpolarized near-infrared light detection capability, and polarized near-infrared light detection capability in the optoelectronic device 300, the amount of semiconductor manufacturing resources required to manufacture the image processing system (e.g., semiconductor manufacturing tools, raw materials, manpower, and / or computing resources) is reduced.

[0054] As shown in Figure 3, the device (e.g., photoelectric device 300) includes an optical filter structure (e.g., a filter layer 328). The device includes a second photodiode (e.g., photodiode 312b in layer 310b of semiconductor material) in a second device region below the first photodiode. The device includes a polarization shield structure (e.g., polarization shield structure 332) located between the first and second photodiodes.

[0055] Alternatively, in some embodiments, the device (e.g., photoelectric device 300) includes a filter structure (e.g., filter layer 328) having a transmittance that allows red visible light and near-infrared light to pass through the optical filter structure. The device includes a red visible light photodiode in a first device region (e.g., photodiode 312a in layer 310a of semiconductor material, wherein photodiode 312a includes dopants suitable for detecting red VIS light, and layer 310a of semiconductor material includes a material having a band gap suitable for detecting VIS light) located below the optical filter structure. The device includes a near-infrared light photodiode in a second device region (e.g., photodiode 312b in layer 310b of semiconductor material, wherein photodiode 312b includes dopants suitable for detecting NIR light, and layer 310b of semiconductor material includes a material having a band gap suitable for detecting NIR light). The device includes a polarization shield structure (e.g., polarization shield structure 332) located between a red visible light photodiode and a near-infrared light photodiode.

[0056] The number and configuration of components, structures, and / or layers shown in the optoelectronic device 300 in Figure 3 are provided as examples. In practice, the optoelectronic device 300 may include additional components, structures, and / or layers; fewer components, structures, and / or layers; different components, structures, and / or layers; and / or components, structures, and / or layers arranged differently from those shown in Figure 3.

[0057] Figures 4A through 4D are schematic diagrams of an exemplary embodiment 400 of the polarization mask structure described in this disclosure. Exemplary embodiment 400 includes details that may relate to the polarization mask structure 332 in Figure 3 and other parts of this disclosure.

[0058] As shown in Figure 4A, a polarization mask structure 332 may be formed on a first portion (e.g., portion 306b1) of the dielectric region 306. The polarization mask structure 332 includes a polarized beam structure 402 that is axially dispersed approximately parallel to the polarization axis 404.

[0059] The polarization beam structure 402 includes a substrate layer 406 and a capping layer 408. The substrate layer 406 and the capping layer 408 may comprise materials that reflect and / or do not transmit VIS and / or NIR light waves. For example, the substrate layer 406 may comprise titanium (Ti). Alternatively, the capping layer 408 may comprise gold (Au), copper (Cu), nickel-cobalt (NiCo), or nickel-iron (NiFe).

[0060] Figure 4B illustrates an example dimension of the polarization mask structure 332. In some embodiments, the width D1 of the polarization beam structure 402 may include a range of about 180 nanometers to about 220 nanometers. Alternatively, the spacing D2 between the polarization beam structures 402 may include a range of about 360 nanometers to about 440 nanometers. If the width D1 is greater than about 220 nanometers and the spacing D2 is less than about 360 nanometers, the amount of light passing through the polarization mask structure 332 (e.g., the amount of light wave 336) may be insufficient for the underlying photodiode (e.g., photodiode 312b) to sense it. If the width D1 is less than about 180 nanometers and the spacing is greater than about 440 nanometers, the effectiveness of the polarization mask structure 332 may be reduced, making it impossible for the light detected by the underlying photodiode to distinguish it from unpolarized light. However, other values ​​and ranges of width D1 and spacing D2 are also within the scope of this disclosure.

[0061] Alternatively, the height D3 of the polarization beam structure 402 may range from about 180 nanometers to about 220 nanometers. If the height D3 is greater than about 220 nanometers, shielding, reflection, and / or distortion of light waves (e.g., light wave 336) passing through the polarization shield structure may occur. If the height is less than about 180 nanometers, the effectiveness of the polarization shield structure 332 may be reduced, making it impossible to distinguish light detected by the underlying photodiode (e.g., photodiode 312b) from unpolarized light. However, other values ​​and ranges of height D3 are also within the scope of this disclosure.

[0062] In some embodiments, and as shown, the height D4 of the capping layer 408 may include a range of about 185 nanometers to about 215 nanometers. Alternatively, the height D5 of the substrate layer 406 may include a range of about 8 nanometers to about 12 nanometers. If heights D4 and D5 do not meet these ranges, the height D3 of the polarizing beam structure 402 may not be included in the range of about 180 nanometers to about 220 nanometers. Alternatively, if heights D4 and D5 do not meet these ranges, the cost of manufacturing the polarizing mask structure 332 may increase. However, other values ​​and ranges of heights D4 and D5 are also within the scope of this disclosure.

[0063] Figure 4C illustrates an example orientation of the polarization mask structure 332. As shown in Figure 4C, the polarization beam structure 402a of the polarization mask structure 332a is approximately parallel to the polarization axis 404a. Alternatively, as shown in Figure 4C, the polarization beam structure 402b of the polarization mask structure 332b may be approximately parallel to the polarization axis 404b, wherein the polarization axis 404b is approximately orthogonal to the polarization axis 404a. Alternatively, as shown in Figure 4C, the polarization beam structure 402c of the polarization mask structure 332c may be approximately parallel to the polarization axis 404c, wherein the polarization axis 404c forms an angle of approximately +45 degrees (°) relative to the polarization axis 404a. Alternatively, as shown in Figure 4C, the polarization beam structure 402d of the polarization mask structure 332 may be approximately parallel to the polarization axis 404d, wherein the polarization axis 404d forms an angle of approximately -45 degrees relative to the polarization axis 404a.

[0064] Figure 4D illustrates an isometric exploded view of a filter layer 328 comprising a first portion (e.g., portion 306b1) relative to the polarizing shield structure 332 and the dielectric region 306. In some embodiments, as shown in Figure 4D, the filter layer 328 may include a portion 328a that transmits red VIS light waves (e.g., blocking electromagnetic waves with wavelengths less than about 620 nm or greater than about 750 nm), a portion 328b that transmits blue VIS light waves (e.g., blocking electromagnetic waves with wavelengths less than about 450 nm or greater than about 495 nm), a portion 328c that transmits green VIS light waves (e.g., blocking electromagnetic waves with wavelengths less than about 495 nm or greater than about 570 nm), and a portion 328d that transmits NIR light waves (e.g., blocking electromagnetic waves with wavelengths less than about 750 nm or greater than about 2500 nm).

[0065] For space-saving purposes, and in some embodiments, a "hybrid" portion may be included in the filter layer 328. As an example, the hybrid portion may transmit overlapping spectra (e.g., wavelength ranges) associated with sub-spectral characteristics of red VIS light and / or NIR light, thereby eliminating the need for separate and individual portions (parts 328a and 328d) of the filter layer 328 and the underlying photodiode. For example, the hybrid portion may block electromagnetic waves with wavelengths less than about 600 nanometers and greater than about 1000 nanometers. If the hybrid portion transmits electromagnetic waves with wavelengths less than about 600 nanometers, green and / or blue visible light may cause inaccurate sensing of red visible light by the underlying photodiode configured to sense red visible light (e.g., the underlying photodiode, such as one or more of photodiodes 312a, including materials and dopants selected to sense red VIS light). If the hybrid portion is transmissive to electromagnetic waves with wavelengths greater than approximately 1000 nanometers, mid-wavelength near infrared (MW-NIR) and / or long-wavelength near infrared (LW-NIR) light may cause inaccurate sensing by the underlying photodiode configured to sense short-wavelength near infrared (SW-NIR) light (e.g., one or more of the underlying photodiodes, such as photodiode 312b, including materials and dopants selected to sense SW-NIR light). However, other values ​​and ranges of light wavelengths blocked by such a hybrid portion are also within the scope of this disclosure.

[0066] In some embodiments, and in embodiments based on an optoelectronic device (e.g., optoelectronic device 300) and / or an image processing system using information from the optoelectronic device, the polarization mask structure 332 may be associated with a selected spectrum transmitted by a corresponding portion of the filter layer 328 (e.g., associated with a selected spectrum of VIS light and / or a selected spectrum of NIR light). In this case, the polarization mask structure 332 may be coaxially positioned with the selected portion of the filter layer 328. Furthermore, and in some embodiments, the approximate angular direction of the polarization axis of the polarization mask structure 332 may be the same, regardless of the selected associated spectrum. Alternatively or additionally, the approximate angular direction of the polarization axis of the polarization mask structure 332 may be different approximate angular directions based on the selected associated spectrum.

[0067] The number and configuration of components, structures, positions, and / or orientations of the polarization mask structure 332 in Figures 4A to 4D are provided as examples. In practice, the polarization mask structure 332 may include additional components, structures, positions, and / or orientations; and / or components, structures, positions, and / or layers configured differently from those shown in Figures 4A to 4D.

[0068] Figures 5A to 5S are schematic diagrams of an example embodiment 500 of the optoelectronic device 300 forming Figure 3. As part of embodiment 500, a series of operations can be performed by combining one or more of the semiconductor processing tools 102-116 and / or wafer / wafer transfer tools 118 described in Figure 1.

[0069] As shown in Figure 5A, the formation of the first device (e.g., device 302b) included in the optoelectronic device 300 can begin from a carrier structure 502 (e.g., a glass carrier structure or a silicon carrier structure, etc.) supporting the semiconductor material layer 310b. The deposition tool 102 can be used in PVD, ALD, CVD, epitaxial, oxidation, another type of deposition operation described in conjunction with Figure 1, and / or other suitable deposition operations. In some embodiments, a planarization tool 110 planarizes the semiconductor material layer 310b after the deposition tool 102 has deposited it.

[0070] As shown in Figure 5B, and as part of a series of operations, a photodiode 312b can be formed in layer 310b of semiconductor material. As an example, a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, and / or an ion implantation tool can perform a combination of deposition, lithography, etching, and / or implantation operations to implant ions into a defined region below the substrate surface to form the photodiode 312b.

[0071] As shown in Figure 5C, and as part of a series of operations, the semiconductor material layer 310b of the photodiode 312b is transferred to the carrier structure 504 (e.g., a glass carrier structure or a silicon carrier structure, etc.). As an example, the bonding / separating / disconnecting tool 116 can separate the semiconductor material layer 310b from the carrier structure 502 and transfer the semiconductor material layer 310b to the carrier structure 504.

[0072] Moving to Figure 5D, and as part of a series of operations, etching tool 108 can form a cavity 506 (e.g., a cavity for DTI structure 318b) in the semiconductor material layer 310b. In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor material layer 310b to form the cavity 506. In these embodiments, deposition tool 102 forms a photoresist layer on the semiconductor material layer 310b. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose the pattern. Etching tool 108 etches the semiconductor material layer 310b based on the pattern to form the cavity 506 in the semiconductor material layer 310b. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative to layer 310b based on patterned etched semiconductor material.

[0073] As shown in Figure 5E, an oxide layer 316b is formed on and / or on the semiconductor material layer 310b. The deposition tool 102 may deposit the oxide layer 316b in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes the oxide layer 316b after the deposition tool 102 has deposited it. As part of the formation of the oxide layer 316b, the cavity 506 may be filled with oxide to form a DTI structure 318b. In some embodiments, the deposition tool 102 deposits an anti-reflective (ARC) layer before depositing the oxide layer 316b.

[0074] As shown in Figure 5F, a first portion (e.g., portion 306b1) of the dielectric region 306 is formed on and / or over the oxide layer 316b. To form the first portion of the dielectric region 306, the deposition tool 102 may deposit one or more layers of dielectric material in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes one or more layers of dielectric material after the deposition tool 102 has deposited it.

[0075] As further shown in Figure 5F, and as part of a series of operations, a polarizing mask structure 332 is formed on a first portion of the dielectric region 306. Deposition tools 102 and / or plating tools 112 may deposit the substrate layer 406 and / or the capping layer 408 in CVD, PVD, ALD, electroplating, another deposition operation described above in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, after the deposition tools 102 and / or plating tools 112 deposit the substrate layer 406 and / or the capping layer 408, a planarization tool 110 planarizes the substrate layer 406 and / or the capping layer 408.

[0076] In some embodiments, and as part of forming the polarizing mask structure 332, a pattern in the photoresist layer is used to etch the substrate layer 406 and / or the capping layer 408 to form the polarizing beam structure 402. In these embodiments, a deposition tool 102 forms the photoresist layer on the capping layer 408. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches the substrate layer 406 and / or the capping layer 408 based on the pattern to form the polarizing beam structure 402. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0077] Moving to Figure 5G, a second portion (e.g., portion 306b2) of the dielectric region 306b is formed on and / or above the oxide layer 316b. To form the second portion of the dielectric region 306b, the deposition tool 102 may deposit one or more layers of dielectric material in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes one or more layers of dielectric material after the deposition tool 102 has deposited it.

[0078] As part of the forming apparatus 302, a metallization layer 308b is formed within a second portion (e.g., portion 306b2) of the dielectric region 306b. To form the metallization layer 308b, the deposition tool 102 and / or the electroplating tool 112 may deposit the metallization layer 308b in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, another deposition operation described above in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 planarizes the metallization layer 308b after deposition by the deposition tool 102 and / or the electroplating tool 112.

[0079] In some embodiments, the pattern in the photoresist layer can be used to etch the metallization layer 308b to form the penetration region 334b. In these embodiments, a deposition tool 102 forms the photoresist layer on the metallization layer 308b. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches the metallization layer 308b based on the pattern to form the penetration region 334b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0080] As shown in Figure 5H, a second device (e.g., device 302a) is formed and included in the optoelectronic device 300. As shown in Figure 5H, a carrier structure 508 (glass carrier structure or silicon carrier structure, etc.) supports a layer 310a of semiconductor material. The deposition tool 102 can deposit the layer 310a of semiconductor material in PVD, ALD, CVD, epitaxial, oxidation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes the layer 310a of semiconductor material after the deposition tool 102 has deposited it.

[0081] As part of a series of operations, the STI region 314 is formed in the layer 310a of the semiconductor material. As an example, the deposition tool 102, the exposure tool 104, the development tool 106 and / or the etching tool 108 can perform a combination of lithography, etching and deposition operations to form the STI region 314 in the layer 310a of the semiconductor material.

[0082] Moving to Figure 5I, and as part of a series of operations, a photodiode 312a is formed in a layer 310a of semiconductor material. As an example, a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, and / or an ion implantation tool 114 can perform a combination of deposition, lithography, etching, and / or implantation operations to implant ions into a defined region below the substrate surface to form the photodiode 312a.

[0083] As shown in Figure 5J, dielectric region 306a is formed on and / or on layer 310a of semiconductor material. As part of forming dielectric region 306a, and as an example, deposition tool 102 may use CVD operation, PVD operation, ALD operation, another deposition operation described above in conjunction with Figure 1, and / or another suitable deposition operation to deposit one or more dielectric layers of dielectric region 306a. In some embodiments, planarization tool 110 planarizes one or more dielectric layers after deposition tool 102 has deposited the dielectric layers.

[0084] Alternatively, or as part of forming the dielectric region 306a, the deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 may perform a combination of deposition, lithography, and / or etching operations to form the metallization layer 308a. To form one or more metallization layers, the deposition tool 102 and / or electroplating tool 112 may deposit one or more metallization layers 308a in a CVD operation, PVD operation, ALD operation, electroplating operation, another deposition operation described above in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 planarizes one or more of the metallization layers 308 after deposition.

[0085] In some embodiments, the pattern in the photoresist layer can be used to etch the metallization layer 308a to form the penetration region 334a. In these embodiments, a deposition tool 102 forms the photoresist layer on the metallization layer 308a. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches the metallization layer 308a based on the pattern to form the penetration region 334a. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0086] As shown in Figure 5K, and as part of a series of operations, the bonding / separating / separating tool 116 can remove the carrier structure 508 (e.g., separate the carrier structure 508 and the semiconductor material layer 310a). Furthermore, as shown in Figure 5K, the bonding / separating tool can bond a portion of the dielectric region 306b and a portion of the device 302a including the photodiode 312a. In some embodiments, bonding a portion of the device 302a including the photodiode 312a includes performing a eutectic bonding operation using the bonding / separating / separating tool 116 to form a bonding interface 304 between the dielectric regions 306a and 306b. In some embodiments, forming the bonding interface 304 includes bonding the surfaces of conductive materials (e.g., copper) and / or dielectric materials at the surfaces of the dielectric regions 306a and 306b.

[0087] Moving to Figure 5L, and as part of a series of operations, etching tool 108 can form cavities 510 (e.g., cavities for DTI structure 318b) and cavities 512 (e.g., cavities for HA region 320). In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor material layer 310a to form cavities 510 and 512. In these embodiments, deposition tool 102 forms a photoresist layer on the semiconductor material layer 310a. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose the pattern. Etching tool 108 etches the semiconductor material layer 310a based on the pattern to form cavities 510 and 512 in the semiconductor material layer 310a. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some implementations, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0088] As shown in Figure 5M, an oxide layer 316a is formed on and / or on the semiconductor material layer 310a. The deposition tool 102 may deposit the oxide layer 316a in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes the oxide layer 316a after the deposition tool 102 has deposited it. As part of the formation of the oxide layer 316a, cavities 510 and 512 may be filled with oxide to form a DTI structure 318a and an HA region 320. In some embodiments, the deposition tool 102 deposits an anti-reflective (ARC) layer prior to the deposition of the oxide layer 316a.

[0089] As shown in Figure 5N, a BSI oxide layer 322 is formed on and / or on oxide layer 316a. Deposition tool 102 can deposit the BSI oxide layer 322 in PVD, ALD, CVD, epitaxial, oxidation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, planarization tool 110 planarizes the BSI oxide layer 322 after deposition by deposition tool 102.

[0090] Moving to Figure 50, and as part of a series of operations, a cavity 514 is formed through the BSI oxide layer 322, oxide layer 316a, and semiconductor material layer 310a to the STI region 314. In some embodiments, a pattern in the photoresist layer is used to etch the BSI oxide layer 322, oxide layer 316a, and semiconductor material layer 310a to form the cavity 514. In these embodiments, a deposition tool 102 forms a photoresist layer on the semiconductor material layer 310a. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches the cavity 514 based on the pattern to form the cavity 514 within the BSI oxide layer 322, oxide layer 316a, and semiconductor material layer 310a. In some embodiments, the etching operations include plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative to pattern-based etching of BSI oxide layer 322, oxide layer 316a, and semiconductor material layer 310a.

[0091] As shown in Figure 5P, a buffer oxide layer 324 is formed on and / or on the BSI oxide layer 322. The deposition tool 102 may deposit the buffer oxide layer 324 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction with Figure 1, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes the buffer oxide layer 324 after the deposition tool 102 has deposited it.

[0092] As shown in Figure 5Q, the cavity 516 is formed through the buffer oxide layer 324, through the STI region 314, and into the dielectric region 306a. In some embodiments, a pattern in the photoresist layer is used to etch the buffer oxide layer 324, the STI region 314, and the dielectric region 306a to form the cavity 516. In these embodiments, a deposition tool 102 forms a photoresist layer on the buffer oxide layer 324. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches the buffer oxide layer 324, the STI region 314, and the dielectric region 306a based on the pattern to form the cavity 516 through the buffer oxide layer 324, through the STI region 314, and into the dielectric region 306a. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative to the pattern-based etch buffer oxide layer 324, STI region 314, and dielectric region 306a.

[0093] As part of a series of operations and as shown in Figure 5R, bonding pads 326 are formed in cavity 516. As an example, deposition tool 102, exposure tool 104, development tool 106 and / or etching tool 108 may perform a combination of deposition, lithography and / or etching operations to form bonding pads 326.

[0094] Moving to Figure 5S, and as part of a series of operations, the filter layer 328 and the microlens layer 330 are formed on and / or on the buffer oxide layer 324. As an example, the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 can perform a combination of deposition, lithography, and / or etching operations to form the filter layer 328 and the microlens layer 330.

[0095] As described above, Figures 5A through 5S are provided as examples. Other examples may differ from those described with respect to Figures 5A through 5S.

[0096] Figure 6 is a schematic diagram of an example optoelectronic device 600 including the polarization shield structure 332 described herein. As shown in Figure 6, the optoelectronic device 600 includes photodiodes 312a and 312c. In the exemplary embodiment shown in Figure 6, the exemplary optoelectronic device 600 includes a large-polarization NIR photodiode (e.g., photodiode 312c). The large size of the polarization NIR photodiode can increase the absorption of NIR light and can increase the efficiency of the optoelectronic device 600, etc.

[0097] In some embodiments of the optoelectronic device 600, multiple portions of the device 302a include photodiodes 312a that facilitate the sensing of VIS light waves. For example, the semiconductor material layer 310a may include silicon (Si), and the photodiode 312a may include dopants such as boron (B), aluminum (Al), phosphorus (P), or arsenic (As) dopants.

[0098] Furthermore, in some embodiments of the optoelectronic device 600, multiple portions of the device 302b include photodiodes 312c that facilitate the sensing of NIR light waves. For example, the semiconductor material layer 310b may include indium gallium arsenide (InGaAs), and the photodiode 312c may include dopants such as silicon (Si) dopants.

[0099] Alternatively, the width D6 of photodiode 312c may be larger than the width D7 of photodiode 312a. As an example, the width D6 may range from about 2000 nanometers to about 2500 nanometers, and the width D7 may range from about 500 nanometers to about 700 nanometers.

[0100] If the width D6 is less than about 2000 nanometers, the sensitivity of the photodiode 312c (e.g., sensitivity to NIR light waves) may not meet the performance threshold. If the width D6 is greater than about 2500 nanometers, the size of the optoelectronic device 300 may increase and fail to meet the size threshold and / or increase the cost of the optoelectronic device. However, other values ​​and ranges of the width D6 are also within the scope of this disclosure.

[0101] Alternatively, if the width D7 is less than about 500 nanometers, the sensitivity of the photodiode 312a (e.g., sensitivity to VIS light waves) may not meet the performance threshold. If the width D7 is greater than about 700 nanometers, the size of the pixel array including the photodiode 312a (e.g., the size of pixel array 200) may increase, failing to meet the size threshold and / or increasing the cost of the optoelectronic device. However, other values ​​and ranges of the width D7 are also within the scope of this disclosure.

[0102] In some embodiments, as shown in Figure 6, device 302b includes at least one isolation structure (e.g., DIT structure 318b) located below polarizing shield structure 332 and adjacent to photodiode 312c. Further, as shown in Figure 6, photodiode 312c, polarizing shield structure 332, and photodiode (of photodiode 312a) are vertically arranged (e.g., coaxially arranged).

[0103] As mentioned above, Figure 6 provides an example. Other examples may differ from those described regarding Figure 6.

[0104] Figure 7 is a schematic diagram of example components of one or more of the devices of Figure 1 described in this disclosure. Device 700 may correspond to one or more of semiconductor processing tools 102-116 and / or wafer / wafer transfer tools 118. In some embodiments, one or more of semiconductor processing tools 102-116 and / or wafer / wafer transfer tools 118 may include one or more devices 700 and / or one or more components of device 700. As shown in Figure 7, device 700 may include bus 710, processor 720, memory 730, input component 740, output component 750, and / or communication component 760.

[0105] Bus 710 may include one or more components enabling wired and / or wireless communication between components of device 700. Bus 710 may couple two or more components of Figure 7 together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 710 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 720 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 720 may be implemented in hardware, firmware, or a combination of hardware and firmware. In some implementations, processor 720 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere in this disclosure.

[0106] Memory 730 may include volatile and / or nonvolatile memory. For example, memory 730 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 730 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus). Memory 730 may be non-transitory computer-readable medium. Memory 730 may store information related to the operation of device 700, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 730 may include one or more memories, such as those coupled (e.g., communication-coupled) to one or more processors (e.g., processor 720) via bus 710. The communication coupling between the processor 720 and the memory 730 enables the processor 720 to read and / or process information stored in the memory 730 and / or store information in the memory 730.

[0107] Input component 740 enables device 700 to receive input, such as user input and / or sensed input. For example, input component 740 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system sensor, global navigation satellite system sensor, accelerometer, gyroscope, and / or actuator. Output component 750 enables device 700 to provide output, such as via a display, speaker, and / or light-emitting diode. Communication component 760 enables device 700 to communicate with other devices via wired and / or wireless connections. For example, communication component 760 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0108] Device 700 can perform one or more operations or processes described in this disclosure. For example, a non-transitory computer-readable medium (e.g., memory 730) can store a set of instructions (e.g., one or more instructions or codes) for execution by processor 720. Processor 720 can execute a set of instructions to perform one or more operations or processes described in this disclosure. In some embodiments, execution of the set of instructions by one or more processors 720 causes one or more processors 720 and / or device 700 to perform one or more operations or processes described in this disclosure. In some embodiments, hardwired circuitry may be used instead of or in combination with instructions to perform one or more operations or processes described in this disclosure. Additionally or alternatively, processor 720 may be configured to perform one or more operations or processes described in this disclosure. Therefore, the embodiments described in this disclosure are not limited to any particular combination of hardware circuitry and software.

[0109] The number and configuration of components illustrated in Figure 7 are provided as examples. Device 700 may include additional components, fewer components, different components, or components arranged differently compared to those shown in Figure 7. Alternatively or additionally, a set of components of device 700 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 700.

[0110] Figure 8 is a flowchart of an example process 800 associated with forming an optoelectronic device including a polarizing shield structure. In some embodiments, one or more processing blocks of Figure 8 are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116). Alternatively or additionally, one or more processing blocks of Figure 8 may be performed by one or more components of device 700, such as processor 720, memory 730, input component 740, output component 750, and / or communication component 760.

[0111] As shown in Figure 8, process 800 may include forming a first photodiode (block 810) in a layer of semiconductor material. For example, one or more of the semiconductor processing tools 102-116 may form the first photodiode (e.g., photodiode 312b) in a layer of semiconductor material (e.g., layer 310b of semiconductor material), as described herein.

[0112] As further shown in Figure 8, process 800 may include forming a first portion (block 820) of a dielectric region over the first photodiode. For example, one or more of semiconductor processing tools 102-116 may form a first portion of the dielectric region over the first photodiode (e.g., portion 306b1 of dielectric region 306b), as described herein.

[0113] As further shown in Figure 8, process 800 may include forming a polarizing mask structure (block 830) over a first portion of the dielectric region. For example, one or more of the semiconductor processing tools 102-116 may form a polarizing mask structure (e.g., polarizing mask structure 332) over the first portion of the dielectric region, as described herein. In some embodiments, forming a polarizing mask structure over the first portion of the dielectric region includes a vertically aligned polarizing mask structure and a first photodiode.

[0114] As further shown in Figure 8, process 800 may include forming a second portion of the dielectric region over a first portion of the dielectric region and over a polarizing mask structure (block 840). For example, one or more of the semiconductor processing tools 102-116 may form a second portion of the dielectric region (e.g., portion 306b2 of dielectric region 306b) over the first portion of the dielectric region and over the polarizing mask structure, as described herein.

[0115] As further shown in Figure 8, process 800 may include joining a dielectric region and a portion of a device including a second photodiode (block 850). For example, one or more of semiconductor processing tools 102-116 may join a dielectric region (e.g., dielectric region 306) to a portion of a device including a second photodiode (e.g., a portion of device 302a including photodiode 312a), as described herein. In some embodiments, joining the dielectric region and the device including the second photodiode includes vertically aligning the second photodiode and a polarizing shield structure.

[0116] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or combined with one or more other processes described elsewhere herein.

[0117] In a first embodiment, forming a polarization mask structure on a first portion of a dielectric region includes forming a substrate layer (e.g., substrate layer 406) on the first portion of the dielectric region, forming a capping layer (e.g., capping layer 408) on the substrate layer, and removing portions of the substrate layer and the capping layer to form an array of polarization beam structures (e.g., polarization beam structure 402) dispersed along a plurality of axes generally parallel to a polarization axis (e.g., polarization axis 404), wherein the array of polarization beam structures includes a plurality of remaining portions of the capping layer above a plurality of remaining portions of the substrate layer.

[0118] In the second embodiment, joining the dielectric region and the device including the second photodiode, either alone or in combination with the first embodiment, includes joining the dielectric region and the device including the second photodiode using a eutectic bonding process.

[0119] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 800 includes forming an optical filter structure (e.g., filter layer 328) over the second photodiode, wherein forming the optical filter structure over the second photodiode includes a vertically aligned optical filter structure and a polarization shield structure.

[0120] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 800 includes forming a metallization layer (e.g., metallization layer 308a) in a second portion of the device region above the polarization shield structure.

[0121] In the fifth embodiment, forming a metallization layer in a second portion of the dielectric region above the polarization mask structure, either alone or in combination with one or more of the first to fourth embodiments, includes forming a penetration region (e.g., penetration region 334a) between segments of the metallization layer, wherein forming the penetration region includes vertically aligning the penetration region and the polarization mask structure.

[0122] Although Figure 8 illustrates example blocks of process 800, in some implementations, process 800 includes additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to those depicted in Figure 8. Alternatively, two or more blocks of process 800 may be executed in parallel.

[0123] Although Figure 8 illustrates example blocks of process 800, in some implementations, process 800 includes additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to those depicted in Figure 8. Alternatively, two or more blocks of process 800 may be executed in parallel.

[0124] Some embodiments described herein include a CIS device and techniques for forming a CIS device. The CIS device includes a first array of photodiodes stacked above a second array of photodiodes. A polarization structure is located between the first array of photodiodes and the second array of photodiodes. Signaling generated by the first array of photodiodes (e.g., a signal corresponding to an unpolarized light wave) can be multiplexed with signaling generated by the second array of photodiodes (e.g., a signal corresponding to a polarized light wave). The CIS device also includes a filter structure that filters VIS and NIR light waves between the first and second arrays of photodiodes.

[0125] In this manner, reflected light waves (including unpolarized VIS, polarized VIS, unpolarized NIR, and / or polarized NIR) from the target object are simultaneously captured by a single CIS device. This improves the performance of an image processing system that multiplexes simultaneously captured unpolarized VIS, polarized VIS, unpolarized NIR, and / or polarized NIR light waves, compared to another image processing system that multiplexes unpolarized VIS, which can be captured by separate, discrete devices with timing offsets. This improved performance leads to a reduction in the computational resources required for the image processing system. Furthermore, by combining unpolarized visible light detection capabilities, polarized visible light detection capabilities, unpolarized near-infrared light detection capabilities, and polarized near-infrared light detection capabilities into a single CIS device, the semiconductor manufacturing resources required to manufacture the image processing system (e.g., semiconductor manufacturing tools, raw materials, manpower, and / or computational resources) are reduced.

[0126] As described in more detail above, some embodiments described herein provide an apparatus. The apparatus includes an optical filter structure. The apparatus includes a first photodiode located in a first device region below the optical filter structure. The apparatus includes a second photodiode in a second device device located below the first photodiode. The apparatus includes a polarizing shield structure located between the first and second photodiodes.

[0127] In some embodiments, the first photodiode and the second photodiode correspond to multiple near-infrared photodiodes. In some embodiments, the first photodiode and the second photodiode correspond to multiple visible light photodiodes. In some embodiments, the device further includes a first dielectric region and a second dielectric region, wherein the first dielectric region includes multiple first metallization layers and is located below the first device region, and wherein the second dielectric region includes multiple second metallization layers and a polarization shield structure, and is located below the first dielectric region and above the second device region. In some embodiments, the first dielectric region includes multiple first penetration regions that allow multiple light waves to pass between multiple segments of the first metallization layers and reach the second dielectric region, and wherein the second dielectric region includes multiple second penetration regions that allow the light waves to pass between multiple segments of the second metallization layers and enter the polarization shield junction. In some embodiments, the device further includes at least one isolation structure located below the polarization shield structure and adjacent to one side of the second photodiode. In some embodiments, the polarization mask structure is a first polarization mask structure comprising at least two first polarized beam structures dispersed along a plurality of first axes generally parallel to a first polarization axis, and further comprising: a second polarization mask structure adjacent to the first polarization mask structure, and comprising at least two second polarized beam structures dispersed along a plurality of second axes generally parallel to a second polarization axis. In some embodiments, the first polarization axis and the second polarization axis comprise different approximate angular directions.

[0128] As described in more detail above, some embodiments described herein provide an apparatus. The apparatus includes an optical filter structure having a transmittance that allows both red visible light and near-infrared light to pass through the optical filter structure. The apparatus includes a red visible light photodiode located in a first device region below the optical filter structure. The apparatus includes a near-infrared photodiode located in a second device region below the red visible light photodiode. The apparatus includes a polarizing shield structure located between the red visible light photodiode and the near-infrared photodiode.

[0129] In some embodiments, the optical filter structure is configured to block multiple electromagnetic waves having wavelengths less than about 600 nanometers and multiple electromagnetic waves having wavelengths greater than about 1000 nanometers. In some embodiments, the width of the near-infrared photodiode includes a width greater than that of a red visible light photodiode. In some embodiments, the polarization shield structure includes an array of multiple polarization beam structures dispersed along multiple axes approximately parallel to the polarization axis. In some embodiments, each polarization beam structure in the array of polarization beam structures includes a substrate layer of a first material and a capping layer of a second material. In some embodiments, the substrate layer of the first material includes titanium, and the capping layer of the second material includes gold, copper, nickel-cobalt, or nickel-iron.

[0130] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first photodiode in a layer of semiconductor material. The method includes forming a first portion of a dielectric region over the first photodiode. The method includes forming a polarizing shield structure over the first portion of the dielectric region, wherein forming the polarizing shield structure over the first portion of the dielectric region includes vertically aligning the polarizing shield structure and the first photodiode. The method includes forming a second portion of the dielectric region over the first portion of the dielectric region and over the polarizing shield structure. The method includes bonding the dielectric region and a portion of a device including a second photodiode, wherein bonding the dielectric region and a portion of the device including the second photodiode includes vertically aligning the second photodiode and the polarizing shield structure.

[0131] In some embodiments, forming a polarizing shield structure over a first portion of the dielectric region includes: forming a substrate layer on the first portion of the dielectric region; forming a capping layer on the substrate layer; and removing multiple portions of the substrate layer and the capping layer to form an array of multiple polarizing beam structures, wherein the array of polarizing beam structures includes multiple remaining portions of the capping layer located over multiple remaining portions of the substrate layer. In some embodiments, connecting the dielectric region and the portion of the device containing the second photodiode includes: bonding the dielectric region and the portion of the device containing the second photodiode using a eutectic bonding process. In some embodiments, the method of manufacturing the optoelectronic device further includes forming a light filter structure over the second photodiode, wherein forming the light filter structure over the second photodiode includes a vertically aligned light filter structure and a polarizing shield structure. In some embodiments, the method of manufacturing the optoelectronic device further includes forming a metallization layer in a second portion of the dielectric region over the polarizing shield structure. In some embodiments, the second portion of the dielectric region over which the metallization layer is formed includes forming a penetration region between multiple segments of the metallization layer, wherein the penetration region includes a vertically aligned penetration region and the polarization mask structure.

[0132] As used herein, the term "and / or" when used in conjunction with multiple items is intended to cover each individual item in the multiple items as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0133] As used in this article, "meeting the threshold" can refer to values ​​that are greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, or not equal to the threshold, depending on the context.

[0134] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can readily use the various embodiments of this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the various embodiments of this disclosure, and that various changes, substitutions, and replacements can be made herein without departing from the spirit and scope of the various embodiments of this disclosure.

[0135] 100: Environment 102: Sedimentation tools 104: Exposure Tools 106: Developing tools 108: Etching Tools 110: Flattening tool 112: Electroplating tools 114: Ion Implantation Tools 116: Joining / Separating / Separation Tools 118: Teleportation Tool 200: pixel array 202: Pixel Sensor 202a: Pixel Sensor 202b: Pixel Sensor 202c: Pixel Sensor 202d: Pixel Sensor 300: Optoelectronic devices 302a: Optoelectronic devices 302b: Optoelectronic device 304: Joint Interface 306a: Dielectric region 306b: Dielectric region 306b1: Partial 306b2: Partial 308a: Metallization layer 308b: Metallization layer 310a: Layer of semiconductor material 310b: Layer of semiconductor material 312a: Photodiode 312b: Photodiode 312c: Photodiode 314: Shallow trench isolation area 316a: Oxide layer 316b: Oxide layer 318a: Deep trench isolation structure 318b: Deep trench isolation structure 320: High absorption region 322: Backside irradiation oxide layer 324: Buffer oxide layer 326: Bonding pad 328: Filter layer 328a: Partial 328b: Partial 328c: Partial 328d: Partial 330: Microlens layer 332: Polarizing Shield Structure 332a: Polarizing shield structure 332b: Polarizing shield structure 332c: Polarizing shield structure 332d: Polarizing shield structure 334a: Penetration Area 334b: Penetration Area 336: Light Wave 400: Implementation Method 402: Polarized beam structure 402a: Polarized beam structure 402b: Polarized beam structure 402c: Polarized beam structure 402d: Polarized beam structure 404: Polarization axis 404a: Polarization axis 404b: Polarization axis 404c: Polarization axis 404d: Polarization axis 406: Basal layer 408: Overlay 500: Implementation Method 502: Carrier Structure 504: Carrier Structure 506: Cavity 508: Carrier Structure 510: Cavity 512: Cavity 514: Cavity 516: Cavity 600: Optoelectronic devices 700: Device 710: Busbar 720: Processor 730: Memory 740: Input Component 750: Output Component 760: Communication Components 800: Process 810: Square 820: Square 830: Square 840: Square 850: Square D1: Width D2: Spacing D3: height D4: Altitude D5: Altitude D6: Width D7: Width

[0136] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An optoelectronic device, comprising: a light filter structure; a first photodiode and a second photodiode disposed in a semiconductor layer and located in a first device region below the light filter structure, wherein an upper surface of the semiconductor layer has a sawtooth structure; a first dielectric region located below the first device region; a third photodiode and a fourth photodiode located in a second device region below the first photodiode; and a first polarization shield structure located between the first photodiode and the third photodiode, and perpendicularly aligned with the first photodiode and the third photodiode. A second polarizing shield structure is located between the second photodiode and the fourth photodiode, and is perpendicularly aligned with the second photodiode and the fourth photodiode; and a second dielectric region is located below the first dielectric region and above the second device region, wherein the first polarizing shield structure and the second polarizing shield structure are located in the second dielectric region, wherein the first dielectric region is directly bonded to the second dielectric region, and there is a bonding interface between the first dielectric region and the second dielectric region.

2. The photoelectric device as described in claim 1, wherein: The first dielectric region includes a plurality of first metallization layers; and the second dielectric region includes a plurality of second metallization layers.

3. The optoelectronic device as claimed in claim 2, wherein the first dielectric region includes: a plurality of first penetration regions that allow a plurality of light waves to pass between a plurality of segments of the first metallization layers and reach the second dielectric region, and wherein the second dielectric region includes: a plurality of second penetration regions that allow the light waves to pass between a plurality of segments of the second metallization layers and enter the first polarization shield structure and the second polarization shield structure.

4. The optoelectronic device as claimed in claim 1 further comprises: at least one isolation structure located below the first polarizing shield structure and the second polarizing shield structure and between the third photodiode and the fourth photodiode.

5. An optoelectronic device, comprising: a light filter structure having a transmittance that allows multiple red visible light waves and multiple near-infrared light waves to pass through the light filter structure; a first red visible light photodiode and a second red visible light photodiode disposed in a semiconductor layer and located in a first device region below the light filter structure, wherein an upper surface of the semiconductor layer has a sawtooth structure; a first dielectric region located below the first device region; and a first near-infrared light photodiode and a second near-infrared light photodiode located in a second device region below the first red visible light photodiode and the second red visible light photodiode. A first polarizing shield structure is located between the first red visible light photodiode and the first near-infrared photodiode; a second polarizing shield structure is located between the second red visible light photodiode and the second near-infrared photodiode; and a second dielectric region is located below the first dielectric region and above the second device region, wherein the first polarizing shield structure and the second polarizing shield structure are located in the second dielectric region, wherein the first dielectric region is directly bonded to the second dielectric region, and a bonding interface is formed between the first dielectric region and the second dielectric region.

6. The optoelectronic device as claimed in claim 5, wherein the width of the first near-infrared photodiode includes a width that is larger than the width of the first red visible photodiode.

7. The optoelectronic device as claimed in claim 5, wherein the first polarizing shield structure or the second polarizing shield structure comprises: an array of a plurality of polarizing beam structures dispersed along a plurality of axes approximately parallel to a polarization axis.

8. The optoelectronic device as claimed in claim 7, wherein each polarization beam structure of the array of polarization beam structures comprises: a substrate layer of a first material and a capping layer of a second material.

9. A method of manufacturing an optoelectronic device, comprising: forming a first photodiode and a second photodiode in a layer of semiconductor material, wherein an upper surface of the layer has a serrated structure; forming a first portion of a first dielectric region above the first photodiode and the second photodiode; forming a first polarizing shield structure and a second polarizing shield structure above the first portion of the first dielectric region, wherein the first polarizing shield structure above the first portion of the first dielectric region includes perpendicular alignment of the first polarizing shield structure and the first photodiode, and perpendicular alignment of the second polarizing shield structure and the second photodiode; forming a second portion of the first dielectric region covering the first portion of the first dielectric region, the first polarizing shield structure, and the second polarizing shield structure; A second dielectric region is formed below a portion of a device including a third photodiode and a fourth photodiode; and the first dielectric region and the second dielectric region are connected such that a bonding interface exists between the first dielectric region and the second dielectric region, wherein after connecting the first dielectric region and the second dielectric region, the third photodiode is perpendicularly aligned with the first polarizing shield structure and the fourth photodiode is perpendicularly aligned with the second polarizing shield structure.

10. The method of manufacturing an optoelectronic device as claimed in claim 9, wherein connecting the first dielectric region and the second dielectric region comprises: bonding the first dielectric region and the second dielectric region using a eutectic bonding process.

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