Semiconductor device

Abstract

This disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a light-emitting structure. The first semiconductor structure includes a first confinement layer and a first cladding layer adjacent to the first confinement layer. The second semiconductor structure is located on the first semiconductor structure and includes a second confinement layer. The light-emitting structure is located between the first semiconductor structure and the second semiconductor structure and includes a first multiple quantum well structure. The first multiple quantum well structure has multiple pairs of semiconductor stacks. Each pair of semiconductor stacks consists of a well layer and a barrier layer. The first confinement layer and the second confinement layer are adjacent to the light-emitting structure. The well layer and the barrier layer in each pair of semiconductor stacks contain the same quaternary III-V semiconductor material, which includes InGaAsP, AlGaInAs, or InGaNAs.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor optoelectronic device comprising a light-emitting structure. Prior Technology

[0002] Semiconductor components play a crucial role in information transmission and energy conversion, and research and development of related materials continues. For example, group III-V semiconductor materials, containing group III and group V elements, can be used in various optoelectronic components, such as light-emitting diodes (LEDs), laser diodes (LDs), and solar cells. In recent years, these optoelectronic components have also been widely used in lighting, displays, communications, sensing, and power systems. LEDs are suitable for solid-state lighting sources and have advantages such as low power consumption and long lifespan. They have gradually replaced traditional light sources and are widely used in traffic signals, display backlight modules, various lighting and medical devices. Summary of the Invention

[0003] This disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a light-emitting structure. The first semiconductor structure includes a first confinement layer and a first cladding layer adjacent to the first confinement layer. The second semiconductor structure is located on the first semiconductor structure and includes a second confinement layer. The light-emitting structure is located between the first semiconductor structure and the second semiconductor structure and includes a first multiple quantum well structure. The first multiple quantum well structure has multiple pairs of semiconductor stacks, each pair of semiconductor stacks consisting of a well layer and a barrier layer. The first confinement layer and the second confinement layer are adjacent to the light-emitting structure, and the well layer and the barrier layer in each pair of semiconductor stacks contain the same quaternary III-V semiconductor material, including InGaAsP, AlGaInAs, or InGaNAs.

[0004] The well layer has a first indium content percentage, the barrier layer has a second indium content percentage less than the first indium content percentage, and the light-emitting structure emits radiation when the semiconductor device is in operation. The radiation is non-homogeneous light with a peak wavelength in the range of 700 nm to 3000 nm. The first or second barrier layer and the light-emitting structure contain different materials, and the first coating layer contains a ternary semiconductor material.

[0005] This disclosure provides a packaging structure for a semiconductor device, including a carrier, a semiconductor device, and a packaging material. The semiconductor device is located on the carrier. The packaging material covers the semiconductor device. Simple Explanation of the Diagram

[0006] Figure 1A is a top view of a semiconductor device according to an embodiment of this disclosure.

[0007] Figure 1B is a cross-sectional view and a partially enlarged view of a semiconductor device according to an embodiment of this disclosure.

[0008] Figure 1C is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 1D is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1E is a cross-sectional structural diagram of a semiconductor device according to an embodiment of this disclosure.

[0011] Figure 2 shows the relationship between the luminous power and current of the semiconductor device AC in an experimental example of this disclosure.

[0012] Figure 3 shows the relationship between the luminous power and current of a semiconductor element DF in an experimental example of this disclosure.

[0013] Figure 4 shows the relationship between the luminous power and current of the semiconductor device GI in an experimental example of this disclosure.

[0014] Figure 5 shows the relationship between the luminous power of semiconductor device JL and the logarithm of the semiconductor stack in an experimental example of this disclosure.

[0015] Figure 6 is a schematic cross-sectional view of a semiconductor packaging structure according to an embodiment of the present disclosure. Implementation

[0016] The following embodiments will illustrate the concept of the invention with accompanying drawings. In the drawings or description, similar or identical components are represented by the same reference numerals, and unless otherwise specified, the shapes or dimensions of the elements in the drawings are merely illustrative and are not actually limited thereto. It should be noted that elements not shown or described in the drawings may be in forms known to those skilled in the art.

[0017] In the present disclosure, if there is no special description, the general formula InGaAsP represents In a1Ga 1-a1As b1P 1-b1, where 0 < a1 < 1 and 0 < b1 < 1; the general formula InGaP represents In a2Ga 1-a2P, where 0 < a2 < 1; the general formula InGaAs represents In a3Ga 1-a3As, where 0 < a3 < 1; the general formula AlGaAs represents Al a4Ga 1-a4As, where 0 < a4 < 1; the general formula AlGaInAs represents Al a5Ga a6In 1-a5-a6As, where 0 < a5 < 1 and 0 < a6 < 1; the general formula InGaNAs represents In a7Ga 1-a7N a8As 1-a8, where 0 < a7 < 1 and 0 < a8 < 1. Adjusting the content of the elements can achieve different purposes, such as, but not limited to, adjusting the energy level, or when the semiconductor device is a light-emitting device, adjusting the main emission wavelength of the light-emitting device.

[0018] Those of ordinary skill in the art should understand that other components can be added based on the embodiments described below. For example, without special description, similar descriptions such as "the first layer (or structure) is located on the second layer (or structure)" can include embodiments where the first layer (or structure) is in direct contact with the second layer (or structure), and can also include embodiments where there are other structures between the first layer (or structure) and the second layer (or structure) and they are not in direct contact with each other. In addition, it should be understood that the up-down positional relationship of each layer (or structure) may change depending on the observation direction. Furthermore, in the present disclosure, the description that a layer or structure "substantially consists of X" means that the main component of the above layer or structure is X, but does not exclude that the above layer or structure contains additives or inevitable impurities.

[0019] The qualitative or quantitative analysis of the composition of each layer and additives included in the semiconductor device of the present disclosure can be obtained by any suitable method, such as a secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be obtained by any suitable method, such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0020] Figure 1A is a top view of a semiconductor element 10 according to an embodiment of the present disclosure. Figure 1B is a cross-sectional view and a partially enlarged view of the semiconductor element 10 in Figure 1A along line A-A'. As shown in Figure 1B, the semiconductor element 10 includes a substrate 100, a first semiconductor structure 110, a second semiconductor structure 120, a light-emitting structure 130, a first electrode 140, and a second electrode 150. The first semiconductor structure 110 and the second semiconductor structure 120 are located on the substrate 100. The light-emitting structure 130 is located between the first semiconductor structure 110 and the second semiconductor structure 120. The first electrode 140 is in contact with the substrate 100 and forms an electrical connection, and the second electrode 150 is in contact with the second semiconductor structure 120 and forms an electrical connection. The first semiconductor structure 110, the second semiconductor structure 120, and the light-emitting structure 130 can be obtained by epitaxial growth. Epitaxial growth methods include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE).

[0021] The substrate 100 may contain a conductive material, such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or silicon (Si) substrate. The substrate 100 may be, for example, a growth substrate used for the aforementioned epitaxial growth, but is not limited thereto. In one embodiment, the substrate 100 may be a support substrate bonded to the epitaxial structure using a bonding layer after the growth substrate has been removed.

[0022] The first semiconductor structure 110 and the second semiconductor structure 120 are located on both sides of the light-emitting structure 130 and adjacent to it. The first semiconductor structure 110 and the second semiconductor structure 120 may each be composed of a single layer or multiple layers. The first semiconductor structure 110 and the second semiconductor structure 120 may each contain binary, ternary, or quaternary III-V group semiconductor materials, preferably materials containing aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In), such as InP, InAlAs, GaAs, InGaP, AlGaAs, AlGaInAs, etc. The first semiconductor structure 110 and the second semiconductor structure 120 may have opposite conductivity types to provide electrons and holes, respectively. For example, the first semiconductor structure 110 may be n-type and the second semiconductor structure 120 may be p-type, or the first semiconductor structure 110 may be p-type and the second semiconductor structure 120 may be n-type. The conductivity of the first semiconductor structure 110 and the second semiconductor structure 120 can be adjusted by adding different dopants, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si) or tellurium (Te).

[0023] The light-emitting structure 130 is located on the substrate 100 and may contain a III-V group semiconductor material, such as a ternary or quaternary semiconductor material, and preferably contains aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In one embodiment, the light-emitting structure 130 is an undoped semiconductor structure, that is, no other dopants are intentionally added during the formation of the light-emitting structure 130. The light-emitting structure 130 may contain a multiple quantum well structure M. The multiple quantum well structure M may contain n pairs of semiconductor stacks formed by alternating stacks of multiple well layers and multiple barrier layers, and each semiconductor stack may be represented by Cn, where n = 1, 2, 3, …, N. In some embodiments, N is preferably a positive integer greater than or equal to 2, and may be a positive integer less than or equal to 20, such as 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20. Each semiconductor stack Cn can be composed of a well layer Wn and an adjacent barrier layer Bn, where n = 1, 2, 3, …, N. In one embodiment, the barrier layer Bn in the semiconductor stack Cn of the multiple quantum well structure M has a thickness less than that of the adjacent well layer Wn. In some embodiments, the thickness of the barrier layer Bn being less than that of the well layer Wn can make the carrier distribution in the multiple quantum well structure M more uniform, improve the local recombination of electrons and holes in the multiple quantum well structure M, and thus help improve the internal quantum efficiency (IQE). In one embodiment, the ratio of the thickness of the well layer Wn to the thickness of the barrier layer Bn is greater than 1 and less than or equal to 5, for example: 1.5, 2, 2.5, 3, 3.5, 4, or 4.5. In one embodiment, the ratio of the thickness of the well layer Wn to the thickness of the barrier layer Bn in at least two pairs of semiconductor stacks Cn is greater than 1 and less than or equal to 5, for example: 1.5, 2, 2.5, 3, 3.5, 4, or 4.5. In another embodiment, the ratio of the thickness of the well layer Wn to the thickness of the barrier layer Bn in each pair of semiconductor stacks Cn is greater than 1 and less than or equal to 5, for example: 1.5, 2, 2.5, 3, 3.5, 4, or 4.5. In some embodiments, the thickness ratio of the barrier layer Bn to the well layer Wn in each pair of semiconductor stacks Cn is between 1:1.5 and 1:5, for example: 1:2, 1:2.5, 1:3, 1:3.5, 1:4, or 1:4.5. In some embodiments, the thickness of the well layer Wn and the thickness of the barrier layer Bn fall within the range of 1 nm to 20 nm, for example: 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm or 19 nm.By ensuring that the thickness ratio of the barrier layer Bn to the well layer Wn falls within the aforementioned range, the semiconductor device 10 can exhibit superior luminous power. In one embodiment, the thickness of the barrier layer Bn in at least two pairs of semiconductor stacks Cn is greater than the thickness of the well layer Wn. In one embodiment, the thickness of the barrier layer Bn in each pair of semiconductor stacks Cn included in the multiple quantum well structure M is greater than the thickness of the well layer Wn.

[0024] A partial enlarged view in Figure 1B illustrates a multiple quantum well structure M according to one embodiment. As shown in Figure 1B, in this embodiment, the multiple quantum well structure M comprises more than three pairs of semiconductor stacks (i.e., n>3), such as well layers W1, W2, ..., WN, barrier layers B1, B2, ..., and BN, where N is a positive integer greater than or equal to 4. Well layer W1 is adjacent to and in direct contact with the first semiconductor structure 110, and barrier layer BN is adjacent to and in direct contact with the second semiconductor structure 120. In this embodiment, well layer W1 and barrier layer B1 form a pair of semiconductor stacks C1, well layer W2 and barrier layer B2 form a pair of semiconductor stacks C2, and well layer WN and barrier layer BN form a pair of semiconductor stacks CN. In Figure 1B, only three pairs of semiconductor stacks are shown for the sake of simplicity; other semiconductor stacks are not depicted. In reality, the form of the light-emitting structure 130 is not limited to this.

[0025] Specifically, the material of the multiple quantum well structure M may include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In one embodiment, the multiple quantum well structure M may include a quaternary semiconductor material, such as InGaAsP, AlGaInAs, or InGaNAs. In one embodiment, the multiple quantum well structure M is substantially composed of a quaternary semiconductor material (such as InGaAsP, AlGaInAs, or InGaNAs). In one embodiment, the well layer Wn and the barrier layer Bn contain the same quaternary semiconductor material, such as InGaAsP, AlGaInAs, or InGaNAs. In one embodiment, the well layer Wn and the barrier layer Bn are substantially each composed of the same quaternary semiconductor material (such as InGaAsP, AlGaInAs, or InGaNAs). In one embodiment, the well layer Wn in each semiconductor stack Cn contains the same quaternary semiconductor material (such as InGaAsP, AlGaInAs, or InGaNAs), for example, well layer W1 and well layer W2 are made of the same material. In one embodiment, the barrier layer Bn in each semiconductor stack Cn comprises the same quaternary semiconductor material (such as InGaAsP, AlGaInAs, or InGaNAs). For example, barrier layer B1 and barrier layer B2 are made of the same material. In another embodiment, the well layer Wn and the barrier layer Bn in each semiconductor stack Cn comprise the same quaternary semiconductor material (such as InGaAsP, AlGaInAs, or InGaNAs). For example, well layer W1, well layer W2, barrier layer B1, and barrier layer B2 are all made of the same material.

[0026] In some embodiments, the well layer Wn in each semiconductor stack Cn has lattice mismatch with the substrate 100, resulting in tensile or compressive stress. In some embodiments, when the well layer Wn has compressive stress, it can reduce interval band absorption losses and improve quantum efficiency. In some embodiments, the barrier layer Bn in each semiconductor stack Cn has lattice mismatch with the substrate 100, resulting in tensile or compressive stress. In some embodiments, the barrier layer Bn and the well layer Wn in each semiconductor stack Cn may have stresses in the same direction or opposite directions relative to the substrate 100. In some embodiments, when the barrier layer Bn has stresses opposite to those of the well layer Wn, it can have a stress compensation effect, which can prevent epitaxial defects. In some embodiments, the barrier layer Bn has tensile strain relative to the substrate 100, and the well layer Wn has compressive strain. In one embodiment, the barrier layer Bn has compressive stress relative to the substrate 100, and the well layer Wn has tensile stress. In some embodiments, there is a lattice mismatch between the well layer Wn and the barrier layer Bn. In one embodiment, there is a lattice mismatch between a well layer Wn and a barrier layer Bn in a semiconductor stack Cn. In one embodiment, there is a lattice mismatch between the well layer Wn and the barrier layer Bn in each pair of semiconductor stacks Cn included in the multiple quantum well structure M. By subjecting the well layers and barrier layers in the semiconductor device to stress relative to the substrate, the forward voltage (Vf) of the semiconductor device can be further improved, and the efficiency of the semiconductor device can be enhanced.

[0027] In one embodiment, both the barrier layer Bn and the well layer Wn in each semiconductor stack Cn are made of aluminum. In one embodiment, the percentage of aluminum content in the barrier layer Bn in each semiconductor stack Cn is greater than the percentage of aluminum content in the well layer Wn. In some embodiments, the percentage of aluminum content in the barrier layer Bn in the semiconductor stack Cn is greater than the percentage of aluminum content in the well layer Wn, and also greater than the percentage of aluminum content in the well layer of the adjacent semiconductor stack (e.g., semiconductor stack Cn+1 or Cn-1). In some embodiments, the percentage of aluminum content in the well layer Wn in the semiconductor stack Cn is less than the percentage of aluminum content in the barrier layer, and also less than the percentage of aluminum content in the barrier layer of the adjacent semiconductor stack (e.g., semiconductor stack Cn+1 or Cn-1). In some embodiments, the multiple quantum well structure M comprises a structure formed by alternating stacks of barrier layers with an aluminum content percentage greater than 50% and well layers with an aluminum content percentage less than 50%. In these embodiments, the internal quantum efficiency can be further improved by making the thickness of the barrier layer Bn in each semiconductor stack Cn smaller than the thickness of the well layer Wn. In some embodiments, the difference in the percentage of aluminum content between the two barrier layers or the two well layers in two adjacent semiconductor stacks is preferably no more than 10%.

[0028] Specifically, the percentage of aluminum content in each barrier layer Bn and each well layer Wn in the luminescent structure 130 can be obtained as follows: Each barrier layer Bn and each well layer Wn in the luminescent structure 130 is measured using an energy dispersive spectroscopy (EDX) instrument, and the percentage of aluminum content (Al%) in each barrier layer and each well layer is calculated from the measurement results. For example, barrier layer Bn contains Alx1Gay1In1-x1-y1As, and well layer Wn contains Alx2Gay2In1-x2-y2As. From the EDX measurement results, x1, y1, x2, and y2 (atom%) can be obtained, from which 1-x1-y1 and 1-x2-y2 can be calculated respectively. Here, the percentage of aluminum content (Al%) in the barrier layer Bn is defined as Al%=x1 / (x1+y1), and the percentage of aluminum content (Al%) in the well layer Wn is defined as Al%=x2 / (x2+y2).

[0029] In some embodiments, the percentage of aluminum content (Al%) in the well layer Wn can be in the range of 30% to 35%. In some embodiments, the percentage of aluminum content (Al%) in the barrier layer Bn can be in the range of 70% to 95%. The ratio of the percentage of aluminum content in the barrier layer Bn to the percentage of aluminum content in the well layer Wn can be greater than 1 and less than or equal to 3.5, for example, approximately 1.5, 2, 2.5, or 3. In some embodiments, 0 < 1 - x1 - y1 < 0.53. 1 - x1 - y1 is, for example, 0.2, 0.25, 0.3, 0.35, 0.4, or 0.45. In some embodiments, 0.3 ≤ x1 ≤ 0.8. x1 is, for example, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, or 0.75. In one embodiment, 1 > 1 - x² - y² > 0.53. 1 - x¹ - y¹ is, for example, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, or 0.95. In one embodiment, 0.1 ≤ x² ≤ 0.2. x² is, for example, 0.12, 0.15, or 0.18.

[0030] When the semiconductor element 10 is operated, the light-emitting structure 130 can emit radiation, such as infrared light with a peak wavelength in the range of 700 nm to 3000 nm, red light with a peak wavelength in the range of 610 nm to 700 nm, or yellow light with a peak wavelength in the range of 530 nm to 570 nm. The radiation is preferably red or infrared, such as near-infrared (NIR) light. When the radiation is near-infrared, the peak wavelength is, for example, 720 nm, 810 nm, 850 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, or 2000 nm. The red or infrared light can be incoherent or coherent.

[0031] The first electrode 140 and the second electrode 150 can be electrically connected to an external power source and to the light-emitting structure 130. The first electrode 140 and the second electrode 150 contain conductive materials. The materials of the first electrode 140 and the second electrode 150 can be the same or different, and may include, for example, metal oxides, metals, or alloys. Metal oxides include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO), etc. Metals may include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), or nickel (Ni), copper (Cu), etc. The alloy may contain at least two of the metals selected from the group consisting of the metals mentioned above, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

[0032] The second electrode 150 may include a main electrode and a plurality of extended electrodes connected to the main electrode. In some embodiments, the plurality of extended electrodes extend from the main electrode toward the side of the upper surface of the semiconductor element 10 to improve current distribution. In some embodiments, the extended electrodes may include portions parallel or perpendicular to any side of the semiconductor element 10. As shown in Figure 1A, the semiconductor element may include one main electrode 150a and four extended electrodes 150b. In this embodiment, the main electrode 150a is circular, while each of the extended electrodes 150b is T-shaped. The main electrode 150a may have a width ranging from 50 µm to 150 µm. When the main electrode 150a is circular, the width is its diameter. The extended electrodes 150b may have a width ranging from 1 µm to 10 µm. Preferably, the width of the extended electrodes 150b is less than 10 times the width of the main electrode.

[0033] In one embodiment, the second semiconductor structure 120 may optionally include a contact layer (not shown) adjacent to the second electrode 150 for conducting current. The contact layer may be a doped or undoped semiconductor layer, and may contain binary semiconductor materials such as GaAs, InP, etc. In one embodiment, the second electrode contains a metal or alloy material, and an ohmic contact may be formed between the contact layer and the second electrode 150, thereby further improving the contact resistance between the second electrode 150 and the light-emitting structure 130.

[0034] Figure 1C is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the first semiconductor structure 110 includes a first confinement layer 112, a first cladding layer 114, a second cladding layer 116, and a first window layer 118, while the second semiconductor structure 120 includes a second confinement layer 122, a third cladding layer 124, a fourth cladding layer 126, and a second window layer 128. As shown in Figure 1C, the first confinement layer 112 and the second confinement layer 122 are adjacent to the light-emitting structure 130 and are located on opposite sides of the light-emitting structure 130. The first confinement layer 112 or the second confinement layer 122 may be a doped or undoped semiconductor layer, and may contain the same or different materials as the light-emitting structure 130. In one embodiment, the first confinement layer 112 and the second confinement layer 122 are preferably undoped and contain a quaternary semiconductor material. In one embodiment, the first confinement layer 112 and the second confinement layer 122 respectively comprise quaternary semiconductor materials, such as InGaAsP, AlGaInAs, or InGaNAs. In one embodiment, the first confinement layer 112 and the second confinement layer 122 are substantially composed of quaternary semiconductor materials (such as InGaAsP, AlGaInAs, or InGaNAs). In one embodiment, the first confinement layer 112 and the second confinement layer 122 comprise the same material. In one embodiment, the thickness of the first confinement layer 112 or the second confinement layer 122 is greater than the thickness of the well layer Wn or the barrier layer Bn in the light-emitting structure 130. In one embodiment, the thickness of the first confinement layer 112 and the second confinement layer 122 are respectively in the range of 10 nm to 50 nm, for example, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, or 45 nm.

[0035] In this embodiment, the first cladding layer 114 is adjacent to and located below the first confinement layer 112, and the second cladding layer 116 is adjacent to and in direct contact with the first window layer 118. The first cladding layer 114 and the second cladding layer 116 can be doped or undoped semiconductor layers, respectively. In one embodiment, the first cladding layer 114 and the second cladding layer 116 may contain aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In one embodiment, the first cladding layer 114 or the second cladding layer 116 may each contain a ternary semiconductor material such as InAlAs, InGaAs, InGaP, etc. The first cladding layer 114 or the second cladding layer 116 may contain the same material. The thickness of the first cladding layer 114 or the second cladding layer 116 may be greater than the thickness of the first confinement layer 112. In one embodiment, the thickness of the first cladding layer 114 or the second cladding layer 116 is in the range of 50 nm to 800 nm, for example, 80 nm, 100 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, or 750 nm. In some embodiments, the first cladding layer 114 and the second cladding layer 116 may be made of the same material. In this case, when the first cladding layer 114 and the second cladding layer 116 are observed by SEM, the interface between the first cladding layer 114 and the second cladding layer 116 may not be obvious.

[0036] In this embodiment, the third cladding layer 124 is adjacent to and located on the second confinement layer 122, and the fourth cladding layer 126 is adjacent to the third cladding layer 124 and in direct contact with the second window layer 128. The third cladding layer 124 and the fourth cladding layer 126 can be doped or undoped semiconductor layers, respectively. In one embodiment, the third cladding layer 124 is an undoped semiconductor layer, and the fourth cladding layer 126 is a doped semiconductor layer. In one embodiment, the third cladding layer 124 and the fourth cladding layer 126 may contain aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). The third cladding layer 124 and the fourth cladding layer 126 may contain the same material. In one embodiment, the third cladding layer 124 and the fourth cladding layer 126 respectively contain ternary semiconductor materials such as InAlAs, InGaAs, InGaP, etc. The thickness of the third cladding layer 124 and the fourth cladding layer 126 may be greater than the thickness of the second confinement layer 122. In one embodiment, the thickness of the third cladding layer 124 or the fourth cladding layer 126 is in the range of 50 nm to 800 nm, for example, 80 nm, 100 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, or 750 nm. In some embodiments, the constituent materials of the third cladding layer 124 or the fourth cladding layer 126 may be the same. In this case, when the third cladding layer 124 or the fourth cladding layer 126 is observed by SEM, the interface between the third cladding layer 124 or the fourth cladding layer 126 may not be obvious.

[0037] In this embodiment, the first window layer 118 is adjacent to and below the second cladding layer 116. The second window layer 128 is adjacent to and above the fourth cladding layer 126. The first window layer 118 and the second window layer 128 are transparent to the light emitted by the light-emitting structure, and can serve as light extraction layers to improve the luminous efficiency of the semiconductor device. The first window layer 118 and the second window layer 128 can be doped or undoped semiconductor layers, respectively. The first window layer 118 and the second window layer 128 can contain the same material. In one embodiment, the first window layer 118 and the second window layer 128 can contain aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In one embodiment, the first window layer 118 and the second window layer 128 respectively contain binary or ternary semiconductor materials such as GaAs, InP, InAlAs, InGaAs, InGaP, etc. In one embodiment, the first window layer 118 and the second window layer 128 may be doped and comprise the same material as the substrate 100. In one embodiment, the first window layer 118 and the second window layer 128 are substantially composed of binary or ternary semiconductor materials (such as GaAs, InP, InAlAs, InGaAs, InGaP). In one embodiment, the thickness of the second window layer 128 is greater than that of the first window layer 118. In one embodiment, the thickness of the first window layer 118 or the second window layer 128 is in the range of 800 nm to 8000 nm, for example, 850 nm, 900 nm, 950 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 5500 nm, 6000 nm, 6500 nm, 7000 nm, or 7500 nm.

[0038] In one embodiment, the first cladding layer 114, the second cladding layer 116, and the first window layer 118 may be doped with the same dopant to have the same conductivity type, for example, they may be doped with silicon (Si) to become n-type semiconductor layers. In one embodiment, the dopant concentration in the first window layer 118 is greater than the dopant concentration in the first cladding layer 114, and the dopant concentration in the first cladding layer 114 is greater than the dopant concentration in the second cladding layer 116. The third cladding layer 124, the fourth cladding layer 126, and the second window layer 128 may be doped with the same dopant to have the same conductivity type, for example, they may be doped with zinc (Zn) to become p-type semiconductor layers. In one embodiment, the dopant concentration in the second window layer 128 is greater than the dopant concentration in the fourth cladding layer 126, and the dopant concentration in the fourth cladding layer 126 is greater than the dopant concentration in the third cladding layer 124.

[0039] In one embodiment, depending on different application requirements, the second cladding layer 116 and / or the first window layer 118 and / or the fourth cladding layer 126 and / or the second window layer 128 may be selectively formed in the semiconductor element 10. The location, composition, and materials of other layers or structures in this embodiment have been described in detail in the previous embodiments, and therefore will not be repeated here.

[0040] Figure 1D is a cross-sectional view of a semiconductor device according to an embodiment of this disclosure. In this embodiment, a reflective structure 160 is further included between the first semiconductor structure 110 and the substrate 100. The reflective structure 160 may be a single layer or multiple layers. In one embodiment, the reflective structure 160 reflects light emitted by the light-emitting structure 130 so that it exits the semiconductor device in the direction of the second semiconductor structure 120. The material of the reflective structure 160 may include metals or alloys. Metals include, for example, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). Alloys may include at least two selected from the group consisting of the aforementioned metals. In one embodiment, the reflective structure 116 may include a distributed Bragg reflector structure (DBR). Furthermore, in this embodiment, the width of the first semiconductor structure 110 near the reflective structure 160 is greater than the width near the light-emitting structure 130. The first semiconductor structure 110 has the same width as the reflective structure 160 on the side near the reflective structure 160.

[0041] The location, composition, and materials of other layers or structures in this embodiment have been described in detail in previous embodiments, and therefore will not be repeated here.

[0042] Figure 1E is a schematic cross-sectional view of a semiconductor device according to an embodiment of this disclosure. In this embodiment, the light-emitting structure 130 includes a first active structure 130a and a second active structure 130b. Furthermore, an intermediate structure 170 may be included between the first active structure 130a and the second active structure 130b. When operating the semiconductor device, the first active structure 130a and the second active structure 130b each emit radiation. The radiation may be red light or infrared light. In one embodiment, one of the first active structure 130a and the second active structure 130b emits red light, and the other emits infrared light. When the radiation is red light, the peak wavelength may be in the range of 610 nm to 700 nm, such as 630 nm, 640 nm, 650 nm, 660 nm, 670 nm, 680 nm, 690 nm, etc. When the radiation is infrared light, the peak wavelength can be in the range of 800 nm to 3000 nm, such as: 720 nm, 810 nm, 850 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, 2000 nm, etc. In one embodiment, the red light or infrared light can be non-homogeneous light or homogeneous light.

[0043] The first active structure 130a and the second active structure 130b may contain the same material, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), or indium (In). In one embodiment, the first active structure 130a and the second active structure 130b each contain a multiple quantum well structure. The composition of each multiple quantum well structure can be referred to the description of the foregoing embodiments. In one embodiment, one of the first active structure 130a or the second active structure 130b has the state of the multiple quantum well structure of the foregoing embodiments. The intermediate structure 170 may electrically connect the first active structure 130a and the second active structure 130b, and may be a single layer or multiple layers. The intermediate structure 170 may contain binary, ternary, or quaternary semiconductor materials, such as AlAs, InAlAs, AlGaAs, InGaAs, InGaP, InGaAsP, AlGaInAs, or InGaNAs, etc. In one embodiment, the conductivity of the intermediate structure 170 can be adjusted by adding different dopants, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), or tellurium (Te).

[0044] The location, composition, and materials of other layers or structures in this embodiment have been described in detail in previous embodiments, and therefore will not be repeated here.

[0045] Figure 2 shows the relationship between the luminous power and current of semiconductor device A in an experimental example of this disclosure. Semiconductor device A has the structure shown in Figure 1B, wherein the substrate is an InP substrate, and the luminous structure 130 has 10 pairs of semiconductor stacks, including alternating well layers and barrier layers. Each barrier layer in semiconductor device A contains Al x1Ga y1In 1-x1-y1As, and each well layer contains Al x2Ga y2In 1-x2-y2As. In semiconductor device A, neither the well layer nor the barrier layer has stress relative to the substrate. The difference between semiconductor device B and semiconductor device A is that each well layer in semiconductor device B has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer does not have stress relative to the substrate (lattice matching). The difference between semiconductor device C and semiconductor device A is that in semiconductor device C, each well layer has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer has tensile stress relative to the substrate (In% < 0.53 in the barrier layer). The light-emitting structure composition of semiconductor device AC can be referred to in Table 1 below.

[0046] Table 1 In the well formation, In% = 1 - x² - y² In the barrier layer, In% = 1 - x1 - y1 Well layer thickness (nm) Barrier layer thickness (nm) Semiconductor stack-up logarithm Semiconductor Component A 0.53 0.53 10 5 10 Semiconductor Component B 0.58 0.53 10 5 10 Semiconductor Component C 0.58 0.44 10 5 10

[0047] The luminous power of semiconductor device AC was tested under different currents, and the results are shown in Figure 2. Semiconductor device C showed the best luminous power under different currents, followed by semiconductor devices B and A. The experimental results show that the luminous power of the device is better when the well layers in the multiple quantum well structure have compressive stress relative to the substrate. Furthermore, when the barrier layer and the well layers in the multiple quantum well structure have opposite stresses relative to the substrate, the output power can be further improved, and the device brightness performance is better.

[0048] Figure 3 shows the relationship between the luminous power and current of semiconductor device DF, an experimental example of this disclosure. Semiconductor device E has the structure shown in Figure 1B, wherein the substrate is an InP substrate, and the luminous structure 130 has 10 pairs of semiconductor stacks, including alternating well layers and barrier layers. Each barrier layer in semiconductor device DF contains Al x1Ga y1In 1-x1-y1As, and each well layer contains Al x2Ga y2In 1-x2-y2As. Each well layer in semiconductor device D has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer has tensile stress relative to the substrate (In% < 0.53 in the barrier layer). Each well layer in semiconductor device E has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer has no stress relative to the substrate (lattice matching). The difference between semiconductor element F and semiconductor element E is that each barrier layer in semiconductor element F also has compressive stress relative to the substrate (In% > 0.53 in the barrier layer). The light-emitting structure composition of semiconductor element DF can be referred to Table 2 below.

[0049] Table 2 In the well formation, In% = 1 - x² - y² In the barrier layer, In% = 1 - x1 - y1 Well layer thickness (nm) Barrier layer thickness (nm) Semiconductor stack-up logarithm Semiconductor element D 0.58 0.44 10 5 10 Semiconductor Component E 0.58 0.53 10 5 10 Semiconductor element F 0.58 0.58 10 5 10

[0050] The luminous power of semiconductor device DF was tested under different currents, and the results are shown in Figure 3. Semiconductor device D showed the best luminous power under different currents, followed by semiconductor devices E and F. The experimental results show that the device brightness is better when the barrier layer and well layer in the multiple quantum well structure have opposite stress conditions relative to the substrate. Furthermore, when the barrier layer and well layer have the same stress conditions relative to the substrate (e.g., both have compressive or tensile stress relative to the substrate), the barrier layer and well layer may be more prone to epitaxial defects, thus affecting the internal quantum efficiency and resulting in poor device brightness.

[0051] Figure 4 shows the relationship between the luminous power and current of the semiconductor device in one of the experimental examples disclosed herein. The semiconductor device GI in this experimental example has the structure shown in Figure 1B, where the substrate is an InP substrate, and the luminous structure 130 has 10 pairs of semiconductor stacks, including alternating well layers and barrier layers. Each barrier layer in semiconductor device GI contains Al x1Ga y1In 1-x1-y1As, and each well layer contains Al x2Ga y2In 1-x2-y2As. Each well layer has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer has tensile stress relative to the substrate (In% < 0.53 in the barrier layer). The difference in semiconductor device GI lies in the different thicknesses of the barrier layers, which are set to 5 nm, 7 nm, and 10 nm, respectively. The luminous structure composition of semiconductor device GI can be referred to in Table 3 below.

[0052] Table 3 In the well formation, In% = 1 - x² - y² In the barrier layer, In% = 1 - x1 - y1 Well layer thickness (nm) Barrier layer thickness (nm) Semiconductor stack-up logarithm Semiconductor element G 0.58 0.44 10 5 10 Semiconductor Component H 0.58 0.44 10 7 10 Semiconductor Component I 0.58 0.44 10 10 10

[0053] The luminous power of semiconductor device GI was tested under different currents, and the results are shown in Figure 4. As shown in Figure 4, semiconductor device G exhibited the best luminous power under different currents, followed by semiconductor devices H and I. Furthermore, the forward voltage (Vf) of semiconductor device I was slightly higher than that of semiconductor devices G and H. That is, when the well layer thickness was fixed while the barrier layer thickness was varied, the results showed that reducing the ratio of barrier layer to well layer thickness helped improve the luminous power, and the forward voltage (Vf) was also further improved. Specifically, a barrier layer to well layer thickness ratio of 1:2 was more effective than 7:10 or 1:1.

[0054] Figure 5 shows the relationship between the luminous power of the semiconductor device and the number of semiconductor stacks in the luminous structure 130 of the experimental example disclosed herein. The semiconductor device JL in this experimental example has the structure shown in Figure 1B, wherein the substrate is an InP substrate, and the luminous structure 130 includes alternating stacked well layers and barrier layers. Each barrier layer in semiconductor device JL contains Al x1Ga y1In 1-x1-y1As, and each well layer contains Al x2Ga y2In 1-x2-y2As. Each well layer has compressive stress relative to the substrate (In% > 0.53 in the well layer), while each barrier layer has tensile stress relative to the substrate (In% < 0.53 in the barrier layer). The difference between semiconductor devices JL lies in the number of semiconductor stack pairs, which are set to 6 pairs, 10 pairs, and 15 pairs respectively. The composition of the luminous structure of semiconductor device JL can be referred to in Table 4 below.

[0055] Table 4 In the well formation, In% = 1 - x² - y² In the barrier layer, In% = 1 - x1 - y1 Well layer thickness (nm) Barrier layer thickness (nm) Semiconductor stack-up logarithm Semiconductor Component J 0.58 0.44 10 5 6 Semiconductor element K 0.58 0.44 10 5 10 Semiconductor element L 0.58 0.44 10 5 15

[0056] The luminous power of semiconductor device JL was tested under the same conditions. The results showed that, under the same test conditions, semiconductor device K, which has 10 pairs of barrier layers and well layers, had the highest brightness, followed by semiconductor device L and semiconductor device J. This result indicates that the brightness of semiconductor devices can be further optimized by adjusting the number of semiconductor stack pairs in the light-emitting structure.

[0057] Figure 6 is a schematic diagram of a semiconductor device packaging structure according to an embodiment of this disclosure. Referring to Figure 6, the packaging structure 600 includes a semiconductor device 60, a packaging substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a packaging material 68. The packaging substrate 61 may contain ceramic or glass material. The packaging substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with a conductive material such as metal to facilitate conductivity and / or heat dissipation. The carrier 63 is located on one side of the surface of the packaging substrate 61 and also contains a conductive material such as metal. The contact structure 66 is located on the other side of the surface of the packaging substrate 61. In this embodiment, the contact structure 66 includes contact pads 66a and 66b, and the contact pads 66a and 66b can be electrically connected to the carrier 63 through the through holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the contact pads 66a and 66b. Semiconductor element 60 is located on carrier 63 and can be any of the semiconductor elements described in any embodiment of this disclosure. In this embodiment, carrier 63 includes a first portion 63a and a second portion 63b, and semiconductor element 60 is electrically connected to the second portion 63b of carrier 63 via bonding wire 65. The bonding wire 65 may be made of metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. Encapsulation material 68 covers semiconductor element 60 and has the effect of protecting semiconductor element 60. Specifically, encapsulation material 68 may contain resin materials such as epoxy resin, silicone resin, etc. Encapsulation material 68 may further contain a plurality of wavelength conversion particles (not shown) to convert the first light emitted by semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0058] In summary, the semiconductor devices disclosed herein can achieve further improvements in photoelectric properties (such as luminous power or forward voltage) and can have better internal quantum efficiency (IQE).

[0059] The semiconductor components disclosed herein can be used in products in the fields of lighting, medical, display, communication, sensing, and power systems, such as lamps, monitors, mobile phones, tablets, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, and medical devices.

[0060] While the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art should understand that modifications or alterations can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims. Furthermore, the above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

[0061] 10, 60: Semiconductor components 100:Substrate 110: First semiconductor structure 112: First Restriction Layer 114: First drapery 116: Second drapery 118: First window layer 120: Second semiconductor structure 122: Second Restriction Layer 124: Third drapery 126: Fourth drapery 128: Second window layer 130: Light-emitting structure 130a: First active structure 130b: Second active structure 140: First electrode 150: Second electrode 150a: Main electrode 150b: Extended electrode 160: Reflective Structure 170: Intermediate Structure 600: Package structure 61: Packaging substrate 62: Through hole 63: Carrier 63a: Part 1 63b: Part Two 65: Joint line 66: Contact Structure 66a, 66b: Contact pads 68: Packaging materials B1, B2, BN: Barrier Layer C1, C2, CN: Semiconductor stack M: Multiple quantum well structure W1, W2, WN: well formations A, B, C, D, E, F, G, H, I: Lines

Claims

1. A semiconductor device, comprising: A first semiconductor structure includes a first confinement layer and a first cladding layer adjacent to the first confinement layer; a second semiconductor structure is located on the first semiconductor structure and includes a second confinement layer; a light-emitting structure is located between the first semiconductor structure and the second semiconductor structure and includes a first multiple quantum well structure, the first multiple quantum well structure having multiple pairs of semiconductor stacks, each pair of semiconductor stacks consisting of a well layer and a barrier layer; and a reflective structure is located below the first semiconductor structure; wherein the first confinement layer and the second confinement layer are adjacent to the light-emitting structure, the well layer and the barrier layer in each pair of semiconductor stacks contain the same quaternary III-V semiconductor material, the quaternary III-V semiconductor material including InGaAsP, AlGaInAs or InGaNAs, the well layer has a first indium content percentage, the barrier layer has a second indium content percentage less than the first indium content percentage, and when the semiconductor device is in operation, the light-emitting structure emits radiation, the radiation is non-coordinated light and has a peak wavelength between 700 nm and 3000 nm. Within the nm range, the first confinement layer or the second confinement layer contains different materials from the light-emitting structure, and the first coating layer contains a ternary semiconductor material.

2. The semiconductor element as described in claim 1, wherein the first indium content percentage is greater than 0.53 and less than 1, and the second indium content percentage is less than 0.53 and greater than 0.

3. The semiconductor device as described in claim 1, wherein the well layer has a first aluminum content percentage, the barrier layer has a second aluminum content percentage, and the ratio of the second aluminum content percentage to the first aluminum content percentage may be greater than 1 and less than or equal to 3.

5.

4. The semiconductor device as described in claim 1, wherein the thickness of the first confinement layer and the second confinement layer is greater than the thickness of the well layer or the barrier layer.

5. The semiconductor element as described in claim 1, wherein the width of the first semiconductor structure near the reflective structure is greater than the width near the light-emitting structure.

6. The semiconductor element as described in claim 1 further includes a first electrode located under the first semiconductor structure; and a second electrode located on the second semiconductor structure, wherein the second electrode includes a circular main electrode.

7. The semiconductor element as described in claim 1, wherein the reflective structure is multilayered.

8. The semiconductor device as described in claim 1, wherein the ratio of the thickness of the well layer to the thickness of the barrier layer is greater than 1 and less than or equal to 5.

9. The semiconductor device as described in claim 1, wherein the ternary semiconductor material comprises InAlAs, InGaAs, or InGaP.

10. A packaging structure for a semiconductor device, comprising: One carrier; A semiconductor element as described in any one of claims 1 to 9 is located on the carrier; And a packaging material covering the semiconductor element.

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