Erase algorithm with a weak program pulse for non-volatile memory

Abstract

This invention provides improved erasure techniques and apparatus to enhance the performance and lifespan of non-volatile memory. Various disclosed techniques involve performing an erase operation on a group of such memory cells, followed by a weak programming operation. One or more subsequent erase-verify operations may be performed until no erase interference state of the memory cells is detected, or until a maximum erase-verify cycle count is reached. In one or more embodiments, additional weak programming and erase-verify cycles may be performed to enhance the cycle life of the group of non-volatile memory and reduce erase interference states.

Description

Technical Field

[0001] U.S. Patent Application 16 / 291,467, filed on March 4, 2019, entitled “RESISTIVE RANDOM ACCESS MEMORY PROGRAM AND ERASE TECHNIQUES AND APPARATUS”, the entire contents and all purposes of which are incorporated herein by reference.

[0002] This disclosure generally relates to the operation of controlling non-volatile memory, and as an illustrative example, relates to an enhanced erase algorithm for non-volatile memory. Prior Technology

[0003] Resistive-switching memory represents the latest innovation in integrated circuit technology. While most resistive-switching memory technologies are still under development, various technical concepts have been demonstrated and are in one or more validation phases to prove or refute related theories or technologies. The inventors believe that resistive-switching memory technology demonstrates compelling evidence of its significant advantages over competing technologies in the semiconductor electronics industry.

[0004] Resistive switching memory cells can be configured to have multiple states, each with a different measurable resistance value. For example, a single bit cell can be configured to exist in a relatively low resistance state or a relatively high resistance state. Multi-bit cells can have additional states with their own resistances, which are distinct from each other and different from the relatively low and relatively high resistance states. The different resistance states of the resistive switching memory cells can be associated with logical information states, thereby facilitating digital memory operations. Therefore, an array of many such memory cells can provide digital memory storage of many bits.

[0005] In response to external conditions, resistive switching memory can be induced to enter one resistive state or another. Therefore, in transistor terms, applying or removing external conditions can be used to program or de-program (e.g., erase) the memory. Furthermore, depending on the physical configuration and electrical arrangement, resistive switching memory cells can typically maintain a programmed or deprogrammed state. Maintaining this state may require other conditions to be met (e.g., the presence of a minimum operating voltage, a minimum operating temperature, etc.), or may not meet any conditions, depending on the characteristics of the memory cell device.

[0006] The inventors have proposed several suggestions for the practical application of resistive switching technology in memory applications of electronic devices. For example, resistive switching elements are often theoretically envisioned, at least in part, as a viable alternative to metal-oxide-semiconductor (MOS) type memory transistors for electronic storage of digital information. The model of resistive-switched memory devices offers several potential technological advantages over non-volatile FLASH MOS type transistors.

[0007] In view of the above, the patentee of this invention is committed to the continuous development of practical applications of resistance switching technology. Summary of the Invention

[0008] The following is a simplified overview of this specification to provide a basic understanding of certain aspects of it. This content is not a comprehensive overview of the specification. Its purpose is neither to identify key or critical elements of this specification, nor to define the scope of any particular embodiment of this specification or any scope of the claims. Its purpose is to present some concepts of this specification in a simplified form as a prelude to the more detailed descriptions presented in this disclosure.

[0009] This invention provides improved erasure techniques and apparatus for enhancing the performance and lifespan of non-volatile memory. Various techniques involve performing an erase operation on a group of such memory cells, followed by a weak programming operation. One or more subsequent erase verification operations are performed until no erase interference state of the memory cells is detected, or until a maximum erase-verification cycle count is reached. In one or more embodiments, additional weak programming and erase-verification cycles may be performed to enhance the cycle life of the group of non-volatile memory and reduce erase interference states.

[0010] In one embodiment, a method for reducing bit interference associated with erasing memory cells of a non-volatile, resistive-switched memory device is disclosed. The method may include performing a programming process on a plurality of non-volatile memory cells of an array of non-volatile, resistive-switched memory devices, including a first non-volatile memory cell and a second non-volatile memory cell, and performing a first erase-verify process on the first and second non-volatile memory cells. The first erase-verify process may further include erasing the first and second non-volatile memory cells, and reading the first and second non-volatile memory cells to determine whether both memory cells are in an erased state. Furthermore, the method may include performing a first weak programming process on the first and second non-volatile memory cells in response to determining that both memory cells are in the erased state. In various embodiments, the weak programming process may include at least one of the following: a lower pulse count, a lower voltage amplitude, or a lower pulse duration than the programming process. Furthermore, the method may include performing a second erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell. The second erase-verify process may include performing the erase process on the first non-volatile memory cell and the second non-volatile memory cell and reading the first non-volatile memory cell and the second non-volatile memory cell to determine whether both memory cells are in the erased state. Additionally, the method may include performing a final read process to determine that both the first non-volatile memory cell and the second non-volatile memory cell are in the erased state.

[0011] In another embodiment, a method for erasing a non-volatile memory device is disclosed. The method may include erasing each of a plurality of non-volatile memory cells in a programmed state of the memory device, and detecting whether any of the plurality of non-volatile memory cells is associated with an erase interference state after the erasure. Additionally, the method may include, in response to the absence of an erase interference state detected, weakly programming each of the plurality of non-volatile memory cells with a polarity opposite to the erasure polarity, and further erasing each of the plurality of non-volatile memory cells. Furthermore, the method may include, in response to the further erasure, detecting whether any of the non-volatile memory cells is associated with the erase interference state, and, in response to the absence of an erase interference state associated with any of the non-volatile memory cells, reading the erase state of the plurality of non-volatile memory cells.

[0012] In addition to the above, this disclosure also provides a method. The method may include programming a non-volatile memory cell of a non-volatile memory device to a programmed state, erasing the non-volatile memory cell, and detecting whether any of the non-volatile memory cells has an erase interference state. The method may also include, in response to detecting an erase interference state in one of the non-volatile memory cells, optionally re-erasing the non-volatile memory cell. Furthermore, the method may include weakly programming the non-volatile memory cell at a voltage, pulse duration, or pulse count less than the programming voltage, further erasing the non-volatile memory cell in response to the weak programming, and receiving temperature data indicating the operating temperature of the non-volatile memory device compared to a temperature threshold or threshold range. In one or more embodiments, the method may include one of the following steps: in response to the operating temperature being below the temperature threshold or the threshold range, detecting an erase interference state associated with a portion of the non-volatile memory cell in response to the further erase, and further re-erasing only that portion of the non-volatile memory cell; or in response to the operating temperature being equal to or above the temperature threshold or the threshold range, detecting the erase interference state associated with that portion of the non-volatile memory cell, and further re-erasing all of the non-volatile memory cells. Furthermore, the method may include reading the final erase state of the non-volatile memory cell.

[0013] The following description and accompanying drawings illustrate certain illustrative aspects of the specification. However, these aspects indicate only a few of the various ways in which the principles of this specification can be employed. Other advantages and novel features of the specification will become apparent when considered in conjunction with the accompanying drawings, based on the following detailed description. Simple Explanation of the Diagram

[0014] Various aspects or features of the invention are described with reference to the accompanying drawings, wherein the same element symbols are used throughout to refer to the same components. Numerous specific details are set forth in this specification to provide a thorough understanding of the disclosure. However, it should be understood that certain aspects of the disclosure may be practiced without these specific details, or with other methods, components, materials, etc. In other instances, known structures and devices are shown in block diagram form to facilitate the description of the disclosure.

[0015] Figure 1 depicts a schematic diagram of an example two-terminal resistor-switched memory array and operating circuitry according to the disclosed embodiment;

[0016] Figure 2 depicts a table illustrating an example erase process using weak programming and illustrative erase interference response for a set of non-volatile memory cells in the embodiment;

[0017] Figure 3 shows an example cell state response of the example erasure process of Figure 2 according to an additional embodiment;

[0018] Figure 4 shows an example graph of bit failure count versus erase cycle count for a non-volatile memory cell disclosed in another embodiment;

[0019] Figure 5 depicts an example graph of bit failure count and weak programming count according to an additional embodiment of the present invention;

[0020] Figure 6 shows example graphs of bit failure counts and weak programming counts for different temperatures in the embodiments;

[0021] Figure 7 shows example graphs of weak programming counts versus target erasure interference at different temperatures in other embodiments;

[0022] Figure 8 depicts a flowchart of an example method for an erasure process utilizing one or more weak programming pulses in another embodiment;

[0023] Figure 9 shows a flowchart of an example method for the erasure process utilizing a weak programming loop and an erasure verification process in other embodiments;

[0024] Figure 10 illustrates a flowchart of an example method for erasing a resistively switched memory cell using one or more weak programming pulses in various aspects of the present invention.

[0025] Figure 11 shows a flowchart of an example method for erasing non-volatile memory cells based at least in part on the temperature of the memory device.

[0026] Figure 12 shows a block diagram of an example operation and control environment of a memory device according to the present invention;

[0027] Figure 13 is a block diagram depicting an example computing environment that facilitates one or more other forms of the present invention. Implementation

[0028] introduce

[0029] Various embodiments of the present invention provide an improved erasure process for non-volatile memory. For example, in one or more embodiments, the improved erasure process may utilize one or more weak programming pulses in conjunction with erasing both ends of the memory device, switching the memory device with a non-volatile resistor. In some embodiments, the number of weak programming pulses used in the erasure process may be determined in part based on the target erase disturb or erase failure count. In other embodiments, the number of weak programming pulses may depend in part on the operating temperature of the memory device. In still other embodiments, the operating temperature may determine in part a portion of the memory cells on which weak programming or cyclic erasure can be performed.

[0030] As used herein, the term “substantially” and other related terms or degrees (e.g., about, approximately, substantially, etc.) are intended to have the meaning explicitly specified in connection with their use herein, or may have the meaning of a reasonable variation in a particular quality or quantity that can be reasonably inferred by a person skilled in the art, or that a person skilled in the art could understand by referring to the entire specification (including conventional knowledge of a person skilled in the art and data incorporated herein). For example, the term degree may refer to reasonable manufacturing tolerances within which a particular quality or quantity can be achieved using manufacturing equipment. Thus, as a specific illustration, although not limiting, for an element of an integrated circuit device explicitly identified as having a size of about 50 angstroms (Å), the relative term “about” may mean a reasonable variation of about 50 Å, and a person skilled in the art would expect the specified dimensions of the component to be achievable using commercial manufacturing equipment, industrial manufacturing equipment, laboratory manufacturing equipment, etc., and not limited to mathematically precise quantities (or qualities). In other examples, the term "degree" may refer to a variation of + / - 0.3%, + / - 0.5%, or + / - 0.10% in a explicitly specified value, to achieve the specified function or feature of the element disclosed herein, in a manner suitable to those skilled in the art. In other examples, the term "degree" may refer to any suitable variation in quality or quantity suitable for achieving the explicitly disclosed function or feature of the disclosed element. Therefore, this specification is by no means limited to the specific quality and quantity disclosed herein, but includes all variations of the specific quality or quantity reasonably conveyed to a person skilled in the art through the context of this disclosure.

[0031] As the name suggests, a two-ended memory device has two terminals or electrodes. In this document, the terms "electrode" and "terminal" are used interchangeably. Typically, the first electrode of a two-ended resistance switching device is referred to as the "top electrode" (TE), and the second electrode as the "bottom electrode" (BE). However, it should be understood that the two electrodes of a two-ended resistance switching device can be arranged in any suitable configuration, including a horizontal arrangement, where the components of the memory cells are (substantially) side-by-side rather than stacked on top of each other. Between the TE and BE of a two-ended memory device is typically an interface layer, sometimes called a switching layer, resistance switching medium (RSM), or resistance switching layer (RSL). When an RSM is incorporated, the two-ended memory device can be referred to as a (two-ended) resistance switching device.

[0032] Generally, the composition of memory cells can vary depending on the device, with different components, materials, or deposition processes selected to achieve the desired characteristics (e.g., stoichiometry / non-stoichiometry, volatility / non-volatility, on / off current ratio, switching time, read time, memory durability, program / erase cycles, etc.). Examples of conductive bridge random access memory (RAM) or programmable metallized cell devices may include: a relatively (electrochemically) inert conductive layer, such as a metal, metal alloy, metal nitride, etc. (e.g., including W, Ni, Pt, TixNy (where x and y are suitable positive numbers), Ir, or other suitable metal compounds) and an electrochemically active conductive layer, such as a metal, metal alloy, metal nitride, etc. (e.g., containing AlxNy (e.g., non-stoichiometric and conductive), Ag, Cu, or other suitable metal compounds), separated by a resistive switching layer (RSL) (e.g., containing AlxOy, SixOy, TixOy, or other suitable oxides). Under appropriate conditions, an active metallized layer can provide filament-forming ions (e.g., Al, Ag, Cu, etc.) to the RSL. In such embodiments, the conductive filaments (e.g., formed by ions) can promote conductivity through at least a subset of the RSL, and as an example, the resistance of a filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. Memory cells with such characteristics can be described as programmable metallized cells, conductive bridge RAMs, or filament-based devices.

[0033] Resistive switching media (RSLs, also known in the art as resistor-switching media (RSMs)) may include, for example, undoped amorphous silicon-containing layers, intrinsically semiconductor layers, stoichiometric or non-stoichiometric silicon nitrides (e.g., SiN, Si3N4, SiNx, etc.), Si suboxides (e.g., SiOx, where the value of x is between 0.1 and 2), Si subnitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, and so on. Other examples of materials suitable for RSLs may include SixGeyOz (where x, y, and z are suitable positive numbers), silicon oxides (e.g., SiON, where N is a suitable positive number), silicon oxynitrides, undoped amorphous silicon (a-Si), amorphous SiGe (a-SiGe), TaOB (where B is a suitable positive number), HfOC (where C is a suitable positive number), TiOD (where D is a suitable number), Al2OE (where E is a suitable positive number), etc., nitrides (e.g., AlN, SiN), or suitable combinations thereof.

[0034] In some embodiments, the RSL (non-volatile RSL) used as part of a non-volatile memory device may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to trap neutral metal particles within the RSL (e.g., at low voltages). The large number of voids or defects can facilitate the formation of a thick and stable structure of neutral metal particles. In such a structure, these trapped particles can maintain the non-volatile memory device in a low-resistance state without external stimuli (e.g., electrical power), thereby enabling non-volatile operation.

[0035] The active metal layer for the wire-based memory cell can include (but is not limited to): silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In certain aspects of the present invention, other suitable conductive materials and stoichiometric or non-stoichiometric compounds, nitrides, oxides, alloys, mixtures, or combinations of the foregoing or similar materials can be used for the active metal layer. Additionally, in at least one embodiment, non-stoichiometric compounds, such as non-stoichiometric metal oxides / metal-oxygen or metal nitrides / metal nitrogen (e.g., AlOx, AlNx, CuOx, CuNx, AgOx, AgNx, etc., where x is a suitable positive number such as 0 < x < 2, 0 < x < 3, 0 < x < 4, or other numbers / number ranges, depending on the metal compound and may vary for different non-stoichiometric compounds) or other suitable metal compounds can be used for the active metal layer.

[0036] In one or more embodiments, the disclosed filamentary resistive switching device can include an active metal layer that includes a metal nitride selected from: TiNx, TaNx, AlNx, CuNx, WNx, and AgNx, where x is a positive number (or number range) that can vary depending on the metal nitride material. In one or more additional embodiments, the active metal layer can include a metal oxide selected from: TiOx, TaOx, AlOx, CuOx, WOx, and AgOx, where x is a positive number (or number range) that can similarly vary depending on the metal oxide material. In yet one or more embodiments, the active metal layer can include a metal oxynitride selected from: TiOaNb, AlOaNb, CuOaNb, WOaNb, and AgOaNb, where a and b are suitable positive numbers / number ranges. The disclosed filamentary resistive switching device can further include a switching layer that includes a switching material selected from: SiOy, AlNy, TiOy, TaOy, AlOy, CuOy, TiNx, TiNy, TaNx, TaNy, SiOx, SiNy, AlNx, CuNx, CuNy, AgNx, AgNy, TiOx, TaOx, AlOx, CuOx, AgOx, and AgOy, where x and y are positive numbers (or ranges) and y is greater than x. Within the scope of the embodiments of the present invention, various combinations of the above can be envisioned and expected.

[0037] In one example, the disclosed filamentary resistance switching device includes a particle donor layer (e.g., an actively metallized layer) and a resistance switching layer, the particle donor layer comprising a stoichiometric or non-stoichiometric metal compound (or mixture). In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MNx, such as AgNx, TiNx, AlNx, etc., and the resistance switching layer comprises a metal nitride: MNy, such as AgOy, TiOy, AlOy, and so on, where y and x are positive numbers (or ranges), and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises a metal oxide: MOx, such as AgOx, TiOx, AlOx, etc., and the resistance switching layer comprises a metal oxide: MOy, such as AgOy, TiOy, AlOy, etc., where y and x are positive numbers (or ranges), and in some cases y is greater than x. In another alternative, the metal compound of the particle donor layer is MNx (e.g., AgNx, TiNx, AlNx, etc.), and the resistance switching layer is selected from MOy (e.g., AgOy, TiOy, AlOy, etc.) and SiOy, where x and y are typically non-stoichiometric values, or vice versa in another embodiment.

[0038] As used herein, variables x, y, a, b, etc., representing the value or ratio of one element relative to another element (or other elements) in a compound or mixture may have different values ​​(or ranges) applicable to the various compounds / mixtures and are not intended to represent the same or similar values ​​or ratios between compounds. A mixture may refer to non-stoichiometric materials containing free elements, such as metal-rich nitrides or oxides (metal oxides / nitrides having free metal atoms), metal-poor nitrides or oxides (metal oxides / nitrides having free oxygen / nitrogen atoms) – and other combinations of elements understood in the art that do not form conventionally stoichiometric compounds. Some details relating to the embodiments disclosed in this subject matter can be found in the following U.S. patent applications, which are licensed to the assignee of this patent application: Serial No. 11 / 875,541, filed October 19, 2007, and Serial No. 12 / 575,921, filed October 8, 2009, each of which is incorporated herein by reference in its entirety and for all purposes.

[0039] Some embodiments disclosed herein may employ a switching device that operates as a bipolar switching device in a first operating mode (e.g., referred to herein as standard forming, multiple programmable (MTP) operation, etc.). This bipolar switching device exhibits a first switching response to an electrical signal of a first polarity (e.g., programming to one of a set of programming states) and a second switching response to an electrical signal having a second polarity (e.g., erasing to an erase state). For example, this bipolar switching device contrasts with a unipolar device, which exhibits a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity but different amplitudes.

[0040] One resistance-switching mode of a bipolar device involves a reversibly formed conductive filament. A reversibly formed conductive filament (also known as a filament-based switching device) can operate differently in response to external stimuli of different polarities. As an example, a conductive path or filament is formed through a non-volatile RSL in response to a suitable programming voltage applied across the memory cell. Specifically, upon application of the programming voltage, metal ions are generated from the active metallized layer and migrate to the non-volatile RSL layer. The metal ions can occupy void or defect sites within the non-volatile RSL layer. In some embodiments, after the bias voltage is removed, the metal ions become neutral metal particles and remain trapped in the voids or defects of the non-volatile RSL layer. When a sufficient number of particles are trapped, a filament is formed and the memory cell switches from a relatively high-resistance state to a relatively low-resistance state.

[0041] Once a conductive filament is formed, the trapped conductive particles manifest a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance between one or more of these particles and the conductive material of the adjacent non-volatile RSL layer. In some resistance-switching devices, an erase process can be performed to at least partially deform the conductive filament, causing the memory cell to return from a low-resistance state to a high-resistance state. More specifically, when an erase bias is applied, metal particles trapped in the voids or defects of the non-volatile RSL become mobile ions and migrate back to the active metal layer, or dissociate within the RSL (or a combination thereof), thereby disrupting the conductivity of the conductive filament passing through the RSL layer. In the case of memory, this change of state can be associated with the corresponding state of a binary bit.

[0042] In some disclosed embodiments, the completion of the conductive filament (e.g., standard formation) may involve only a small number or even fewer conductive material particles (e.g., atoms, ions, conductive compounds, etc.). As a particular example, an electrically continuous conductive filament can be established by positioning 1-3 atoms at the boundary of the switching layer, while in some embodiments, the repositioning of one or more of these atoms can disrupt this electrical continuity. Because the scale between the completed and incomplete filaments can be very small, erased cells may become disturbed over time, and if the atoms removed from the boundary drift to the appropriate locations to reform the electrical continuity of the conductive filament, the programmable or conductive state is restored. This recovery from the erased state to the programmable state is called erase interference, or more generally, bit failure. In the case of a non-volatile memory cell array with only a few erase interference cells, memory bits allocated to error correction code (ECC) data and algorithms can be used to detect and correct disturbed bits. When the number of erase interference bits exceeds the number that ECC can correct, data loss may occur. The various embodiments disclosed herein provide an improved erasure process to significantly reduce erase interference bits, thereby mitigating or avoiding data loss in non-volatile resistive switching memory devices.

[0043] summary

[0044] For memory devices that have switching characteristics based on the presence or absence of conductive wires to change the resistance of the memory device between a low-resistance state (wire present) and a high-resistance state (wire broken), retention problems (short-term memory erase failures) may occur in some memory devices. Such failures include erase interference conditions, which involve erasing the memory with a negative voltage and causing the memory itself to return to a programmed state after a period of time (e.g., from a high-resistance state to a low-resistance state).

[0045] Although the filaments of a programmed memory cell may be destroyed immediately during an erase cycle, the physical movement of the conductive particles within the filaments can be erratic. More specifically, some time after an erase cycle, the destroyed conductive particles may relax and reform the conductive filaments. This timeframe may be short for some memory devices with the same memory structure (corresponding to short-term memory issues), while for others it may be long (corresponding to long-term memory durability issues).

[0046] The embodiments disclosed herein propose a modified erase process in which a weak programming cycle (typically with a positive voltage or a second polarity voltage) is applied after an initial erase cycle (typically with a negative voltage or a first polarity voltage) on one or more memory devices. It is believed that the weak programming cycle causes or facilitates programming (e.g., re-entering a low-resistance state) in memory devices with a tendency for short-term or long-term memory erasure. In some embodiments, instead of immediately returning to zero bias after applying the erase voltage (typically negative) and erase current, a weak programming voltage (typically positive) may be applied, followed by a return to zero bias. In other words, in some embodiments, the weak programming pulse may be considered part of the erase process, or in other embodiments, it may be an operation separate from the erase process.

[0047] In various embodiments, the weak programming signal can be smaller than the normal programming signal (e.g., 25% to 75% of the programming voltage, programming current, programming duration, etc.). In some embodiments, the amplitude of the weak programming signal can be approximately the same as or greater than that of conventional programming, but the duration can be significantly shorter; for example, a voltage pulse or pulse with a very short duration or fewer programming pulses can be implemented. As an example, where a typical programming signal utilizes multiple programming pulses, a weak programming signal can utilize fewer programming pulses, or a single programming pulse. In still other embodiments, the weak programming signal can combine the foregoing (e.g., fewer programming pulses, shorter programming duration, lower programming voltage, lower programming current, etc.).

[0048] In another embodiment, memory cells of the memory device can be selectively measured after the weak programming signal to identify erase interference bits. An erase pulse can be applied, followed by a verification pulse (e.g., read processing) to identify any erase interference bits. If erase interference is detected, the erase pulse can be repeated on the memory cells. Generally, the erase pulse can be repeated on all memory cells to be erased. However, in at least some embodiments, the erase pulse can be repeated on a portion of the memory cells (e.g., when the operating temperature is below a threshold; see Figure 11). In one or more embodiments, the erase signal can be repeated until no erase interference bits are detected, or until the maximum erase cycle count is reached.

[0049] In various embodiments, repeated erase cycles may have the same characteristics as previous erase cycles (e.g., having a default or predetermined voltage amplitude, erase current, cycle duration, number of cycles, etc.), or may involve different (e.g., higher or lower) erase voltage amplitudes, different (e.g., higher or lower) erase currents, different (e.g., longer or shorter, fewer or more) erase cycles, repeated erase cycles, etc. In some cases, if a memory cell cannot maintain its erased state after multiple weak programming cycles as described above, the memory cell may be marked as faulty and removed from the memory table, etc.

[0050] Figure 1 shows a block diagram of an example integrated circuit arrangement 100 of an electronic device according to one or more embodiments of the present invention. The integrated circuit arrangement 100 may include an array of two-terminal memory cells 102, each connected at its respective first end to one of a set of bit lines 104 and at its respective second end to one of a set of source lines 108. For a memory cell-resistor cell configuration (1T1R) in a transistor, access to the memory cell array can be facilitated via the corresponding word line 106.

[0051] The operation circuit 150 uses the multiplexer 130 to access the corresponding bit line 104 and the decoder 120 to access the corresponding source line 108 (and word line 106). For the convenience of the memory operations disclosed herein, the operation circuit 150 may include a programming circuit 152, an erasing circuit 154, and a read circuit 156.

[0052] Programming circuit 152 can be configured to apply a programming process with preset characteristics, including voltage, current, pulse duration or number of pulses (during programming), or suitable combinations thereof. Example preset voltages for the programming process can range from 2.9 volts (V) to 4.0 V (e.g., 3 V, 3.3 V, 3.5 V, 3.8 V, 4 V, etc.), example preset pulse durations can range from 1 microsecond (μs) to 100 μs (e.g., 1 μs, 5 μs, 10 μs, 25 μs, 30 μs, ...), and example preset number of pulses can be multiple pulses, ten pulses, 20 pulses, 50 pulses, 100 pulses, 500 pulses, or any suitable value or range thereof.

[0053] Furthermore, the programming circuit 152 can be configured to apply a weak programming process having at least one characteristic different from a preset characteristic. Different characteristics may include different voltages, currents, pulse durations or pulse numbers, or combinations thereof; however, the weak programming process will have the same polarity as the programming process. It should be understood that, generally, the weak programming process will have a reduced voltage amplitude (e.g., a reduction of about 25% to about 75% of the voltage amplitude, or a suitable value between thereand), a reduced current, a reduced pulse duration, or a reduced number of pulses, but in at least some embodiments, the weak programming process may increase at least one of these characteristics while decreasing one or more other characteristics. As an example, the weak programming process may have a voltage from about 1.6V to about 2.6V (e.g., 1.8V, 2.0V, 2.2V, 2.3V, 2.5V, etc.), a pulse duration from 1μs to 100μs (e.g., about 5μs, about 10μs, about 15μs, about 20μs, etc.), and fewer than five pulses (e.g., two pulses, one pulse, etc.).

[0054] The erase circuit 154 can be configured to apply an erase process with preset characteristics, including voltage, current, pulse duration or number of pulses (during the erase process), or a suitable combination thereof. For the bipolar memory cell 102, the erase process will typically have a voltage of opposite polarity to the programming process, but may also have the aforementioned characteristics with different values. In various embodiments, the erase circuit 154 may utilize a voltage in the range of approximately -1.6V to -2.6V, a pulse duration in the range of approximately 1μs to approximately 100μs, and fewer than five pulses (e.g., three pulses, four pulses, one pulse, etc.) to generate the erase process.

[0055] The read circuit 156 can provide a read pulse configured to maintain—or otherwise avoid—the current state of the memory cell 102 at both ends, while determining its resistance state. The amplitude of the read pulse is typically smaller than the programming or erasing pulse (e.g., 2.0V or less; 1.5V or less, etc.). In various embodiments, the read pulse may be implemented by the read circuit 156 after a programming pulse (or weak programming pulse) implemented by the programming circuit 152 or after an erasing pulse implemented by the erasing circuit 154.

[0056] Figure 2 illustrates an example erase process 200 incorporated into a weak programming process in various embodiments of the present invention. The erase process 200 is arranged in a graph with the following rows: pulse number 202 and pulse type 204, total cell error 206, programming error 208, and erase error 210 (also referred to herein as erase interference). These categories are described in the consecutive portions of the erase process 200 listed in the columns of the graph.

[0057] Erasure process 200 is applied to a plurality of nonvolatile memory (NVM) cells, such as the two-ended memory cell 102 shown in Figure 1. The number of NVM cells in an error state after each pulse is given in their respective rows 206, 208, and 210. Starting from the first column, the programming process is applied to the NVM cells and all NVM cells are verified, resulting in zero errors. For the second column, an erase-verify pulse is applied to erase all but one of the NVM cells, thereby generating a bit of interference under erase error row 210 (and total error row 206). Erasure process 200 can be configured to repeat the erase-verify pulse until no bit interference state is detected, or until the maximum erase-verify count is reached. Executing a second erase-verify pulse does not generate bit interference.

[0058] Next, a first weak programming (and verification) process is performed, generating 1017 erase interference cells. A third erase-verification process is then executed, successfully erasing all NVM cells without generating bit interference events. In various embodiments, multiple weak programming processes can be implemented as part of the erase process 200. The multiple weak programming processes can be, for example, a predetermined fixed number or a variable number. The variable number can depend on the number of erase interference bits, the operating temperature of the memory device, or a suitable combination of the foregoing.

[0059] As shown in Figure 2, in column 6, a second weak programming process can be implemented, generating 580 erase interference bits, followed by a fourth erase-verify pulse that generates a single erase interference bit. If the erase-verify limit is greater than one, a fifth erase-verify pulse is implemented as shown, generating a zero erase interference bit. Next is the third weak programming process, generating 442 erase interference bits. The sixth erase-verify process generates one erase interference bit, which is corrected by the seventh erase-verify process.

[0060] A fourth weak programming pulse is applied to the twelfth column, causing 348 erase interference bits. For erase process 200, the eighth erase-verify process does not produce bit errors, and a final read process is performed, and erase process 200 ends. Erase process 200 may implement the final read process and end after a maximum number of weak programming processes (e.g., four in the illustrated example, or any suitable number between one and ten), or in response to fewer than a threshold number of erase interference bits (e.g., less than 400, or 350, less than 50%, less than 40%, less than 30%, etc.), or a suitable combination of the foregoing.

[0061] Figure 3 illustrates an example cell state 300 of the erase process 200 of Figure 2. Cell state 300 depicts the erase or programmable states of four memory cells as an example representative of a group of memory cells on which the erase process 200 is implemented. Cell state 300 provides example states for these representative memory cells in response to the operating pulses of the erase process 200. It should be understood that the example cell state 300 is merely illustrative and is not intended to limit the responses of other suitable memory cells to the erase process 200 of the individual memory cells in the group of memory cells, including random or pseudo-random effects understood by those skilled in the art. Rather, other suitable memory cell responses are also within the scope of this invention.

[0062] Representative memory units include memory units 1312, 2314, 3316, and 4328 (collectively referred to below as memory units 312-318). Each memory unit 312-318 is aligned with a row, and the units below each row define the state of the corresponding memory unit 312-318 for a set of operation pulses in the column of the depicted graph. Each column depicts the continuous operation pulses of the erase process 200 under column heading pulse ID 302. As will be understood by those skilled in the art, within the scope of this disclosure, different sequences of operation pulses may be used for other erase processes, or, as may be reasonably conveyed to those skilled in the art through the context provided herein.

[0063] Similar to the erase process 200 in Figure 2, this process begins after the programming process, which programs all memory cells 312-318. The dark shaded block with the letter "P" indicates the programming state of the corresponding memory cell 312-318. Initiating the erase process 200 is the first erase cycle 322. Erasure cycle 322 is defined as a number of erase-verify pulses (E&V) sufficient to erase all memory cells 312-318, up to a maximum number of erase-verify pulses. The erase-verify pulses include an erase pulse and a verify pulse (e.g., a read) to detect the programming or erase state of each memory cell after the erase pulse. The maximum number of erase-verify pulses can be any number greater than zero; in the present case, the maximum number can be 2, 3, 4, or other suitable numbers. In response to the erase-verify pulse, a bit is verified as either in an erase state or in a programming state. If in a programming state, the bit is determined to be an erase interference. The first erase-verify pulse generates erase interference bits (memory cell 4318, which remains in the programmed state after the first erase-verify pulse) and three erase bits. This triggers the second erase-verify pulse, which puts all memory cells 312-318 into the erase state. Since no erase interference bits remain, the first erase cycle 322 ends.

[0064] A first weak programming (and verification) 324 is performed on memory cells 312-318. Note that the weak programming pulse is selected to have characteristics such as lower voltage, pulse duration, pulse number, etc. (or a suitable combination thereof) compared to a normal programming operation. Therefore, it is expected that the weak programming will not change the erase state of the memory cells to be properly erased, and thus the memory cells that become programmed in response to weak programming 324 are identified as erase interference bits. As shown in cell state 300, there are three memory cells 314, 316, and 318 that become programmed after the first weak programming 324 and are therefore identified as erase interference bits. A second erase cycle 322 is performed after the first weak programming 324, which includes a third erase-verify pulse, resulting in all memory cells 312-318 being successfully erased. Therefore, the erase process 200 proceeds to the second weak programming 324.

[0065] After the second weak programming 324, memory cells 312 and 318 are shown to have been programmed and are therefore identified as erase interference bits. A third erase cycle 322 is executed, where a fourth erase-verify pulse causes memory cell 312 to become erased (while memory cells 314 and 316 remain erased), while memory cell 318 remains an erase interference bit. This results in a fifth erase-verify pulse for the third erase cycle 322. The fifth erase-verify pulse successfully erases memory cells 312-318.

[0066] The third weak programming 324 causes only a single erase interference: memory cell 218. The fourth erase cycle 322 initiates the sixth erase-verify pulse, which causes no change in the erase interference of memory cell 218. The seventh erase-verify pulse is implemented and causes all memory cells to be erased. After the fourth weak programming 324, memory cell 218 is interfered with again, while memory cells 312-316 remain erased. The fifth erase cycle 322 and the eighth erase-verify pulse cause all memory cells 312-318 to be in an erased state.

[0067] The erase process 200 ends with a final read following the fourth weak programming 324 and the fourth erase cycle 322. In other embodiments, more or fewer weak programming and erase cycles may be implemented. In some embodiments, the number of weak programming and erase cycles may be a fixed predetermined number. In other embodiments, the number of weak programming and erase cycles may depend at least in part on the bit interference response of memory cells 312-318 to the weak programming signal, or the successful erase response of the memory cells to the erase-verify pulse, or a combination of the foregoing. In other embodiments, the number of weak programming and erase cycles may depend in part on a predetermined minimum number, a predetermined maximum number, the bit interference response to the weak programming signal, or the successful erase response to the erase-verify pulse, or a suitable combination of the foregoing.

[0068] Figure 4 illustrates an example graph 400 of the failure count (or erase interference) relative to the erase cycle count for various states according to the disclosed embodiments. On the vertical axis, graph 400 plots the erase failure count 420 (or the number of erase interference bits) in parts per million (ppm), and on the horizontal axis, graph 400 plots the number of (normal) programming and erase cycles. Additionally, graph 400 provides two relationships between the failure count 420 and the cycle count 410: a first relationship 432 plotting the erase interference versus programming-cycle count for a single weak programming-erasing cycle, and a second relationship 430 plotting the erase interference versus programming-cycle count for an erase process 200 having multiple weak programming-erasing cycles (four weak programming-erasing cycles in the example of erase process 200).

[0069] As clearly seen in Figure 400, the first relation 432 increases rapidly in the failure count 420 as the program-erase cycle number 410 increases. The second relation 430 associated with the erase process 200 has a much lower failure count 420 to increase the program-erase cycle number 410. Compared to the cycle lifetime of the first relation 432 associated with a single weak program-erase process, the erase process 200 increases the cycle lifetime of the resistive switching memory cell by many times.

[0070] Figure 5 illustrates an example graph 500 of the failure count 520 versus the weak programming pulse count 510 according to a further embodiment of the invention. At four weak programming pulses or less, the failure count drops to approximately 100 ppm or less. This low failure count can generally be understood as addressable by ECC correction or other correction techniques and is therefore not fatal for proper memory storage. In various embodiments, multiple weak programming pulses can be selected for the disclosed erase process to reduce the failure count 520 to a target level, as shown in graph 500.

[0071] Figure 6 illustrates an example graph 600 of failure count 620 versus weak programming pulse count 610 for different operating temperatures of a resistive switching memory device in a further embodiment of the invention. The illustration in Figure 6 indicates that the response of failure count 620 at 125°C relative to weak programming pulse count 610 is represented by a dark circle, while at room temperature it is represented by a light-shaded circle. Graph 600 shows that failure count 620 increases significantly with higher operating temperatures. For the absence of weak programming pulses, the failure count (in ppm) increases approximately tenfold at high temperatures. However, as the weak programming pulse count increases, the failure count decreases rapidly even at high temperatures. In six weak programming pulse events, even at high temperatures, the failure count is below 250 ppm. At ten weak programming pulses, the high-temperature response is similar to the room-temperature response. In one or more embodiments, the number of weak programming pulses used for the disclosed erase process can be selected at least in part based on the operating temperature of the memory device in which the erase process is performed. For example, when a fault count below 250 ppm is required, a single weak programming pulse can be implemented for an operating temperature of room temperature (e.g., approximately 20-25 degrees Celsius), while five or six weak programming pulses can be implemented for an operating temperature of 125 degrees Celsius. As another example, for a fault count below 100 ppm, four or five weak programming pulses can be used for a memory device at room temperature, and eight or nine weak programming pulses can be used for the same device at 125 degrees Celsius, and so on.

[0072] Figure 7 shows an example graph 700 of weak programming counts relative to the target erase interference count in ppm. Graph 700 plots the minimum number of weak programming pulses 720 on the vertical axis and the target erase interference count 710 (in ppm) on the horizontal axis. The caption for Graph 700 identifies the black circles as the response to an operating temperature of 125°C and the lightly shaded circles as the response to room temperature. Graph 700 shows the minimum number of weak programming pulses required to achieve the target erase interference value in ppm for the erase process disclosed at a given temperature.

[0073] The figures included herein are for the description of multiple circuits and arrays of a resistor switching device or an integrated circuit device comprising multiple circuits or arrays. It should be understood that such figures may include those circuits and arrays specified therein, some specified circuits / arrays, or additional circuits / arrays not explicitly depicted but known in the art or reasonably conveyed to those skilled in the art through the context provided herein. Components of the disclosed integrated circuit device may also be implemented as sub-components of another disclosed component, and other components disclosed as sub-components may be separate components in various embodiments. Furthermore, embodiments in certain figures of this specification may be applied, in whole or in part, to other embodiments depicted in other figures, without limitation, solely to achieve the suitability for realizing the disclosed functions or purposes as understood by those skilled in the art, and vice versa.

[0074] Given the exemplary figures described above, reference to the flowcharts of Figures 8-11 will provide a better understanding of the process methods that can be implemented according to the disclosed subject matter. Although the methods of Figures 8-11 are shown and described as a series of blocks for simplicity, it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may appear in a different order or simultaneously with other blocks, regardless of what is depicted and described herein. Furthermore, not all shown blocks need to implement the methods described herein, and in some embodiments, additional steps known in the art or reasonably conveyed to those skilled in the art through the context provided herein may be implemented as methods disclosed within the scope of this disclosure. Additionally, where appropriate, some steps shown as part of a process may be implemented for another process; within the scope of the invention, other steps of one or more processes may be added to or substituted for other processes disclosed herein. Furthermore, it should also be understood that the methods disclosed throughout this specification can be stored on an article of manufacture for easy transfer and transfer to an electronic device, embedded memory within an electronic device, etc. As used, the term "article of manufacture" is intended to encompass computer programs accessible from any computer-readable device, a device coupled with a carrier, or a storage medium, etc.

[0075] Figure 8 illustrates a flowchart of an example method 800 for reducing bit interference associated with erasing memory cells of a non-volatile, two-terminal resistance-switched memory device, according to a disclosed embodiment. At step 802, method 800 may include performing a programming process on a plurality of non-volatile memory cells in an array of non-volatile memory cells. In various embodiments, the non-volatile memory cells may be two-terminal resistance-switched memory devices in an array of two-terminal resistance-switched memory devices. The plurality of non-volatile memory cells includes at least two memory cells: a first non-volatile memory cell and a second non-volatile memory cell.

[0076] At step 804, method 800 may include performing a first erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell. In one or more embodiments, the first erase-verify process may further include applying an erase process to the first non-volatile memory cell and the second non-volatile memory cell, and reading the first non-volatile memory cell and the second non-volatile memory cell to determine whether the two memory cells are in an erased state. At step 806, method 800 may include performing a first weak programming process on the first non-volatile memory cell and the second non-volatile memory cell. In some disclosed embodiments, the weak programming process may respond to determining that the first and second memory cells are in an erased state, or respond to reaching a maximum erase pulse for the erase-verify process. In at least some embodiments of the invention, the weak programming process may include at least one of the following: a lower pulse count than the programming process; a lower voltage amplitude than the programming process; or a shorter pulse duration than the programming process.

[0077] At step 808, method 800 may include performing a second erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell. In another embodiment, performing the second erase-verify process further includes applying an erase process to the first non-volatile memory cell and the second non-volatile memory cell, and reading the first non-volatile memory cell and the second non-volatile memory cell to determine whether both memory cells are in an erased state.

[0078] At step 810, method 800 may include performing a final read process to determine that both the first non-volatile memory cell and the second non-volatile memory cell are in an erased state.

[0079] In an embodiment, in response to determining after the first erase-verify process that neither memory cell is in an erased state, method 800 may further include repeating the first erase-verify process on the first and second non-volatile memory cells. Repeating the first erase-verify process may further include performing an erase process and reading the first and second non-volatile memory cells until the reading determines that both memory cells are in an erased state.

[0080] In another embodiment, method 800 may also include performing a second weak programming process on the first and second memory cells and a third erase-verification process on the first and second non-volatile memory cells after performing the second erase-verification process. Furthermore, in response to detecting an erase interference state of the first or second non-volatile memory cell in response to the third erase-verification process, method 800 may include performing additional weak programming and erase-verification processes on the first and second non-volatile memory cells. Additionally, in at least one embodiment, method 800 may further include repeating the additional weak programming and erase-verification processes until no erase interference state of the first or second non-volatile memory cell is detected.

[0081] In some variations of the disclosed embodiments, method 800 may further include repeating the weak programming and erase-verify processes on the first and second non-volatile memory cells a predetermined number of times before performing the final read process. As an example, the predetermined number of times may be a number selected from the group consisting of: two, three, four, five, six, seven, eight, nine, and ten.

[0082] Figure 9 illustrates a flowchart of an example method 900 according to further embodiments of the present invention. At step 902, method 900 may include performing a programming process on a plurality of non-volatile memory cells of a non-volatile memory cell array. At step 904, method 900 may include performing an erase-verify process on the plurality of non-volatile memory cells, and at step 906, determining whether any erase interference cells are detected in response to the erase-verify process. If no erase interference cells are detected, method 900 may proceed to step 910. If erase interference cells are detected, method 900 proceeds to step 908 and may include determining whether a maximum erase count has been met. If not, method 900 returns to step 904; otherwise, method 900 proceeds to step 910.

[0083] At step 910, method 900 may include performing a weak programming process on a plurality of memory cells. At step 912, method 900 may include performing an erase-verify process on the plurality of memory cells in response to the weak programming process. At step 914, it is determined whether any erase interference cells were identified after the erase-verify process. If not, method 900 proceeds to step 918. If erase interference cells were identified, method 900 may proceed to step 916 and determine whether a maximum erase count was reached after the weak programming process at step 910. If not, method 900 returns to step 912; otherwise, method 900 proceeds to step 918.

[0084] In step 918, it is determined whether the maximum weak programming count has been reached. If not, method 900 returns to step 910. If the maximum weak programming count has been reached, method 900 proceeds to step 920 and may include performing a final read procedure on a plurality of memory cells. The final read procedure can confirm that the plurality of memory cells are in an erased state.

[0085] Figure 10 illustrates a flowchart of an example method 1000 for erasing a non-volatile memory device. At step 1002, method 1000 may include erasing each of a plurality of non-volatile memory cells (NVM cells) in a programmed state of the memory device. At step 1004, method 1000 may include detecting whether any of the erased NVM cells is associated with an erase interference state. At step 1006, method 1000 may include weakly programming each of the plurality of NVM cells with the opposite polarity to the erase, in response to the detection of an erase interference state. At step 1008, method 1000 may include further erasing each of the plurality of non-volatile memory cells, and at step 1010, method 1000 may include detecting whether any of the NVM cells is associated with an erase interference state in response to this further erasure. At step 1012, method 1000 may include reading the states of a plurality of NVM cells in response to detecting that no erase interference state is associated with any NVM cell.

[0086] In another embodiment, method 1000 may include re-erasing each of a plurality of non-volatile memory cells and detecting, after re-erasing, whether an erase interference state is associated with any of the plurality of NVM cells. Furthermore, the re-erasing and detection may be in response to either erasing each of the plurality of NVM cells at step 1002 or further erasing each of the plurality of NVM cells at step 1008, detecting that an erase interference state is associated with any of the plurality of NVM cells.

[0087] In more embodiments, method 1000 may further include repeating the re-erasure and the detection until none of the plurality of NVM cells detects an erasure interference state. In another alternative embodiment, the re-erasure and the detection may be repeated until a maximum re-erasure count of the re-erasure and the detection is reached, wherein the maximum re-erasure count is one or greater.

[0088] In one or more other variations of the disclosed embodiments, method 1000 may include repeatedly performing weak programming on each of the plurality of NVM cells before reading the erase state of the plurality of NVM cells, and further erasing each of the plurality of NVM cells. Furthermore, method 1000 may also include repeating the weak programming and the further erasure a predetermined number of times selected from a range of 1 to 9.

[0089] In one or more other disclosed embodiments, method 1000 may further include receiving temperature data relating to the non-volatile memory device and comparing the temperature data with a threshold temperature value. Method 1000 may also include adjusting for repeated weak programming and further erasure based on temperature data indicating that the current operating temperature of the non-volatile memory device is higher than the threshold temperature value.

[0090] In another disclosed embodiment, erasure includes an erasure process defined by one or more of the following: a negative polarity voltage in the voltage range of -1.6V to -2.6V, a pulse duration in the duration range of 1 microsecond (μs) to 100μs, or a single pulse. In another embodiment, a programming process for a non-volatile memory device to give a plurality of NVM cells a programming state is defined by: a positive polarity voltage in a second range of +2.9V to +3.8V, a pulse duration in a second duration range of 1μs to 10μs, and two or more pulses having the positive polarity voltage in the second voltage range and the pulse duration in the second duration range.

[0091] Figure 11 illustrates a flowchart of an example method 1100 according to a further embodiment of the present disclosure. At step 1102, method 1100 may include programming an NVM cell of a non-volatile memory device to a programmed state, and at step 1104, method 1100 may include erasing the NVM cell. At step 1106, method 1100 may include detecting whether any cell in the NVM cell has an erase interference state. At step 1108, method 1100 may include selectively re-erasing the NVM cell in response to detecting an erase interference state in one of a plurality of NVM cells.

[0092] At step 1110, method 1000 may include weakly programming the NVM cell. At step 1102, the weak programming may use a voltage, pulse duration, or pulse count less than the programming voltage. At step 1112, method 1100 may include further erasing the NVM cell in response to the weak programming.

[0093] Furthermore, at step 1114, method 1100 may include determining the operating temperature of the memory device. As an example, determining the operating temperature may include receiving temperature data indicating a comparison between the operating temperature of the non-volatile memory device and a temperature threshold or threshold range. At step 1116, it is determined whether the operating temperature is greater than the temperature threshold. If it is greater than the temperature threshold, method 1100 may proceed to step 1118 and may include further erasing all NVM cells in response to erasing interference bits. If it is less than the operating temperature, method 1100 may proceed to step 1120 and may include further erasing a portion of the NVM cells having erasing interference bits. At step 1122, method 1100 may include reading the final erase state of the NVM cells. In at least one additional embodiment, in response to the operating temperature being at or above the temperature threshold or threshold range, the weak programming and the further erasure are repeated one or more times before reading the final erase state of the non-volatile memory cells.

[0094] Operating environment example

[0095] Figure 12 shows an example block diagram of the operation and control environment 1200 of the memory array 1202 of the memory device according to various embodiments of the present disclosure. In some embodiments, the control environment 1200 and the memory array 1202 may be formed within a single semiconductor die, but the present disclosure is not limited thereto, and in other embodiments, certain components of the control environment 1200 may be formed on a separate semiconductor die communicatively connected to the single semiconductor die. In at least one embodiment of the present disclosure, the memory array 1202 may include memory selected from various memory cell technologies. In at least one embodiment, the memory array 1202 may include two-terminal resistive switching technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal resistive switching technology may include resistive-switching memory, conductive-bridging memory, phase-change memory, organic memory, magnetoresistive-resistive memory, etc., or suitable combinations of the above technologies. In another embodiment, the two-terminal resistive switching technology may be two-terminal resistive switching technology.

[0096] The row controller 1206 includes a sense amplifier and write circuitry 1208, and may be formed adjacent to the memory array 1202. Furthermore, the row controller 1206 may be configured to activate (or identify for activation) a subset of bit lines in the memory array 1202. The row controller 1206 may activate and operate individual bit lines in this subset of bit lines using control signals provided by a reference and control signal generator 1218, and may apply appropriate programming, erasing, or read voltages to these bit lines. Inactive bit lines may be maintained at a suppression voltage (also applied by the reference and control signal generator 1218) to mitigate or avoid bit interference effects on these inactive bit lines.

[0097] Furthermore, the operating and control environment 1200 may include a column controller 1204. The column controller 1204 may be adjacent to and electrically connected to the word lines of the memory array 1202. Also utilizing the control signals of the reference and control signal generator 1218, the column controller 1204 may select one or more columns of memory cells using an appropriate selection voltage. Furthermore, the column controller 1204 may facilitate programming, erasing, or reading operations by applying an appropriate voltage to the selected word lines.

[0098] The sensing amplifier and write circuit 1208 can read data from and write data to the active memory cells of the memory array 1202, selected by the row controller 1206 and the column controller 1204, respectively. Data read from the memory array 1202 can be provided to the input / output buffer 1212. Similarly, data to be written to the memory array 1202 can be received from the input / output buffer 1212 and written to the active memory cells of the memory array 1202.

[0099] Clock source 1210 can provide its own clock pulse to time read, write, and program operations of column controller 1204 and row controller 1206. Clock source 1210 can further facilitate the selection of word lines or bit lines in response to external or internal commands received by operating and control environment 1200. Input / output buffer 1212 includes command and address inputs as well as bidirectional data inputs and outputs. Commands are provided via command and address inputs, and data to be written to and read from memory array 1202 is transmitted via bidirectional data inputs and outputs, facilitating connection to external host devices, such as computers or other processing devices (not shown, but see computer 1302 in Figure 13, see below).

[0100] The input / output buffer 1212 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, receive address data and command data, and the address data of each command. Address data can be transferred to the column controller 1204 and the row controller 1206 via the address register 1214. Furthermore, input data is transmitted to the memory array 1202 via the signal input line between the row controller 1206 and the input / output buffer 1212, and output data is received from the memory array 1202 via the sense amplifier (1208) and provided to the input / output buffer 1212 via the signal output line. Input data can be received from the host device, and output data can be transmitted to the host device via the I / O bus.

[0101] Commands received from the host device can be provided to command interface 1216. Command interface 1216 can be configured to receive external control signals from the host device and determine whether the data input to input / output buffer 1212 is write data, a command, or an address. Input commands can be transmitted to state machine 1220.

[0102] State machine 1220 is configurable to manage the programming and reprogramming of memory array 1202. Instructions provided to state machine 1220 are executed according to control logic configuration, enabling state machine 1220 to manage read, write, erase, data input, data output, and other functions related to memory cell array 1202. In some states, state machine 1220 can send and receive acknowledgments and negative acknowledgments regarding the successful reception or execution of various commands. In further embodiments, state machine 1220 can decode and execute state-related commands, as well as decode and execute configuration commands, etc.

[0103] To perform functions such as reading, writing, erasing, input, and output, state machine 1220 can control clock source 1210 or reference and control signal generator 1218. Control of clock source 1210 can generate output pulses, which are configured to facilitate specific functions of column controller 1204 and row controller 1206. For example, output pulses can be transmitted by row controller 1206 to selected bit lines, or by column controller 1204 to selected word lines.

[0104] Regarding Figure 13, the systems, apparatuses, or processes described herein may be embodied in hardware, such as a single integrated circuit (IC) chip, multiple ICs, application-specific integrated circuits (ASICs), or similar hardware. Furthermore, the order in which some or all of the process steps appear in each process should not be considered a limitation. Rather, it should be understood that some process steps may be performed in multiple orders, and not all orders are explicitly stated herein.

[0105] Referring to FIG13, a suitable environment 1300 for implementing various forms of the claimed subject matter includes a computer 1302. The computer 1302 includes a processing unit 1304, system memory 1310, a codec 1314, and a system bus 1308. The system bus 1308 couples system components, including but not limited to system memory 1310, to the processing unit 1304. The processing unit 1304 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1304.

[0106] The system bus 1308 can be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, or local buses using various available bus architectures, including but not limited to Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association (PCMCIA) bus, FireWire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0107] System memory 1310 includes volatile memory 1310A and non-volatile memory 1310B. The basic input / output system (BIOS) contains basic routines for transferring information between components within computer 1302 (e.g., during startup), and the BIOS is stored in non-volatile memory 1310B. Furthermore, according to present invention, codec 1314 may include at least one encoder or decoder, wherein the at least one encoder or decoder may consist of hardware, software, or a combination of hardware and software. Although codec 1314 is depicted as a separate component, codec 1314 may be contained within non-volatile memory 1310B. By way of illustration and not limitation, non-volatile memory 1310B may include read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, two-terminal memory, etc. Volatile memory 1310A includes random access memory (RAM), and in some embodiments may be embodied as cache memory. By way of illustration and not limitation, random access memory can take many forms, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), and enhanced synchronous dynamic random access memory (ESDRAM), etc.

[0108] Computer 1302 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 13 shows disk storage 1306. Disk storage 1306 includes, but is not limited to, disk drives, solid-state disks (SSDs), floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards or memory sticks, universal serial bus (USB) memory, mini-USB memory, micro-USB memory, and other non-volatile memory hardware modes. Furthermore, disk storage 1306 may include individual storage media or be used in combination with other storage media, including but not limited to optical drives, such as compact disk ROM (CD-ROM) devices, CD-R drives, CD-RW drives, or digital versatile disk ROM (DVD-ROM) drives. To facilitate connection of the disk storage device 1306 to the system bus 1308, a removable or non-removable interface, such as storage interface 1312, is typically used. It is understood that the storage device 1306 can store user-related information. This information may be stored on a server, provided to a server, or provided to an application running on the user's device. In one embodiment, the user may be notified (e.g., via output device 1332) of the type of information stored in the disk storage device 1306 or transmitted to the server or application. The user has the option to choose whether to collect and / or share this information via the server or application (e.g., via input through input device 1342).

[0109] It is understood that Figure 13 illustrates software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1300. Such software includes an operating system 1306A. The operating system 1306A, which may be stored on disk storage 1306, controls and allocates the resources of the computer system 1302. The application 1306C has the advantage of managing resources via program modules 1306D through the operating system 1306A, and program data 1306D (e.g., start / stop transaction tables, etc.) stored in system memory 1310 or on disk storage 1306. It is understood that the subject matter for which protection is sought can be implemented through various operating systems or combinations of operating systems.

[0110] Users input commands or information to computer 1302 via input device 1342. Input device 1342 includes, but is not limited to, pointing devices such as mice, trackballs, styluses, touchpads, keyboards, microphones, joysticks, gamepads, satellite dishes, scanners, TV tuner cards, digital cameras, digital camcorders, webcams, etc. These and other input devices are connected to processing unit 1304 via system bus 1308 and input port 1340. Input port 1340 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1332 uses some of the same type of ports as input device 1342. Therefore, for example, a USB port can be used to provide input to computer 1302 and output information from computer 1302 to output device 1332. Output adapter 1330 is provided to illustrate that, among other output devices 1332, some output devices 1332 (such as monitors, speakers, and printers) require special adapters. By way of illustration and not limitation, output adapter 1330 includes a video card and an audio card to provide a connection between output device 1332 and system bus 1308. It is worth noting that other devices and / or device systems may provide both input and output functionality simultaneously, such as remote computer 1338.

[0111] Computer 1302 can operate in a network environment using logical connections to one or more remote computers (such as remote computer 1324). Remote computer 1324 can be a personal computer, server, router, networked PC, workstation, microprocessor-based device, peer-to-peer device, smartphone, tablet, or other network node, and typically includes many components associated with computer 1302. For simplicity, only remote computer 1324 and its memory storage device 1326 are described. Remote computer 1324 is logically connected to computer 1302 via network 1322 and then via communication interface 1320. Network 1322 includes wired or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), and cellular networks. Local area network (LAN) technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, and Token Ring. Wide area network (WAN) technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN) and its variants), packet-switched networks, and Digital Subscriber Line (DSL).

[0112] Communication interface 1320 refers to the hardware / software used to connect network 1322 to bus 1308. Although for clarity, communication interface 1320 is shown inside computer 1302, it can also be outside computer 1302. The hardware / software required to connect to network 1322 includes internal and external technologies such as modems (including ordinary telephone-grade modems, coaxial cable modems, and DSL modems), ISDN adapters, wired and wireless Ethernet cards, hubs, and routers.

[0113] The configurations disclosed herein can also be implemented in distributed computing environments, where certain tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules or stored information, instructions, etc., can reside in local or remote memory storage devices.

[0114] Furthermore, it is understood that the various components described herein may include circuits that may include components and circuit elements with appropriate values ​​to implement embodiments of this disclosure. Additionally, it is understood that many of the various components may be implemented on one or more integrated circuit wafers. For example, in one embodiment, a set of components may be implemented on a single integrated circuit wafer. In other embodiments, one or more components may be fabricated or implemented on different integrated circuit wafers.

[0115] Regarding the various functions performed by the aforementioned components, architectures, circuits, processes, etc., unless otherwise stated, the terms used to describe such components (including references to "means") are intended to correspond to any component (e.g., a functionally equivalent element) that performs a specific function of the component, even if it is not structurally equivalent to the disclosed structure, performing the functions in the exemplary patterns of the embodiments described herein. In this regard, embodiments of the invention may also include a system and a computer-readable medium having computer-executable instructions for performing the actions and / or events of various processes.

[0116] Furthermore, while a particular feature may be described only in one embodiment of several implementations, it may be combined with one or more other features in other implementations, which may be desirable and advantageous for any given or particular application. Moreover, the terms “comprising,” “including,” and variations thereof, as used in the Detailed Description or the claims, are intended to be included in a manner similar to the term “comprising.”

[0117] The term “or” as used in this application refers to an inclusive “or”, not an exclusive “or.” That is, unless otherwise specified or the context clearly indicates, “X adopts A or B” means any natural inclusive arrangement. In other words, “X adopts A or B” is true if X adopts A; X adopts B; or X adopts both A and B. Furthermore, the article “a” as used in this application and the appended claims should generally be understood as “one or more”, unless otherwise stated or clearly understood to be singular in the context.

[0118] In other embodiments, combinations or sub-combinations of the disclosed embodiments can be advantageously implemented. For ease of understanding, the block diagrams and flowcharts have been grouped. However, it should be understood that in other embodiments of this disclosure, combinations of blocks, addition of new blocks, rearrangement of blocks, etc., can be considered.

[0119] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and those skilled in the art may make various modifications or alterations thereto, which should be included within the spirit and scope of this application and the scope of the appended claims.

[0120]

[0121] 100: Integrated circuit device

[0122] 102: Two-terminal memory unit, bipolar two-terminal memory unit

[0123] 104: Bitline

[0124] 106: Character Line

[0125] 108: Source Line

[0126] 120: Decoder

[0127] 130: Multiplexer

[0128] 150: Operating Circuit

[0129] 152: Programming Circuit

[0130] 154: Eraser Circuit

[0131] 156: Reading Circuit

[0132] 200: Erasing process

[0133] 202: Pulse Count

[0134] 204: Pulse Type

[0135] 206: Total Unit Error, Total Error, Line Error

[0136] 208: Programming Error, Line Error

[0137] 210: Erase errors, lines

[0138] 300: Cell Status

[0139] 302: Line header pulse ID

[0140] 312: Memory Unit 1, Memory Unit

[0141] 314: Memory Unit 2, Memory Unit

[0142] 316: Memory Unit 3, Memory Unit

[0143] 318: Memory Unit 4, Memory Unit

[0144] 322: First erase cycle, second erase cycle, third erase cycle, fourth erase cycle, fifth erase cycle, erase cycle

[0145] 324: First weak programming, second weak programming, third weak programming, fourth weak programming, weak programming

[0146] 400: Chart

[0147] 410: Loop Count, Programming - Erasing Loop Count

[0148] 420: Erase failure count, failure count

[0149] 430: Second Relationship

[0150] 432: First Relationship

[0151] 500: Chart

[0152] 510: Weakly Programmable Pulse Counting

[0153] 520: Failure Count

[0154] 600: Chart

[0155] 610: Weakly Programmable Pulse Counting

[0156] 620: Failure Count

[0157] 700: Chart

[0158] 710: Target erasure interference

[0159] 720: Weakly Programmable Pulse

[0160] 800: Method

[0161] 802: Steps

[0162] 804: Steps

[0163] 806: Steps

[0164] 808: Steps

[0165] 810: Steps

[0166] 900: Method

[0167] 902: Steps

[0168] 904: Steps

[0169] 906: Steps

[0170] 908: Steps

[0171] 910: Steps

[0172] 912: Steps

[0173] 914: Steps

[0174] 916: Steps

[0175] 918: Steps

[0176] 920: Steps

[0177] 1000: Method

[0178] 1002: Steps

[0179] 1004: Steps

[0180] 1006: Steps

[0181] 1008: Steps

[0182] 1010: Steps

[0183] 1012: Steps

[0184] 1100: Method

[0185] 1102: Steps

[0186] 1104: Steps

[0187] 1106: Steps

[0188] 1108: Steps

[0189] 1110: Steps

[0190] 1112: Steps

[0191] 1114: Steps

[0192] 1116: Steps

[0193] 1118: Steps

[0194] 1120: Steps

[0195] 1122: Steps

[0196] 1200: Operating and control environment, control environment

[0197] 1202: Memory Array

[0198] 1204: Column Controller

[0199] 1206: Line Controller

[0200] 1208: Sensing Amplifier and Write Circuit

[0201] 1210: Time Source

[0202] 1212: Input / Output Buffer

[0203] 1214: Address Register

[0204] 1216: Command Interface

[0205] 1218: Reference and Control Signal Generator

[0206] 1220: State Machine

[0207] 1300: Environment, Operating Environment

[0208] 1302: Computer, computer system

[0209] 1304: Processing Unit

[0210] 1306: Disk storage device, disk storage unit, storage device

[0211] 1306A: Operating System

[0212] 1306C: Application

[0213] 1306D: Program Module

[0214] 1308: System bus, bus

[0215] 1310: System Memory

[0216] 1310A: Volatile Memory

[0217] 1310B: Non-volatile memory

[0218] 1312: Storage Interface

[0219] 1314: Codec

[0220] 1320: Communication Interface

[0221] 1322: Network

[0222] 1324: Remote computer

[0223] 1326: Memory storage device

[0224] 1330: Adapter

[0225] 1332: Output device

[0226] 1340: Input Port

[0227] 1342: Input device

Claims

1. A method for reducing bit interference associated with erasing memory cells in a non-volatile, two-terminal resistive switching memory device, comprising: The method involves performing a programming process on a plurality of non-volatile memory cells of an array of non-volatile, resistive-switched memory devices, the plurality of non-volatile memory cells including a first non-volatile memory cell and a second non-volatile memory cell; performing a first erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell, further comprising: performing an erase process on the first non-volatile memory cell and the second non-volatile memory cell; and reading the first non-volatile memory cell and the second non-volatile memory cell to determine whether both memory cells are in an erased state; and, in response to determining that both memory cells are in the erased state, performing a first weak programming process on the first non-volatile memory cell and the second non-volatile memory cell, wherein the weak programming process includes at least one of the following: a lower pulse count than the programming process, a lower voltage amplitude than the programming process, or a lower pulse duration than the programming process; In response to determining after the first erase-verify process that neither memory cell is in the erased state: repeating the first erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell, wherein repeating the first erase-verify process further includes: performing the erase process and reading the first non-volatile memory cell and the second non-volatile memory cell until the reading determines that both memory cells are in the erased state; performing a second erase-verify process on the first non-volatile memory cell and the second non-volatile memory cell, further including: performing the erase process on the first non-volatile memory cell and the second non-volatile memory cell; and reading the first non-volatile memory cell and the second non-volatile memory cell to determine whether both memory cells are in the erased state; and performing a final read process to determine that both the first non-volatile memory cell and the second non-volatile memory cell are in the erased state.

2. The method as described in claim 1, further comprising: After performing the second erase-verify process, a second weak programming process is performed on the first non-volatile memory cell and the second non-volatile memory cell, and a third erase-verify process is performed on the first non-volatile memory cell and the second non-volatile memory cell.

3. The method as described in claim 2 further includes: In response to the detection of an erase interference state for the first non-volatile memory cell or the second non-volatile memory cell in response to the third erase-verify process, an additional weak programming process and an erase-verify process are performed on the first non-volatile memory cell and the second non-volatile memory cell.

4. The method described in claim 3 further includes: Repeat the additional weak programming process and erase-verify process until no erase interference state is detected for the first non-volatile memory cell or the second non-volatile memory cell.

5. The method as described in claim 1, further comprising: Before performing the final read process, the weak programming process and the erase verification process are repeated a predetermined number of times for the first non-volatile memory cell and the second non-volatile memory cell.

6. The method as described in request item 5, wherein, The number of times is selected from one of the following groups: two, three, four, five, six, seven, eight, nine, and ten.

7. A method for erasing a non-volatile memory device, comprising: Erases each of the plurality of non-volatile memory cells in the programmed state of the memory device; Detect whether any one of the plurality of non-volatile memory cells is associated with an erase interference state after the erase; In response to no erase interference state being detected, perform weak programming on each of the plurality of non-volatile memory cells with a polarity opposite to that of the erase; Further erase each of the plurality of non-volatile memory cells; In response to the further erase, detect whether any one of the non-volatile memory cells is associated with the erase interference state; And in response to the absence of an erase interference state associated with any of the non-volatile memory cells, the erase state of the plurality of non-volatile memory cells is read; wherein the erase includes an erase process defined by one or more of the following: a negative polarity voltage ranging from -1.6V to -2.6V; a pulse duration ranging from 1μs to 100μs; or a single pulse.

8. The method as described in claim 7, further comprising: In response to detecting that the erasure interference state is associated with any of the plurality of nonvolatile memory cells after erasing each of the plurality of nonvolatile memory cells or after further erasing each of the plurality of nonvolatile memory cells: re-erase each of the plurality of nonvolatile memory cells; and detect whether the erasure interference state is associated with any of the plurality of nonvolatile memory cells after the re-erasure.

9. The method as described in claim 8, further comprising: Repeat the erase and detection process until none of the plurality of non-volatile memory cells are found to be in an erase interference state.

10. The method as described in claim 8, further comprising: Repeat the re-erase and the detection until the maximum re-erase count is reached, where the maximum re-erase count is 1 or greater.

11. The method as described in claim 7, further comprising: Before reading the erase state of the plurality of non-volatile memory cells, the weak programming of each of the plurality of non-volatile memory cells and the further erasure of each of the plurality of non-volatile memory cells are repeated.

12. The method as described in claim 11, further comprising: The weak programming and the further erasure are repeated a predetermined number of times, wherein the predetermined number of times is selected from the range of 1 to 9.

13. The method as described in claim 11, further comprising: Receive temperature data related to the non-volatile memory device and compare the temperature data with a threshold temperature value; And based on the temperature data indicating that the non-volatile memory device operates at a higher temperature than the threshold temperature value, the repeated weak programming and further erasure are adjusted.

14. The method as described in claim 7, wherein, The weak programming includes a programming procedure defined by one or more of the following: a positive voltage ranging from +1.6V to +2.6V; a pulse duration ranging from 1μs to 100μs; or a single pulse.

15. The method as described in claim 14, wherein, The programming process used by the non-volatile memory device to bring the plurality of non-volatile memory cells into the programming state is defined by the following: a positive voltage with a second voltage range of +2.9V to +3.8V; a pulse duration with a second duration range of 1μs to 10μs; and two or more pulses having the positive voltage with the second voltage range and the pulse duration with the second duration range.

16. A method for erasing non-volatile memory cells based on the temperature of a non-volatile memory device, comprising: Program the non-volatile memory cell of the non-volatile memory device to a programmed state; erase the non-volatile memory cell; Detect whether any of the non-volatile memory cells has an erase interference state; Optionally, in response to detecting an erase interference state of one of the non-volatile memory cells, the non-volatile memory cell is re-erased; the non-volatile memory cell is weakly programmed with a voltage, pulse duration, or pulse count less than the programming voltage; in response to the weak programming, the non-volatile memory cell is further erased; temperature data indicating the operating temperature of the non-volatile memory device compared to a temperature threshold or threshold range is received; one of the following: in response to the operating temperature being lower than the temperature threshold or threshold range, an erase interference state associated with a portion of the non-volatile memory cell in response to the further erase is detected, and only that portion of the non-volatile memory cell is further re-erased; or in response to the operating temperature being equal to or higher than the temperature threshold or threshold range, the erase interference state associated with that portion of the non-volatile memory cell is detected, and all the non-volatile memory cells are further re-erased; and the final erase state of the non-volatile memory cell is read.

17. The method as described in claim 16, further comprising: In response to an operating temperature equal to or higher than the temperature threshold or the threshold range, the weak programming and the further erasure are repeated once or multiple times before the final erase state of the non-volatile memory cell is read.

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