Dynamic random-access memory (DRAM) device

Abstract

This disclosure provides a dynamic random access memory (DRAM) device. The DRAM device includes a plurality of slave DRAM chips and a master DRAM chip. Each of the plurality of slave DRAM chips includes a slave fuse circuit and a slave reference voltage generator. The slave fuse circuit provides a slave setting signal according to a slave fuse setting operation. The slave reference voltage generator provides a slave reference voltage according to the slave setting signal. The master DRAM chip controls the operation of the plurality of slave DRAM chips.

Description

Technical Field

[0001] This invention relates to a memory device, and more specifically, to a dynamic random-access memory (DRAM) device. Prior Technology

[0002] Generally, Dynamic Random Access Memory (DRAM) devices consist of memory chips. All memory chips require at least one reference voltage to determine the received signal or data. It should be noted that all memory chips require DC current to provide at least one reference voltage. Therefore, DRAM devices with memory chips have high power consumption. Summary of the Invention

[0003] This disclosure provides a dynamic random access memory (DRAM) device with low power consumption.

[0004] The disclosed DRAM device includes a plurality of slave DRAM chips and a master DRAM chip. Each of the plurality of slave DRAM chips includes a slave fuse circuit and a slave reference voltage generator. The slave fuse circuit provides a slave setting signal according to a slave fuse setting operation. The slave reference voltage generator provides a slave reference voltage according to the slave setting signal. The master DRAM chip is coupled to the plurality of slave DRAM chips. The master DRAM chip controls the operation of the plurality of slave DRAM chips.

[0005] Based on the above, each slave DRAM chip provides a slave reference voltage according to the slave fuse setting operation. In this way, the power consumption of the DRAM device can be reduced.

[0006] To make the foregoing easier to understand, several embodiments accompanied by accompanying drawings are described in detail below. Simple Explanation of the Diagram

[0007] This disclosure includes accompanying drawings to provide a further understanding of the disclosure, and the drawings are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, are used to explain the principles of the disclosure. Figure 1 shows a schematic diagram of a dynamic random access memory (DRAM) device according to an embodiment of the present disclosure. Figure 2 shows a schematic diagram of a dynamic random access memory (DRAM) device according to an embodiment of the present disclosure. Figure 3 shows a schematic diagram of a slave reference voltage generator according to an embodiment of the present disclosure. Figure 4 shows a schematic diagram of a master reference voltage generator according to an embodiment of the present disclosure. Implementation

[0008] This disclosure can be understood by referring to the following detailed description in conjunction with the drawings described below. It should be noted that, for the purpose of clarity and ease of understanding, the various drawings in this disclosure depict only a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. Furthermore, the number and dimensions of each device depicted in the drawings are illustrative only and are not intended to limit the scope of this disclosure.

[0009] Certain terms are used throughout the description and claims to refer to specific elements. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to elements. This document is not intended to distinguish between elements with different names rather than different functions. In the following description and in the claims, the terms “comprising,” “including,” and “having” are used in an open-ended manner and should therefore be construed as meaning “including, but not limited to…”. Thus, when the terms “comprising,” “including,” and / or “having” are used in the description of this disclosure, it indicates the presence, but is not limited to, the presence of one or more corresponding features, areas, steps, operations, and / or elements.

[0010] It should be understood that when a component is referred to as "coupled to," "connected to," or "conducted to" another component, it can be directly connected to the other component and establish a direct electrical connection, or an intervening component can exist between these components for relay electrical connections (indirect electrical connections). In contrast, when a component is referred to as "directly coupled to," "directly conducted to," or "directly connected to" another component, there is no intervening component.

[0011] Please refer to FIG1, which shows a schematic diagram of a dynamic random access memory (DRAM) device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 100 includes slave DRAM chips 110_1 to 110_n and a master DRAM chip 120. Each of the slave DRAM chips 110_1 to 110_n includes a slave fuse circuit and a slave reference voltage generator.

[0012] For example, slave DRAM chip 110_1 includes slave fuse circuit 111_1 and slave reference voltage generator 112_1. Slave fuse circuit 111_1 provides a slave setting signal SSL_1 according to a slave fuse setting operation. Slave reference voltage generator 112_1 provides a slave reference voltage VREFSL_1 according to the slave setting signal SSL_1. Furthermore, when the slave fuse setting operation of slave fuse circuit 111_1 is completed, slave fuse circuit 111_1 provides a slave setting signal SSL_1 with a high voltage level. Slave reference voltage generator 112_1 is deactivated to stop providing slave reference voltage VREFSL_1. For example, the slave fuse setting operation is a deactivation setting operation of slave DRAM chip 110_1, but this disclosure is not limited to this. Therefore, when the slave DRAM chip 110_1 completes the slave fuse setting operation (i.e., the disable setting operation), the power consumption of the slave reference voltage generator 112_1 will be very low.

[0013] When the slave fuse circuit 111_1 does not perform the slave fuse setting operation, the slave reference voltage generator 112_1 is enabled to provide the slave reference voltage VREFSL_1. The slave reference voltage VREFSL_1 can be a reference voltage used to determine the logic level of the received signal or received data.

[0014] Slave DRAM chip 110_2 includes a slave fuse circuit 111_2 and a slave reference voltage generator 112_2. Slave fuse circuit 111_2 provides a slave set signal SSL_2 according to its slave fuse set operation. Slave reference voltage generator 112_2 provides a slave reference voltage VREFSL_2 according to SSL_2. Similarly, slave DRAM chip 110_n includes a slave fuse circuit 111_n and a slave reference voltage generator 112_n. Slave fuse circuit 111_n provides a slave set signal SSL_n according to its slave fuse set operation. Slave reference voltage generator 112_n provides a slave reference voltage VREFSL_n according to SSL_n.

[0015] In this embodiment, the master DRAM chip 120 is coupled to slave DRAM chips 110_1 to 110_n. The master DRAM chip 120 controls the operations of slave DRAM chips 110_1 to 110_n. For example, the master DRAM chip 120 controls the write and read operations of slave DRAM chips 110_1 to 110_n, but this disclosure is not limited thereto.

[0016] It is worth mentioning that each of the slave DRAM chips 110_1 to 110_n provides a slave reference voltage according to the slave fuse setting operation. In this way, the power consumption of the DRAM device 100 can be reduced.

[0017] In this embodiment, slave DRAM chips 110_1 to 110_n and master DRAM chip 120 are stacked on top of each other. For example, slave DRAM chips 110_1 to 110_n and master DRAM chip 120 are stacked to form a three-dimensional (3D) stacked DRAM structure.

[0018] Please refer to FIG2, which shows a schematic diagram of a dynamic random access memory (DRAM) device according to an embodiment of the present disclosure. In this embodiment, the DRAM device 200 includes slave DRAM chips 210_1 to slave DRAM chips 210_n and a master DRAM chip 220. Slave DRAM chip 210_1 includes a slave fuse circuit 111_1, a slave reference voltage generator 112_1, and a data receiver 213_1. The slave fuse circuit 111_1 and the slave reference voltage generator 112_1 have been clearly explained in the embodiment of FIG1, and therefore will not be repeated here.

[0019] In this embodiment, data receiver 213_1 is coupled to slave reference voltage generator 112_1. Data receiver 213_1 receives data DT1 and slave reference voltage VREFSL_1. Data receiver 213_1 determines the logic level of data DT1 based on slave reference voltage VREFSL_1. For example, when the voltage value of data DT1 is higher than the voltage value of slave reference voltage VREFSL_1, data receiver 213_1 determines that the logic level of data DT1 is high logic. When the voltage value of data DT1 is less than or equal to the voltage value of slave reference voltage VREFSL_1, data receiver 213_1 determines that the logic level of data DT1 is low logic. For example, slave reference voltage VREFSL_1 may be the reference voltage "VrefDQ" of slave DRAM chip 210_1.

[0020] Slave DRAM chip 210_2 includes slave fuse circuit 111_2, slave reference voltage generator 112_2, and data receiver 213_2. The slave fuse circuit 111_2 and slave reference voltage generator 112_2 have been clearly explained in the embodiment of FIG. 1, and therefore will not be repeated here. Data receiver 213_2 receives data DT2 and slave reference voltage VREFSL_2. Data receiver 213_2 determines the logic level of data DT2 based on slave reference voltage VREFSL_2. Similarly, slave DRAM chip 210_n includes slave fuse circuit 111_n, slave reference voltage generator 112_n, and data receiver 213_n. The slave fuse circuit 111_n and slave reference voltage generator 112_n have been clearly explained in the embodiment of FIG. 1, and therefore will not be repeated here. Data receiver 213_n receives data DTn and slave reference voltage VREFSL_n. The data receiver 213_n determines the logic level of the data DTn based on the slave reference voltage VREFSL_n.

[0021] In this embodiment, the main DRAM chip 220 includes a main fuse circuit 221 and a main reference voltage generator 222. The main fuse circuit 221 provides a main setting signal SMA according to the main fuse setting operation of the main fuse circuit 221. The main reference voltage generator 222 provides a main reference voltage VREFMA according to the main setting signal SMA.

[0022] For example, when the main fuse circuit 221 completes its main fuse setting operation, it provides a main setting signal SMA with a high voltage level. The main reference voltage generator 222 is deactivated to stop providing the main reference voltage VREFMA. Therefore, the power consumption of the main reference voltage generator 222 is very low. When the main fuse circuit 221 is not performing a main fuse setting operation, the main reference voltage generator 222 is enabled to provide the main reference voltage VREFMA. The main reference voltage VREFMA can be a reference voltage used to determine the logic level of a received signal or received data.

[0023] In this embodiment, the main DRAM chip 220 also includes a data receiver 223. The data receiver 223 is coupled to a main reference voltage generator 222. The data receiver 223 receives data DT and a main reference voltage VREFMA. The data receiver 223 determines the logic level of data DT based on the main reference voltage VREFMA. For example, when the voltage value of data DT is higher than the voltage value of the main reference voltage VREFMA, the data receiver 223 determines that the logic level of data DT is high logic. When the voltage value of data DT is less than or equal to the voltage value of the main reference voltage VREFMA, the data receiver 223 determines that the logic level of data DT is low logic. For example, the main reference voltage VREFMA can be the reference voltage "VrefDQ" of the main DRAM chip 220.

[0024] Please refer to Figures 1 and 3. Figure 3 shows a schematic diagram of a slave reference voltage generator according to an embodiment of the present disclosure. In this embodiment, the slave reference voltage generator 112_1 includes a slave switch SW1, a slave resistor R1, and a slave resistor R2. The first terminal of the slave switch SW1 is coupled to a reference high voltage VDDQ. The control terminal of the slave switch SW1 is coupled to a slave fuse circuit 111_1. The first terminal of the slave resistor R1 is coupled to a second terminal of the slave switch SW1. The second terminal of the slave resistor R1 outputs a slave reference voltage VREFSL_1. The slave resistor R2 is coupled between the second terminal of the slave resistor R1 and a reference low voltage VSSQ. In this embodiment, the slave switch SW1 may be implemented using a P-type transistor, but the present disclosure is not limited thereto.

[0025] In this embodiment, when the slave fuse circuit 111_1 does not perform a slave fuse setting operation, the slave switch SW1 is turned on. When the slave fuse circuit 111_1 completes the slave fuse setting operation, the slave switch SW1 is turned off. For example, when the slave fuse circuit 111_1 does not perform a slave fuse setting operation, the slave fuse circuit 111_1 provides a slave setting signal SSL_1 with a low voltage level. Therefore, the slave switch SW1 is turned on. The slave reference voltage generator 112_1 generates a slave reference voltage VREFSL_1 based on the voltage difference between the reference high voltage VDDQ and the reference low voltage VSSQ, the resistance value of the slave resistor R1, and the resistance value of the slave resistor R2. When the slave fuse circuit 111_1 completes the slave fuse setting operation, the slave fuse circuit 111_1 provides a slave setting signal SSL_1 with a high voltage level. Therefore, the slave switch SW1 is turned off. Therefore, slave reference voltage generator 112_1 does not generate slave reference voltage VREFSL_1. For example, the slave fuse setting operation is a deactivation setting operation for slave DRAM chip 110_1. When the slave fuse setting operation is completed, slave reference voltage generator 112_1 does not generate slave reference voltage VREFSL_1. In this way, when slave DRAM chip 110_1 is deactivated, slave reference voltage generator 112_1 does not generate slave reference voltage VREFSL_1 to reduce power consumption.

[0026] Please refer to Figures 2 and 4. Figure 4 shows a schematic diagram of a main reference voltage generator according to an embodiment of this disclosure. In this embodiment, the main reference voltage generator 222 includes a main switch SW2, a main resistor R3, and a main resistor R4. The first terminal of the main switch SW2 is coupled to the reference high voltage VDDQ. The control terminal of the main switch SW2 is coupled to the main fuse circuit 221. The first terminal of the main resistor R3 is coupled to the second terminal of the main switch SW2. The second terminal of the main resistor R3 outputs the main reference voltage VREFMA. The main resistor R4 is coupled between the second terminal of the main resistor R3 and the reference low voltage VSSQ. In this embodiment, the main switch SW2 may be implemented using a P-type transistor, but this disclosure is not limited thereto.

[0027] In this embodiment, when the main fuse circuit 221 does not perform the main fuse setting operation, the main switch SW2 is turned on. When the main fuse circuit 221 completes the main fuse setting operation, the main switch SW2 is turned off. For example, when the main fuse circuit 221 does not perform the main fuse setting operation, the main fuse circuit 221 provides a main setting signal SMA with a low voltage level. Therefore, the main switch SW2 is turned on. The main reference voltage generator 222 generates a main reference voltage VREFMA based on the voltage difference between the reference high voltage VDDQ and the reference low voltage VSSQ, the resistance value of the main resistor R3, and the resistance value of the main resistor R4. When the main fuse circuit 221 completes the main fuse setting operation, the main fuse circuit 221 provides a main setting signal SMA with a high voltage level. Therefore, the main switch SW2 is turned off. Therefore, the main reference voltage generator 222 does not generate the main reference voltage VREFMA. For example, the main fuse setting operation is a deactivation setting operation for the main DRAM chip 220. When the main fuse setting operation is completed, the main reference voltage generator 222 does not generate the main reference voltage VREFMA. In this way, when the main DRAM chip 220 is deactivated, the main reference voltage generator 222 does not generate the main reference voltage VREFMA, thereby reducing the power consumption of the main DRAM chip 220.

[0028] In some embodiments, when the main fuse circuit 221 does not perform the main fuse setting operation, the main DRAM chip 220 can control the slave DRAM chips 210_1 to 210_n.

[0029] In some embodiments, each of the slave fuse circuits 111_1 to 111_n and the master fuse circuit 221 may be implemented by any type of electric fuse circuit, but this disclosure is not limited thereto.

[0030] Based on the foregoing, each slave DRAM chip provides a slave reference voltage according to a slave fuse setting operation. Therefore, the power consumption of the DRAM device can be reduced. For example, the slave fuse setting operation is a deactivation setting operation for the slave DRAM chip. When the slave fuse setting operation is completed, the slave reference voltage generator is deactivated, and the slave reference voltage generator does not generate a slave reference voltage, thereby reducing power consumption.

[0031] It will be apparent to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

[0032] 100, 200: DRAM devices 110_1, 110_2, ..., 110_n, 210_1, 210_2, ..., 210_n: Subordinate DRAM chips 111_1, 111_2, 111_n: Slave fuse circuits 112_1, 112_2, 112_n: Slave reference voltage generator 120, 220: Main DRAM chips 213_1, 213_2, 213_n, 223: Data receiver 221: Main fuse circuit 222: Main Reference Voltage Generator DT, DT1, DT2, DTn: Data R1, R2: Subordinate resistors R3, R4: Main resistors SMA: Master Setting Signal SSL_1, SSL_2, SSL_n: Slave setting signals SW1: Slave switch SW2: Main switch VDDQ: Reference high voltage VREFMA: Main Reference Voltage VREFSL_1, VREFSL_2, VREFSL_n: Slave reference voltages VSSQ: Reference Low Voltage

Claims

1. A dynamic random access memory device, comprising: A plurality of slave dynamic random access memory (DRAM) chips, each of the plurality of slave DRAM chips comprising: a slave fuse circuit configured to provide a slave setting signal according to a slave fuse setting operation of the slave fuse circuit; and a slave reference voltage generator configured to provide a slave reference voltage according to the slave setting signal; and a master DRAM chip coupled to the plurality of slave DRAM chips and configured to control the operation of the plurality of slave DRAM chips, wherein when the slave fuse circuit completes the slave fuse setting operation, the slave reference voltage generator stops providing the slave reference voltage.

2. The dynamic random access memory device as claimed in claim 1, wherein when the slave fuse circuit does not perform the slave fuse setting operation, the slave reference voltage generator provides the slave reference voltage.

3. The dynamic random access memory device as claimed in claim 1, wherein the slave reference voltage generator comprises: A slave switch, wherein the first terminal of the slave switch is coupled to a reference high voltage, and the control terminal of the slave switch is coupled to the slave fuse circuit; A first slave resistor, the first end of which is coupled to the second end of the slave switch, and the second end of the first slave resistor outputs the slave reference voltage; And a second slave resistor, coupled between the second terminal of the first slave resistor and the reference low voltage.

4. The dynamic random access memory device as described in claim 3, wherein: The slave switch is turned on when the slave fuse circuit does not perform the slave fuse setting operation, and the slave switch is turned off when the slave fuse circuit completes the slave fuse setting operation.

5. The dynamic random access memory device as claimed in claim 1, wherein the main dynamic random access memory chip comprises: The main fuse circuit is configured to provide a main setting signal according to the main fuse setting operation of the main fuse circuit; And a main reference voltage generator, configured to provide a main reference voltage according to the main setting signal.

6. The dynamic random access memory device as claimed in claim 5, wherein the main reference voltage generator provides the main reference voltage when the main fuse circuit does not perform the main fuse setting operation.

7. The dynamic random access memory device as claimed in claim 5, wherein when the main fuse circuit completes the main fuse setting operation, the main reference voltage generator stops providing the main reference voltage.

8. The dynamic random access memory device as claimed in claim 5, wherein each of the primary reference voltage and the secondary reference voltage is a reference voltage for determining the logic level of received data.

9. The dynamic random access memory device as claimed in claim 5, wherein the master reference voltage generator comprises: The main switch has its first terminal coupled to a reference high voltage and its control terminal coupled to the main fuse circuit. A first main resistor, the first end of which is coupled to the second end of the main switch, and the second end of which outputs the main reference voltage; And a second main resistor, coupled between the second terminal of the first main resistor and the reference low voltage.

10. The dynamic random access memory device as claimed in claim 9, wherein: The main switch is turned on when the main fuse circuit does not perform the main fuse setting operation, and the main switch is turned off when the main fuse circuit completes the main fuse setting operation.

11. The dynamic random access memory device as claimed in claim 1, wherein: The plurality of subordinate dynamic random access memory chips and the master dynamic random access memory chip are stacked on top of each other.

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