Flyback converter and method for the same

Abstract

This disclosure provides a flyback switching circuit, including a primary-side power switch, a secondary-side rectifier switch, a control circuit, and a primary-side drive circuit. The control circuit provides a primary-side control signal, a secondary-side control signal, and a monitoring signal. The primary-side drive circuit generates a drive signal to drive the primary-side power switch based on the primary-side control signal and the monitoring signal. When the interval between two adjacent switching cycles of the flyback switching circuit is longer than a reference duration, the monitoring signal controls the drive circuit to provide a weak drive, causing the primary-side power switch to transition from an off state to a fully on state at a first speed. When the interval between two adjacent switching cycles is shorter than the reference duration, the monitoring signal drives the signal circuit to provide a strong drive, causing the primary-side power switch to transition from an off state to a fully on state at a second speed.

Description

Technical Field

[0001] This disclosure relates to an electronic circuit, and more specifically, in particular to a flyback switching circuit and its method. Prior Technology

[0002] A flyback converter is a typical converter in AC-to-DC conversion applications. A typical circuit of a flyback converter is shown in Figure 1, which includes: a transformer T with a primary-side coil T0 and a secondary-side coil T1, a primary-side power switch Q0, a secondary-side rectifier switch Q1, and a voltage-off buffer RCD.

[0003] In flyback switching applications, zero-voltage turn-on (ZVTO) technology is typically used to reduce switching losses on the primary-side power switch. ZVTO refers to a technique where, before the primary-side power switch Q0 turns on, the secondary-side power switch Q1 conducts for an additional period after its freewheeling phase, or an auxiliary power switch Q2 connected in series with the auxiliary coil T2 (as shown by the dotted line in Figure 1) conducts for a period, thus achieving zero-voltage turn-on for the primary-side power switch Q0. After this additional conduction time, a negative magnetizing current is generated on the primary side. This negative magnetizing current amplifies the amplitude of the discontinuous oscillation of the primary-side power switch Q0, resulting in a relatively low turn-on voltage for Q0.

[0004] However, when the circuit load decreases, causing the converter to enter burst mode, and then exits burst mode as the load increases, the voltage across the capacitor in the voltage-off buffer RCD will drop very low. If the secondary rectifier switch Q1 is turned on for an additional period of time before the primary power switch Q0 is turned on, the current flowing through the secondary rectifier switch during this additional on-time will be very large, resulting in a large voltage ripple in the output voltage. Summary of the Invention

[0005] According to one embodiment of this disclosure, a flyback switching circuit is proposed, including a primary-side power switch, a secondary-side rectifier switch, a control circuit, and a primary-side drive circuit. The primary-side power switch is coupled to the primary winding of a transformer. The secondary-side rectifier switch is coupled to the secondary winding of the transformer. The control circuit provides a primary-side control signal, a secondary-side control signal, and a monitoring signal. The primary-side power switch and the secondary-side rectifier switch are periodically turned on and off under the control of the control circuit, converting the input voltage into an output voltage. The primary-side drive circuit generates a drive signal to drive the primary-side power switch based on the primary-side control signal and the monitoring signal. When the interval between two adjacent switching cycles of the flyback switching circuit is longer than a reference duration, the monitoring signal control drive circuit provides a weak drive, causing the primary-side power switch to transition from an off state to a fully on state at a first speed. When the interval between two adjacent switching cycles of the flyback switching circuit is shorter than the reference duration, the monitoring signal drive signal circuit provides a strong drive, causing the primary-side power switch to transition from an off state to a fully on state at a second speed.

[0006] According to another embodiment of this disclosure, a method for a flyback switching circuit is proposed. The flyback switching circuit has a primary-side power switch and a secondary-side rectifier switch. The method includes: periodically controlling the on and off states of the primary-side power switch and the secondary-side rectifier switch to convert an input voltage into an output voltage; and determining the interval between two adjacent switching cycles of the flyback switching circuit: if the interval between two adjacent switching cycles of the flyback switching circuit is longer than a reference interval, providing a weak drive to the primary-side power switch, causing the primary-side power switch to transition from an off state to a fully on state at a first speed; if the interval between two adjacent switching cycles of the flyback switching circuit is shorter than the reference interval, providing a strong drive to the primary-side power switch, causing the primary-side power switch to transition from an off state to a fully on state at a second speed. Simple Explanation of the Diagram

[0007] To better understand the embodiments of this disclosure, the disclosure will be described in detail with reference to the following drawings. Like elements are indicated by like reference numerals. The following drawings are for illustrative purposes only and may only show a portion of the device, and are not necessarily drawn to scale. [Figure 1] is a schematic diagram of the circuit structure of a flyback converter. [Figure 2] is a schematic diagram of the circuit structure of a flyback switching circuit according to an embodiment of the present disclosure. [Figure 3] illustrates waveform diagrams showing the driving circuit according to an embodiment of the present disclosure providing different driving currents under different conditions. [Figure 4] illustrates a waveform diagram of the drive signal under weak drive current according to an embodiment of the present disclosure. [Figure 5] illustrates a waveform diagram of the drive signal under a strong drive current according to an embodiment of the present disclosure. [Figure 6] illustrates a schematic diagram of the circuit structure of a drive circuit according to an embodiment of the present disclosure. [Figure 7] illustrates a circuit structure diagram of a flyback switching circuit according to an embodiment of the present disclosure. [Figure 8] illustrates a circuit structure diagram of a flyback switching circuit according to an embodiment of the present disclosure. [Figure 9] is a flowchart of a method for a flyback switching circuit according to an embodiment of the present disclosure. Implementation

[0008] Specific embodiments of this disclosure will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that these specific details are not necessary to implement this disclosure. In other instances, known circuits, materials, or methods have not been specifically described to avoid obscuring this disclosure.

[0009] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment disclosed herein. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as "coupled to" or "connected to" another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly coupled to" or "directly connected to" another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0010] Figure 2 is a schematic diagram of the circuit structure of a flyback converter circuit 200 according to an embodiment of the present disclosure. In the embodiment shown in Figure 2, the flyback converter circuit 200 includes: a primary-side power switch Q0 coupled to the primary-side coil T0 of a transformer T; a secondary-side rectifier switch Q1 coupled to the secondary-side coil T1 of a transformer T; a control circuit 110 providing a primary-side control signal GPS, a secondary-side control signal GSR, and a monitoring signal MS; and a primary-side drive circuit 120 generating a drive signal DR based on the primary-side control signal GPS and the monitoring signal MS to drive the primary-side power switch Q0. The primary-side power switch Q0 and the secondary-side rectifier switch Q1 are periodically turned on and off under the control of the control circuit 110, converting the input voltage Vin into the output voltage VO. Specifically, when the interval between two adjacent switching cycles of the flyback switching circuit 200 is longer than the reference duration, the monitoring signal MS control drive circuit 120 provides a weak drive so that the primary-side power switch Q0 changes from the off state (i.e., the cut-off state) to the fully on state at a first speed; when the interval between two adjacent switching cycles of the flyback switching circuit 200 is shorter than the reference duration, the monitoring signal MS drive signal circuit 120 provides a strong drive so that the primary-side power switch Q0 changes from the off state to the fully on state at a second speed.

[0011] In one embodiment disclosed herein, the first speed is less than the second speed, that is, the time required for the primary-side power switch Q0 to go from the off state to the fully on state under weak drive conditions is greater than the time required for it to go from the off state to the fully on state under strong drive conditions.

[0012] In one embodiment disclosed herein, when the flyback switching circuit operates normally and has not entered the burst mode, the interval between two adjacent switching cycles of the flyback switching circuit 200 is less than the reference duration, the monitoring signal MS control drive circuit 120 provides strong drive, and the primary-side power switch Q0 changes from the off state to the fully on state at a second speed; when the flyback switching circuit 200 enters the burst mode and then exits the burst mode, the interval between two adjacent switching cycles of the flyback switching circuit 200 is longer than the reference duration, the monitoring signal MS control drive circuit 120 provides weak drive, and the primary-side power switch Q0 changes from the off state to the fully on state at a first speed.

[0013] In one embodiment disclosed herein, the term "strong drive" refers to the drive circuit providing a relatively large drive current, a relatively large drive voltage, or a relatively strong drive pulse, causing the drive signal DR to increase rapidly, thereby causing the primary-side power switch Q0 to quickly transition from the off state to the fully on state. Conversely, the term "weak drive" refers to the drive circuit providing a relatively small drive current, a relatively small drive voltage, or a relatively weak drive pulse, causing the drive signal DR to increase slowly, thereby causing the primary-side power switch Q0 to slowly transition from the off state to the fully on state.

[0014] Figure 3 illustrates the waveform diagrams of the drive circuit 120 providing different drive currents IG under different conditions according to an embodiment of the present disclosure. Figure 4 illustrates the waveform diagram of the drive signal DR under a weak drive current according to an embodiment of the present disclosure; Figure 5 illustrates the waveform diagram of the drive signal DR under a strong drive current according to an embodiment of the present disclosure. As can be seen from Figure 3, when the time interval between two adjacent primary-side control signals GPS is greater than the reference duration TREF, the drive current IG provided by the drive circuit 120 is relatively small (as shown by the small drive current IGL in Figure 3). At this time, the drive signal DR slowly increases from low to high, and the primary-side power switch Q0 is slowly turned on, as shown in Figure 4. When the time interval between two adjacent primary-side control signals GPS is less than the reference duration TREF, the drive current IG provided by the drive circuit 120 is relatively large (as shown by the large drive current IGH in Figure 3). At this time, the drive signal DR rapidly increases from low to high, and the primary-side power switch Q0 is rapidly turned on, as shown in Figure 5.

[0015] In one embodiment of this disclosure, after the flyback conversion circuit 200 enters the surge mode (i.e., when in surge mode), the control circuit 110 controls the primary-side power switch Q0 and the secondary-side rectifier switch Q1 not to perform switching operations.

[0016] In one embodiment of this disclosure, during the startup phase of the flyback switching circuit 200, the control circuit 110 controls the drive circuit 120 to provide a weak drive, and the primary-side power switch Q0 transitions from an off state to a fully on state at a first speed.

[0017] In one embodiment disclosed herein, the primary-side power switch Q0 and the secondary-side rectifier switch Q1 comprise metal-oxide-semiconductor field-effect transistors (MOSFETs). However, those skilled in the art will understand that the primary-side power switch Q0 and the secondary-side rectifier switch Q1 may comprise other controllable switching devices, such as bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), gallium nitride field-effect transistors (GaN FETs), silicon carbide field-effect transistors (SiC FETs), or common-source-common-gate stacked circuits (such as a stacked circuit of a junction field-effect transistor (JFET) and a MOSFET), etc.

[0018] In one embodiment of this disclosure, when the flyback switching circuit 200 is operating normally and has not entered the surge mode, after the primary-side power switch Q0 is turned off, the control circuit 110 controls the secondary-side rectifier switch Q1 to turn on until the condition for the secondary-side rectifier switch Q1 to turn off is met (e.g., the current flowing through the secondary-side rectifier switch Q1 drops to a reference value near zero). Before the primary-side power switch Q0 is turned on in the next switching cycle, the control circuit 110 controls the secondary-side rectifier switch Q1 to turn on for an additional period of time. When the flyback switching circuit 200 enters the surge mode and then exits the surge mode, before the primary-side power switch Q0 is turned on in the next switching cycle, the control circuit 110 controls the secondary-side rectifier switch Q1 to no longer turn on for an additional period of time. Specifically, when the flyback switching circuit 200 enters and exits the rush mode, during the initial n switching cycles after exiting the rush mode, the control circuit 110 controls the secondary rectifier switch Q1 to not conduct for an additional period of time in the next switching cycle of the primary power switch Q0, where n is an integer greater than or equal to 1; and after exiting the rush mode and after these n switching cycles, the control circuit 110 resumes controlling the secondary rectifier switch Q1 to conduct for an additional period of time before the primary power switch Q0 is turned on in the next switching cycle.

[0019] Figure 6 illustrates a schematic diagram of the circuit structure of the drive circuit 120 according to an embodiment of the present disclosure. As shown in Figure 6, the drive circuit 120 includes: a first current source 201 providing a first drive current I1; a second current source 202 providing a second drive current I2; and a third current source 203 providing a discharge current I3. When the primary-side control signal GPS indicates that the primary-side power switch Q0 is turned on, under the control of the monitoring signal MS, the drive circuit 120 selects either the first drive current I1 or the second drive current I2 to drive the primary-side power switch Q0. When the primary-side control signal GPS indicates that the primary-side power switch Q0 is turned off, the drive circuit 120 selects the third current source 203 to provide a discharge path for the primary-side power switch Q0, thereby successfully turning off the primary-side power switch Q0.

[0020] In the embodiment shown in Figure 6, the driving circuit 120 further includes a switching circuit 204, which, under the control of the primary side control signal GPS and the monitoring signal MS, selects a first current source 201, a second current source 202 or a third current source 203 to charge (i.e., drive the primary side power switch Q0 to conduct) or discharge (i.e., disconnect the primary side power switch Q0).

[0021] In one embodiment, the first drive current I1 is a weak drive current, and the second drive current I2 is a strong drive current. For example, the magnitude of the second drive current I2 is approximately five times that of the first drive current I1. When the monitoring signal MS indicates that the interval between two adjacent switching cycles of the flyback switching circuit 200 is longer than the reference duration, the switching circuit 204 selects the first current source 201, causing the first drive current I1 to drive the primary-side power switch Q0, thereby causing the primary-side power switch Q0 to transition from the off state to the fully on state at a relatively slow first speed. When the monitoring signal MS indicates that the interval between two adjacent switching cycles of the flyback switching circuit 200 is shorter than the reference duration, the switching circuit 204 selects the second current source 202, causing the second drive current I2 to drive the primary-side power switch Q0, thereby causing the primary-side power switch Q0 to transition from the off state to the fully on state at a relatively fast second speed.

[0022] Figure 7 illustrates a schematic diagram of the circuit structure of a flyback switching circuit 700 according to an embodiment of this disclosure. The embodiment shown in Figure 7 specifically illustrates a schematic diagram of the circuit structure of a control circuit 110. Specifically, in the embodiment shown in Figure 7, the control circuit 110 includes: a primary-side controller 101 having a setting circuit 11 and a logic circuit 12 (such as an RS flip-flop), the setting circuit 11 providing a setting signal set to the logic circuit 12 to control the conduction of the primary-side power switch Q0; a secondary-side controller 102 providing a secondary-side control signal GSR; and a timer 103 timing the time interval between two adjacent setting signal sets to generate a monitoring signal MS. When the time interval between two adjacent setting signal sets is greater than a reference duration, the drive circuit 120 provides a weak drive, and the primary-side power switch Q0 transitions from an off state to a fully on state at a first speed; when the time interval between two adjacent setting signal sets is less than the reference duration, the drive circuit 120 provides a strong drive, and the primary-side power switch Q0 transitions from an off state to a fully on state at a second speed.

[0023] In one embodiment disclosed herein, the setting signal set can be transmitted from the secondary side (as shown in Figure 8 below); it can also be generated autonomously by the primary side. For example, during the startup phase, when the output voltage VO has not reached the set voltage value and the secondary side control has not yet been established, the primary side can achieve startup by performing an autonomous switching action.

[0024] Figure 8 illustrates a schematic diagram of the circuit structure of a flyback converter circuit 800 according to an embodiment of the present disclosure. The embodiment shown in Figure 8 specifically illustrates a schematic diagram of the circuit structure of the control circuit 110. Specifically, in the embodiment shown in Figure 8, the control circuit 110, in addition to the primary-side controller 101, the secondary-side controller 102, and the timer 103, further includes: an error amplifier 104, which amplifies and integrates the difference between the feedback voltage VFB (representing the output voltage VO) and the reference voltage Vref to generate a compensation signal CMP; and a hysteresis comparator 105, which compares the compensation signal CMP with the threshold voltage VTH to generate a judgment signal BRT, indicating whether the flyback converter circuit 800 has entered or exited the surge mode. The secondary-side controller 102 generates a secondary-side signal syn0 and the secondary-side control signal GSR based on a signal representing the current flowing through the secondary-side rectifier switch Q1 (such as the voltage VDSR across the secondary-side rectifier switch Q1), the compensation signal CMP, and the judgment signal BRT. The control circuit 110 further includes: a transmission module 106 that converts the secondary side signal syn0 into a primary side signal syn1; the primary side controller 101 that generates the primary side control signal GPS based on the primary side signal syn1; and the timer 103 that generates the monitoring signal MS based on the primary side signal syn1.

[0025] In the embodiment shown in Figure 8, if the compensation signal CMP is less than the threshold voltage VTH, it indicates that the output voltage VO is low (i.e., the load is light), and the flyback conversion circuit 800 enters the surge mode. If the load increases, the compensation signal CMP increases. When the compensation signal CMP increases to the sum of the threshold voltage VTH and the hysteresis value of the hysteresis comparator 105, it indicates that the flyback conversion circuit 800 exits the surge mode. When the flyback conversion circuit 800 exits the surge mode, the drive circuit 120 provides a weak drive, causing the primary-side power switch Q0 to switch from the off state to the on state at a first speed.

[0026] In one embodiment of this disclosure, the transmission module 106 includes an isolation capacitor. In other embodiments of this disclosure, the transmission module 106 may also include an isolation feedback element such as an optocoupler.

[0027] Figure 9 is a flowchart 900 of a method for a flyback converter circuit according to an embodiment of the present disclosure. The flyback converter circuit has a primary-side power switch and a secondary-side rectifier switch, and the method includes steps 901 to 904.

[0028] Step 901: Periodically control the on and off of the primary-side power switch and the secondary-side rectifier switch to convert the input voltage into the output voltage.

[0029] Step 902: Determine the interval between two adjacent switching cycles of the flyback switching circuit. If the interval between two adjacent switching cycles of the flyback switching circuit is longer than the reference interval, proceed to step 903; if the interval between two adjacent switching cycles of the flyback switching circuit is shorter than the reference interval, proceed to step 904.

[0030] Step 903: Provide a weak drive to the primary-side power switch, so that the primary-side power switch changes from the off state to the fully on state at a first speed.

[0031] Step 904: Provide a strong drive to the primary-side power switch, causing the primary-side power switch to change from the off state to the fully on state at a second speed.

[0032] In one embodiment of this disclosure, the first speed is less than the second speed.

[0033] In one embodiment of this disclosure, providing a strong drive includes providing a relatively large drive current, a relatively large drive voltage, or a relatively strong drive pulse; providing a weak drive includes providing a relatively small drive current, a relatively small drive voltage, or a relatively weak drive pulse.

[0034] In one embodiment of this disclosure, the method further includes providing a weak drive to the primary-side power switch during the startup phase of the flyback switching circuit.

[0035] In one embodiment of this disclosure, the method further includes: providing a strong drive to the primary-side power switch when the flyback converter is operating normally and has not entered the surge mode; and providing a weak drive to the primary-side power switch when the flyback converter enters the surge mode and then exits the surge mode. When the flyback converter enters the surge mode, the primary-side power switch and the secondary-side rectifier switch are controlled not to perform switching operations.

[0036] In one embodiment disclosed herein, when the flyback switching circuit enters and exits the flyback mode, a weak drive is provided to the primary-side power switch during the initial n switching cycles immediately after exiting the flyback mode, where n is an integer greater than or equal to 1; and a strong drive is provided to the primary-side power switch after exiting the flyback mode and after the n switching cycles have elapsed.

[0037] The aforementioned flyback switching circuit and method according to various embodiments of this disclosure, when the interval between two adjacent switching cycles of the circuit is long (such as when the system enters a surge mode or during the startup phase), provides a weak drive to the primary-side power switch, causing the primary-side power switch to slowly transition from an off state to a fully on state, thereby reducing voltage spikes across the secondary-side rectifier switch and improving circuit performance.

[0038] Although this disclosure has been described with reference to several exemplary embodiments, it should be understood that the terminology used is illustrative and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from its spirit or substance, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations falling within the scope of the claims or their equivalents should be covered by the appended claims.

[0039] 200: Flyback Conversion Circuit Vin: Input voltage T0: Primary side coil T1: Secondary coil T: Transformer Q0: Primary-side power switch Q1: Secondary side rectifier switch VO: Output voltage GPS: Primary side control signal GSR: Secondary control signal MS: Monitoring signal 110: Control Circuit 120: Primary-side drive circuit DR: Drive Signal RCD: Voltage-off type buffer T2: Auxiliary coil Q2: Auxiliary power switch 201, 202, 203: Current Source I1, I2, I3: Current 204: Switching Circuit 700, 800: Flyback Conversion Circuit 101: Primary Side Controller 102: Secondary-side controller 103: Timer 11: Setting Circuit 12: Logic Circuits set: Set signal 104: Error Amplifier 105: Hysteresis Comparator 106: Transfer Module VFB: Feedback Voltage Vref: Reference voltage CMP: Compensation Signal VTH: Threshold voltage VDSR: Voltage BRT: Determine the signal syn0: Secondary side signal syn1: Primary side signal 900: Method Flowchart 901, 902, 903, 904: Steps

Claims

1. A flyback switching circuit, comprising: A primary-side power switch is coupled to a primary-side coil of a transformer; a secondary-side rectifier switch is coupled to the primary-side coil of the transformer; a control circuit is used to provide a primary-side control signal, a secondary-side control signal and a monitoring signal, wherein the primary-side power switch and the secondary-side rectifier switch are periodically turned on and off under the control of the control circuit to convert an input voltage into an output voltage; And a primary-side drive circuit for generating a drive signal to drive the primary-side power switch based on the primary-side control signal and the monitoring signal; wherein: when the interval between two adjacent switching cycles of the flyback switching circuit is longer than a reference duration, the monitoring signal controls the drive circuit to provide a weak drive, causing the primary-side power switch to move from an off state to a fully on state at a first speed; when the interval between two adjacent switching cycles of the flyback switching circuit is shorter than the reference duration, the monitoring signal drives the signal circuit to provide a strong drive, causing the primary-side power switch to move from the off state to the fully on state at a second speed.

2. The flyback switching circuit as described in claim 1, wherein: During the startup phase of the flyback switching circuit, the drive circuit provides the weak drive, and the primary-side power switch moves from the off state to the fully on state at the first speed.

3. The flyback switching circuit as described in claim 1, wherein the first speed is less than the second speed.

4. The flyback switching circuit as described in claim 1, wherein: When the flyback switching circuit is operating normally and has not entered a surge mode, the drive circuit provides strong drive to the primary-side power switch; when the flyback switching circuit enters the surge mode and then exits the surge mode, the drive circuit provides weak drive to the primary-side power switch.

5. The flyback switching circuit as claimed in claim 1, wherein the control circuit comprises: A primary-side controller has a setting circuit and a logic circuit, the setting circuit being used to provide a setting signal to the logic circuit to control the conduction of the primary-side power switch; and a timer being used to time a time interval between two adjacent setting signals to generate the monitoring signal.

6. The flyback switching circuit as claimed in claim 1, wherein the drive circuit comprises: A first current source is provided to provide a first drive current; And a second current source for providing a second drive current; wherein: when the primary-side control signal indicates that the primary-side power switch is turned on, if the monitoring signal indicates that the interval between two adjacent switching cycles of the flyback switching circuit is longer than the reference duration, the first current source is selected so that the first drive current drives the primary-side power switch; when the primary-side control signal indicates that the primary-side power switch is turned on, if the monitoring signal indicates that the interval between two adjacent switching cycles of the flyback switching circuit is shorter than the reference duration, the second current source is selected so that the second drive current drives the primary-side power switch, wherein the second drive current is greater than the first drive current.

7. A method for a flyback converter circuit having a primary-side power switch and a secondary-side rectifier switch, the method comprising: The primary-side power switch and the secondary-side rectifier switch are periodically turned on and off to convert an input voltage into an output voltage. And determine the interval duration between two adjacent switching cycles of the flyback switching circuit: if the interval duration between two adjacent switching cycles of the flyback switching circuit is longer than a reference duration, provide a weak drive to the primary-side power switch, so that the primary-side power switch changes from an off state to a fully on state at a first speed; if the interval duration between two adjacent switching cycles of the flyback switching circuit is shorter than the reference duration, provide a strong drive to the primary-side power switch, so that the primary-side power switch changes from the off state to the fully on state at a second speed.

8. The method as described in claim 7, further comprising: When the flyback switching circuit is operating normally and has not entered a surge mode, it provides strong drive to the primary-side power switch. And when the flyback switching circuit enters the burst mode and then exits the burst mode, it provides the weak drive to the primary-side power switch.

9. The method as described in claim 7, wherein the first speed is less than the second speed.

10. The method as described in claim 7, further comprising: During the startup phase of the flyback switching circuit, the weak drive is provided to the primary-side power switch.

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