Halogen-free etching of silicon nitride

Abstract

A semiconductor processing method may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A silicon- and nitrogen-containing material layer may be disposed on the substrate. The method may include forming a plasma effluent of the hydrogen-containing precursor. The method may include contacting the silicon- and nitrogen-containing material layer with the plasma effluent of the hydrogen-containing precursor. This contact may etch a portion of the silicon- and nitrogen-containing material layer.

Description

Technical Field

[0001] This case asserts priority to U.S. Patent Application No. 18 / 203,404, filed on May 30, 2023, entitled “HALOGEN-FREE ETCHING OF SILICON NITRIDE,” the entire contents of which are incorporated herein by reference.

[0002] This invention relates to semiconductor systems and processes. More specifically, this invention relates to halogen-free etching of silicon nitride. Prior Technology

[0003] Integrated circuits are fabricated by creating complex patterned material layers on a substrate surface. Creating patterned material on the substrate requires controlled methods for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist to underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is often desirable to have etching processes that etch one material faster than another, facilitating processes such as pattern transfer. This type of etching process is referred to as material-selective. Due to the diversity of materials, circuits, and processes, etching processes have been developed to be selective for various materials.

[0004] Etching processes, based on the materials used in the process, can be termed wet or dry. For example, wet etching can preferentially remove some oxide dielectrics compared to other dielectrics and materials. However, wet processes can have difficulty penetrating some confined trenches and sometimes deform the remaining material. Dry etching, generated in localized plasma within the substrate processing area, can penetrate more confined trenches and exhibit less deformation of the fine remaining structure. However, localized plasma can damage the substrate through the arc generated when it discharges.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are met by the present invention. Summary of the Invention

[0006] A semiconductor processing method may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A silicon- and nitrogen-containing material layer may be disposed on the substrate. The method may include forming a plasma effluent of the hydrogen-containing precursor. The method may include contacting the silicon- and nitrogen-containing material layer with the plasma effluent of the hydrogen-containing precursor. This contact may etch a portion of the silicon- and nitrogen-containing material layer.

[0007] In some embodiments, the hydrogen-containing precursor may be or include diatomic hydrogen (H2). The processing region may be maintained as halogen-free. A silicon-oxygen-containing material layer, a silicon-containing material layer, or both may be disposed on the substrate. The method may include providing an inert precursor and a hydrogen-containing precursor to the processing region. The flow rate of the inert precursor may be greater than the flow rate of the hydrogen-containing precursor. Plasma effluent may be formed at a plasma power greater than or about 800 W. Plasma effluent may be formed at a plasma power greater than or about 2,000 W. This contact may be formed with silane (SiH4), ammonia (NH3), or both. The substrate may be characterized by a temperature less than or about 50 °C. The substrate may be characterized by a temperature less than or about -25 °C. The pressure within the semiconductor processing chamber may be maintained at less than or about 100 mTorr. This contact may be etched at an etch rate greater than or about 1 Å / min for the silicon-nitrogen-containing material layer.

[0008] Some embodiments of the present invention may cover semiconductor processing methods. The method may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A silicon-oxygen-containing material layer may be disposed on the substrate. A silicon-nitrogen-containing material layer may be disposed on top of the silicon-oxygen-containing material layer. The method may include forming a plasma effluent of the hydrogen-containing precursor. The plasma effluent may be formed at a plasma power greater than or about 1,000 W. The method may include contacting the silicon-nitrogen-containing material layer with the plasma effluent of the hydrogen-containing precursor. This contact may involve selectively etching a portion of the silicon-nitrogen-containing material layer relative to the silicon-oxygen-containing material layer.

[0009] In some embodiments, the processing area may be maintained as halogen-free. The substrate may be characterized by a temperature of less than or about 50 °C.

[0010] Some embodiments of the present invention may cover semiconductor processing methods. The methods may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A silicon-oxygen-containing material layer may be disposed on the substrate. A silicon-nitrogen-containing material layer may be disposed on top of the silicon-oxygen-containing material layer. The methods may include forming a plasma effluent of the hydrogen-containing precursor. The methods may include contacting the silicon-nitrogen-containing material layer with the plasma effluent of the hydrogen-containing precursor. This contact may involve selectively etching a portion of the silicon-nitrogen-containing material layer relative to the silicon-oxygen-containing material layer. The substrate may be characterized by a temperature less than or about -50 °C.

[0011] In some embodiments, the method may include providing helium and a hydrogen-containing precursor to a processing zone. The processing zone may be maintained as halogen-free. Plasma effluent may be formed at a plasma power greater than or about 1,000 W.

[0012] This invention offers numerous advantages over conventional systems and techniques. For example, the process provides high selectivity for silicon nitride etching relative to silicon and / or silicon oxide. Furthermore, the process can be performed without the use of halogen materials. These and other embodiments, and their many advantages and features, are described in more detail in the attached specification and accompanying drawings. Simple Explanation of the Diagram

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the rest of the instruction manual and the diagrams.

[0014] Figure 1 shows a top plan view of an exemplary processing system according to some embodiments of the present invention.

[0015] Figure 2 shows a sectional view of an exemplary processing system according to some embodiments of the present invention.

[0016] Figure 3 shows selected operations in a semiconductor processing method according to some embodiments of the present invention.

[0017] Figures 4A-4B show anatomical views of etched material according to some embodiments of the present invention.

[0018] Several illustrations are included as the subject matter. It will be understood that the illustrations are for illustrative purposes and are not to be regarded as to scale unless explicitly stated otherwise. Furthermore, as the subject matter, the illustrations are provided to aid understanding and may not include all appearances or information compared to real-world representations, and may include exaggerated material for illustrative purposes.

[0019] In the accompanying drawings, similar parts and / or features may have the same element symbols. Furthermore, various parts of the same type may be distinguished by text following the element symbol, which distinguishes similar parts. If only the primary element symbol is used in the specification, this description applies to any similar parts having the same primary element symbol, regardless of the text. Implementation

[0020] Selective etching of silicon nitride (SiN) materials is beneficial in various device processing flows, including the formation of dynamic random access memory (DRAM), FinFETs, and many other devices. SiN can be used as a pad material or barrier material, as an etch-stop material, or as a dielectric material to form insulating film stacks between device circuits. Conventional processes for patterning or removing SiN can utilize halogen precursors or plasma products to etch the SiN. However, these conventional processes have been limited by low selectivity of the SiN material relative to other materials on the substrate. Conventional processes have also suffered from downstream problems due to residues from the presence of halogen precursors. This invention overcomes these limitations by performing a halogen-free etching process that selectively removes SiN using one or more hydrogen precursors. The etching process may include providing hydrogen with one or more inert precursors to soften the material. Furthermore, this invention can utilize low temperatures to achieve extremely high etch selectivity. Furthermore, compared to conventional two-step processes, such as atomic layer etching (ALE) which is required to remove silicon nitride materials, the present invention provides a single-step process for removing silicon nitride materials.

[0021] While the remainder of the disclosure will routinely specify the particular etching processes utilizing the disclosed techniques, it will be readily understood that the system and methods can be equally applied to a variety of other processes, as can occur within the described chambers. Therefore, the invention should not be construed as being limited to use only in the described etching processes. Before describing systems and methods or operations for exemplary processing sequences according to some embodiments of the invention, the disclosure will discuss a possible system and chamber that can be used with the invention. It will be understood that the invention is not limited to the described apparatus, and that the described processes can be performed in any number of processing chambers and systems.

[0022] Figure 1 shows a top plan view of one embodiment of a processing system 10 with deposition, etching, baking, and / or curing chambers according to an embodiment. The tool or processing system 10 depicted in Figure 1 may include a plurality of processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated measurement chamber 28, and a pair of loading gate chambers 16a-b. The processing chambers may include any number of structures or components, and any number or combination of processing chambers.

[0023] To transfer substrates within the chambers, transfer chamber 20 may include a robotic transfer mechanism 22. Transfer mechanism 22 may have a pair of substrate transfer blades 22a, each attached to the distal end of an extendable arm 22b. Blades 22a can be used to carry individual substrates into and out of the processing chambers. In operation, one of the substrate transfer blades of transfer mechanism 22, such as blades 22a, can retrieve substrate W from one of the loading gate chambers, such as chambers 16a-b, and transport substrate W to a first processing stage, for example, the processing steps in chambers 24a-d as described later. Chambers may be included to perform individual or combined operations of the technology. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform preprocessing operations and / or one or more post-processing operations as described above. The invention can cover any number of configurations and can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0024] If a chamber is occupied, the robot can wait until processing is complete and then remove the processed substrate from the chamber using a blade 22a and insert a new substrate using a second blade. Once the substrate has been processed, it is then moved to the second processing stage. For each move, the transfer mechanism 22 typically has one blade carrying the substrate and one blade left empty for substrate exchange. The transfer mechanism 22 can wait in each chamber until the exchange can be completed.

[0025] Once processing is completed within the processing chamber, transfer mechanism 22 can move substrate W from the final processing chamber and transfer substrate W to a cassette within loading gate chambers 16a-b. From loading gate chambers 16a-b, the substrate can be moved into factory interface 12. Factory interface 12 is generally operable to transfer substrates between cassette loaders 14a-d and loading gate chambers 16a-b in a clean atmospheric pressure environment. The clean environment in factory interface 12 can generally be provided through, for example, air filtration treatment (such as HEPA filtration). Factory interface 12 may also include substrate orienters / aligners, which can be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 18a-b, can be positioned in factory interface 12 to transfer substrates between various locations / areas within factory interface 12 and to transfer substrates to other locations communicating with factory interface 12. Robots 18a-b can be configured to travel from a first end to a second end of factory interface 12 along a track system within factory interface 12.

[0026] The processing system 10 may further include an integrated measurement chamber 28 to provide control signals, which can provide suitable control for any processing performed in the processing chamber. The integrated measurement chamber 28 may include any various measuring devices to measure various film properties, such as thickness, roughness, composition, and the measuring devices may further be able to characterize grating parameters, such as critical dimensions, sidewall angles, and feature heights, in an automated manner under vacuum.

[0027] Each processing chamber 24a-d may be configured to perform one or more processing steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations thereof may be used in the multi-chamber processing system 10. For example, any processing chamber may be configured to perform several substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate treatments. Some specific processes that may be performed in any chamber or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. Those skilled in the art will readily appreciate that any other processes may be similarly performed in specific chambers incorporated into the multi-chamber processing system 10, including any processes described below.

[0028] Figure 2 illustrates an anatomical view of an exemplary plasma processing chamber 100 suitable for patterning material layers on a substrate 102 disposed in a plasma processing chamber 100. The exemplary plasma processing chamber 100 is suitable for performing patterning processes; however, it will be understood that the present invention can be performed in any number of chambers, and the substrate support according to the invention can be included in an etching chamber, a deposition chamber, a processing chamber, or any other process chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which the substrate can be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 coupled to a ground 126. The sidewalls 112 may have pads 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and are generally correspondingly larger than the dimensions of the substrate 102 processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter and 450 mm diameter, etc., as well as substrates for displays or solar cells.

[0029] The chamber body 105 may support the chamber cover assembly 110 to enclose the chamber volume 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate access port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 102 into and out of the plasma processing chamber 100. The substrate access port 113 may be coupled to a transfer chamber and / or other chambers of the previously described substrate processing system. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to vent and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0030] Gas distribution plate 160 can be coupled to chamber body 105 via gas line 167 to supply process gas into chamber volume 101. Gas distribution plate 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases, as can be used for any number of processes. Examples of process gases that can be provided by gas distribution plate 160 include, but are not limited to, hydrocarbon gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. In addition, the treated gas may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as any number of additional precursors such as BCl3, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2.

[0031] Valve 166 controls the flow of process gases from sources 161, 162, 163, and 164 of gas distribution disc 160 and can be managed by controller 165. The flow of gas supplied from gas distribution disc 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be used to guide process gases from sources 161, 162, 164, and 163 of gas distribution disc 160 into chamber volume 101. After the process gases are introduced into plasma processing chamber 100, the gases may be energized to form plasma. Antenna 148, such as one or more inductor coils, may be provided adjacent to plasma processing chamber 100. Antenna power supply 142 may power antenna 148 through matching circuit 141 to inductively couple energy, such as RF energy, to the process gases to maintain the plasma formed by the process gases in chamber volume 101 of plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, processing electrodes below and / or above the substrate 102 may be used to capacitively couple RF power to the processing gas to retain plasma within the chamber volume 101. The operation of the antenna power supply 142 may be controlled by a controller, such as controller 165, which also controls the operation of other components in the plasma processing chamber 100.

[0032] A substrate support pedestal 135 may be disposed within chamber volume 101 to support substrate 102 during processing. The substrate support pedestal 135 may include an electrostatic clamp 122 for holding substrate 102 during processing. The electrostatic clamp ("ESC") 122 may use electrostatic attraction to hold substrate 102 to substrate support pedestal 135. ESC 122 may be powered by an RF power supply 125 integrated with matching circuitry 124. ESC 122 may include electrodes 121 embedded within a dielectric body. Electrodes 121 may be coupled to the RF power supply 125 and may provide bias to ESC 122 and substrate 102 situated on the pedestal, the bias attracting plasma ions formed by processing gases in chamber volume 101. The RF power supply 125 may cycle on and off, or pulse, during processing of substrate 102. ESC 122 may have an isolator 128 to reduce plasma attraction on the sidewalls of ESC 122, thereby extending the maintenance life of ESC 122. Additionally, the substrate support pedestal 135 may have a cathode pad 136 to protect the sidewalls of the substrate support pedestal 135 from plasma gas and extend the time between maintenance of the plasma processing chamber 100.

[0033] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide a clamping voltage of about 200 volts to about 2000 volts to electrode 121. Power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing DC current to electrode 121 for clamping and releasing substrate 102. ESC 122 may include a heater disposed within a pedestal and connected to the power supply for heating the substrate, and cooling substrate 129 supporting ESC 122 may include conduits for circulating heat transfer fluid to maintain the temperature of ESC 122 and substrate 102 disposed thereon. ESC 122 may be configured to perform within the temperature range required by the thermal budget of the apparatus manufactured on substrate 102. For example, ESC 122 may be configured to maintain substrate 102 at a temperature of about -150°C or lower to about 500°C or higher, depending on the process performed.

[0034] A cooling substrate 129 may be provided to help control the temperature of the substrate 102. To mitigate process drift and time, the temperature of the substrate 102 can be maintained substantially constant during the time the substrate 102 is in the chamber by means of the cooling substrate 129. In some embodiments, the temperature of the substrate 102 may be maintained between about -150°C and about 500°C during subsequent processing, however any temperature may be used. A cover ring 130 may be disposed on the ESC 122 and around the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of the substrate 102, while shielding the top surface of the substrate support pedestal 135 from the plasma environment within the plasma processing chamber 100. Lifting pins may be selectively adjusted through the substrate support pedestal 135 to lift the substrate 102 above the substrate support pedestal 135 to facilitate access to the substrate 102 by means of a transfer robot or other suitable transfer mechanism described above.

[0035] The controller 165 can be used to control the processing sequence, regulate the gas flow from the gas distribution disk 160 into the plasma processing chamber 100, and other processing parameters. When executed by the CPU, the software routine transforms the CPU into a dedicated computer, such as a controller, which can control the plasma processing chamber 100 so that processing is performed according to the invention. The software routine can also be stored and / or executed by a second controller, which can be associated with the plasma processing chamber 100.

[0036] The previously discussed chambers can be used to perform exemplary methods, including etching methods. Turning to Figure 3 shows an exemplary operation in method 300 according to an embodiment of the invention. Method 300 may include one or more operations prior to the commencement of this method, including front-end processes, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to said operations. Method 300 may include several optional operations that may or may not be explicitly related to some embodiments of the method according to an embodiment of the invention. For example, many operations are illustrated to provide a broader scope of the processing performed, but are not critical to the invention, or may be performed by alternative methods that will be discussed further later. The operations of method 300 are illustrated in Figures 4A-4B, which are illustrated in connection with the operations of method 300. It will be understood that the illustrations show only partial schematic views, and the substrate may contain any number of additional materials and features with various properties and states as illustrated in the figures.

[0037] Method 300 may include or exclude optional operations to develop the semiconductor structure to a specific manufacturing operation. It will be understood that method 300 can be performed on any number of semiconductor structures 400 or substrates 405, as shown in Figure 4A, including exemplary structures on which silicon and nitrogen-containing material removal operations can be performed. Exemplary semiconductor structures may include trenches, vias, or other recessed features, which may include one or more exposed materials. For example, an exemplary substrate may contain silicon or some other semiconductor substrate material and interlayer dielectric material, through which recesses, trenches, vias, or isolation structures may be formed. The exposed material at any point in time during the etching process may be or include one or more dielectric materials, contact materials, transistor materials, or any other materials that can be used in semiconductor processing.

[0038] For example, as shown in Figure 4A, a first material layer 410 may cover a substrate 405. The substrate 405 may be any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials, which may be the substrate 405 or the material formed in structure 400. In structure 400 shown in Figure 4A, the first material layer 410 may be a silicon-containing material, such as silicon. The first material layer 410 may be patterned to form one or more features. The aspect ratio of the height to the width of the one or more features may be greater than or about 2:1, greater than or about 3:1, greater than or about 5:1, greater than or about 10:1, greater than or about 20:1, or greater. A second material layer 415 may cover the first material layer 410. The second material layer 415 may also be a silicon-containing material, such as silicon oxide. A silicon and nitrogen-containing material layer 420 may cover a second material layer 415. The silicon and nitrogen-containing material layer 420 may be silicon nitride. The second material layer 415 and the silicon and nitrogen-containing material layer 420 may extend into one or more features defined by the first material layer 410. It will be understood that any number of additional materials may be formed in the illustrated structure 400. It will be understood that the specified structures are not intended to be limiting, and any variety of other semiconductor structures are similarly covered. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which silicon and nitrogen-containing materials such as silicon nitride are removed relative to one or more other materials, as the present invention may selectively remove silicon and nitrogen-containing materials relative to other exposed materials such as silicon-containing materials and any other materials discussed elsewhere. Furthermore, while high aspect ratio structures can benefit from the present invention, the present invention can also be applied to lower aspect ratios and any other structures.

[0039] Method 300 may include providing one or more precursors into a processing region of a semiconductor processing chamber housing the substrate 405 in operation 305. The one or more precursors may include hydrogen-containing precursors and / or inert precursors. Plasma effluent from one or more precursors may be formed in operation 310. In embodiments, one or more precursors may flow through a distal plasma region of the processing chamber, such as region 215 described above, and plasma from one or more precursors may be formed to produce plasma effluent. While substrate-level plasma may be generated, in some embodiments, the plasma may be distal plasma, which may protect exposed substrate material from ion bombardment that would occur due to substrate-level plasma. In operation 315, whether plasma-enhanced or not, one or more precursors and their plasma effluent may contact the substrate 405, including the exposed silicon and nitrogen-containing material layer 420. This contact may etch a portion of the silicon and nitrogen-containing material layer 420.

[0040] As previously discussed, the precursors used during method 300 and provided in operation 305 may include hydrogen-containing precursors and / or inert precursors. For example, non-limiting hydrogen-containing precursors may include diatomic hydrogen (H2), water (H2O), ammonia (NH3), or any other hydrogen-containing precursor. Exemplary inert precursors in some embodiments may include one or more of argon, xenon, or helium, and any other non-reactive material. In embodiments, the flow rate of the inert precursor may be greater than the flow rate of the hydrogen-containing precursor. For example, the flow rate ratio of the inert precursor to the hydrogen-containing precursor may be greater than or about 2:1, and the flow rate ratio of the inert precursor to the hydrogen-containing precursor may be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35:1, or higher. The increased flow rate of the inert precursor can dilute the hydrogen-containing precursor, which can control the etching rate of the silicon and nitrogen-containing material layer 420. In addition, the inert precursor can bombard the silicon and nitrogen-containing material layer 420, which can soften the material for etching.

[0041] In embodiments, one or more precursors may not include halogen-containing precursors, and the treatment zone may remain halogen-free during method 300. Although conventional techniques have utilized halogen materials for etching nitrogen-containing materials, such as silicon- and nitrogen-containing materials, the present invention does not require halogen materials. Instead, the present invention can remove nitrogen-containing materials, such as silicon- and nitrogen-containing materials, as a halogen-free method while maintaining high selectivity. Furthermore, the present invention can thus reduce and / or avoid the formation of halogen residues, the presence of which can cause problems in downstream processing.

[0042] Plasma effluent can be formed at high plasma power to increase gas density and provide increased dissociation of hydrogen-containing precursors to form more hydrogen-containing plasma effluent to react with the silicon and nitrogen-containing material layer 420. In some embodiments, plasma effluent can be formed at greater than or about 800 W, and at greater than or about 900 W, greater than or about 1,000 W, greater than or about 1,250 W, greater than or about 1,500 W, greater than or about 1,750 W, greater than or about 2,000 W, greater than or about 2,500 W, greater than or about 3,000 W, greater than or about 3,500 W, greater than or about 4,000 W, greater than or about 4,500 W, greater than or about 5,000 W, or greater. At lower plasma power, hydrogen dissociation is reduced, and the etching rate of the silicon and nitrogen-containing material layer 420 can be reduced.

[0043] Plasma effluents containing hydrogen precursors can be characterized by high gas density while maintaining low plasma potential energy. For example, the plasma potential energy of plasma effluents containing hydrogen precursors can be less than or about 5.0 eV, and can be less than or about 4.9 eV, less than or about 4.8 eV, less than or about 4.7 eV, less than or about 4.6 eV, less than or about 4.5 eV, less than or about 4.4 eV, less than or about 4.3 eV, less than or about 4.2 eV, less than or about 4.1 eV, less than or about 4.0 eV, less than or about 3.9 eV, less than or about 3.8 eV, less than or about 3.7 eV, less than or about 3.6 eV, less than or about 3.5 eV, or even lower.

[0044] As shown in Figure 4B, this contact can etch the silicon and nitrogen-containing material layer 420. Although illustrated as removing the entire silicon and nitrogen-containing material layer 420, method 300 can also be controlled to remove a portion of the silicon and nitrogen-containing material layer 420. By contacting the silicon and nitrogen-containing material layer 420 with an inert precursor and / or a hydrogen-containing precursor, or a plasma effluent of the aforementioned, the Si-N bonds in the silicon and nitrogen-containing material layer 420 can be disrupted. This contact and the resulting disruption of the Si-N bonds can form volatile byproducts such as silane (SiH4) and / or ammonia (NH3). During the contact, due to differences in bond energy, at least a portion of the silicon and nitrogen-containing material layer 420 can be selectively etched relative to other materials on the substrate 405, such as a second material layer 415, which may be silicon oxide. The Si-N bonds in the silicon and nitrogen-containing material layer 420 can be characterized as having a bond energy of approximately 3.5 eV, while the Si-O bonds in the second material layer 415 can be characterized as having a bond energy of approximately 4.5 eV. Therefore, by maintaining the plasma potential energy of the hydrogen-containing precursor at the previously discussed values, the Si-N bonds in the silicon and nitrogen-containing material layer 420 can be selectively disrupted compared to the Si-O bonds in the second material layer 415.

[0045] Processing conditions can influence and promote etching according to the invention. For example, the temperature at which the operation is performed affects the extent to which the reaction is inventable. Lower temperatures promote the reaction and high selectivity during contact between silicon-containing and nitrogen-containing material layers and hydrogen-containing precursors or their plasma effluents. Therefore, in some embodiments of the invention, method 300 can be performed at substrate temperatures, stage temperatures, and / or chamber temperatures of less than or about 50 °C, and at temperatures of less than or about 25 °C, less than or about 0 °C, less than or about -25 °C, less than or about -50 °C, less than or about -75 °C, less than or about -100 °C, or lower. Temperatures can also be maintained at any temperature within these ranges, within a smaller range covered by these ranges, or between any of these ranges.

[0046] The pressure within the processing zone of the semiconductor processing chamber also affects the performed operation. To facilitate etching and removal of byproducts, the processing pressure can be less than or about 100 mTorr, and can be maintained at less than or about 80 mTorr, less than or about 60 mTorr, less than or about 40 mTorr, less than or about 20 mTorr, less than or about 15 mTorr, less than or about 10 mTorr, less than or about 8 mTorr, less than or about 6 mTorr, less than or about 4 mTorr, less than or about 3 mTorr, or even lower. The pressure can also be maintained at any pressure within these ranges, within a smaller range encompassed by these ranges, or between any of these ranges.

[0047] By performing the above-described process, the etching rate of silicon nitride can be greater than or about 1.0 Å / min, greater than or about 1.5 Å / min, greater than or about 2.0 Å / min, greater than or about 2.5 Å / min, greater than or about 3.0 Å / min, greater than or about 3.5 Å / min, greater than or about 4.0 Å / min, greater than or about 4.5 Å / min, greater than or about 5.0 Å / min, greater than or about 5.5 Å / min, or greater. Similarly, selective etching of silicon-nitrogen materials relative to existing materials such as silicon or silicon- and oxygen-containing materials can be maintained at a ratio greater than or about 5:1, and selective etching can be maintained at ratios greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35:1, greater than or about 40:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, or greater. In embodiments, existing materials such as silicon or silicon- and oxygen-containing materials may not be etched during the removal of silicon- and nitrogen-containing materials.

[0048] In the preceding description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details, and with the addition of these additional details.

[0049] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, certain well-known treatments and elements have not been described to avoid unnecessarily obscuring the invention. Therefore, the above description should not be construed as limiting the scope of the invention.

[0050] Where numerical ranges are provided, unless the context clearly indicates otherwise, each intermediate value, understood to be the smallest unit between the upper and lower limits of the range, is also explicitly disclosed. Narrower ranges between any stated or unstated intermediate values ​​within the stated range, and any other stated or intermediate value within the stated range, are also included. The upper and lower limits of those smaller ranges may be independently included or excluded from the range, and the invention also includes each range in which any limit value is included, none are included, or both are included, depending on any explicitly excluded limit value in the stated range. Where a stated range includes one or both limit values, ranges excluding either or both of those included limit values ​​are also included.

[0051] When used herein and in the claims of the appended patent applications, the singular forms “a”, “an”, and “the” include the plural forms unless the context clearly indicates otherwise. Thus, for example, “a precursor” includes a plurality of such precursors, and “the layer” includes one or more layers and equivalents known to those usually skilled in the art, and so on.

[0052] Furthermore, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and the following claims, are intended to indicate the presence of a descriptive feature, integral, component, or operation, but do not exclude the presence or addition of one or more other features, integrals, components, operations, actions, or groups.

[0053] 10: Processing System 12: Factory Interface 14a, 14b, 14c, 14d: Cabin Loaders 16a, 16b: Loading gate chamber 18a, 18b: Robots 20: Transfer chamber 22: Conveying mechanism 22a: Blade 22b: Extendable arm 24a, 24b, 24c, 24d: Processing chambers 26: Service Chamber 28: Integrated Measurement Chamber 100: Plasma treatment chamber 101: Chamber volume 102:Substrate 105: Main body of the chamber 110: Cover assembly 112: Sidewall 113: Substrate access port 114: Nozzle 115: Padding 118: Bottom 121: Electrode 122: Electrostatic clamp ("ESC") 124: Matching Circuit 125: RF power supply 126: Grounding 128: Isolator 129: Cooling substrate 130: Coverage ring 135:Substrate support base 136: Cathode pad 141: Matching Circuit 142: Antenna power supply 145: Pumping Port 148: Antenna 150: Power Supply 160: Gas distribution plate 161, 162, 163, 164: Source 165: Controller 166: Valve 167: Gas Circuit 300: Method 305, 310, 315: Operations 400: Structure 405:Substrate 410: First material layer 415: Second material layer 420: Silicon and nitrogen-containing material layer W: substrate

Claims

1. A semiconductor processing method comprising the steps of: providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, and wherein a silicon- and nitrogen-containing material layer is disposed on the substrate; forming a plasma effluent of the hydrogen-containing precursor; and contacting the silicon- and nitrogen-containing material layer with the plasma effluent of the hydrogen-containing precursor, wherein the contact etches a portion of the silicon- and nitrogen-containing material layer, wherein the processing region is maintained as halogen-free.

2. The semiconductor processing method as described in claim 1, wherein the hydrogen-containing precursor comprises diatomic hydrogen (H2).

3. The semiconductor processing method as described in claim 1, wherein a silicon-oxygen material layer, a silicon-containing material layer, or the silicon-oxygen material layer and the silicon-containing material layer are disposed on the substrate.

4. The semiconductor processing method as described in claim 1 further includes the following step: providing an inert precursor and the hydrogen-containing precursor to the processing region.

5. The semiconductor processing method as described in claim 4, wherein the flow rate of the inert precursor is greater than the flow rate of the hydrogen-containing precursor.

6. The semiconductor processing method as claimed in claim 1, wherein the plasma effluent is formed at a plasma power greater than or about 800 W.

7. The semiconductor processing method as claimed in claim 1, wherein the plasma effluent is formed at a plasma power greater than or about 2,000 W.

8. The semiconductor processing method as claimed in claim 1, wherein the contact is formed with silane (SiH4), ammonia (NH3), or silane (SiH4) and ammonia (NH3).

9. The semiconductor processing method as claimed in claim 1, wherein the substrate is characterized by a temperature less than or about 50 °C.

10. The semiconductor processing method as claimed in claim 1, wherein the substrate is characterized by a temperature less than or about -25 °C.

11. The semiconductor processing method as claimed in claim 1, wherein a pressure within the semiconductor processing chamber is maintained at less than or about 100 mTorr.

12. The semiconductor processing method as claimed in claim 1, wherein the contact is etched at an etch rate greater than or about 1 Å / min to the silicon and nitrogen-containing material layer.

13. A semiconductor processing method comprising the steps of: providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a silicon-oxygen material layer is disposed on the substrate, and wherein a silicon-nitrogen material layer is disposed on the silicon-oxygen material layer; forming a plasma effluent of the hydrogen-containing precursor, wherein the plasma effluent is formed at a plasma power greater than or about 1,000 W; and contacting the silicon-nitrogen material layer with the plasma effluent of the hydrogen-containing precursor, wherein the contact selectively etches a portion of the silicon-nitrogen material layer relative to the silicon-oxygen material layer, wherein the processing region remains halogen-free.

14. The semiconductor processing method as described in claim 13, wherein the substrate is characterized by a temperature less than or about 50 °C.

15. A semiconductor processing method comprising the steps of: providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed on a substrate support within the processing region, wherein a silicon-oxygen material layer is disposed on the substrate, and wherein a silicon-nitrogen material layer is disposed on the silicon-oxygen material layer; forming a plasma effluent of the hydrogen-containing precursor; and contacting the silicon-nitrogen material layer with the plasma effluent of the hydrogen-containing precursor, wherein the contact selectively etches a portion of the silicon-nitrogen material layer relative to the silicon-oxygen material layer, and wherein the substrate is characterized by a temperature less than or about -50 °C, wherein the processing region is maintained as halogen-free.

16. The semiconductor processing method as described in claim 15 further comprises the step of: providing helium and the hydrogen-containing precursor to the processing region.

17. The semiconductor processing method as claimed in claim 15, wherein the plasma effluent is formed at a plasma power greater than or about 1,000 W.

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