Semiconductor device and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor device includes forming a substrate region, a source region, and a contact region in a silicon carbide substrate, wherein the substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region; forming an amorphous silicon layer on the top surface of the silicon carbide substrate, such that the substrate region and the source region are covered by the amorphous silicon layer; doping a plurality of N-type dopants in the amorphous silicon layer; crystallizing the amorphous silicon layer to form a polycrystalline silicon layer; oxidizing the upper part of the polycrystalline silicon layer, such that the upper part of the polycrystalline silicon layer defines an oxide layer, and the lower part of the polycrystalline silicon layer defines a channel layer, wherein the thickness of the oxide layer is greater than or equal to the thickness of the channel layer; and forming a gate layer on the oxide layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Prior Technology

[0002] Silicon carbide (SiC) is a high-hardness semiconductor material with a larger bandgap compared to silicon (Si). Silicon carbide can be used in various semiconductor devices, including power components, environmentally resistant components, high-temperature operating components, and high-frequency components, offering advantages such as reduced power loss. Due to these properties, silicon carbide power devices can be made in semiconductor devices with smaller dimensions than silicon power devices.

[0003] The gate structure of a metal-oxide-semiconductor field-effect transistor (MOSFET) consists of a metal layer, an oxide layer, and a semiconductor layer (channel layer) from top to bottom. Silicon carbide substrates can replace traditional silicon substrates. Generally, the channel layer on a silicon carbide substrate is formed by directly oxidizing the surface of the silicon carbide substrate and then annealing it by introducing nitric oxide (NO) or nitrous oxide (N₂O). However, this conventional process and structure cannot improve the problem of poor interfacial mobility (i.e., transistor channel mobility) at the silicon carbide-silicon dioxide (SiO₂) interface. Summary of the Invention

[0004] According to some embodiments disclosed herein, a semiconductor device includes a silicon carbide substrate, a channel layer, an oxide layer, and a gate layer. The silicon carbide substrate has a substrate region, a source region, and a contact region therein. The substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region. The channel layer is located on a first top surface of the silicon carbide substrate and covers a first portion of the substrate region and the source region. The oxide layer is in direct contact with a second top surface of the channel layer. The thickness of the oxide layer is greater than or equal to the thickness of the channel layer. The gate layer is located on the oxide layer.

[0005] In some embodiments, the semiconductor device further includes an interlayer dielectric layer. The interlayer dielectric layer covers a second portion of the gate layer and the source region, and directly contacts the first sidewall of the oxide layer and the second sidewall of the channel layer.

[0006] In some embodiments, the semiconductor device further includes a metal layer. The metal layer is located on the interlayer dielectric layer and extends through the source region to connect to the contact region.

[0007] In some embodiments, the semiconductor device further includes a drain layer. The drain layer is located on the bottom surface of the silicon carbide substrate.

[0008] In some embodiments, the material of the channel layer is polycrystalline silicon.

[0009] According to some embodiments disclosed herein, a method for manufacturing a semiconductor device includes forming a substrate region, a source region, and a contact region in a silicon carbide substrate, wherein the substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region; forming an amorphous silicon layer on the top surface of the silicon carbide substrate, such that the substrate region and the source region are covered by the amorphous silicon layer; doping a plurality of N-type dopants in the amorphous silicon layer; crystallizing the amorphous silicon layer to form a polycrystalline silicon layer; oxidizing the upper part of the polycrystalline silicon layer, such that the upper part of the polycrystalline silicon layer defines an oxide layer, and the lower part of the polycrystalline silicon layer defines a channel layer, wherein the thickness of the oxide layer is greater than or equal to the thickness of the channel layer; and forming a gate layer on the oxide layer.

[0010] In some embodiments, the above-mentioned matrix formation system is formed by doping a silicon carbide substrate with a P-type dopant.

[0011] In some embodiments, the aforementioned N-type dopant in the amorphous silicon layer is applied at a dose ranging from 1e15 cm⁻³ to 1e17 cm⁻³. Crystallization of the amorphous silicon layer involves subjecting the amorphous silicon layer to excimer laser annealing. Oxidation of the upper portion of the polycrystalline silicon layer is achieved by oxidizing the upper portion of the polycrystalline silicon layer at a temperature ranging from 750°C to 900°C.

[0012] In some embodiments, after forming the gate layer on the oxide layer, the method of manufacturing the semiconductor device further includes: etching the oxide layer and the channel layer on the source region, such that the channel layer covers a first portion of the source region, while exposing the first portion that is not the source region; forming an interlayer dielectric layer covering a second portion of the gate layer and the source region, such that the interlayer dielectric layer directly contacts a first sidewall of the oxide layer and a second sidewall of the channel layer; etching the source region on the contact region, exposing the contact region; and forming a metal layer on the interlayer dielectric layer and extending through the source region to connect to the contact region.

[0013] In some embodiments, before forming the substrate region, source region and contact region in the silicon carbide substrate, the method for manufacturing the semiconductor device further includes forming a drain layer on the bottom surface of the silicon carbide substrate.

[0014] In the above-disclosed embodiment, the semiconductor device is manufactured by first forming an amorphous silicon layer on the top surface of a silicon carbide substrate, then doping the amorphous silicon layer with multiple N-type dopants, and finally crystallizing the amorphous silicon layer to form a polycrystalline silicon layer. Therefore, an oxide layer can be formed by oxidizing the upper part of the polycrystalline silicon layer, and the lower part of the polycrystalline silicon layer serves as a channel layer. In subsequent processes, a gate layer can be formed on the oxide layer, making the oxide layer the gate dielectric layer. In other words, the stacked oxide layer and channel layer are formed from the amorphous silicon layer, effectively improving the channel mobility of this semiconductor device and addressing the problem of poor interface mobility at the conventional silicon carbide-silicon dioxide interface. Simple Explanation of the Diagram

[0015] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying illustrations and by the embodiments described below. Note that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation. Figure 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 2 illustrates a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figures 3 through 8 illustrate cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of this disclosure at an intermediate stage. Implementation

[0016] The following disclosure of embodiments provides many different implementations, or examples, for carrying out different features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0017] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0018] Figure 1 illustrates a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a silicon carbide (SiC) substrate 110, a channel layer 120, an oxide layer 130, and a gate layer 140. The silicon carbide substrate 110 has a substrate region 112, a source region 114, and a contact region 116 therein. The substrate region 112 covers the source region 114 and the contact region 116, and the contact region 116 is connected to the bottom of the source region 114. In some embodiments, the substrate region 112 and the contact region 116 may be P-type, and the source region 114 may be N-type. The channel layer 120 is located on a first top surface 111 of the silicon carbide substrate 110, and the channel layer 120 covers a first portion 115a of the substrate region 112 and the source region 114. The oxide layer 130 is in direct contact with a second top surface 121 of the channel layer 120. The oxide layer 130 and the channel layer 120 may overlap in the vertical direction. Furthermore, the thickness of the oxide layer 130 is greater than or equal to the thickness of the channel layer 120. In some embodiments, the thicknesses H of the oxide layer 130 and the channel layer 120 are in the range of 50 nm to 100 nm, and the thickness h of the oxide layer 130 is in the range of 25 nm to 60 nm. A gate layer 140 is located on the oxide layer 130.

[0019] In some embodiments, the channel layer 120 is made of polysilicon, and the gate layer 140 is a polysilicon gate. The oxide layer 130 is the gate dielectric layer. The semiconductor device 100 is a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) with an embedded polysilicon channel diode (PCD). Furthermore, the semiconductor device 100 can be a power device, applicable to fields such as vehicles (e.g., electric vehicles) and solar inverters.

[0020] The oxide layer 130 and channel layer 120 of the semiconductor device 100 are formed from the upper and lower parts of a single amorphous silicon layer, respectively (described later). The thickness and H of the oxide layer 130 and channel layer 120 are in the range of 50 nanometers to 100 nanometers, and the thickness h of the oxide layer 130 is in the range of 25 nanometers to 60 nanometers. The above design can effectively improve the channel mobility of the semiconductor device 100 and improve the problem of poor interface mobility of traditional silicon carbide and silicon dioxide.

[0021] In some embodiments, the semiconductor device 100 further includes an interlayer dielectric layer 150 and a metal layer 160. The interlayer dielectric layer 150 covers the gate layer 140 and a second portion 115b of the source region 114, and directly contacts the first sidewall 131 of the oxide layer 130 and the second sidewall 122 of the channel layer 120. The metal layer 160 is located on the interlayer dielectric layer 150 and extends through the source region 114 to connect to the contact region 116. Furthermore, the semiconductor device 100 may also include a drain layer 170. The drain layer 170 is located on the bottom surface of the silicon carbide substrate 110.

[0022] It should be understood that the component connections, materials, and functions already described will not be repeated, but will be stated in the preceding text. The following description will explain the manufacturing method of the semiconductor device 100.

[0023] Figure 2 illustrates a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. First, in step S1, a substrate region, a source region, and a contact region are formed in a silicon carbide substrate, wherein the substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region. Next, in step S2, an amorphous silicon layer is formed on the top surface of the silicon carbide substrate, such that the substrate region and the source region are covered by the amorphous silicon layer. Then, in step S3, a plurality of N-type dopants are doped into the amorphous silicon layer. Next, in step S4, the amorphous silicon layer is crystallized to form a polycrystalline silicon layer. Then, in step S5, the upper portion of the polycrystalline silicon layer is oxidized, such that the upper portion of the polycrystalline silicon layer defines an oxide layer, and the lower portion of the polycrystalline silicon layer defines a channel layer, wherein the thickness of the oxide layer is greater than or equal to the thickness of the channel layer. Subsequently, in step S6, a gate layer is formed on the oxide layer.

[0024] Each of steps S1 to S6 may include a plurality of detailed steps, and the method for manufacturing this semiconductor device may also include other steps between step S1 and step S6, other steps before step S1, and other steps after step S6. Steps S1 to S6 will be described in detail in the following description.

[0025] Figures 3 through 8 illustrate cross-sectional views of an intermediate stage in a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Referring to Figure 3, a substrate region 112, a source region 114, and a contact region 116 are formed in a silicon carbide substrate 110. The substrate region 112 is formed by doping the silicon carbide substrate 110 with a p-type dopant (such as aluminum or boron) and performing a high-temperature (such as 1700°C) annealing step. In some embodiments, the substrate region 112 is doped with a p-type dopant in the range of 1e16 cm⁻³ to 1e18 cm⁻³. The source region 114 may be formed by implanting n-type ions (such as nitrogen), and the contact region 116 may be formed by implanting p-type ions (such as aluminum). Furthermore, before the substrate region 112, the source region 114, and the contact region 116 are formed in the silicon carbide substrate 110, the drain layer 170 may be formed on the bottom surface of the silicon carbide substrate 110.

[0026] Referring to Figure 4, an amorphous silicon layer 120a is then formed on the first top surface 111 of the silicon carbide substrate 110, covering the substrate region 112 and the source region 114. In some embodiments, the thickness H of the amorphous silicon layer 120a is in the range of 50 nanometers to 100 nanometers. Furthermore, the amorphous silicon layer 120a can be formed by deposition, such as chemical vapor deposition (CVD).

[0027] Referring to Figure 5, after the amorphous silicon layer 120a is formed, a plurality of N-type dopants can be doped into the amorphous silicon layer 120a. In some embodiments, the amorphous silicon layer 120a is doped with an N-type dopant in a dose ranging from 1e15 cm⁻³ to 1e17 cm⁻³. The N-type dopant may be, for example, phosphorus or arsenic. After doping the amorphous silicon layer 120a with N-type dopants, the amorphous silicon layer 120a can be crystallized to form a polycrystalline silicon layer 120b. Crystallization of the amorphous silicon layer 120a can be achieved by subjecting the amorphous silicon layer 120a to excimer laser annealing.

[0028] Referring to Figures 5 and 6, after the polycrystalline silicon layer 120b is formed, its upper portion can be oxidized to define an oxide layer 130, while the lower portion remains unoxidized, defining a channel layer 120. In other words, the channel layer 120 in Figure 6 is the lower portion of the polycrystalline silicon layer 120b in Figure 5, and the oxide layer 130 in Figure 6 is formed by oxidizing the upper portion of the polycrystalline silicon layer 120b in Figure 5. The thickness of the oxide layer 130 is greater than or equal to the thickness of the channel layer 120. In some embodiments, the thickness of the oxide layer 130 is in the range of 25 nm to 60 nm, and the combined thickness of the oxide layer 130 and the channel layer 120, H, is in the range of 50 nm to 100 nm. In the step of oxidizing the upper part of the polycrystalline silicon layer 120b, the upper part of the polycrystalline silicon layer 120b can be oxidized at a temperature in the range of 750°C to 900°C, which is a low-temperature oxidation process.

[0029] Specifically, since the manufacturing method of this semiconductor device is to first form an amorphous silicon layer 120a on the first top surface 111 of the silicon carbide substrate 110, then dop a plurality of N-type dopants in the amorphous silicon layer 120a, and crystallize the amorphous silicon layer 120a to form a polycrystalline silicon layer 120b, an oxide layer 130 can be formed by oxidizing the upper part of the polycrystalline silicon layer 120b, and the lower part of the polycrystalline silicon layer 120b serves as a channel layer 120.

[0030] Referring to Figure 7, after the oxide layer 130 is formed, a gate layer 140 can be formed on the oxide layer 130. In some embodiments, the gate layer 140 is made of polycrystalline silicon.

[0031] Referring to Figure 8, after the gate layer 140 is formed on the oxide layer 130, the oxide layer 130 and the channel layer 120 on the source region 114 can be etched, so that the channel layer 120 covers the first portion 115a of the source region 114, while exposing the first portion 115a that is not the source region 114, for example, exposing the second portion 115b of the source region 114. The oxide layer 130 can serve as the gate dielectric layer. Next, an interlayer dielectric layer 150 can be formed to cover the gate layer 140 and the second portion 115b of the source region 114, so that the interlayer dielectric layer 150 directly contacts the first sidewall 131 of the oxide layer 130 and the second sidewall 122 of the channel layer 120. Then, the source region 114 on the contact region 116 is etched, exposing the contact region 116, thus obtaining the structure shown in Figure 8.

[0032] Referring to Figure 8 and Figure 1, after the structure in Figure 8 is formed, a metal layer 160 can be formed on the interlayer dielectric layer 150, and the metal layer 160 passes through the source region 114 and connects to the contact region 116, thereby obtaining the semiconductor device 100 in Figure 1.

[0033] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

[0034] 100: Semiconductor devices 110: Silicon carbide substrate 111: First top surface 112:Matrix area 114: Source Region 115a: Part 1 115b: Part Two 116: Contact Area 120: Channel Layer 120a: Amorphous silicon layer 120b: Polycrystalline silicon layer 121: Second top surface 122: Second sidewall 130: Oxide layer 131: First sidewall 140: Gate layer 150: Interlayer dielectric layer 160: Metal layer 170: Basal layer H: Thickness, thickness and h: thickness S1, S2, S3, S4, S5, S6: Steps

[0035] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: A silicon carbide substrate having a substrate region, a source region, and a contact region, wherein the substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region; a channel layer located on a first top surface of the silicon carbide substrate, and the channel layer covering a first portion of the substrate region and the source region; an oxide layer in direct contact with a second top surface of the channel layer, wherein the thickness of the oxide layer is greater than or equal to the thickness of the channel layer, the channel layer and the oxide layer are defined by the same polycrystalline silicon layer, wherein the polycrystalline silicon layer is formed by crystallization of an amorphous silicon layer, an upper portion of the polycrystalline silicon layer defines the oxide layer, the material of the oxide layer including silicon oxide, and a lower portion of the polycrystalline silicon layer defines the channel layer, the material of the channel layer including polycrystalline silicon; and a gate layer located on the oxide layer.

2. The semiconductor device as described in claim 1, further comprising: An inter-dielectric layer covers a second portion of the gate layer and the source region, and directly contacts a first sidewall of the oxide layer and a second sidewall of the channel layer.

3. The semiconductor device as described in claim 2, further comprising: A metal layer is located on the interlayer dielectric layer and is connected to the contact region through the source region.

4. The semiconductor device as described in claim 1, further comprising: A bottom layer is located on the bottom surface of the silicon carbide substrate.

5. A method for manufacturing a semiconductor device, comprising: A substrate region, a source region, and a contact region are formed in a silicon carbide substrate, wherein the substrate region covers the source region and the contact region, and the contact region is connected to the bottom of the source region; an amorphous silicon layer is formed on the top surface of the silicon carbide substrate, such that the substrate region and the source region are covered by the amorphous silicon layer; a plurality of N-type dopants are doped in the amorphous silicon layer; the amorphous silicon layer is crystallized to form a polycrystalline silicon layer; an upper portion of the polycrystalline silicon layer is oxidized, such that the upper portion of the polycrystalline silicon layer defines an oxide layer, and a lower portion of the polycrystalline silicon layer defines a channel layer, wherein the thickness of the oxide layer is greater than or equal to the thickness of the channel layer; and a gate layer is formed on the oxide layer.

6. A method for manufacturing a semiconductor device as claimed in claim 5, wherein the substrate system is formed by doping the silicon carbide substrate with a P-type dopant.

7. A method of manufacturing a semiconductor device as claimed in claim 5, wherein doping the amorphous silicon layer with the N-type dopants is performed by doping the amorphous silicon layer with the N-type dopants in a dose ranging from 1e15 cm⁻³ to 1e17 cm⁻³, wherein crystallizing the amorphous silicon layer is performed by excimer laser annealing the amorphous silicon layer, and wherein oxidizing the upper portion of the polycrystalline silicon layer is performed by oxidizing the upper portion of the polycrystalline silicon layer at a temperature ranging from 750°C to 900°C.

8. A method for manufacturing a semiconductor device as claimed in claim 5, wherein after forming the gate layer on the oxide layer, the method further comprises: The oxide layer and the channel layer on the source region are etched so that the channel layer covers a first portion of the source region, while exposing the first portion that is not the source region; an interlayer dielectric layer is formed to cover a second portion of the gate layer and the source region, so that the interlayer dielectric layer directly contacts a first sidewall of the oxide layer and a second sidewall of the channel layer; the source region on the contact region is etched to expose the contact region; and a metal layer is formed on the interlayer dielectric layer and extends through the source region to connect to the contact region.

9. A method for manufacturing a semiconductor device as claimed in claim 5, wherein before forming the substrate region, the source region, and the contact region in the silicon carbide substrate, the method further comprises: An electrode layer is formed on the bottom surface of the silicon carbide substrate.

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