Semiconductor memory devices and heating methods for semiconductor memory devices

Abstract

One embodiment provides a semiconductor memory device that can extend product lifespan and a heating method for the semiconductor memory device. The semiconductor memory device of one embodiment includes a substrate, a sealing member, a first memory chip, and non-signal wiring. The non-signal wiring is disposed on one or more of the surface of the sealing member, the interior of the sealing member, a first surface of the substrate, the interior of the substrate, or the surface of the first memory chip, and overlaps with the first memory chip when viewed from a first direction. The non-signal wiring has: a first end electrically connected to a power supply unit; a second end electrically connected to a ground wire; and a wiring body connecting the first end and the second end. The wiring body includes: a first portion extending along a second direction intersecting the first direction; a second portion folded back from the end of the first portion; and a third portion folded back from the end of the second portion.

Description

Technical Field

[0001] [Related Applications] This application enjoys priority to Japanese Patent Application No. 2023-151706 (filed on September 19, 2023). This application incorporates the entire contents of the said basic application by reference.

[0002] The present invention relates to a semiconductor memory device and a heating method for the semiconductor memory device. Prior Technology

[0003] A semiconductor memory device is known, comprising a substrate, a memory chip mounted on the substrate, and a sealing member for sealing the memory chip. Summary of the Invention

[0004] One embodiment provides a semiconductor memory device that can extend product lifespan and a heating method for the semiconductor memory device.

[0005] One embodiment of a semiconductor memory device includes a substrate, a sealing member, a first memory chip, and non-signal wiring. The substrate has a first surface. When viewed from the thickness direction of the substrate, i.e., a first direction, the sealing member covers the first surface. The first memory chip is disposed between the first surface and the sealing member in the first direction. The non-signal wiring is different from the signal wiring of the semiconductor memory device. The non-signal wiring is disposed on one or more of the surface of the sealing member, the interior of the sealing member, the first surface of the substrate, the interior of the substrate, or the surface of the first memory chip, and overlaps with the first memory chip when viewed from the first direction. The non-signal wiring has: a first end electrically connected to a power supply unit; a second end electrically connected to a ground wire; and a wiring body connecting the first end and the second end. The wiring body includes: a first portion extending along a second direction intersecting the first direction; a second portion extending parallel to the first portion from the end of the first portion toward a first side of the second direction; and a third portion extending parallel to the second portion from the end of the second portion toward a second side of the second direction opposite to the first side. Simple Explanation of the Diagram

[0006] Figure 1 is a plan view of the storage element in the first embodiment. Figures 2(a) and (b) are diagrams showing the NAND package of the first embodiment. Figures 3(a) to (d) are diagrams illustrating a manufacturing method of a NAND package according to a first embodiment. Figure 4 is a perspective view illustrating the regeneration method of the NAND package in the first embodiment. Figures 5(a) and (b) are diagrams showing a modified example of the NAND package of the first embodiment. Figures 6(a) and (b) are diagrams illustrating the NAND package of the second embodiment. Figures 7(a) and (b) are diagrams showing the NAND package of the first example of the second embodiment. Figures 8(a) to (d) are diagrams illustrating the manufacturing method of the NAND package of the first example of the second embodiment. Figures 9(a) and (b) are diagrams showing a second example of a NAND package in the second embodiment. Figures 10(a) to (d) are diagrams illustrating a manufacturing method of a NAND package according to a second example of the second embodiment. Figures 11(a) and (b) are diagrams showing the NAND package of the third example of the second embodiment. Figures 12(a) to (d) are diagrams illustrating the manufacturing method of the NAND package of the third example of the second embodiment. Figures 13(a) and (b) are diagrams illustrating the NAND package of the third embodiment. Figures 14(a) to (d) are diagrams illustrating the manufacturing method of the NAND package in the third embodiment. Figures 15(a) and (b) are diagrams illustrating the NAND package of the fourth embodiment. Figures 16(a) and (b) are diagrams illustrating the NAND package of the fifth embodiment. Figures 17(a) to (d) are diagrams illustrating the manufacturing method of the NAND package in the fifth embodiment. Figure 18 is a diagram showing the NAND package of the first variant of the fifth embodiment. Figure 19 is a diagram showing a second variant of the NAND package in the fifth embodiment. Figures 20(a) to (c) are diagrams showing the NAND package of the third variant of the fifth embodiment. Figure 21 is a diagram showing the NAND package of the fourth variant of the fifth embodiment. Figure 22 is a diagram showing a fifth variation of the NAND package in the fifth embodiment. Figure 23 is a diagram showing the NAND package of the sixth variant of the fifth embodiment. Figure 24 is a diagram showing the NAND package of the seventh variant of the fifth embodiment. Figure 25 is a diagram showing the NAND package of the eighth variant of the fifth embodiment. Figure 26 is a diagram showing the NAND package of the sixth embodiment. Figure 27 is a perspective view illustrating the regeneration method of the NAND package in the sixth embodiment. Figure 28 is a diagram showing a modified example of the sixth embodiment of the NAND package. Figure 29 is a diagram showing the seventh embodiment of the NAND package. Implementation

[0007] The following description, with reference to the accompanying drawings, will illustrate an embodiment of a semiconductor memory device and a heating method thereof. In this description, structures having the same or similar functions will be labeled with the same symbols. Furthermore, repeated descriptions of these structures will sometimes be omitted. Additionally, in some of the drawings, the structures are sometimes shown schematically.

[0008] In this application, the terms "parallel," "orthogonal," or "identical" can respectively include cases of "approximately parallel," "approximately orthogonal," or "approximately identical." In this application, "overlapping" refers to the imaginary projected images of two objects overlapping each other. That is, "overlapping" is not limited to the situation where two objects are in contact, but can include situations where two objects are not in contact (e.g., where there is space or other components between the two objects). Furthermore, in this application, "overlapping" can include situations where a portion of two objects overlaps each other. In this application, "connection" is not limited to mechanical connection, but can include electrical connection. That is, "connection" is not limited to a direct connection to an object, but can include a connection to an object through the presence of other components as intervening elements.

[0009] In this application, the +X, -X, +Y, -Y, +Z, and -Z directions are defined as follows: The +X, -X, +Y, and -Y directions are directions parallel to the first surface 11a of the substrate 11 (see Figure 1). The +X direction is the direction from the second end 11e2 of the substrate 11 towards the first end 11e1 (see Figure 1). The -X direction is the direction opposite to the +X direction. Without distinguishing between the +X and -X directions, they are simply referred to as the "X direction." The +Y and -Y directions are directions intersecting (e.g., orthogonal) to the X direction. The +Y direction is the direction from the fourth end 11e4 of the substrate 11 towards the third end 11e3 (see Figure 1). The -Y direction is the direction opposite to the +Y direction. Without distinguishing between the +Y and -Y directions, they are simply referred to as the "Y direction." The +Z and -Z directions are directions intersecting (e.g., orthogonal) to the X and Y directions, and are the thickness directions of the substrate 11. The +Z direction is the direction from the substrate 11 toward the NAND package 14 (see Figures 2(a) and (b)). The -Z direction is the opposite direction to the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the "Z direction".

[0010] The Z direction is an example of the "first direction". The X direction is an example of the "second direction". The -X direction side is an example of the "first side". The +X direction side is an example of the "second side". Hereinafter, the +Z direction side will sometimes be referred to as "up" and the -Z direction side as "down". However, these expressions are for ease of explanation and do not specify the direction of weight.

[0011] (First Implementation Form) <1. Overall Structure of Storage Elements> The storage element 1 of the first embodiment will be described with reference to Figures 1 to 4. The storage element 1 is, for example, a memory device such as a solid-state drive (SSD). The storage element 1 is installed in a host device and serves as the host device's memory device. The host device may be a personal computer, a mobile device, a video recorder, or an in-vehicle device, but is not limited to these examples.

[0012] Figure 1 is a plan view showing storage element 1. Storage element 1 includes, for example, a substrate 11, a controller 12, dynamic random access memory (DRAM) 13, multiple NAND flash memory modules 14 (hereinafter referred to as "NAND packages 14" for convenience), and multiple capacitors 15. Furthermore, storage element 1 may also have a housing that accommodates the substrate 11, controller 12, DRAM 13, multiple NAND packages 14, and multiple capacitors 15.

[0013] Substrate 11 is a plate member extending along the X and Y directions. Substrate 11 is a printed circuit board, including an insulating substrate and a wiring pattern disposed on the insulating substrate. Substrate 11 has a first surface 11a and a second surface 11b located on the side opposite to the first surface 11a (see Figures 2(a) and (b)). The first surface 11a and the second surface 11b extend along the X and Y directions, respectively.

[0014] The substrate 11 has a connector 11c at its +X direction end. The connector 11c is a connection part that can be connected to the connector of the host device. The connector 11c has multiple metal terminals that can be connected to the connector of the host device.

[0015] The controller 12 is a component that comprehensively controls the entire storage element 1. The controller 12 is, for example, a semiconductor package including a System On a Chip (SoC), which integrates host interface circuitry for the host device, control circuitry for controlling the DRAM 13, and control circuitry for controlling multiple NAND packages 14 onto a single semiconductor chip. The controller 12 is, for example, disposed on the first surface 11a of the substrate 11.

[0016] DRAM 13 is a semiconductor package that includes a volatile semiconductor memory chip. DRAM 13 is a data buffer that temporarily stores write-object data received from a host device or read-object data read from a NAND package 14. DRAM 13 is disposed, for example, on the first surface 11a of substrate 11. DRAM 13 may also be disposed inside controller 12.

[0017] NAND package 14 is a semiconductor package that includes a non-volatile semiconductor memory chip. NAND package 14 is disposed, for example, on a first surface 11a and a second surface 11b of substrate 11. In this embodiment, multiple NAND packages 14 each have heating wiring 30. NAND package 14 is an example of a "semiconductor memory device".

[0018] Capacitor 15 is one of the electronic components electrically connected to substrate 11. Capacitor 15, for example, performs a power backup function to protect data in the event of an unexpected power outage. In this embodiment, in the event of an unexpected power outage from the host device, capacitor 15 supplies power to controller 12, DRAM 13, and multiple NAND packages 14 for a certain period of time. Multiple capacitors 15 are, for example, arranged along the X-direction between controller 12 and DRAM 13 and multiple NAND packages 14.

[0019] <2. NAND Packaging Structure> Next, the structure of NAND package 14 will be explained. Figures 2(a) and (b) are diagrams illustrating a NAND package 14. The NAND package 14 includes, for example, a substrate 21, multiple connection terminals 23, multiple memory chips 24, multiple adhesive films 25, multiple bonding wires 26, a sealing member 27, heating wiring 30, a first solder pad 41, and a second solder pad 42. Hereinafter, to distinguish the substrate 21 of the NAND package 14 from the substrate 11 described above, the substrate 21 will be referred to as the "package substrate 21".

[0020] The packaging substrate 21 is a plate component along the X and Y directions. When viewed from the Z direction, the packaging substrate 21 has a rectangular shape identical to that of the NAND package 14. The packaging substrate 21 has a first surface 21a and a second surface 21b located on the side opposite to the first surface 21a. The first surface 21a is the surface facing the +Z direction. The first surface 21a has a plurality of solder pads 22a respectively connected to the bonding lines 26 described later. The second surface 21b is the surface facing the -Z direction. The second surface 21b has a plurality of solder pads 22b respectively connected to the connection terminals 23 described later.

[0021] The packaging substrate 21 is a printed circuit board and includes an insulating substrate 21i and a wiring pattern 21w. The insulating substrate 21i is an insulating rigid component formed of an insulating material such as glass epoxy resin or polyimide. The wiring pattern 21w is a conductive portion disposed on the surface or inside the insulating substrate 21i.

[0022] Wiring pattern 21w includes, for example, power wiring 21p and signal wiring 21s. Power wiring 21p is a wiring for the flow of current supplied from substrate 11 to NAND package 14. Power wiring 21p is electrically connected to memory chip 24 via pad 22a and supplies current for the supply of power to memory chip 24. Signal wiring 21s is wiring for transmitting signals. For example, signals input from substrate 11 to NAND package 14, signals output from NAND package 14 to substrate 11, or signals transmitted within NAND package 14 flow through signal wiring 21s.

[0023] Connection terminals 23 are disposed on the second surface 21b of substrate 21 and exposed to the outside of NAND package 14. Connection terminals 23 are electrical connections that connect to the pads of substrate 11. Multiple connection terminals 23 may be arranged in a grid pattern along the X and Y directions, for example. In this embodiment, the multiple connection terminals 23 are solder balls of a ball grid array (BGA). However, connection terminals 23 are not limited to the above example. Connection terminals 23 may be pads connected to the outside via conductive paste, terminals such as lead frames or pins, or terminals connected to the outside in other forms.

[0024] The memory chip 24 is, for example, a non-volatile semiconductor memory chip, such as a NAND flash memory chip. The memory chip 24 includes a plurality of memory cell transistors and peripheral circuitry for enabling the plurality of memory cell transistors to function as memory components. The memory chip 24 may, for example, have charge-trapping type memory cell transistors. However, the memory chip 24 is not limited to the described example and may also have floating-gate type memory cell transistors.

[0025] Memory chips 24 are plate-shaped along the X and Y directions. Multiple memory chips 24 are stacked along the Z direction with an adhesive film 25 spaced between them. The adhesive film 25 is, for example, a die attach film. Multiple memory chips 24 are stacked on a first surface 21a of a packaging substrate 21. Multiple memory chips 24 are disposed in the Z direction between the first surface 21a of the packaging substrate 21 and a sealing member 27. One of the multiple memory chips 24 is an example of a "first memory chip". One of the multiple memory chips 24 located in the Z direction between the first memory chip and the sealing member 27 is an example of a "second memory chip".

[0026] The plurality of memory chips 24 includes, for example, a first group of memory chips 24A and a second group of memory chips 24B. In the first group of memory chips 24A, the memory chips 24A further away from the packaging substrate 21 are offset towards the +X direction. In the second group of memory chips 24B, they are located on the +Z direction side relative to the memory chips 24A. In the second group of memory chips 24B, the memory chips 24B further away from the packaging substrate 21 are offset towards the -X direction. Each memory chip 24 has a first region R1 and a second region R2. The first region R1 is the region that overlaps with the adjacent memory chip 24 located on the +Z direction side when viewed from the Z direction. The second region R2 is the region that is offset from the adjacent memory chip 24 located on the +Z direction side when viewed from the Z direction (the region that does not overlap with the adjacent memory chip 24 located on the +Z direction side). The second region R2 of the memory chip 24 has solder pads 24s.

[0027] The bonding wire 26 is an electrical connection portion that connects the package substrate 21 to the memory chip 24. The plurality of bonding wires 26 may include, for example, a first group of bonding wires 26A (only one is shown in Figures 2(a) and (b)) and a second group of bonding wires 26B (only one is shown in Figures 2(a) and (b)). The bonding wire 26A is disposed at the -X direction end of the first group of memory chips 24A and connects the pads 24s of the first group of memory chips 24A to the pads 22a of the package substrate 21. On the other hand, the bonding wire 26B is disposed at the +X direction end of the second group of memory chips 24B and connects the pads 24s of the second group of memory chips 24B to the pads 22a of the package substrate 21.

[0028] The sealing member 27 is an insulating portion that protects the plurality of memory chips 24 and the plurality of bonding wires 26. The sealing member 27 is, for example, a molding resin. The sealing member 27 is disposed on the first surface 21a of the packaging substrate 21 and covers the first surface 21a of the packaging substrate 21 when viewed from the Z direction. The sealing member 27 covers the plurality of memory chips 24 and the plurality of bonding wires 26 from the side opposite to the first surface 21a of the packaging substrate 21. For example, when viewed from the Z direction, the sealing member 27 is formed into a rectangular shape with the same shape as the NAND package 14.

[0029] <3. Heating Wiring and Solder Pads> Next, the heating wiring 30, the first solder pad 41, and the second solder pad 42 will be described. The heating wiring 30 is used to heat the memory chip 24. The heating wiring 30 is different from the power wiring 21p and signal wiring 21s described above. The heating wiring 30 is an example of a "non-signal wiring". In this embodiment, the heating wiring 30 is located at a position different from the surface of the plurality of memory chips 24. In this embodiment, the heating wiring 30 is located on the surface of the sealing member 27 (e.g., the surface on the +Z direction side). When viewed from the Z direction, the heating wiring 30 overlaps with the plurality of memory chips 24. For example, when viewed from the Z direction, the heating wiring 30 overlaps with the first region R1 and the second region R2 of the plurality of memory chips 24.

[0030] The heating wiring 30 has, for example, a first end 31, a second end 32, and a wiring body 33. The first end 31 and the second end 32 are the two ends of the heating wiring 30. During the heat treatment of the memory chip 24, the first end 31 is electrically connected to the power supply section PSa (see Figure 4) of the external power supply device PS via the first pad 41 (described later). During the heat treatment of the memory chip 24, the second end 32 is electrically connected to the ground line PSb (see Figure 4) of the external power supply device PS via the second pad 42 (described later). The wiring body 33 extends between the first end 31 and the second end 32, connecting the first end 31 and the second end 32.

[0031] The wiring body 33 includes, for example, a first part 33a, a second part 33b, a third part 33c, a fourth part 33d, and a fifth part 33e. The first part 33a extends in a straight line along the X direction. The second part 33b folds back from the +X direction end of the first part 33a towards the -X direction, extending in a straight line parallel to the first part 33a. The third part 33c folds back from the -X direction end of the second part 33b towards the +X direction, extending in a straight line parallel to the second part 33b. The fourth part 33d folds back from the +X direction end of the third part 33c towards the -X direction, extending in a straight line parallel to the third part 33c. The fifth part 33e folds back from the -X direction end of the fourth part 33d towards the +X direction, extending in a straight line parallel to the fourth part 33d. Furthermore, the wiring body 33 has the same structure as the first part 33a to the fifth part 33e along the Y direction between the first end 31 and the second end 32.

[0032] The lengths in the X direction of the first part 33a, the second part 33b, the third part 33c, the fourth part 33d, and the fifth part 33e are, for example, the same as each other. The lengths in the X direction of each of the first part 33a, the second part 33b, the third part 33c, the fourth part 33d, and the fifth part 33e are more than half the length in the X direction of the sealing member 27.

[0033] The first part 33a to the fifth part 33e are arranged along the Y direction in the order of the first part 33a, the second part 33b, the third part 33c, the fourth part 33d, and the fifth part 33e. For example, the first part 33a, the second part 33b, the third part 33c, the fourth part 33d, and the fifth part 33e are arranged at equal intervals along the Y direction. That is, the distance S in the Y direction between the first part 33a and the second part 33b, the distance S in the Y direction between the second part 33b and the third part 33c, the distance S in the Y direction between the third part 33c and the fourth part 33d, and the distance S in the Y direction between the fourth part 33d and the fifth part 33e are the same. The distance S is, for example, less than twice the wiring width W1 of the heating wiring 30 described later.

[0034] The first solder pad 41 is a solder pad that protrudes to the outside of the sealing member 27. In this embodiment, the first solder pad 41 is disposed on the surface of the sealing member 27 (e.g., the surface on the +Z direction side). The first solder pad 41 is connected to the first end 31 of the heating wiring 30.

[0035] The second solder pad 42 is a solder pad that protrudes to the outside of the sealing member 27. In this embodiment, the second solder pad 42 is disposed on the surface of the sealing member 27 (e.g., the surface on the +Z direction side). The second solder pad 42 is connected to the second end 32 of the heating wiring 30.

[0036] In this embodiment, the heating wiring 30, the first solder pad 41, and the second solder pad 42 are formed by spraying conductive material onto the surface of the sealing member 27 using an inkjet spraying method. The conductive material is, for example, silver particles, copper particles, or nickel particles, but is not limited to these. The thickness T1 in the Z direction of each of the heating wiring 30, the first solder pad 41, and the second solder pad 42 is greater than the thickness T2 in the Z direction of the power wiring 21p, and greater than the thickness T3 in the Z direction of the signal wiring 21s. Furthermore, the wiring width W1 of the heating wiring 30 is greater than the wiring width W2 of the power wiring 21p, and greater than the wiring width W3 of the signal wiring 21s. In this application, the term "wiring width" refers to the width of the wiring in a direction orthogonal to its extension direction, and is the width of the narrowest part of the wiring's total length.

[0037] In this embodiment, the heating wiring 30, the first solder pad 41, and the second solder pad 42 are electrically insulated from the internal wiring (e.g., power wiring 21p or signal wiring 21s) of the NAND package 14. The heating wiring 30, the first solder pad 41, and the second solder pad 42 are in a floating state except during the heating process described later. Alternatively, the heating wiring 30, the first solder pad 41, and the second solder pad 42 may also be electrically connected to the ground of the NAND package 14, and are at the same potential.

[0038] Next, an example of the dimensions of the heating wiring 30 will be described. However, the dimensions of the heating wiring 30 are not limited to the examples described below.

[0039] Here, we consider a NAND package 14 having the following conditions: The resistivity of the heating wiring 30 is 4 μΩ·cm (silver wiring). The die size of the NAND package 14 is 10 mm × 10 mm. The current density flowing through the heating wiring 30 is 100 A / mm² or less. The power supplied to the heating wiring 30 is 1 W or more. Furthermore, the "wiring" described here refers to the portions of the heating wiring 30 extending in a specific direction as described in Parts 1 to 5, as in Parts 33a to 33e.

[0040] The dimensions are as follows: Wiring width is 1000 μm. Minimum spacing between wirings is 50 μm. In this embodiment, "spacing between wirings" refers to the distance S shown in Figures 2(a) and (b). Wiring thickness (thickness T1) is 30 μm. Number of wirings is 9. In this embodiment, "number of wirings" refers to the total number of multiple straight sections arranged parallel to each other in the circuit breaker spacing. In this embodiment, "number of wirings" refers to the total number of the first section 33a, the second section 33b, the third section 33c, ... shown in Figures 2(a) and (b). The total length of the heating wiring 30 is 90 mm. The wiring resistance of the heating wiring 30 is 0.12 Ω. The voltage is 0.36 V. The current is 3 A. The power is 1.08 W.

[0041] <4. Manufacturing Methods of NAND Packaging> Next, the manufacturing method of NAND package 14 will be explained. Figures 3(a) to (d) illustrate the manufacturing method of the NAND package 14. First, a package substrate 21 with solder pads 22a is prepared. Next, a plurality of memory chips 24 are deposited on the first surface 21a of the package substrate 21 along the Z direction (see Figure 3(a)).

[0042] Next, multiple bonding wires 26 are provided to electrically connect the package substrate 21 to multiple memory chips 24 (see Figure 3(b)). Next, a sealing member 27 is provided to seal the multiple memory chips 24 and the multiple bonding wires 26 (see Figure 3(c)). Next, a conductive material is sprayed onto the surface of the sealing member 27 using an inkjet printer to form a heating wiring 30, a first solder pad 41, and a second solder pad 42 (Figure 3(d)). This completes the NAND package 14.

[0043] <5. NAND Package Regeneration Method (Heating Method)> Next, the regeneration method (heating method) of NAND package 14 will be described. Figure 4 is a perspective view illustrating the regeneration method of NAND package 14. In this embodiment, for example, with NAND package 14 mounted on substrate 11 (or, for example, with storage element 1 connected to host device), power is supplied to heating wiring 30 using an external power supply device PS. For example, the power supply part PSa of the power supply device PS is connected to the first pad 41, and the ground line PSb of the power supply device PS is connected to the second pad 42. Furthermore, by supplying power from the power supply part PSa to the first pad 41, a heating process for regenerating NAND package 14 is performed.

[0044] As a heating process, for example, the NAND package 14 may be heated at 200°C for 3 hours, at 150°C for 8 hours, or at 125°C for several days. This allows the memory cell transistors contained in the memory chip 24 to recover from their deteriorated state, thereby regenerating the NAND package 14. Furthermore, in this application, "deterioration" refers to the degradation of characteristics in the memory cell transistors, such as a shorter data retention time and a wider distribution width of the threshold voltage used to determine the written data value. Additionally, in this application, "regeneration" means bringing the deteriorated state closer to its pre-deterioration state. Furthermore, in this application, "regeneration" is not limited to a complete restoration to the initial state, but also corresponds to the partial restoration of the state of the deteriorated memory cell transistors.

[0045] <6. Advantages> If write and erase cycles are repeatedly performed from the initial state of the NAND package 14, characteristic degradation occurs, such as a shorter data retention time and a wider distribution width of the threshold voltage used to determine the data value being written. If this characteristic degradation worsens, the number of bits that result in errors during data reading exceeds the number of bits that can be corrected by error correction, causing the NAND package 14 to reach its product lifespan. For example, in NAND packages 14 that have been increasingly multi-valued in recent years, there is a tendency for the NAND package 14 to reach its product lifespan due to the degradation of the memory cell transistors, even when there are no defects in the surrounding circuitry.

[0046] Here, according to the research of the inventors, it was found that even if the NAND package 14 deteriorates, if the NAND package 14 is heated under specified conditions (e.g., under conditions where the heating temperature and heating time as described above are ensured), part or all of the deterioration state of the memory cell transistors will be restored.

[0047] However, if the entire storage element 1 is heated in order to restore the deteriorated state of the memory cell transistors, there is a possibility that the heating may cause malfunctions in components other than the NAND package 14 (such as the controller 12 or DRAM 13).

[0048] Therefore, in this embodiment, the NAND package 14 has a heating wiring 30. The heating wiring 30 is disposed on the surface of the sealing member 27 and overlaps with the memory chip 24 when viewed from the Z direction. The heating wiring 30 has: a first end 31 electrically connected to the power supply portion PSa of the power supply device PS; a second end 32 electrically connected to the ground line PSb of the external power supply device PS; and a wiring body 33 connecting the first end 31 and the second end 32. The wiring body 33 includes: a first portion 33a extending in the X direction; a second portion 33b extending parallel to the first portion 33a from the end of the first portion 33a to a first side; and a third portion 33c extending parallel to the second portion 33b from the end of the second portion 33b to a second side opposite to the first side.

[0049] Based on this structure, the following heating process can be performed: localized heating of the NAND package 14 is achieved within the storage element 1 using heating wiring 30 provided in the NAND package 14. Compared to heating the entire storage element 1, this heating process can suppress the impact on components such as the controller 12 or DRAM 13, while simultaneously restoring at least a portion of the deterioration state of the memory cell transistors. This extends the product lifespan of the NAND package 14.

[0050] In this embodiment, the heating wiring 30 is formed by inkjet printing of conductive material. With this structure, it is easier to form the heating wiring 30 on the surface of the sealing member 27 of the NAND package 14 compared to other methods. This improves the manufacturability of the storage element 1. Furthermore, when the heating wiring 30 is formed by inkjet printing, the thickness T1 in the Z direction of the heating wiring 30 can be easily and arbitrarily set.

[0051] In this embodiment, the packaging substrate 21 has a power supply line 21p for supplying current to the memory chip 24. The thickness T1 in the Z direction of the heating line 30 is larger than the thickness T2 in the Z direction of the power supply line 21p. With this structure, a large current for heating the NAND package 14 can be easily passed through. This allows the NAND package 14 to be easily heated to the temperature required for regeneration.

[0052] In this embodiment, the width W1 of the heating wiring 30 is larger than the width W2 of the power wiring 21p. This structure allows for the easy flow of a large current for heating the NAND package 14. Consequently, the NAND package 14 can be easily heated to the temperature required for its regeneration.

[0053] In this embodiment, the heating wiring 30 is disposed on the surface of the sealing member 27. With this structure, the internal structure of the NAND package 14 (e.g., the internal circuitry) can be identical to that of a conventional NAND package 14. This improves the manufacturability of the NAND package 14.

[0054] In this embodiment, the NAND package 14 includes: a first pad 41 exposed to the outside of the sealing member 27 and electrically connected to a first end 31 of the heating wiring 30; and a second pad 42 exposed to the outside of the sealing member 27 and electrically connected to a second end 32 of the heating wiring 30. With this structure, compared to the case where the heating wiring 30 is disposed inside the NAND package 14, it is easier to supply heating power to the heating wiring 30 from an external power supply device PS. Therefore, compared to the case where the structure associated with the heating wiring 30 is disposed inside the NAND package 14, the internal structure of the NAND package 14 can be simplified. This improves the manufacturability of the NAND package 14.

[0055] <7. Variations> Next, a modified example of the NAND package 14A of the first embodiment will be described. The difference between this modified example and the first embodiment is that the heating wiring 30 is disposed inside the sealing member 27. Furthermore, the structure is the same as that of the first embodiment, except for the structure described below.

[0056] Figures 5(a) and (b) are diagrams showing a modified example of the NAND package 14A according to the first embodiment. In this modified example, the sealing member 27 includes a main body portion 27a and a cover portion 27b. The main body portion 27a and the cover portion 27b are molded resin and have insulating properties.

[0057] Similar to the sealing member 27 in the first embodiment, the main body 27a is disposed on the first surface 21a of the packaging substrate 21, and covers the plurality of memory chips 24 and the plurality of bonding lines 26 from the side opposite to the first surface 21a of the packaging substrate 21. When viewed from the Z direction, the main body 27a is formed into a rectangular shape with the same shape as the NAND package 14. Heating wiring 30, first solder pad 41 and second solder pad 42 are disposed on the surface of the main body 27a on the +Z direction side.

[0058] The cover portion 27b is formed of, for example, the same material as the main body portion 27a and is deposited on the surface of the main body portion 27a in the +Z direction. Furthermore, the material of the cover portion 27b may also be different from the material of the main body portion 27a. For example, to improve thermal insulation, the cover portion 27b may be formed of a resin material with poor heat dissipation compared to the material of the main body portion 27a. Alternatively, from a different perspective, for example, for the purpose of heat control, the material of the cover portion 27b may also be different from the material of the main body portion 27a.

[0059] The cover portion 27b covers the heating wiring 30 from the side opposite to the main body portion 27a. The cover portion 27b is a protective layer that protects the heating wiring 30. The cover portion 27b has openings 27h at positions corresponding to the first solder pad 41 and the second solder pad 42. The first solder pad 41 and the second solder pad 42 are exposed to the outside of the NAND package 14A through the openings 27h. The power supply portion PSa of the external power supply device PS is connected to the first solder pad 41 through the openings 27h. The ground wire PSb of the external power supply device PS is connected to the second solder pad 42 through the openings 27h.

[0060] Even with this structure, the product lifespan of the NAND package 14A can be extended by performing heat treatment using the heating wiring 30. Furthermore, in this modified example, the heating wiring 30 is located at a different position from the surfaces of the plurality of memory chips 24 and is inside the sealing member 27. For example, the heating wiring 30 is covered and protected by the cover portion 27b. This suppresses the occurrence of defects associated with the heating wiring 30, thereby reliably extending the product lifespan of the NAND package 14A.

[0061] In this modified example, the heating wiring 30 includes: a first portion 33a; a second portion 33b, which folds back from the end of the first portion 33a to a first side and extends parallel to the first portion 33a; and a third portion 33c, which folds back from the end of the second portion 33b to a second side opposite to the first side and extends parallel to the second portion 33b. According to this structure, during the step of providing the cover portion 27b, air can easily escape between the first portion 33a and the second portion 33b, and between the second portion 33b and the third portion 33c, and gaps are less likely to form between the main body portion 27a and the cover portion 27b.

[0062] (Second Implementation Form) Next, the NAND package 14B of the second embodiment will be described. This embodiment differs from the first embodiment in that it includes electrical connection portions 51 and 52 that connect the heating wiring 30 to the substrate 11. Furthermore, the structure, except for the structure described below, is the same as that of the first embodiment.

[0063] Figures 6(a) and (b) are diagrams showing the NAND package 14B according to a second embodiment. In this embodiment, the NAND package 14B has a first electrical connection portion 51 and a second electrical connection portion 52.

[0064] The first electrical connection portion 51 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 to the packaging substrate 21. When viewed from the Z direction, the first electrical connection portion 51 is disposed in a region offset from the memory chip 24. The first electrical connection portion 51 is disposed inside the sealing member 27. The first electrical connection portion 51 is, for example, a through hole (Through Hole Via) disposed in the sealing member 27. The first electrical connection portion 51 may also be, for example, a wire including a vertical wire (VW), a pillar including a metal pillar, or a through mold via (TMV). For example, multiple first electrical connection portions 51 may be provided. The first electrical connection portion 51 extends in the Z direction and penetrates the sealing member 27, electrically connecting the first end 31 of the heating wiring 30 to the packaging substrate 21.

[0065] The second electrical connection portion 52 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 to the packaging substrate 21. When viewed from the Z direction, the second electrical connection portion 52 is disposed in a region offset from the memory chip 24. The second electrical connection portion 52 is disposed inside the sealing member 27. The second electrical connection portion 52 is, for example, a through hole provided in the sealing member 27. The second electrical connection portion 52 may also be, for example, a wire including VW, a pillar including a metal pillar, or a TMV. For example, multiple second electrical connection portions 52 may be provided. The second electrical connection portion 52 extends in the Z direction and penetrates the sealing member 27, electrically connecting the second end 32 of the heating wiring 30 to the packaging substrate 21.

[0066] In this embodiment, instead of an external power supply device PS, power is supplied from the substrate 11 of the storage element 1 to the heating wiring 30 via the connection terminal 23 and the packaging substrate 21. The substrate 11 of the storage element 1 is an example of a "power supply unit".

[0067] Even with this structure, the product lifespan of the NAND package 14B can be extended by performing a heat treatment using the heating wiring 30. Furthermore, in this embodiment, the NAND package 14B includes: a first electrical connection portion 51 disposed inside the sealing member 27, electrically connecting the first end 31 of the heating wiring 30 to the package substrate 21; and a second electrical connection portion 52 disposed inside the sealing member 27, electrically connecting the second end 32 of the heating wiring 30 to the package substrate 21. According to this structure, power can be supplied to the heating wiring 30 from the substrate 11 of the storage element 1. Therefore, for example, even when multiple storage elements 1 are arranged in a high density, power supply to the heating wiring 30 can be easily performed.

[0068] (First example of the second implementation) Figures 7(a) and (b) are diagrams showing the NAND package 14B of the first example of the second embodiment. In the first example, the case where a first electrical connection portion 51A and a second electrical connection portion 52A are provided as a vertical wire (VW) will be described. In this application, "VW" refers to a wire extending in a direction perpendicular to the first surface 21a of the package substrate 21. In this application, "vertical direction" may include "generally vertical direction".

[0069] In the first example, the first surface 21a of the packaging substrate 21 has a solder pad 22c that connects the first electrical connection portion 51A or the second electrical connection portion 52A. The first electrical connection portion 51A and the second electrical connection portion 52A are, for example, wires extending linearly from the solder pad 22c along the +Z direction.

[0070] The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, 20 μm. The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, smaller than the wiring width W1 of the heating wiring 30. The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, smaller than the distance S between the wirings of the heating wiring 30.

[0071] In the first example, multiple (e.g., three) first electrical connection portions 51A are provided. These multiple (e.g., three) first electrical connection portions 51A are electrically connected in parallel between the packaging substrate 21 and the first end 31 of the heating wiring 30. For example, the multiple (e.g., three) first electrical connection portions 51A are arranged along the extension direction of the first end 31 of the heating wiring 30, i.e., the X direction. Similarly, in the first example, multiple (e.g., three) second electrical connection portions 52A are provided. These multiple (e.g., three) second electrical connection portions 52A are electrically connected in parallel between the packaging substrate 21 and the second end 32 of the heating wiring 30. For example, the multiple (e.g., three) second electrical connection portions 52A are arranged along the extension direction of the second end 32 of the heating wiring 30, i.e., the X direction.

[0072] Materials used for the first electrical connection portion 51A and the second electrical connection portion 52A may include, for example, monomers of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, composite materials of two or more of these, or alloys of two or more of these. More ideally, Au, Ag, Cu, or CuPd may be used as materials for the first electrical connection portion 51A and the second electrical connection portion 52A. Even more ideally, Cu or CuPd, which are hard materials, may be used as materials for the first electrical connection portion 51A and the second electrical connection portion 52A. Materials for the first electrical connection portion 51A and the second electrical connection portion 52A may also be metals obtained by coating Cu with Pd.

[0073] Figures 8(a) to (d) illustrate a method for manufacturing the NAND package 14B of the first example of the second embodiment. First, a package substrate 21 with solder pads 22a and 22c provided is prepared. Next, a plurality of memory chips 24 are deposited along the Z direction on the first surface 21a of the package substrate 21 (see Figure 8(a)).

[0074] Next, multiple bonding lines 26 are provided to electrically connect the packaging substrate 21 to multiple memory chips 24. Additionally, a first electrical connection portion 51A and a second electrical connection portion 52A as VW are provided (see Figure 8(b)). The first electrical connection portion 51A and the second electrical connection portion 52A are formed, for example, by extending upwards until exceeding the height of the highest memory chip 24, and then cutting it using a known technique such as a full cut.

[0075] Next, a sealing member 27 is provided to seal multiple memory chips 24, multiple bonding wires 26, multiple first electrical connections 51A, and multiple second electrical connections 52A (see Figure 8(c)). The sealing member 27 is formed, for example, by cutting off the +Z direction end of the sealing member 27Z after the sealing member 27Z is provided with the first electrical connections 51A and the second electrical connections 52A embedded within it (see the black arrow in the figure). This exposes the +Z direction ends of the first electrical connections 51A and the second electrical connections 52A to the outside of the sealing member 27. Alternatively, a portion of the +Z direction ends of the first electrical connections 51A and the second electrical connections 52A may also be cut off. Next, a conductive material is sprayed onto the surface of the sealing member 27 using an inkjet spraying method to form a heating wiring 30 (Figure 8(d)). This completes the first example of the NAND package 14B.

[0076] (Second example of the second implementation) Figures 9(a) and (b) are diagrams showing a second example of the NAND package 14B according to the second embodiment. In this second example, the case where a first electrical connection portion 51B and a second electrical connection portion 52B, which are provided as conductive pillars, will be described. In this application, a "pillar" refers to a pillar-shaped electrode portion extending in a direction perpendicular to the first surface 21a of the package substrate 21. The "pillar" may be a metal pillar or a pillar formed of a conductive material different from metal. Furthermore, in this application, the term "conductive pillar" is not limited to the case where the entire pillar is conductive. For example, if the "conductive pillar" has a central portion (core) and a coating portion covering the outer periphery of the central portion, only one of the central portion and the coating portion may be conductive.

[0077] The first electrical connection portion 51B and the second electrical connection portion 52B are, for example, columnar electrode portions extending linearly from the solder pad 22c (not shown) in the +Z direction. In the second example, the width (e.g., diameter) of each of the first electrical connection portion 51B and the second electrical connection portion 52B is, for example, larger than the wiring width W1 of the heating wiring 30. For example, one of each of the first electrical connection portion 51B and the second electrical connection portion 52B is provided. However, multiple of each of the first electrical connection portion 51B and the second electrical connection portion 52B may also be provided. As the material for the first electrical connection portion 51B and the second electrical connection portion 52B, for example, the material described in the first example can be used.

[0078] Figures 10(a) to (d) illustrate a method for manufacturing a NAND package 14B according to a second embodiment. First, a package substrate 21 with solder pads 22a and 22c is prepared. Next, a plurality of memory chips 24 are deposited along the Z-direction on the first surface 21a of the package substrate 21. Additionally, a first electrical connection portion 51B and a second electrical connection portion 52B are provided as pillars (see Figure 10(a)). Furthermore, the steps of providing the first electrical connection portion 51B and the second electrical connection portion 52B can be performed after the step of providing the bonding wire 26.

[0079] Next, multiple bonding lines 26 are provided to electrically connect the packaging substrate 21 to multiple memory chips 24 (see Figure 10(b)). Then, a sealing member 27 is provided to seal the multiple memory chips 24, the multiple bonding lines 26, the first electrical connection portion 51B, and the second electrical connection portion 52B (see Figure 10(c)). The sealing member 27 is formed, for example, by cutting off the +Z direction end of the sealing member 27Z after the sealing member 27Z, into which the first electrical connection portion 51B and the second electrical connection portion 52B are embedded (see the black arrow in the figure). This exposes the +Z direction end of the first electrical connection portion 51B and the second electrical connection portion 52B to the outside of the sealing member 27. Alternatively, for example, a portion of the +Z direction end of the first electrical connection portion 51B and the second electrical connection portion 52B may also be cut off. Next, conductive material is sprayed onto the surface of the sealing member 27 by inkjet printing to form the heating wiring 30 (d in FIG10). This completes the second example of the NAND package 14B.

[0080] (The third example of the second implementation) Figures 11(a) and (b) are diagrams showing a third example of the NAND package 14B according to the second embodiment. In the third example, the case where a first electrical connection portion 51C and a second electrical connection portion 52C are provided as a through mold via (TMV) will be described. In this application, "TMV" refers to a through hole that extends in a direction perpendicular to the first surface 21a of the package substrate 21 and penetrates at least a portion of the sealing member 27. "TMV" can be a metallic through hole or a through hole formed of a conductive material different from metal. In addition, in this application, "through hole" is not limited to the case where the entire through hole is conductive. For example, when the "through hole" has a central portion (core) and a film portion covering the outer periphery of the central portion, only one of the central portion and the film portion may be conductive.

[0081] The first electrical connection portion 51C and the second electrical connection portion 52C are, for example, columnar electrode portions that penetrate the sealing member 27 along the Z direction and are connected to the first surface 21a of the encapsulation substrate 21. In the third example, the width (e.g., diameter) of each of the first electrical connection portion 51C and the second electrical connection portion 52C is, for example, larger than the wiring width W1 of the heating wiring 30. For example, one of each of the first electrical connection portion 51C and the second electrical connection portion 52C is provided. However, multiple first electrical connection portions 51C and second electrical connection portions 52C may also be provided. As the material for the first electrical connection portion 51C and the second electrical connection portion 52C, for example, the material described in the first example can be used.

[0082] Figures 12(a) to (d) illustrate a method for manufacturing the NAND package 14B of the third example of the second embodiment. First, a package substrate 21 with solder pads 22a is prepared. Next, a plurality of memory chips 24 are deposited along the Z direction on the first surface 21a of the package substrate 21 (see Figure 12(a)). Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 to the plurality of memory chips 24. Next, a sealing member 27 is provided to seal the plurality of memory chips 24 and the plurality of bonding wires 26 (see Figure 12(b)).

[0083] Next, a through hole 27ha is provided, penetrating the sealing member 27 along the Z direction. Furthermore, by supplying materials for the first electrical connection portion 51C and the second electrical connection portion 52C into the through hole 27ha, the first electrical connection portion 51C and the second electrical connection portion 52C are formed (see Figure 12(c)). Next, by spraying conductive material onto the surface of the sealing member 27 using an inkjet printing method, a heating wiring 30 is formed (Figure 12(d)). This completes the third example of the NAND package 14B.

[0084] (Third Implementation Form) Next, the third embodiment of the NAND package 14C will be described. The difference between this embodiment and the first embodiment is that heating wiring 30 is provided on the first surface 21a of the package substrate 21. Furthermore, the structure, except for the structure described below, is the same as that of the first embodiment.

[0085] Figures 13(a) and (b) are diagrams illustrating a third embodiment of the NAND package 14C. In this embodiment, a heating wiring 30 is disposed on the first surface 21a of the package substrate 21. The heating wiring 30 is located, for example, in the X direction, between a plurality of bonding pads 22a separately disposed on both sides of the memory chip 24. The memory chip 24 located on the side closest to the -Z direction among the plurality of memory chips 24 is disposed on the heating wiring 30 via an adhesive film 25. A portion of the adhesive film 25 extends between the first portion 33a and the second portion 33b, between the second portion 33b and the third portion 33c, between the third portion 33c and the fourth portion 33d, and between the fourth portion 33d and the fifth portion 33e of the heating wiring 30. When viewed from the Z direction, the heating wiring 30 overlaps with the plurality of memory chips 24 respectively.

[0086] Furthermore, the shape and size of the heating wiring 30 are not limited to the example described above. For example, when viewed from the Z direction, the heating wiring 30 may extend to a region that does not overlap with the memory chip 24 (the region located on the outer periphery of the memory chip 24). When the heating wiring 30 extends to the outer periphery of the memory chip 24 when viewed from the Z direction, the heating wiring 30 is positioned to avoid the plurality of solder pads 22a. For example, when viewed from the Z direction, the first portion 33a, the second portion 33b, the third portion 33c, the fourth portion 33d, and the fifth portion 33e of the heating wiring 30 extend between the plurality of solder pads 22a separately disposed on both sides of the memory chip 24 in the X direction, while folding back sequentially along the -X direction and the +X direction.

[0087] In this embodiment, the first end 31 and the second end 32 of the heating wiring 30 are electrically connected to the packaging substrate 21. Power is supplied from the substrate 11 of the storage element 1 to the heating wiring 30 via the connection terminal 23 and the packaging substrate 21.

[0088] Next, the manufacturing method of NAND package 14C will be explained. Figures 14(a) to (d) illustrate a method for manufacturing a NAND package 14C. First, heating wiring 30 is provided on the first surface 21a of the package substrate 21 (see Figure 14(a)). The heating wiring 30 is formed, for example, by spraying conductive material onto the first surface 21a of the package substrate 21 using an inkjet printer. Alternatively, the heating wiring 30 can also be formed by the same steps as the solder pads 22a and other wiring on the first surface 21a of the package substrate 21 (e.g., etching the copper-clad laminate). Next, a plurality of memory chips 24 are deposited on the first surface 21a of the package substrate 21 along the Z direction (see Figure 14(b)).

[0089] Next, multiple bonding lines 26 are provided to electrically connect the package substrate 21 to multiple memory chips 24 (see Figure 14(c)). Then, a sealing member 27 is provided to seal the multiple memory chips 24 and the multiple bonding lines 26 (see Figure 14(d)). This completes the NAND package 14C.

[0090] Even with this structure, the product lifespan of the NAND package 14C can be extended. Furthermore, in this embodiment, the heating wiring 30 is disposed on the first surface 21a of the package substrate 21. With this structure, power can be supplied to the heating wiring 30 from the substrate 11 of the storage element 1. Therefore, for example, even with a simpler structure compared to the first and second embodiments, power can still be supplied to the heating wiring 30.

[0091] In this embodiment, the heating wiring 30 includes: a first portion 33a; a second portion 33b, which extends parallel to the first portion 33a from the end of the first portion 33a toward a first side; and a third portion 33c, which extends parallel to the second portion 33b from the end of the second portion 33b toward a second side opposite to the first side. According to this structure, during the stacking of the memory chip 24, air easily escapes between the first portion 33a and the second portion 33b, and between the second portion 33b and the third portion 33c, and voids are less likely to form between the first surface 21a of the packaging substrate 21 and the bottommost adhesive film 25.

[0092] (Fourth Implementation Form) Next, the fourth embodiment of the NAND package 14D will be described. This embodiment differs from the first embodiment in that heating wiring 30 is provided inside the package substrate 21. Furthermore, the structure, except for the structure described below, is the same as that of the first embodiment.

[0093] Figures 15(a) and (b) are diagrams showing the NAND package 14D of the fourth embodiment. In this embodiment, heating wiring 30 is disposed in the inner layer of the package substrate 21. For example, the heating wiring 30 is disposed in the inner layer of the multiple inner layers of the package substrate 21 that is closest to the first surface 21a. When viewed from the Z direction, the heating wiring 30 overlaps with the multiple memory chips 24.

[0094] Even with this structure, the product lifespan of the NAND package 14D can be extended by performing heat treatment using the heating wiring 30. Furthermore, in this embodiment, the heating wiring 30 is disposed inside the package substrate 21. With this structure, power can be supplied to the heating wiring 30 from the substrate 11 of the storage element 1. Therefore, for example, even with a simpler structure compared to the first and second embodiments, power can still be supplied to the heating wiring 30.

[0095] (Fifth Implementation Form) Next, the fifth embodiment of the NAND package 14E will be described. This embodiment differs from the first embodiment in that heating wiring 30 is provided on the surface of the memory chip 24. Furthermore, the structure, except for the structure described below, is the same as that of the first embodiment.

[0096] Figures 16(a) and (b) are diagrams illustrating the NAND package 14E of the fifth embodiment. In this embodiment, heating wiring 30 is provided on the surfaces of a plurality of (e.g., all) memory chips 24. The heating wiring 30 is provided on the surface of each memory chip 24 on the +Z direction side.

[0097] In this embodiment, each memory chip 24 has a first region R1 and a second region R2. In each memory chip 24, a plurality of solder pads 24s are disposed in the second region R2. The plurality of solder pads 24s are arranged, for example, along the Y direction.

[0098] In this embodiment, the wiring body 33 of the heating wiring 30 is disposed in the first region R1. A portion of the adhesive film 25 for fixing the memory chips 24 adjacent in the +Z direction enters between the first portion 33a and the second portion 33b, between the second portion 33b and the third portion 33c, between the third portion 33c and the fourth portion 33d, and between the fourth portion 33d and the fifth portion 33e of the heating wiring 30.

[0099] On the other hand, the first solder pad 41 and the second solder pad 42 are disposed in the second region R2. For example, the first solder pad 41 and the second solder pad 42 are separately disposed on both sides of the plurality of solder pads 24s in the Y direction. In this embodiment, the NAND package 14E has bonding lines 61 and bonding lines 62.

[0100] The bonding wire 61 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 to the packaging substrate 21. The bonding wire 61 is an example of a "first electrical connection portion". The bonding wire 61 is connected to the first pad 41, and the first end 31 of the heating wiring 30 is electrically connected to the pad 22a of the packaging substrate 21 via the first pad 41. The bonding wire 61 connects the first pads 41 of the multiple memory chips 24 sequentially in a manner that electrically connects the first pads 41 of the multiple memory chips 24 in series.

[0101] The bonding wire 62 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 to the packaging substrate 21. The bonding wire 62 is an example of a "second electrical connection portion". The bonding wire 62 is connected to the second pad 42, and the second end 32 of the heating wiring 30 is electrically connected to the pad 22a of the packaging substrate 21 via the second pad 42. The bonding wire 62 connects the second pads 42 of the multiple memory chips 24 sequentially in a manner that electrically connects the second pads 42 of the multiple memory chips 24 in series.

[0102] Next, an example of the dimensions of the heating wiring 30 will be described. However, the dimensions of the heating wiring 30 are not limited to the examples described below. Here, similar to the first embodiment, a NAND package 14E with the following conditions is considered: The resistivity of the heating wiring 30 is 4 μΩ·cm (silver wiring). The chip size of the NAND package 14E is 10 mm × 10 mm. The current density flowing through the heating wiring 30 is 100 A / mm² or less. The power supplied to the heating wiring 30 is 1 W or more. Furthermore, the "wiring" described here refers to the portions of the heating wiring 30 that extend in a specific direction, as described in the first part 33a to the fifth part 33e.

[0103] The dimensions are as follows: Wiring width is 200 μm. Minimum spacing between wirings is 50 μm. Wiring thickness (thickness T1) is 10 μm. Number of wirings is 40. Total length of heating wiring 30 is 400 mm. Wiring resistance of heating wiring 30 is 8 Ω. Voltage is 1 V. Current is 0.125 A. 0.125 W of power is supplied to one of the memory chips 24. Therefore, in this embodiment, as shown in FIG16(b), there are 8 memory chips 24, and the total power in the multiple memory chips 24 is 1 W.

[0104] Next, the manufacturing method of NAND package 14E will be explained. Figures 17(a) to (d) illustrate a method for manufacturing the NAND package 14E. First, heating wiring 30 is provided on the surface of the memory chip 24 before the plurality of memory chips 24 are monolithically assembled (see Figure 17(a)). Next, a plurality of memory chips 24 are stacked along the Z direction on the first surface 21a of the package substrate 21 (see Figure 17(b)).

[0105] Next, multiple bonding lines 26 are provided to electrically connect the packaging substrate 21 to the solder pads 24s of the multiple memory chips 24. Additionally, bonding lines 61 are provided to electrically connect the packaging substrate 21 to the first solder pads 41 of the multiple memory chips 24. Furthermore, bonding lines 62 are provided to electrically connect the packaging substrate 21 to the second solder pads 42 of the multiple memory chips 24 (see Figure 17(c)). Next, a sealing member 27 is provided to seal the multiple memory chips 24, the multiple bonding lines 26, the bonding lines 61 and 62 (see Figure 17(d)). This completes the NAND package 14E.

[0106] Even with this structure, the product lifespan of the NAND package 14E can be extended by performing heat treatment using the heating wiring 30. Furthermore, in this embodiment, the heating wiring 30 is disposed on the surface of the memory chip 24. With this structure, each memory chip 24 can be heated more directly.

[0107] <Variations of the Fifth Implementation> Next, several variations of the fifth embodiment will be described. Furthermore, in each variation, the structure other than the structure described below is the same as the structure of the fifth embodiment.

[0108] (First variation) Figure 18 is a diagram showing a first modified example of the NAND package 14F. In this modified example, the NAND package 14F has the same number of bonding lines 61 and the same number of bonding lines 62 as the plurality of memory chips 24.

[0109] Multiple bonding lines 61 are configured one-to-one with multiple memory chips 24, connecting the first pad 41 of the corresponding memory chip 24 to the packaging substrate 21. In this modified example, the multiple bonding lines 61 electrically connect the first pad 41 of the multiple memory chips 24 to the packaging substrate 21 in parallel.

[0110] Multiple bonding lines 62 are configured one-to-one with multiple memory chips 24, connecting the second pads 42 of the corresponding memory chips 24 to the packaging substrate 21. In this modified example, the multiple bonding lines 62 electrically connect the second pads 42 of the multiple memory chips 24 to the packaging substrate 21 in parallel.

[0111] Even with this structure, the product life of the NAND package 14F can be extended by performing heat treatment using the heating wiring 30. In addition, in this modified example, since bonding wires 61 and 62 are provided for each memory chip 24, it is easy to carry a large current in the heating wiring 30 of each memory chip 24.

[0112] (Second variation) Figure 19 is a diagram showing a second modified NAND package 14G. In this modified example, in the NAND package 14G, a plurality of bonding lines 61 are provided corresponding to the first bonding pads 41 of each memory chip 24, and a plurality of bonding lines 62 are provided corresponding to the second bonding pads 42 of each memory chip 24.

[0113] A plurality of bonding lines 61, corresponding to the first bonding pads 41 of each memory chip 24, are electrically connected to the first bonding pads 41 of the memory chip 24 in parallel. Similarly, a plurality of bonding lines 62, corresponding to the second bonding pads 42 of each memory chip 24, are electrically connected to the second bonding pads 42 of the memory chip 24 in parallel.

[0114] Even with this structure, the product lifespan of the NAND package 14G can be extended by performing heat treatment using the heating wiring 30. Furthermore, in this modified example, multiple bonding lines 61 and multiple bonding lines 62 are provided corresponding to each memory chip 24. Therefore, it is easy to conduct large currents in the heating wiring 30 of each memory chip 24.

[0115] (Third variation) Figures 20(a) to (c) are diagrams showing a third modified example of the NAND package 14H. In this modified example, the NAND package 14H has a first electrical connection portion 71 and a second electrical connection portion 72 instead of the bonding wire 61 and the bonding wire 62.

[0116] In this modified example, the memory chip 24 has a first surface S1 and a second surface S2. The first surface S1 is a surface facing the +Z direction and extends along the X and Y directions. The second surface S2 is a surface corresponding to the side surface of the memory chip 24. The second surface S2 is a plane facing the X direction and extends along the Y and Z directions.

[0117] The first electrical connection portion 71 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 to the packaging substrate 21. In this modified example, the first electrical connection portion 71 is arranged in a stepped manner on the first surface S1 and the second surface S2 of the plurality of memory chips 24 in a continuous manner, and is connected to the pads 22a of the packaging substrate 21. The first electrical connection portion 71 connects the first pads 41 of the plurality of memory chips 24 sequentially in a manner that electrically connects the first pads 41 of the plurality of memory chips 24 in series. The first electrical connection portion 71 is formed, for example, by spraying conductive material onto the first surface S1 and the second surface S2 of the plurality of memory chips 24 using an inkjet method.

[0118] The second electrical connection portion 72 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 to the packaging substrate 21. In this modified example, the second electrical connection portion 72 is arranged in a stepped manner on the first surface S1 and the second surface S2 of the plurality of memory chips 24 in a continuous manner, and is connected to the pads 22a of the packaging substrate 21. The second electrical connection portion 72 connects the second pads 42 of the plurality of memory chips 24 sequentially in a manner that electrically connects the second pads 42 of the plurality of memory chips 24 in series. The second electrical connection portion 72 is formed, for example, by spraying conductive material onto the first surface S1 and the second surface S2 of the plurality of memory chips 24 using an inkjet method.

[0119] Even with this structure, the product lifespan of the NAND package 14H can be extended by performing heat treatment using the heating wiring 30. Furthermore, in this modified example, the NAND package 14H has a first electrical connection portion 71 and a second electrical connection portion 72 formed by inkjet printing. Depending on the inkjet printing method, the thickness or wiring width of the first electrical connection portion 71 and the second electrical connection portion 72 can be arbitrarily formed. Therefore, it is easy to conduct large currents in the heating wiring 30 of each memory chip 24.

[0120] (Fourth variation) Figure 21 is a diagram showing a fourth modified example of the NAND package 14I. In this modified example, the NAND package 14I has a plurality of electrical connection portions 73 instead of a plurality of bonding wires 26. The plurality of electrical connection portions 73 are arranged in a stepped manner on the first surface S1 and the second surface S2 of the plurality of memory chips 24 in a continuous manner, and are connected to the pads 22a of the package substrate 21. The plurality of electrical connection portions 73 connect the pads 24s of the plurality of memory chips 24 sequentially in a manner that electrically connects the pads 24s of the plurality of memory chips 24 in series. The plurality of electrical connection portions 73 are formed, for example, by spraying conductive material onto the first surface S1 and the second surface S2 of the plurality of memory chips 24 using an inkjet method.

[0121] Even with this structure, the lifespan of the NAND package 14I can be extended by performing a heat treatment using the heating wiring 30. Furthermore, in this modified example, an electrical connection portion 73 is provided to connect the solder pads 24s of the memory chip 24 to the package substrate 21. According to this structure, the first electrical connection portion 71, the second electrical connection portion 72, and the electrical connection portion 73 have similar structures. Therefore, the manufacturability of the NAND package 14I can be improved.

[0122] (Fifth variation) Figure 22 is a diagram showing the fifth modified example of the NAND package 14J. In this modified example, the heating wiring 30 is provided on only a portion of the memory chips 24 among the plurality of memory chips 24. For example, when the plurality of memory chips 24 are regarded as a stacked module SB, the heating wiring 30 is provided on the surface of the memory chip 24 closest to the center in the Z direction of the stacked module SB. Even with this structure, the product life of the NAND package 14J can be extended by performing heat treatment using the heating wiring 30.

[0123] (Sixth variation) Figure 23 is a diagram showing the NAND package 14K of the sixth modification. In this modification, heating wiring 30 is provided on only a portion of the memory chips 24 among the plurality of memory chips 24. For example, heating wiring 30 is provided on the surface of every other memory chip 24 in the Z direction (e.g., the odd-numbered memory chip 24 counting from the bottommost memory chip 24). Even with this structure, the lifespan of the NAND package 14K can be extended by performing heat treatment using heating wiring 30.

[0124] (Seventh variation) Figure 24 is a diagram showing the NAND package 14L of the seventh modification. In this modification, heating wiring 30 is provided in only a portion of the area of ​​each memory chip 24. Each memory chip 24 has a plurality (e.g., four) memory planar regions MP. The memory planar regions MP have: a memory region including a plurality of memory cell transistors; a circuit region including peripheral circuitry that enables the plurality of memory cell transistors to function; and a wiring region including wiring that connects the memory region to the peripheral circuitry.

[0125] In this variation, when viewed from the Z-direction, each memory planar region MP has a memory region MPa and a wiring region MPb. The memory region MPa includes multiple word lines stacked along the Z-direction and multiple memory pillars penetrating the multiple word lines along the Z-direction, with memory cell transistors formed at the intersections of the word lines and memory pillars. The circuit region is stacked, for example, above or below the memory region MPa in the Z-direction. On the other hand, the wiring region MPb is a region offset from the memory region MPa. The wiring region MPb includes multiple contacts extending along the Z-direction to connect the memory region MPa to the circuit region.

[0126] In this modified example, the heating wiring 30 is provided in the memory region MPa of each memory plane region MP, but not in the wiring region MPb. With this structure, the memory region, including the memory cell transistors to be regenerated, can be heated more efficiently.

[0127] (Eighth variation) Figure 25 is a diagram showing the NAND package 14M of the eighth variation. In this variation, the memory region MPa of each memory planar region MP includes a first region MPaa and a second region MPab. The first region MPaa is the area in the memory region MPa that overlaps with the sense amplifier and column decoder contained in the circuit region when viewed from the Z direction. The second region MPab is the area that deviates from the first region MPaa when viewed from the Z direction. The second region MPab is the area that does not overlap with the sense amplifier and column decoder contained in the circuit region when viewed from the Z direction.

[0128] In this modified example, the heating wiring 30 is provided in the second region MPab of the memory region MPa in each memory plane region MP, but not in the first region MPaa of the memory region MPa and the wiring region MPb. According to this structure, the memory region including the memory cell transistors to be regenerated can be heated more efficiently, and, for example, compared to the seventh modified example, the impact of the heating process on the sense amplifier and column decoder can be suppressed.

[0129] Furthermore, details regarding the "memory cell transistor," "contact," "readout amplifier," and "column decoder" in this application are described, for example, in Japanese Patent Application 2023-111719. The entire contents of that document are incorporated herein by reference. For example, "readout amplifier" and "column decoder" correspond to "readout amplifier module" and "column decoder module" in the aforementioned documents, respectively.

[0130] (Sixth Implementation Form) Next, the NAND package 14N of the sixth embodiment will be described. This embodiment differs from the first embodiment in that it utilizes electromagnetic induction heating. Furthermore, the structure, except for the structure described below, is the same as that of the first embodiment.

[0131] Figure 26 is a diagram showing a sixth embodiment of the NAND package 14N. The NAND package 14N has a metal portion 81 for electromagnetic induction heating instead of heating wiring 30. The metal portion 81 is, for example, a metal film provided on the surface of the sealing member 27 in the +Z direction. When viewed from the Z direction, the metal portion 81 covers the entire sealing member 27. When viewed from the Z direction, the metal portion 81 overlaps with each of the multiple memory chips 24. The thickness T4 of the metal portion 81 in the Z direction is, for example, 0.3 μm or more. For example, the metal portion 81 can be formed using a sputtering apparatus. For example, by using a sputtering apparatus, a metal film of 0.3 μm or more can be formed. Alternatively, the thickness T4 of the metal portion 81 in the Z direction can be several μm to several hundred μm. For example, the thickness T4 of the metal portion 81 in the Z direction is 1.0 μm or more.

[0132] Furthermore, the metal part 81 used for electromagnetic induction heating is not limited to a metal part specifically for electromagnetic induction heating; it can also be implemented using a metal film provided for shielding. That is, the heat treatment of the NAND package 14N can also be performed using a metal film provided for shielding and electromagnetic induction heating.

[0133] Next, the regeneration method (heating method) for NAND package 14N will be explained. Figure 27 is a perspective view illustrating the regeneration method (heating method) for the NAND package 14N. In this embodiment, for example, with the NAND package 14N mounted on the substrate 11 (or, for example, with the storage element 1 connected to the host device), an external induction heating device IH applies a magnetic field (magnetic lines G) to the metal portion 81. For example, the coil C of the induction heating device IH is positioned facing the NAND package 14N, and an alternating current flows through the coil C. As a result, a current generated by electromagnetic induction flows through the metal portion 81, and the metal portion 81 heats up due to Joule heating. This performs a heating process on the NAND package 14N.

[0134] (advantage) In this embodiment, the NAND package 14N has a metal portion 81 for electromagnetic induction heating, which is disposed on the surface of the sealing member 27 and overlaps with the memory chip 24 when viewed from the Z direction. With this structure, heat treatment is performed using electromagnetic induction heating of the metal portion 81, thereby extending the product lifespan of the NAND package 14N.

[0135] (Modified Example) Figure 28 is a diagram showing a modified example of the sixth embodiment of the NAND package 14P. In this modified example, the metal portion 81 is disposed inside the sealing member 27. For example, the metal portion 81 is disposed at a position different from the surface of the plurality of memory chips 24 and is inside the sealing member 27.

[0136] In this modified example, the sealing member 27 includes a main body portion 27a and a cover portion 27b. A metal portion 81 is disposed on the surface of the main body portion 27a in the +Z direction. The cover portion 27b is deposited on the surface of the main body portion 27a in the +Z direction. The cover portion 27b covers the metal portion 81 from the side opposite to the main body portion 27a. The cover portion 27b is a protective layer that protects the metal portion 81. Even with this structure, the lifespan of the NAND package 14P can be extended by performing heat treatment using electromagnetic induction heating of the metal portion 81.

[0137] (Seventh Implementation Form) Next, the seventh embodiment of the NAND package 14Q will be described. The difference between this embodiment and the sixth embodiment is that the metal portion 91 for electromagnetic induction heating is deposited on the memory chip 24 inside the NAND package 14Q. Furthermore, the structure, except for the structure described below, is the same as that of the sixth embodiment.

[0138] Figure 29 is a diagram showing a modified example of the seventh embodiment of the NAND package 14Q. In this embodiment, the NAND package 14Q has a metal portion 91 for electromagnetic induction heating. The metal portion 91 is deposited inside the NAND package 14Q on the uppermost memory chip 24. The metal portion 91 is fixed to the uppermost memory chip 24, for example, by an adhesive film 25. When viewed from the Z direction, the metal portion 91 overlaps with at least a portion of each of the plurality of memory chips 24. The thickness T4 of the metal portion 91 in the Z direction is 1.0 μm or more. For example, the thickness T4 of the metal portion 91 in the Z direction is several μm to several hundred μm. The metal portion 91 is, for example, a metal plate.

[0139] Even with this structure, the product life of the NAND package 14Q can be extended by using electromagnetic induction heating of the metal part 91 for heating treatment.

[0140] The above describes several embodiments and modifications. However, the embodiments and modifications are not limited to the examples described. For example, the various embodiments and modifications can also be combined with each other.

[0141] In the described embodiment, the X direction is an example of a "second direction," with the first portion 33a to the fifth portion 33e of the heating wiring 30 extending along the X direction. Alternatively, the Y direction can also be an example of a "second direction," with the first portion 33a to the fifth portion 33e of the heating wiring 30 extending along the Y direction.

[0142] According to at least one embodiment described above, a semiconductor memory device includes non-signal wiring. The non-signal wiring is disposed on one or more of the surface of a sealing member, the interior of the sealing member, a first surface of a substrate, the interior of the substrate, or the surface of a memory chip, and overlaps with the memory chip. The non-signal wiring includes: a first end electrically connected to a power supply section, a second end electrically connected to a ground wire, and a wiring body connecting the first end and the second end. The wiring body includes a first portion, a second portion folded back from an end of the first portion, and a third portion folded back from an end of the second portion. With this structure, the product lifespan of the semiconductor memory device can be extended.

[0143] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and likewise included in the scope of the invention described in the claims and their equivalents.

[0144] 1: Storage element 11:Substrate 11a, 21a, S1: First page 11b, 21b, S2: Second side 11c: Connector 11e1: First end 11e2: Second end 11e3: Third end 11e4: Fourth end 12: Controller 13: DRAM 14, 14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H, 14I, 14J, 14K, 14L, 14M, 14N, 14P, 14Q: NAND package (semiconductor memory device) (NAND flash memory) 15: Capacitor 21: Packaging substrate (substrate) 21i: Insulating substrate 21p: Power wiring 21s: Signal wiring 21w: Wiring pattern 22a, 22b, 22c, 24s: solder pads 23: Connecting terminal 24, 24A, 24B: Memory chips 25: Adhesive membrane 26, 26A, 26B: Joint lines 27, 27Z: Sealing components 27a: Main body 27b: Cover body 27h: Opening 27ha: Through hole 30: Heating wiring (non-signal wiring) 31: First end 32: Second end 33: Main body of wiring 33a: Part 1 33b: Part Two 33c: Part Three 33d: Part Four 33e: Part Five 41: First solder pad 42: Second solder pad 51: First electrical connection part (electrical connection part) 51A, 51B, 51C, 71: First electrical connection part 52: Second electrical connection part (electrical connection part) 52A, 52B, 52C, 72: Second electrical connection part 61: Connecting wire (first electrical connection part) 62: Connecting wire (second electrical connection part) 73: Electrical connection part 81, 91: Metal Department C: Coil G: Magnetic field lines IH: Induction heating device MP: Memory Planar Region MPa: Memory area MPaa, R1: First Region MPab, R2: Second region [ ] MPb: Wiring area PS: Power supply equipment PSa: Ministry of Electricity Supply PSb: Ground wire S: Distance SB: Stacked body T1, T2, T3, T4: Thickness W1, W2, W3: Wiring width X, Y, Z: Direction

Claims

1. A semiconductor memory device, comprising: The substrate has a first surface; A sealing member that covers the first surface when viewed from the thickness direction of the substrate, i.e., the first direction; A first memory chip is disposed in the first direction between the first surface and the sealing member; non-signal wiring is different from the signal wiring of the semiconductor memory device; And an adhesive film is disposed between the first memory chip and the non-signal wiring. The non-signal wiring is disposed on the first surface of the substrate between the substrate and the first memory chip, and overlaps with the first memory chip when viewed from the first direction. The non-signal wiring has: a first end, which is electrically connected to the power supply unit. The second terminal is electrically connected to the ground wire; The wiring body connects the first end and the second end. The wiring body includes: a first portion extending along a second direction intersecting the first direction; a second portion extending parallel to the first portion from the end of the first portion toward a first side of the second direction; and a third portion extending parallel to the second portion from the end of the second portion toward a second side of the second direction opposite to the first side. The lengths of the first portion, the second portion, and the third portion in the second direction are greater than the length of the first memory chip in the first direction.

2. The semiconductor memory device as claimed in claim 1, wherein, The non-signal wiring is formed by spraying conductive material using an inkjet printer.

3. The semiconductor memory device as claimed in claim 1 or 2, wherein, The substrate has power lines for current flow to supply the first memory chip, and the thickness of the non-signal lines in the first direction is greater than the thickness of the power lines in the first direction.

4. The semiconductor memory device as claimed in claim 1 or 2, wherein, The substrate has power lines for current flow to the first memory chip, and the width of the non-signal lines is larger than the width of the power lines.

5. A semiconductor memory device, comprising: The substrate has a first surface; A sealing member that covers the first surface when viewed from the thickness direction of the substrate, i.e., the first direction; A first memory chip is disposed between the first surface and the sealing member in the first direction; and a non-signal wiring, which is different from the signal wiring of the semiconductor memory device, is disposed on the surface of the sealing member and overlaps with the first memory chip when viewed from the first direction, the non-signal wiring having: a first end electrically connected to a power supply unit; The second terminal is electrically connected to the ground wire; The device includes a wiring body that connects the first end to the second end. The wiring body comprises: a first portion extending along a second direction intersecting the first direction; a second portion extending parallel to the first portion from the end of the first portion toward a first side of the second direction; and a third portion extending parallel to the second portion from the end of the second portion toward a second side of the second direction opposite to the first side. The lengths of the first portion, the second portion, and the third portion in the second direction are greater than the length of the first memory chip in the first direction. The semiconductor memory device includes a plurality of memory chips, the plurality of memory chips including the first memory chip and deposited on the substrate; a first solder pad exposed to the outside of the sealing member and electrically connected to the first end; a second solder pad exposed to the outside of the sealing member and electrically connected to the second end; and a non-signal wiring overlapping a plurality of the plurality of memory chips when viewed from the first direction. The non-signal wiring is located at a position different from the surface of the plurality of memory chips and is disposed on the surface of the sealing member, and is electrically connected to the power supply device disposed above the sealing member via the first solder pad and the second solder pad.

6. The semiconductor memory device as claimed in claim 5, wherein, The plurality of memory chips includes a second memory chip disposed between the first memory chip and the sealing member in the first direction. The first memory chip has: a first region that overlaps with the second memory chip when viewed from the first direction; and a second region that is offset from the second memory chip when viewed from the first direction. When viewed from the first direction, the non-signal wiring overlaps with the first region of the first memory chip, the second region of the first memory chip, and the second memory chip.

7. The semiconductor memory device as claimed in claim 5, wherein, The non-signal wiring is formed by spraying conductive material using an inkjet printer.

8. The semiconductor memory device as claimed in claim 5 or 6, wherein, The substrate has power lines for current flow to supply the first memory chip, and the thickness of the non-signal lines in the first direction is greater than the thickness of the power lines in the first direction.

9. The semiconductor memory device as claimed in claim 5 or 6, wherein, The substrate has power lines for current flow to the first memory chip, and the width of the non-signal lines is larger than the width of the power lines.

10. A semiconductor memory device, comprising: The substrate has a first surface; A sealing member that covers the first surface when viewed from the thickness direction of the substrate, i.e., the first direction; A first memory chip is disposed in the first direction between the first surface and the sealing member; and a non-signal wiring, which is different from the signal wiring of the semiconductor memory device, is disposed inside the substrate and overlaps with the first memory chip when viewed from the first direction, the non-signal wiring having: a first end electrically connected to a power supply unit; The second terminal is electrically connected to the ground wire; The wiring body connects the first end and the second end. The wiring body includes: a first portion extending along a second direction intersecting the first direction; a second portion extending parallel to the first portion from the end of the first portion toward a first side of the second direction; and a third portion extending parallel to the second portion from the end of the second portion toward a second side of the second direction opposite to the first side. The lengths of the first portion, the second portion, and the third portion in the second direction are greater than the length of the first memory chip in the first direction. The non-signal wiring is disposed inside the substrate and is located on the layer closest to the first surface of the substrate.

11. The semiconductor memory device as claimed in claim 10, wherein, The non-signal wiring is formed by spraying conductive material using an inkjet printer.

12. The semiconductor memory device as claimed in claim 10 or 11, wherein, The substrate has power lines for current flow to supply the first memory chip, and the thickness of the non-signal lines in the first direction is greater than the thickness of the power lines in the first direction.

13. The semiconductor memory device as claimed in claim 10 or 11, wherein, The substrate has power lines for current flow to the first memory chip, and the width of the non-signal lines is larger than the width of the power lines.

14. The semiconductor memory device as claimed in claim 1 or 10, further comprising a second memory chip disposed above the first memory chip and arranged in the first direction between the first memory chip and the sealing member, wherein the non-signal wiring overlaps with the second memory chip when viewed from the first direction.

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