Display device

Abstract

The display device includes: a substrate comprising a plurality of pixel regions separated from each other and a plurality of transmissive regions located between the pixel regions, wherein each of the pixel regions comprises a plurality of sub-pixels; and a plurality of signal lines extending on the substrate along a first direction, wherein the sub-pixels comprise a plurality of pixel circuits, and wherein the signal lines overlap the pixel circuits but do not overlap the transmissive regions. Therefore, the pixel regions and the signal lines are located in the same area to reduce the size of the opaque area and increase the size of the transmissive area in the entire display device, thereby realizing a transparent display device.

Description

Technical Field

[0001] This invention relates to transparent display devices, and more particularly to transparent display devices using light-emitting diodes (LEDs). Prior Technology

[0002] As display devices used for screens in computers, televisions, or mobile phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require an independent light source.

[0003] The applications of display devices have diversified to personal digital assistants and computer and television screens, and research is underway on display devices with large display areas and reduced size and weight.

[0004] Furthermore, in recent years, LED-incorporated display devices have garnered attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they offer superior reliability, resulting in a longer lifespan compared to liquid crystal displays or organic light-emitting diode displays. Moreover, LEDs possess fast light emission speed, excellent luminous efficiency, and high shock resistance, leading to excellent stability and the ability to display high-brightness images. Summary of the Invention

[0005] One objective of this invention is to provide a transparent display device with high transmittance.

[0006] Another objective of this invention is to provide a display device in which the size of the transmissive area is maximized.

[0007] Another objective of this invention is to provide a display device in which interference between the driving transistors of the pixel area and multiple data lines is reduced.

[0008] Another objective of this invention is to provide a display device that reduces fluctuations in the voltage and drive current of the driving transistors caused by data lines.

[0009] Another objective of this invention is to provide a display device that reduces the coupling between data lines and driving transistors to improve display quality.

[0010] The purpose of this invention is not limited to the purposes mentioned above, and those skilled in the art to which this invention pertains will clearly understand from the following description any purposes not mentioned above.

[0011] This invention provides a display device according to an independent item. Preferred embodiments are described in the appendices. According to one embodiment of the invention, the display device includes: a substrate including a plurality of pixel regions separated from each other and a plurality of transmissive regions located between the pixel regions; and a plurality of data lines extending on the substrate along a first direction, wherein the pixel regions overlap the data lines, and the data lines do not overlap the transmissive regions. The first direction described herein may be a row direction. The second direction described herein may be a column direction.

[0012] In one embodiment, the display device includes: a substrate including a pixel region and a light-transmitting region that is more transparent than the pixel region; a first insulating layer located on the substrate; a driving transistor located on the first insulating layer in the pixel region; a signal line overlapping the driving transistor in the pixel region; a light-emitting element electrically connected to the driving transistor in the pixel region; and a second insulating layer located between the signal line and the driving transistor in the pixel region, the thickness of the second insulating layer being greater than the thickness of the first insulating layer.

[0013] In one embodiment, the display device includes: a substrate defining a plurality of pixel regions configured to be separated from each other and a plurality of transmissive regions disposed between the pixel regions; and a plurality of lines extending in a row direction on the substrate, wherein the pixel regions overlap areas where the lines are disposed.

[0014] Further details of the exemplary embodiments are included in the implementation methods and figures.

[0015] According to one aspect of the present invention, a transparent display device with improved transmittance can be realized.

[0016] According to another aspect of the invention, the opaque configurations in the display device overlap each other to maximize the size of the transmissive area in the display device. According to some embodiments, opaque pixel areas and multiple lines overlap to maximize the size of the transmissive area.

[0017] According to another aspect of the present invention, voltage fluctuations and drive current fluctuations of the drive transistor caused by the coupling between the data lines and the drive transistor can be reduced.

[0018] According to another aspect of the present invention, crosstalk and brightness variations caused by the coupling of data lines and driving transistors can be reduced.

[0019] The effects of the present invention are not limited to the examples above, and many more effects are included in this specification. Simple Explanation of the Diagram

[0020] The above and other aspects, features, and other advantages of the invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention;

[0022] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present invention;

[0023] Figure 2B is a perspective view of a splicing display device according to an exemplary embodiment of the present invention;

[0024] Figure 3 is a planar enlarged schematic diagram of the active area of ​​a display device according to an exemplary embodiment of the present invention;

[0025] Figure 4 is a planar enlarged view of the active area of ​​a display device according to an exemplary embodiment of the present invention;

[0026] Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present invention;

[0027] Figure 6 shows the simulation results of crosstalk measurement based on the thickness of the insulation layer;

[0028] Figure 7 is a plan view of a display device according to another exemplary embodiment of the present invention;

[0029] Figure 8 is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present invention;

[0030] Figure 9A is a graph obtained by measuring the voltage and drive current of the drive gate electrode based on the data voltage in the display device of the comparative example; and

[0031] Figure 9B is a graph obtained by measuring the voltage and drive current of the drive gate electrode of the data voltage in a display device according to another exemplary embodiment of the present invention. Implementation

[0032] The advantages, features, and implementation methods of the present invention will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the exemplary embodiments disclosed herein and may be implemented in various forms. These exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the invention and its scope.

[0033] The shapes, dimensions, proportions, angles, quantities, etc., illustrated in the accompanying drawings, which are used to describe various exemplary embodiments of the present invention, are merely examples, and the present invention is not limited thereto. Similar symbols throughout the specification generally denote similar elements. Furthermore, in the following description of the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the spirit of the invention. Unless used with the word "only," terms such as "comprising," "having," and "containing" as used herein are generally intended to allow for the addition of other components. Unless explicitly stated otherwise, any singular reference may include the plural.

[0034] Even without explicit description, components are still interpreted as including a general tolerance range.

[0035] When using terms such as “above,” “on top,” “below,” and “beside,” to describe the positional relationship between two parts, one or more parts may be placed between the two parts unless used with the terms “exactly” or “directly.”

[0036] When one element or layer is disposed "on" another element or layer, the element or layer may be directly disposed on the other element or layer, or another element or layer may be disposed between the element or layer and the other element or layer.

[0037] Although terms such as "first" and "second" are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this invention, the first component to be mentioned below may be the second component.

[0038] Similar symbols throughout the instruction manual usually represent similar components.

[0039] The dimensions and thicknesses of the components shown in the drawings are for ease of description, and the present invention is not limited to the dimensions and thicknesses of the components shown.

[0040] The features of various embodiments of the present invention can be partially or entirely coupled or combined with each other, and can be interlocked and operated in various technical ways, and these embodiments can be implemented independently or in association with each other.

[0041] Hereinafter, a display device according to several exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a schematic diagram of a display device 100 according to an exemplary embodiment of the present invention. In Figure 1, for ease of description, the display panel PN, gate driver GD, data driver DD, and timing controller TC are shown among the various components of the display device 100.

[0043] Please refer to Figure 1. The display device 100 includes a display panel PN containing multiple sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0044] The gate driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gate control signals supplied from the timing controller TC. Even though one gate driver GD is shown in Figure 1 set to be separate from one side of the display panel PN, the number of gate drivers GD and their placement are not limited thereto.

[0045] The data driver DD supplies data voltage to multiple data lines DL (e.g., signal lines) based on multiple data control signals and image data supplied from the timing controller TC. The data driver DD uses a reference gamma voltage to convert image data into data voltage and can supply the converted data voltage to these data lines DL.

[0046] The timing controller TC adjusts (aligns) the externally input image data to supply the image data to the data driver DD. The timing controller TC can use externally input synchronization signals to generate gate control signals and data control signals, such as dot clock signals, data enable signals, and horizontal / vertical synchronization signals. Furthermore, the timing controller TC supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD respectively to control the gate driver GD and the data driver DD.

[0047] The display panel PN is configured to display images to the user and includes multiple sub-pixels SP. In the display panel PN, these scan lines SL and these data lines DL intersect each other, and these sub-pixels SP are connected to the scan lines SL and data lines DL at the intersection of the scan lines SL and data lines DL.

[0048] In the display panel PN, the active area AA and the inactive area NA can be defined.

[0049] The active area AA is the area in the display device 100 where an image is displayed. Within the active area AA, multiple sub-pixels SP, each comprising multiple pixels PX, and a pixel circuit (or multiple pixel circuits) for driving these sub-pixels SP can be provided. These sub-pixels SP are the smallest unit for configuring the active area AA, and n sub-pixels SP form one pixel PX (e.g., n=3 or n=4). In each of these sub-pixels SP, a light-emitting diode 120 and a thin-film transistor for driving the light-emitting diode 120 can be provided. These light-emitting diodes 120 of the sub-pixels SP can be defined in different ways depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, each of these light-emitting diodes 120 can be a light-emitting diode (LED) or a micro-light-emitting diode (LED).

[0050] In the active area AA, multiple signal lines are provided to transmit various signals to the sub-pixels SP. For example, these signal lines include multiple data lines DL that supply data voltage to each of the sub-pixels SP and multiple scan lines SL that supply scan signals to each of the sub-pixels SP. The scan lines SL extend in one direction and connect to the sub-pixels SP in the active area AA, and the data lines DL extend in a direction different from the stated direction and connect to the sub-pixels SP in the active area AA. Furthermore, low-potential power lines and high-potential power lines may be further provided in the active area AA, but the present invention is not limited thereto.

[0051] The non-active area NA is a region where no image is displayed, and is thus defined as an area extending from the active area AA. In one embodiment, the non-active area NA surrounds the active area AA in the plan view of the display device. Within the non-active area NA, connection lines, pad electrodes, or driver ICs such as gate driver ICs or data driver ICs may be provided for transmitting signals to the sub-pixels SP of the active area AA.

[0052] Meanwhile, the non-active area NA can be located on the rear surface of the display panel PN, that is, the surface where sub-pixels SP are not set or can be omitted, and is not limited to what is shown in the figure.

[0053] Meanwhile, drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active area NA as an in-board gate (GIP), or installed in the active area AA between these sub-pixels SP as an active area in-gate (GIA).

[0054] For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards, and the display panel PN is electrically connected to the data driver DD and the timing controller TC by bonding the flexible film and the printed circuit board to the pad electrodes formed in the non-active area NA of the display panel PN.

[0055] As another example, when the gate driver GD is mounted in the active area AA in a GIA configuration and has side lines SRL formed connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. Therefore, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN as described above, a borderless zero-bezel configuration can be substantially achieved, which will be described in more detail with reference to Figures 2A and 2B.

[0056] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present invention. Figure 2B is a perspective view of a splicing display device according to an exemplary embodiment of the present invention.

[0057] In the inactive area NA of the display panel PN, multiple pad electrodes are provided for transmitting various signals to these sub-pixels SP. For example, in the inactive area NA on the front surface of the display panel PN, a first pad electrode PAD1 is provided for transmitting signals to these sub-pixels SP. In the inactive area NA on the rear surface of the display panel PN, a second pad electrode PAD2 is provided, electrically connected to driving components such as flexible films and printed circuit boards.

[0058] In this case, even if not shown in the diagram, various signal lines, such as scan lines SL or data lines DL, connected to these sub-pixels SP extend from the active area AA to the inactive area NA and are electrically connected to the first pad electrode PAD1.

[0059] Furthermore, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving components on the rear surface of the display panel PN can be transmitted to these sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Thus, the driving components are disposed on the rear surface of the display panel PN, and the signal transmission path between the front and rear surfaces of the display panel PN is formed to minimize the size of the non-active area NA on the front surface of the display panel PN.

[0060] Furthermore, referring to Figure 2B, a large-screen splicing display device TD can be realized by connecting multiple display devices 100. At this time, as shown in Figure 2A, when the splicing display device TD is implemented using display devices 100 with minimized bezels, the seam area between multiple display devices 100 where no image is displayed is minimized, thereby improving display quality.

[0061] For example, a pixel PX may contain multiple sub-pixels SP, and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another display device 100 adjacent to the one display device can be implemented as equal to the distance D1 between the multiple pixels PX in one display device 100. Therefore, the distance between the multiple pixels PX between multiple display devices 100 is configured to be constant, thereby minimizing the seam area.

[0062] However, Figures 2A and 2B are illustrative, so that the display device 100 according to an exemplary embodiment of the present invention may be a general display device with a bezel, but is not limited thereto.

[0063] Hereinafter, the display panel PN of the display device 100 according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 6.

[0064] Figure 3 is a planar enlarged schematic diagram of a pixel unit in the active area of ​​a display device according to an exemplary embodiment of the present invention. Figure 4 is a planar enlarged view of the active area of ​​a display device according to an exemplary embodiment of the present invention. Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present invention. Figure 6 shows the simulation results of measuring crosstalk based on the thickness of the insulating layer. In Figure 3, for ease of description, only the scan line SL and the data line DL are shown among the multiple lines, and only one pixel area UPA and the multiple transmission areas TA surrounding the one pixel area UPA are shown.

[0065] Referring to Figure 3, in the active region AA, a pixel region UPA with a pixel PX and a plurality of transmissive regions TA surrounding the pixel region UPA are formed. In one embodiment, each transmissive region TA does not have a pixel PX and is more transparent than the pixel region UPA. In each pixel PX of the active region AA, a pixel circuit containing a driving element and a light-emitting diode 120 driven by the pixel circuit are formed, such that these pixel regions UPA with the pixel PX can be substantially opaque. Furthermore, these transmissive regions TA without the pixel PX can be substantially transparent. In this case, the pixel region UPA defined by the pixel PX formed therein is a region that displays light emitted from the light-emitting diode 120, so it is also defined as a light-emitting region. Furthermore, the pixel region UPA defined by the pixel PX formed therein is a region that has a pixel circuit containing a driving element, so it is also defined as a circuit region.

[0066] Within the active area AA, multiple pixel areas UPA are formed. Each of these pixel areas UPA is an area equipped with a driving element and a light-emitting diode 120 to display an image. These pixel areas UPA can be configured to be separated from each other, and multiple transmissive areas TA are located between these pixel areas UPA. For example, these pixel areas UPA can be configured by forming multiple columns and multiple rows.

[0067] Multiple sub-pixels SP are disposed in each of these pixel regions UPA. Each of these sub-pixels SP includes a light-emitting diode 120 and pixel circuitry for independent light emission. For example, these sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit different colors of light. For example, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but the invention is not limited thereto.

[0068] The following description assumes that a pixel PX contains two first sub-pixels SP1, two second sub-pixels SP2, and two third sub-pixels SP3. That is, for example, it contains two red sub-pixels, two green sub-pixels, and two blue sub-pixels, but the configuration of pixel PX is not limited to this.

[0069] Simultaneously, a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3 can be used as primary sub-pixels SP and redundant sub-pixels SP, respectively. For example, one of the first sub-pixels SP1 in the pair of first sub-pixels SP1, one of the second sub-pixels SP2 in the pair of second sub-pixels SP2, and one of the third sub-pixels SP3 in the pair of third sub-pixels SP3 can be the primary sub-pixels SP used substantially when the display device 100 is driven. When displaying an image, according to one embodiment, the primary sub-pixels SP can be used. Furthermore, the remaining first sub-pixels SP1 in the pair of first sub-pixels SP1, the remaining second sub-pixels SP2 in the pair of second sub-pixels SP2, and the remaining third sub-pixels SP3 in the pair of third sub-pixels SP3 can be redundant sub-pixels SP, so that when the primary sub-pixels SP are defective, the redundant sub-pixels SP can be used to replace the primary sub-pixels.

[0070] Furthermore, the placement order of the primary subpixel SP can be configured to be the same as the placement order of the redundant subpixel SP. For example, the subpixels SP forming the primary subpixel SP are arranged in the order of first subpixel SP1, second subpixel SP2, and third subpixel SP3. Similarly, the subpixels SP forming the redundant subpixel SP can also be arranged in the order of first subpixel SP1, second subpixel SP2, and third subpixel SP3.

[0071] However, the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 are not limited to the primary sub-pixels SP and the redundant sub-pixels SP, and all sub-pixels can always be used while driving the display device 100. Furthermore, the placement order of the sub-pixels SP is not limited to the aforementioned placement order.

[0072] The pixel region UPA can overlap lines extending in the row direction, such as data lines DL and reference lines RL. In this specification, the row direction may be referred to as the first direction. The pixel region UPA is formed in an area provided with multiple opaque lines to ensure the size of the transmissive area TA in the entire active area AA. Specifically, due to the arrangement of pixel circuits and light-emitting diodes 120 provided in these sub-pixels SP, the pixel region UPA with these sub-pixels SP has low transmittance and is essentially opaque. Therefore, these sub-pixels SP of the pixel region UPA can be configured to overlap opaque lines extending in the row direction, such as data lines DL, reference lines RL, low-potential power lines VSS, and high-potential power lines VDD. Thus, these sub-pixels SP of the pixel region UPA are configured to overlap these lines to reduce the size of the opaque area in the entire active area AA and maximize the size of the transmissive area TA.

[0073] The subpixels SP disposed in a pixel region UPA can be formed to have either a rectangular shape or an "L" shape in the plan view of the display device. For example, a first subpixel SP1 (e.g., a first primary subpixel), a second subpixel SP2 (e.g., a second primary subpixel), and a third subpixel SP3 (e.g., a third primary subpixel) are disposed on one side (e.g., the first side) of the scan line SL, and a first subpixel SP1 (e.g., a first redundant subpixel), a second subpixel SP2 (e.g., a second redundant subpixel), and a third subpixel SP3 (e.g., a second redundant subpixel) can be disposed on the other side (e.g., the second side) of the scan line SL. In one embodiment, the first primary subpixel SP1 and the first redundant subpixel SP1 emit light of a first color, the second primary subpixel SP2 and the second redundant subpixel SP2 emit light of a second color, and the third primary subpixel SP3 and the third redundant subpixel SP3 emit light of a third color.

[0074] On one side and the other side of the scanning line SL, a first sub-pixel SP1 is disposed in a rectangular region, and a second sub-pixel SP2 is disposed in an L-shaped region consisting of two adjacent sides of the four sides surrounding the first sub-pixel SP1. Furthermore, a third sub-pixel SP3 may be disposed in an L-shaped region surrounding the L-shaped second sub-pixel SP2. Therefore, a pixel region UPA configured with the first sub-pixel SP1 having a rectangular shape and the second and third sub-pixels SP2 and SP3 having L-shaped shapes can collectively form a rectangular shape. In one embodiment, the second sub-pixel SP2 is located between the first sub-pixel SP1 and the third sub-pixel SP3 in the plan view of the display device.

[0075] Each of these transmissive regions TA excludes the active regions AA from the areas where these lines and pixel regions UPA are located. That is, each transmissive region TA can be an area of ​​the active regions AA without these lines. In other words, the transmissive regions TA may not contain any lines, pixel circuits, or light-emitting diodes. The light transmittance of these transmissive regions TA is higher than that of these pixel regions UPA. Light passes through the transmissive regions TA, and the background located on the rear surface of the display device 100 is visible from the front surface of the display device 100. These transmissive regions TA can be separated from each other, and the lines and pixel regions UPA are located between these transmissive regions TA. These transmissive regions TA can be configured to surround these pixel regions UPA. Therefore, the display device 100 according to an exemplary embodiment of the present invention can be implemented as a transparent display device 100 comprising a plurality of transmissive regions TA.

[0076] Referring to Figures 3 to 5, each of these sub-pixels SP includes a pixel circuit and one or more light-emitting diodes 120. The pixel circuit includes multiple transistors T1, T2, DT and a storage capacitor Cst to supply driving current to the light-emitting diode 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor DT and a storage capacitor Cst. Furthermore, these sub-pixels SP disposed in a pixel area UPA are connected to the scan line SL, the data lines DL, the reference line RL, the high-potential power line VDD and the low-potential power line VSS to be supplied with various signals.

[0077] First, the substrate 110 is a component used to support various parts included in the display device 100 and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. Furthermore, the substrate 110 may be configured to contain polymers or plastics, or may be formed of a flexible material.

[0078] A light-shielding layer LS is disposed on the substrate 110 in each of these sub-pixels SP. The light-shielding layer LS blocks light incident from below the substrate 110 onto the driving active layer DACT of the driving transistor DT, as will be described below. The light incident onto the driving active layer DACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize leakage current.

[0079] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but the present invention is not limited thereto.

[0080] The driving transistor DT, the first transistor T1, and the second transistor T2 are disposed on the buffer layer 111 in each of these sub-pixels SP.

[0081] The driving transistors DT, T1, and T2 of each of these sub-pixels SP can be p-type or n-type thin-film transistors. For example, in a p-type thin-film transistor, since holes move from the source electrode to the drain electrode, current flows from the source electrode to the drain electrode. In an n-type thin-film transistor, since electrons move from the source electrode to the drain electrode, current flows from the drain electrode to the source electrode. Hereinafter, the description assumes that the driving transistor DT, T1, and T2 are p-type thin-film transistors in which current flows from the source electrode to the drain electrode, but the present invention is not limited thereto.

[0082] First, driving transistors DT are disposed in each of these sub-pixels SP on buffer layer 111. Driving transistor DT is a transistor that controls the driving current supplied to the light-emitting diode 120. In a pixel region UPA, the driving transistors DT of each of these sub-pixels SP can be arranged in a straight line along the row direction. These driving transistors DT of these sub-pixels SP can be arranged in a straight line while overlapping the areas where reference lines RL and data lines DL are disposed.

[0083] The driving transistor DT includes the driving active layer DACT, the driving gate electrode DGE, the driving source electrode DSE, and the driving drain electrode DDE.

[0084] The active driving layer DACT is disposed on the buffer layer 111. The active driving layer DACT may be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0085] A gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer that insulates the driving active layer DACT from the driving gate electrode DGE. The gate insulating layer 112 may be configured as a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0086] The driving gate electrode DGE is disposed on the gate insulating layer 112. The driving gate electrode DGE may be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0087] A first interlayer insulating layer 113a is disposed on the driving gate electrode DGE. A contact hole for contact between the driving source electrode DSE and the driving active layer DACT is formed in the first interlayer insulating layer 113a. The first interlayer insulating layer 113a is an insulating layer protecting the components beneath it. The first interlayer insulating layer 113a may be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0088] The driving source electrode DSE is disposed on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through contact holes formed in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the driving source electrode DSE can be electrically connected to the second transistor T2. The driving source electrode DSE can be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0089] The second interlayer insulating layer 113b is disposed on the drive source electrode DSE. The second interlayer insulating layer 113b is an insulating layer that protects the components below it. The second interlayer insulating layer 113b may be configured as a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0090] A first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer that protects the components below the first passivation layer 114a. The first passivation layer 114a may be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0091] The drive drain electrode (DDE) is disposed on the first passivation layer 114a. The drive drain electrode (DDE) is electrically connected to the drive active layer (DACT) through contact holes formed in the first passivation layer 114a, the first interlayer insulating layer 113a, the second interlayer insulating layer 113b, and the gate insulating layer 112. Furthermore, the drive drain electrode (DDE) can be electrically connected to the low-potential power line (VSS) through contact holes formed in the first passivation layer 114a. The drive drain electrode (DDE) can be configured from a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the aforementioned metals, but is not limited thereto.

[0092] Next, a first transistor T1 is disposed in each of these sub-pixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits the data voltage Vdata to the drive gate electrode DGE of the drive transistor DT and is referred to as a switching transistor. At this time, these first transistors T1 of these sub-pixels SP are arranged to overlap the scan line SL and the protrusion of the scan line SL in a pixel area UPA, and can be arranged as a straight line along the column direction. In this specification, the column direction may be referred to as the second direction.

[0093] Specifically, the scan line SL extends along the column direction on the gate insulating layer 112 and can be configured to pass through these pixel regions UPA. In this case, the scan line SL may include portions protruding towards the sub-pixels SP in the regions overlapping the pixel regions UPA. The portion protruding to one side of the scan line SL may include a portion extending along the row direction and a portion extending along the column direction from the end of the portion extending along the row direction. That is, the scan line SL may further include a protrusion comprising a portion protruding from the scan line SL and extending at least partially along the column direction. For example, the portion protruding from one side of the scan line SL may be formed in an L-shape. Furthermore, the portion protruding from the other side of the scan line SL may include a portion extending along the row direction.

[0094] Furthermore, the first transistors T1 of these sub-pixels SP located on one side of the scan line SL can be configured as a straight line along a portion of the protrusion of the scan line SL extending in the column direction. Furthermore, the first transistors T1 of these sub-pixels SP located on the other side of the scan line SL can be configured as a straight line along the scan line SL extending in the column direction. Therefore, the first transistors T1 located on one side of the scan line SL are configured as a straight line along the column direction on the protrusion of the scan line SL, and the first transistors T1 located on the other side of the scan line SL can be configured as a straight line along the column direction on the scan line SL. The scan line SL is divided into two branches in a pixel region UPA, making it easy to separate the first transistors T1 of the primary sub-pixel SP and the first transistors T1 of the redundant sub-pixel SP. Therefore, the primary sub-pixel SP and the redundant sub-pixel SP are connected to different first transistors T1 to be driven.

[0095] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0096] The first active layer ACT1 is disposed between the buffer layer 111 and the gate insulating layer 112. The first active layer ACT1 may be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0097] The first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 can be electrically connected to the scanning line SL. For example, the first gate electrode GE1 can be integrally formed with the scanning line SL. The first gate electrode GE1 can be configured as a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0098] The first drain electrode DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through contact holes formed in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the first drain electrode DE1 can be electrically connected to the second gate electrode GE2 of the second transistor T2 through contact holes in the first interlayer insulating layer 113a. The first drain electrode DE1 can be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0099] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through contact holes formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. Furthermore, the first source electrode SE1 can be electrically connected to the data line DL. For example, the first source electrode SE1 can be integrally formed with the data line DL. The first source electrode SE1 can be configured from a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0100] Next, a second transistor T2 is disposed in each of these sub-pixels SP on the buffer layer 111. The second transistor T2 is a transistor used to compensate the threshold voltage of the driving transistor DT and is referred to as a sensing transistor. The second transistors T2 of these sub-pixels SP can be configured as a straight line along a portion of the protrusion of the scan line SL extending in the row direction. For example, the second transistors T2 of these sub-pixels SP located on one side of the scan line SL are configured to correspond to a portion of the protrusion of the scan line SL extending in the row direction. The second transistors T2 of these sub-pixels SP located on the other side of the scan line SL can be configured to correspond to the protrusion of the scan line SL. Therefore, these second transistors T2 disposed in a pixel region UPA can be configured as a straight line in the row direction.

[0101] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0102] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0103] At this point, the second active layer ACT2 of these adjacent sub-pixels SP can be connected to each other. For example, the second active layer ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on one side of the scan line SL is connected to each other, extends along the row direction, and is connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. Furthermore, the second active layer ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on the other side of the scan line SL is connected to each other, extends along the row direction, and is connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. That is, the connection portion of the channel region of the second active layer ACT2 connecting these sub-pixels SP and the reference line RL is formed of the transparent material of the second active layer ACT2, rather than an opaque conductive material. Therefore, the transmittance at the outermost edge of the pixel region UPA can be improved. Furthermore, since the connection portion of the channel region of the second active layer ACT2 connecting these sub-pixels SP and the reference line RL is formed of the material of the second active layer ACT2, contact holes can be omitted and the structure of the pixel region UPA can be simplified.

[0104] The second gate electrode GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 can be electrically connected to the scanning line SL. For example, the second gate electrode GE2 can be integrally formed with a protrusion of the scanning line SL to be electrically connected. The second gate electrode GE2 can be configured as a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0105] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through contact holes in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the second source electrode SE2 is integrally formed with the driving source electrode DSE and is electrically connected to the driving source electrode DSE. The second source electrode SE2 may be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0106] The second drain electrode DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through contact holes formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 is integrally formed with the reference line RL and electrically connected to the reference line RL. The second drain electrode DE2 may be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0107] Next, a storage capacitor Cst is disposed on the gate insulating layer 112. While the light-emitting diode 120 emits light, the storage capacitor Cst stores the potential difference between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT, thereby supplying a constant driving current to the light-emitting diode 120. The storage capacitor Cst includes a first capacitor electrode C1 electrically connected to the driving gate electrode DGE and a second capacitor electrode C2 electrically connected to the driving source electrode DSE. Therefore, the storage capacitor Cst can constantly maintain the voltage of the driving gate electrode DGE and the driving source electrode DSE.

[0108] Specifically, the first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 is integrally formed with the driving gate electrode DGE. The second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 can be configured to overlap, and the first interlayer insulating layer 113a is located between the first capacitor electrode C1 and the second capacitor electrode C2. In this case, the second capacitor electrode C2 is integrally formed with the driving source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 can be configured as a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but the present invention is not limited thereto.

[0109] Next, an auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode used to electrically connect the driving source electrode DSE and the first reflecting electrode RE1. The driving source electrode DSE and the first reflecting electrode RE1 are electrically connected to each other via the auxiliary electrode AE. The auxiliary electrode AE ​​may be configured as a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0110] A low-potential power line (VSS) is disposed on the second interlayer insulating layer 113b. The VSS is disposed along the row direction and overlaps these pixel regions UPA. The VSS can be electrically connected to the drive drain electrode (DDE). The VSS can be configured as a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0111] A reference line RL is disposed on the first passivation layer 114a. In one embodiment, the reference line RL overlaps the driving transistor DT. The reference line RL is disposed along the row direction and overlaps these pixel regions UPA. The reference line RL is configured adjacent to the protrusions of the scan line SL and is electrically connected to the second transistors T2 disposed on the protrusions of the scan line SL. The reference line RL may be configured as a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys of the above metals, but is not limited thereto.

[0112] Multiple data lines DL are disposed on the first passivation layer 114a. These data lines DL extend along the row direction and overlap the pixel regions UPA. These data lines DL include data lines DL connected to the first transistor T1 of the first sub-pixels SP1, data lines DL connected to the first transistor T1 of the second sub-pixels SP2, and data lines DL connected to the first transistor T1 of the third sub-pixels SP3. In one embodiment, as shown in FIG5, each data line DL overlaps with the corresponding driving transistor DT.

[0113] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b is an insulating layer protecting the components below it, and can be configured as a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0114] A first planarization layer 115a is disposed on a second passivation layer 114b. The first planarization layer 115a can planarize the upper part of the substrate 110 on which these transistors and storage capacitors Cst are disposed. The first planarization layer 115a can be configured as a single layer or a double layer, for example, it can be formed of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0115] Furthermore, even if not shown in the figures, an additional passivation layer may be further disposed on the first planarization layer 115a. For example, a passivation layer configured as a single or double layer of silicon oxide SiOx or silicon nitride SiNx may be formed on the first planarization layer 115a to protect the configuration beneath the passivation layer.

[0116] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. These first reflective electrodes RE1 are disposed in each of the sub-pixels SP to electrically connect the driving transistor DT and the light-emitting diode 120 and to reflect light emitted from the light-emitting diode 120 to the outside of the display device 100. These first reflective electrodes RE1 may be disposed adjacent to the driving source electrode DSE in each of the sub-pixels SP. These first reflective electrodes RE1 may be formed of an opaque conductive material with high reflectivity, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys of the aforementioned metals, but the present invention is not limited thereto.

[0117] The second reflective electrode RE2 and the high-potential power line VDD are disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high-potential power line VDD are integrally formed to reflect light emitted from the light-emitting diode 120 to the outside of the display device 100, while simultaneously supplying a high-potential power voltage to the light-emitting diode 120. The second reflective electrodes RE2 of these sub-pixels SP are interconnected and integrally formed. The second reflective electrode RE2 and the high-potential power line VDD extend along the row direction and overlap the light-emitting diode 120. The second reflective electrode RE2 and the high-potential power line VDD can be configured to overlap the data lines DL, reference lines RL, and low-potential power lines VSS. The second reflective electrode RE2 and the high-potential power line VDD can be formed of an opaque conductive material with high reflectivity, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys of the above metals, but the present invention is not limited thereto.

[0118] A third passivation layer 114c is disposed on the first reflective electrodes RE1 and the second reflective electrodes RE2. The third passivation layer 114c is an insulating layer that protects the components below the third passivation layer 114c, and may be configured as a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0119] An adhesive layer AD is disposed on the third passivation layer 114c. The adhesive layer AD is formed on the front surface of the substrate 110 to fix the light-emitting diode 120 disposed on the adhesive layer AD. The adhesive layer AD can be formed from a photocurable adhesive material that is cured by light. For example, the adhesive layer AD can be selected from any one of adhesive polymers, epoxy resins, UV resins, polyimides, acrylates, polyurethanes, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0120] These light-emitting diodes 120 are disposed in each of the sub-pixels SP on the adhesive layer AD. Each light-emitting diode 120 is a device that emits light by means of electric current. Furthermore, each light-emitting diode 120 can be a red light-emitting diode 120R that emits red light, a green light-emitting diode 120G that emits green light, or a blue light-emitting diode 120B that emits blue light. Various colors of light, including white, can be implemented by combining these light-emitting diodes 120, such as a combination of red light-emitting diode 120R, green light-emitting diode 120G, and blue light-emitting diode 120B. For example, each light-emitting diode 120 can be a light-emitting diode (LED) or a micro LED, but is not limited to these.

[0121] A red light-emitting diode 120R can be disposed in the first sub-pixel SP1, a green light-emitting diode 120G can be disposed in the second sub-pixel SP2, and a blue light-emitting diode 120B can be disposed in the third sub-pixel SP3. These light-emitting diodes 120 disposed in a pixel region UPA can be arranged in a straight line along the row direction. Furthermore, these light-emitting diodes 120 can be configured to overlap a second reflective electrode RE2 in each of these sub-pixels SP.

[0122] Simultaneously, when these sub-pixels SP are divided into primary sub-pixels SP and redundant sub-pixels SP as described above, these light-emitting diodes 120 can also be divided into primary light-emitting diodes 120 and redundant light-emitting diodes 120. For example, one of a pair of first sub-pixels SP1, one of a pair of second sub-pixels SP2, and one of a pair of third sub-pixels SP3 are primary sub-pixels SP. Therefore, the red light-emitting diode 120R, the green light-emitting diode 120G, and the blue light-emitting diode 120B disposed in each primary sub-pixel SP can be primary light-emitting diodes 120. For example, the other of the pair of first sub-pixels SP1, the other of the pair of second sub-pixels SP2, and the other of the pair of third sub-pixels SP3 are redundant sub-pixels SP. Therefore, the red light-emitting diode 120R, the green light-emitting diode 120G, and the blue light-emitting diode 120B disposed in each redundant sub-pixel SP can be redundant light-emitting diodes 120.

[0123] Each of these light-emitting diodes 120 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0124] A first semiconductor layer 121 is disposed on the adhesive layer AD, and a second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 can be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers doped with n-type and p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurities can be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurities can be silicon (Si), germanium (Ge), tin (Sn), etc., but are not limited thereto.

[0125] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light-emitting layer 122 can be formed from a single layer or a multiple quantum well (MQW) structure, for example, it can be formed from indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0126] A first electrode 124 is disposed on a first semiconductor layer 121. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be configured with a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys of the aforementioned metals, but is not limited thereto.

[0127] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects the high-potential power supply line VDD to the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys of the above metals, but is not limited thereto.

[0128] Next, the encapsulation film 126 is configured to surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes exposing the first electrode 124 and the second electrode 125 are formed in the encapsulation film 126 to electrically connect the first connecting electrode CE1 and the second connecting electrode CE2 to the first electrode 124 and the second electrode 125, respectively.

[0129] Simultaneously, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126 (in other words, this portion of the side surface may not be covered by the encapsulation film 126). During the manufacturing process of the display device 100, the light-emitting diode 120 fabricated on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light-emitting diode 120 from the wafer, a portion of the encapsulation film 126 may be torn. For example, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting diode 120 may be torn during the process of separating the light-emitting diode 120 from the wafer. Therefore, a portion of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. Even if the lower portion of the light-emitting diode 120 is exposed from the encapsulation film 126, the first connection electrode CE1 and the second connection electrode CE2 will still be formed after the formation of the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121. Therefore, short-circuit defects can be reduced or prevented.

[0130] Next, the second planarization layer 115b and the third planarization layer 115c are disposed on the adhesive layer AD and the light-emitting diode 120.

[0131] The second planarization layer 115b overlaps a portion of the side surfaces of the light-emitting diodes 120 to secure and protect them. Tearing portions of the encapsulation film 126 protecting the side surfaces of the first semiconductor layer 121 of the light-emitting diodes 120 can be covered by the second planarization layer 115b. This subsequently suppresses contact and short-circuit defects between the connection electrodes and the first semiconductor layer 121.

[0132] The third planarization layer 115c is formed to cover the second planarization layer 115b and the upper part of the light-emitting diode 120. Contact holes exposing the first electrode 124 and the second electrode 125 of the light-emitting diode 120 are formed in the third planarization layer 115c. The first electrode 124 and the second electrode 125 of the light-emitting diode 120 are exposed from the third planarization layer 115c (in other words, at least a portion of the first electrode 124 and at least a portion of the second electrode 125 may not be covered by the third planarization layer 115c), and the third planarization layer 115c is partially disposed in the region between the first electrode 124 and the second electrode 125 to reduce short-circuit defects. The second planarization layer 115b and the third planarization layer 115c may be configured as a single layer or a double layer, for example, they may be formed from a photoresist or an acrylic-based organic material, but the invention is not limited thereto.

[0133] The first connecting electrode CE1 and the second connecting electrode CE2 are disposed on the third planarization layer 115c.

[0134] The first connecting electrode CE1 is an electrode that electrically connects the first electrode 124 of the light-emitting diode 120 and the driving transistor DT. The first connecting electrode CE1 is electrically connected to the first electrode 124 exposed from the third planarization layer 115c, and simultaneously electrically connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Therefore, the first electrode 124 and the driving source electrode DSE can be electrically connected through the first connecting electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0135] The second connecting electrode CE2 is an electrode that electrically connects the second electrode 125 of the light-emitting diode 120 and the high-potential power line VDD. The second connecting electrode CE2 is electrically connected to the second electrode 125 exposed from the third planarization layer 115c. Furthermore, the second connecting electrode CE2 is electrically connected to the second reflecting electrode RE2 and the high-potential power line VDD through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Therefore, the second electrode 125 and the high-potential power line VDD are electrically connected through the second connecting electrode CE2.

[0136] The first connecting electrode CE1 and the second connecting electrode CE2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0137] Meanwhile, the diagram shows the driving source electrode DSE of the driving transistor DT and the first electrode 124 of the light-emitting diode 120 electrically connected. However, the driving drain electrode DDE of the driving transistor DT and the second electrode 125 of the light-emitting diode 120 may be electrically connected depending on the type of driving transistor DT and the design of the pixel circuit.

[0138] Next, in the pixel region UPA, a dam BB is disposed on the third planarization layer 115c, the first connecting electrode CE1, and the second connecting electrode CE2. The dam BB can be configured to be separated from the light-emitting diode 120 by a predetermined interval. The dam BB is disposed at the boundary between these sub-pixels SP and covers a portion of the first connecting electrode CE1 and the second connecting electrode CE2. The dam BB can be configured to be separated from the transmissive region TA. The dam BB can be formed of an opaque material to reduce color mixing between these sub-pixels SP, for example, it can be formed of black resin, but is not limited thereto.

[0139] A protective layer 116 is disposed on the first connecting electrode CE1, the second connecting electrode CE2, and the embankment BB. The protective layer 116 is a layer configured to protect the material disposed beneath it. The protective layer 116 can be configured as a single layer or a double layer, for example, it can be formed of benzocyclobutene (BCB), a translucent epoxy resin, a photoresist, an acrylic-based organic material, or an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0140] Simultaneously, to expand the size of the transmissive area TA, these sub-pixels SP can be configured to overlap these lines. In this case, driving current fluctuations may occur in each of these sub-pixels SP due to some lines. For example, the driving transistor DT and storage capacitor Cst of each of these sub-pixels SP overlap the data line DL to couple to the data line DL. As shown in Figure 5, the data line DL overlaps at least one of the driving source electrode DSE, driving gate electrode DGE, or driving active layer DACT. In this case, the voltage of the driving gate electrode DGE may fluctuate due to the data line applying different voltages in each frame. When the voltage of the driving gate electrode DGE fluctuates, the driving current flowing through the light-emitting diode 120 fluctuates and brightness changes due to crosstalk, thereby degrading the display quality.

[0141] Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the thickness of the insulating layer is adjusted by considering the permittivity of the insulating layer disposed between the storage capacitor Cst and the driving transistor DT and the data line DL. Thus, voltage fluctuations in the driving gate electrode DGE caused by the data line DL can be reduced. For example, the inorganic insulating layer disposed on the substrate 110, i.e., the insulating layer such as the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a, and the second passivation layer 114b, can be formed to have a thickness of several thousand angstroms (Å). However, the thickness of the first passivation layer 114a and the second interlayer insulating layer 113b, which are the insulating layers disposed between the data line DL and the storage capacitor Cst, is different from the thickness of the other insulating layers and is at least several micrometers (µm). This minimizes voltage fluctuations in the driving transistor DT caused by the data line DL. Therefore, the thickness of the insulating layer between the data line DL and the storage capacitor Cst can be greater than the thickness of the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a, and the second passivation layer 114b.

[0142] Referring to Figure 6, when the width of the data line DL is 1 µm, the thickness of the insulating layer can be determined by the material and dielectric constant of the insulating layer disposed beneath the data line DL. Increasing the thickness of the insulating layer reduces the degree of brightness variation caused by crosstalk. In this case, when the insulating layer is formed of silicon nitride (SiNx) with a dielectric constant of approximately 6.69 and the target crosstalk is 2%, the thickness of the insulating layer will be approximately 16.55 µm or greater to control the degree of brightness variation caused by crosstalk below 2%. Similarly, when the insulating layer is formed of silicon oxide (SiOx) with a dielectric constant of approximately 4.3 and the target crosstalk is 2%, the thickness of the insulating layer will be approximately 10.64 µm or greater to control the degree of brightness variation caused by crosstalk below 2%. Therefore, when the width of the data line DL is 1 µm, the overall thickness of the first passivation layer 114a and the second interlayer insulation layer 113b will be formed to be at least 10.64 µm or greater, in order to minimize the voltage fluctuations of the driving transistor DT and the storage capacitor Cst connected to the driving transistor DT caused by the data line DL. Furthermore, when the width of the data line DL increases, a thicker insulation layer may be required to achieve the same level of crosstalk.

[0143] Therefore, considering the width of the data line DL, the dielectric constants of the first passivation layer 114a and the second interlayer insulating layer 113b, and the target crosstalk level, the overall thickness of the first passivation layer 114a and the second interlayer insulating layer 113b can be determined. Furthermore, the drive current can be kept constant, while minimizing interference between the data line DL and the drive transistor DT and the storage capacitor Cst connected to the drive transistor DT.

[0144] In the display device 100 according to an exemplary embodiment of the present invention, these pixel regions UPA are disposed in areas provided with a plurality of lines extending in the row direction, so as to maximize the size of the transmissive region TA. The pixel regions UPA, which are substantially opaque and include pixel circuitry and a light-emitting diode 120, are disposed together with the opaque lines to reduce the size of the opaque area in the active region AA. For example, data lines DL and / or reference lines RL (as an example of opaque lines extending in the row direction) may be disposed to overlap with the light-emitting diode 120 in a plan view of the display device 100. For example, data lines DL and / or reference lines RL may be disposed between the light-emitting diode 120 and the thin-film transistors (e.g., driving transistors DT) and / or storage capacitors Cst of the pixel circuitry in a cross-sectional view of the display device 100. Therefore, the size of the transmissive region TA is maximized to improve the overall transmittance of the display device 100 and to achieve a transparent display device 100.

[0145] In the display device 100 according to an exemplary embodiment of the present invention, voltage fluctuations of the driving transistor DT caused by the data line DL can be at least reduced or minimized. When the data line DL and the pixel region UPA are formed to overlap in order to ensure the size of the transmissive region TA, the configuration of the data line DL and the pixel region UPA may couple, thereby causing voltage fluctuations. For example, the data line DL of the overlapping driving transistor DT and storage capacitor Cst may therefore couple to the driving transistor DT and storage capacitor Cst, and the voltage of the driving transistor DT and storage capacitor Cst may fluctuate, causing brightness fluctuations and potentially degrading display quality. Therefore, the insulating layer between the data line DL and the driving transistor DT and storage capacitor Cst is formed to be thick to at least reduce or minimize the influence of the data line DL. At this time, the thickness of the insulating layer can be determined by taking into account the dielectric constant of the insulating layer, the width of the data line DL, and the target crosstalk level. Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the thickness of the insulating layer between the data line DL and the driving transistor DT is formed to be relatively thick. Therefore, fluctuations in drive current caused by data line DL are minimized or at least reduced, and display quality is improved.

[0146] Figure 7 is a plan view enlarged of a display device according to another exemplary embodiment of the present invention. Figure 8 is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present invention. Figure 9A is a graph obtained by measuring the voltage and drive current of the driving gate electrode according to the data voltage in the display device according to the comparative example. Figure 9B is a graph obtained by measuring the voltage and drive current of the driving gate electrode according to the data voltage in the display device according to another exemplary embodiment of the present invention. In the display panel PN' of Figures 7 and 8, only the low-potential power line VSS differs from the display panel PN of Figures 1 to 5, while the other configurations are substantially the same, therefore redundant descriptions will be omitted.

[0147] Referring to Figures 7 and 8, the low-potential power line VSS is configured to overlap the data lines DL located between the second interlayer insulating layer 113b and the first passivation layer 114a. The low-potential power line VSS can overlap the area where these data lines DL are located. The low-potential power line VSS has a relatively large width, such that one low-potential power line VSS and these data lines DL overlap. The low-potential power line VSS can cover the storage capacitor Cst and driving transistor DT of these sub-pixels SP'. Only the low-potential power line VSS is located between the second interlayer insulating layer 113b and the first passivation layer 114a, so that the low-potential power line VSS can be easily formed in the remaining area, which excludes the area where contact holes are located.

[0148] In a low-potential power line VSS, overlapping contact hole openings can be formed. For example, in a low-potential power line VSS, overlapping contact holes for connecting the first source electrode SE1 and the first active layer ACT1, and contact holes for connecting the drive drain electrode DDE and the drive active layer DACT can be formed. The first source electrode SE1 and the drive drain electrode DDE are disposed on the low-potential power line VSS, and the first active layer ACT1 and the drive active layer DACT are disposed below the low-potential power line VSS. Therefore, openings are formed in the low-potential power line VSS to facilitate connection to configurations connected to the upper and lower parts of the low-potential power line VSS.

[0149] A low-potential power line VSS is disposed between the storage capacitor Cst and the data lines DL, and between the driving transistor DT and the data lines DL, to act as a barrier film to block voltage fluctuations in the driving transistor DT caused by the data lines DL. A low-potential power line VSS with a constant voltage is disposed between the storage capacitor Cst, the driving transistor DT, and the data lines DL to suppress coupling between the data lines DL, the storage capacitor Cst, and the driving transistor DT. The low-potential power line VSS is configured to at least cover the driving gate electrode DGE of the driving transistor DT to protect the voltage DTG of the driving gate electrode DGE from fluctuations caused by the data lines DL.

[0150] The following description, with reference to Figures 9A and 9B, will illustrate the effectiveness of expanding the low-potential power line VSS.

[0151] Referring to Figure 9A, the display panel 10 according to the comparative example has a structure in which a low-potential power line VSS is not disposed between the data line DL and the driving transistor DT. In the display panel 10 according to the comparative example, since individual blocking films are not disposed between the data line DL and the driving transistor DT, it has been confirmed that the voltage DTG of the driving gate electrode DGE fluctuates according to the voltage fluctuation of the data line DL. It has also been confirmed that when the voltage DTG of the driving gate electrode DGE fluctuates, the driving current ILED flowing through the light-emitting diode 120 also fluctuates. In this case, the brightness fluctuates, which may degrade the display quality.

[0152] Referring to Figure 9B, in a display panel PN' according to another exemplary embodiment of the present invention, a low-potential power line VSS, serving as a barrier film, is disposed between the data line DL and the driving transistor DT, and between the data line DL and the storage capacitor Cst. Therefore, even if the voltage of the data line DL fluctuates, the voltage DTG of the driving gate electrode DGE and the driving current ILED can remain constant. Thus, brightness remains constant, and display quality is improved.

[0153] In a display panel PN' according to another exemplary embodiment of the present invention, a low-potential power line VSS is formed between the data lines DL and the driving transistor DT to minimize voltage fluctuations in the driving transistor DT caused by the data lines DL. The low-potential power line VSS can be configured to cover the driving transistor DT and the storage capacitor Cst located beneath these data lines DL. The low-potential power line VSS, which always maintains a constant voltage, can prevent the data lines DL from interfering with the driving transistor DT and the storage capacitor Cst. In this case, the voltage DTG of the driving gate electrode DGE and the driving current ILED can be kept constant without the need to form a thick insulating layer between these data lines DL and the driving transistor DT and the storage capacitor Cst. Furthermore, instead of forming individual barrier films, the size of the existing low-potential power line VSS is increased to correspond to the area where these data lines DL are disposed, thereby using the low-potential power line VSS as a barrier film. Furthermore, the manufacturing process of the display panel PN' can be simplified. Therefore, in a display panel PN' according to another exemplary embodiment of the present invention, the low-potential power line VSS is formed with an increased size to overlap all of these data lines DL. Therefore, the driving current ILED of the sub-pixel SP' remains stable and constant, improving the reliability of the display panel PN'.

[0154] Meanwhile, in related technologies, the primary and redundant light-emitting diodes are housed together in a single sub-pixel, and are connected in parallel within a pixel circuit. In this case, the first and second electrodes of the primary and redundant light-emitting diodes are connected to the same node, i.e., the same electrodes. When a short-circuit defect occurs in the light-emitting diode or the pixel circuit in this structure, both the primary and redundant light-emitting diodes, which are connected in parallel and share a specific electrode, darken, resulting in a defect. Furthermore, it is difficult to separate and repair only the defective light-emitting diode.

[0155] Conversely, in the display panels PN, PN' according to various exemplary embodiments of the present invention, as described above, these sub-pixels SP, SP' are divided into main sub-pixels SP, SP' containing a main light-emitting diode 120 and redundant sub-pixels SP, SP' containing a redundant light-emitting diode 120. Furthermore, the main light-emitting diode 120 of the main sub-pixels SP, SP' and the redundant light-emitting diode 120 of the redundant sub-pixels SP, SP' can be driven independently. That is, pixel circuits for driving the main light-emitting diode 120 and pixel circuits for driving the redundant light-emitting diode 120 can be formed separately. For example, an L-shaped protrusion is further formed in the scan line SL extending along the column direction. One of the first transistor T1 for driving the main light-emitting diode 120 and the first transistor T1 for driving the redundant light-emitting diode 120 is formed on the scan line SL, and the other is formed on the L-shaped protrusion. Therefore, a first transistor T1 for driving the primary light-emitting diode 120 and a first transistor T1 for driving the redundant light-emitting diode 120 can be formed separately. Therefore, protrusions are further formed in the scanning line SL to individually form the first transistor T1 for driving the primary light-emitting diode 120 and the first transistor T1 for driving the redundant light-emitting diode 120, and to individually drive the primary light-emitting diode 120 and the redundant light-emitting diode 120. Therefore, in the display panels PN, PN' according to various exemplary embodiments of the present invention, the primary light-emitting diode 120 and the redundant light-emitting diode 120 are connected to different pixel circuits. Therefore, a defect in a specific sub-pixel SP or SP' will not affect another sub-pixel SP or SP', and only the defective sub-pixel SP or SP' can be easily detected and repaired.

[0156] Exemplary embodiments of the present invention can also be described as follows:

[0157] According to one aspect of the present invention, a display device includes: a substrate defining a plurality of pixel regions that are configured to be separated from each other and a plurality of transmissive regions disposed between the pixel regions, and a plurality of data lines extending in a row direction on the substrate. The pixel regions overlap areas of the data lines.

[0158] The display device may further include multiple sub-pixels disposed in each of these pixel areas. These sub-pixels may include a first sub-pixel with a rectangular shape, a second sub-pixel on two adjacent sides of the four sides surrounding the first sub-pixel, and a third sub-pixel surrounding the outer portion of the second sub-pixel, and the first sub-pixel, the second sub-pixel and the third sub-pixel may form a rectangular shape.

[0159] The display device may further include scan lines extending on the substrate in a column direction passing through these pixel areas. The sub-pixels of each of these pixel areas may be formed by a first sub-pixel, a second sub-pixel and a third sub-pixel disposed on one side of the scan line and a first sub-pixel, a second sub-pixel and a third sub-pixel disposed on the other side (e.g., opposite side) of the scan line.

[0160] Each of these sub-pixels may further include: a first transistor disposed between the data lines and the substrate and electrically connected to the data lines; a driving transistor disposed between the data lines and the substrate and electrically connected to the first transistor; a second transistor disposed between the data lines and the substrate and electrically connected to the driving transistor; a storage capacitor disposed between the data lines and the substrate and electrically connected to the gate electrode of the driving transistor; and a light-emitting diode disposed on the data lines and electrically connected to the driving transistor.

[0161] In one of these pixel regions, the first transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be set as a straight line along the column direction.

[0162] In one of these pixel regions, the scan line may include a protrusion that protrudes from the scan line and extends at least partially along the column direction. A first transistor of a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed on one side of the scan line may be disposed on the protrusion of the scan line, and a first transistor of a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed on the other side of the scan line may be disposed on the scan line.

[0163] In one of these pixel regions, the second transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be set as a straight line along the row direction.

[0164] In one of these pixel regions, the driving transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be set as a straight line along the row direction.

[0165] In one of these pixel regions, the light-emitting diodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be set as a straight line along the row direction.

[0166] These data lines can be placed on the driving transistors and storage capacitors, and the driving transistors and storage capacitors can be overlapped.

[0167] The display device may further include: a buffer layer disposed between a substrate and a driving transistor; a gate insulating layer disposed on the buffer layer between a driving gate electrode of the driving transistor and a driving active layer; a first interlayer insulating layer covering the driving transistor; and one or more insulating layers covering a storage capacitor on the first interlayer insulating layer. These data lines may be disposed on one or more insulating layers, and the thickness of the one or more insulating layers may be greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

[0168] The display device may further include low-potential power lines disposed between the storage capacitors and these data lines. The low-potential power lines may overlap the areas where these data lines are disposed.

[0169] Low-potential power lines can be used to drive transistors and storage capacitors in parallel.

[0170] The driving active layer of the driving transistor and the first active layer of the first transistor can be disposed below the low-potential power line. The driving drain electrode of the driving transistor and the first source electrode of the first transistor can be disposed on the low-potential power line. The low-potential power line can include multiple openings. The multiple openings overlap to provide contact holes for connecting the driving active layer and the driving drain electrode, and to provide contact holes for connecting the first active layer and the first source electrode.

[0171] According to another aspect of the present invention, the display device may include: a substrate comprising a plurality of pixel regions separated from each other and a plurality of transmissive regions located between the pixel regions, wherein each of the pixel regions comprises a plurality of sub-pixels; and a plurality of signal lines extending on the substrate along a first direction, wherein the sub-pixels comprise a plurality of pixel circuits, wherein the signal lines overlap the pixel circuits but do not overlap the transmissive regions.

[0172] Each sub-pixel may include a light-emitting diode, and each signal line of these signal lines may be configured to overlap with at least one of these light-emitting diodes in a plan view of the display device.

[0173] Each pixel circuit may include a thin-film transistor and a storage capacitor, wherein each signal line of these signal lines may be disposed between at least one of the light-emitting diodes and at least one of the thin-film transistors and / or storage capacitors in a cross-sectional view of the display device.

[0174] These transmissive areas can be configured to be directly adjacent to these pixel areas.

[0175] The display device may further include: a scanning line extending on a substrate in a second direction through the pixel regions, the second direction being different from the first direction, wherein the sub-pixels of each of the pixel regions may include a first primary sub-pixel, a second primary sub-pixel, and a third primary sub-pixel located on a first side of the scanning line, and a first redundant sub-pixel, a second redundant sub-pixel, and a third redundant sub-pixel located on a second side of the scanning line, wherein the first primary sub-pixel and the first redundant sub-pixel emit light of a first color, the second primary sub-pixel and the second redundant sub-pixel emit light of a second color, and the third primary sub-pixel and the third redundant sub-pixel emit light of a third color.

[0176] These signal lines may include at least one of multiple data lines and multiple reference lines.

[0177] Each of these sub-pixels may further include: a first transistor, located between a data line and a substrate from these data lines, the first transistor being electrically connected to the data line; a driving transistor, located between the data line and the substrate, the driving transistor being electrically connected to the first transistor; a second transistor, located between the data line and the substrate, the second transistor being electrically connected to the driving transistor; a storage capacitor, located between the data line and the substrate, the storage capacitor being electrically connected to the gate electrode of the driving transistor; and a light-emitting diode, located on the data line, the light-emitting diode being electrically connected to the driving transistor.

[0178] In one of these pixel regions, the first transistor of the first sub-pixel, the first transistor of the second sub-pixel, and the first transistor of the third sub-pixel can be set as a straight line along a second direction different from the first direction.

[0179] In a pixel region, a scan line may include a protrusion that extends from the scan line along a first direction and at least partially extends along a second direction. A first transistor of a first primary sub-pixel, a first transistor of a second primary sub-pixel, and a first transistor of a third primary sub-pixel located on a first side of the scan line may be located on the protrusion of the scan line. A first transistor of a first redundant sub-pixel, a first transistor of a second redundant sub-pixel, and a first transistor of a third redundant sub-pixel located on a second side of the scan line may be located on the scan line. The first primary sub-pixel and the first redundant sub-pixel may emit light of a first color, the second primary sub-pixel and the second redundant sub-pixel may emit light of a second color, and the third primary sub-pixel and the third redundant sub-pixel may emit light of a third color.

[0180] In one of these pixel regions, the second transistor of the first sub-pixel, the second transistor of the second sub-pixel, and the second transistor of the third sub-pixel can be set as a straight line along the first direction.

[0181] In one of these pixel regions, the driving transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be configured as a straight line along a first direction.

[0182] In one of these pixel regions, the light-emitting diodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be set as a straight line along a first direction.

[0183] These signal lines can be located on top of the driving transistors and storage capacitors, and can overlap the driving transistors and storage capacitors.

[0184] The display device may further include: a buffer layer located between a substrate and a driving transistor; a gate insulating layer located on the buffer layer, the gate insulating layer being located between the driving active layer and the driving gate electrode of the driving transistor; a first interlayer insulating layer covering the driving transistor; and one or more insulating layers covering a storage capacitor on the first interlayer insulating layer, wherein the signal lines may be located on the one or more insulating layers, and the thickness of the one or more insulating layers may be greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

[0185] The display device may further include: power lines located between the storage capacitors and these signal lines, the power lines overlapping the signal lines.

[0186] The power supply line may include or may be a low-potential power supply line or a high-potential power supply line.

[0187] The power supply lines can overlap to drive transistors and storage capacitors.

[0188] The driving active layer of the driving transistor and the first active layer of the first transistor can be located below the power line, the driving drain electrode of the driving transistor and the first source electrode of the first transistor can be located on the power line, and the power line can include multiple openings, the openings overlapping contact holes for connecting the driving active layer and the driving drain electrode and contact holes for connecting the first active layer and the first source electrode.

[0189] The display device may include reference lines that extend on a substrate along a first direction and overlap the pixel areas.

[0190] The reference line may not overlap with these transmission zones.

[0191] The reference circuit may overlap with at least one of these light-emitting diodes in the plan view of the display device.

[0192] Reference circuitry may be disposed between at least one of the light-emitting diodes and at least one of the driving transistors and / or storage capacitors in a cross-sectional view of the display device.

[0193] The reference circuit can be electrically connected to the second transistor, and the reference circuit can be set at the same level as the data circuit.

[0194] The reference circuit can be integrally formed with the second drain electrode of the second transistor.

[0195] These sub-pixels may include: a first sub-pixel having a rectangular shape in a plan view of the display device; a second sub-pixel having two adjacent sides of the four sides surrounding the first sub-pixel in the plan view; and a third sub-pixel having the outer portion surrounding the second sub-pixel in the plan view, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel together form a rectangular shape.

[0196] According to another aspect of the present invention, the display device may include: a substrate including a pixel region and a light-transmitting region that is more transparent than the pixel region; a driving transistor located in the pixel region; a power line located above the driving transistor in the pixel region; a signal line located above the power line in the pixel region; and a light-emitting element located in the pixel region, the light-emitting element being electrically connected to the driving transistor.

[0197] The driving transistor may include a gate electrode, a source electrode, a drain electrode, and an active layer, and the signal lines may overlap at least one of the source electrode, the gate electrode, or the active layer.

[0198] In the cross-sectional view, the signal line can be located between and overlap the driver transistor and the power supply line.

[0199] The signal line can be a data line configured to supply data voltage.

[0200] The display device may include a first insulating layer located on a substrate.

[0201] The display device may include a second insulating layer located between the signal lines and the driving transistors.

[0202] The first insulating layer may be located between the substrate and the driving transistor, or between driving transistors of different layers, or between the driving transistor and the second insulating layer.

[0203] The thickness of the second insulating layer can be greater than the thickness of the first insulating layer.

[0204] The first insulating layer may include at least one of the following: a buffer layer located between the substrate and the driving transistor, a gate insulating layer located between the gate electrode of the driving transistor and the active layer, or a first interlayer insulating layer covering the driving transistor.

[0205] The power supply line can be an overlay signal line and a low-potential power supply line for driving transistors.

[0206] The display device may further include: a scan line located in the pixel area, the scan line including a first portion protruding from the scan line along a first direction and a second portion extending at least partially in the pixel area along a second direction different from the first direction.

[0207] The pixel area may include multiple primary sub-pixels located on the first side of the second part of the scan line and multiple redundant sub-pixels located on the second side of the second part of the scan line.

[0208] These principal sub-pixels may include a first principal sub-pixel configured to emit light of a first color, a second principal sub-pixel configured to emit light of a second color, and a third principal sub-pixel configured to emit light of a third color, and these redundant sub-pixels may include a first redundant sub-pixel configured to emit light of a first color, a second redundant sub-pixel configured to emit light of a second color, and a third redundant sub-pixel configured to emit light of a third color, wherein each of these principal sub-pixels and each of these redundant sub-pixels may include a corresponding pixel driving circuit.

[0209] According to another aspect of the present invention, the display device may include: a substrate defining a plurality of pixel regions configured to be separated from each other and a plurality of transmissive regions disposed between the pixel regions; and a plurality of data lines extending in a row direction on the substrate, wherein the pixel regions overlap the areas of the data lines.

[0210] The circuit may include one or more data circuits, reference circuits, low-potential power supply circuits, and high-potential power supply circuits.

[0211] In the plan view of the display device, at least one of these lines may overlap with the light-emitting diode and / or thin-film transistor of the pixel circuit disposed in the pixel area.

[0212] In a cross-sectional view of the display device, at least one of these lines may be disposed between the light-emitting diode and the thin-film transistor of the pixel circuit disposed in the pixel area.

[0213] Although several exemplary embodiments of the invention have been described in detail with reference to the accompanying drawings, the invention is not limited thereto and may be practiced in many different forms without departing from the technical concept of the invention. Therefore, the various exemplary embodiments of the invention are provided for illustrative purposes only and are not intended to limit the technical concept of the invention. The scope of the technical concept of the invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the invention.

[0214] 10: Display Panel 100: Display device 110:Substrate 111: Buffer layer 112: Gate insulation layer 113a: First interlayer insulation layer 113b: Second interlayer insulation layer 114a: First passivation layer 114b: Second passivation layer 114c: Third passivation layer 115a: First planarization layer 115b: Second planarization layer 115c: Third planarization layer 116: Protective layer 120: Light Emitting Diode 120B: Blue Light Emitting Diode 120G: Green Light Emitting Diode 120R: Red light-emitting diode 121: First semiconductor layer 122: Emissive Layer 123: Second semiconductor layer 124: First electrode 125: Second electrode 126: Encapsulation film AA: Active Zone ACT1: First Active Layer ACT2: Second Active Layer AD: Adhesive layer AE: Auxiliary electrode BB: Embankment C1: First capacitor electrode C2: Second capacitor electrode CE1: First connecting electrode CE2: Second connecting electrode Cst: Storage capacitor D1: Distance DACT: Driver Active Layer DD: Data Drive DDE: Driven Drain Electrode DE1: First drain electrode DE2: Second drain electrode DGE: Drive gate electrode DL: Data Line DSE: Drive source electrode DT, T1, T2: Transistors DTG: Voltage GD: Gate Driver GE1: First gate electrode GE2: Second gate electrode ILED: Drive Current LS: Light-shielding layer NA: Non-active zone PAD1: First pad electrode PAD2: Second pad electrode PN,PN': Display panel PX: pixel RE1: First reflective electrode RE2: Second reflective electrode RL: Reference Line SE1: First source electrode SE2: Second source electrode SL: Scanning Line SP,SP': Subpixels SP1: First sub-pixel SP2: Second subpixel SP3: Third subpixel SRL: Side Line TA: Transmission zone TC: Timing Controller TD: Video Wall Display Device UPA: Pixel Area VDD: High-potential power line Vdtata: Data voltage VSS: Low-potential power line

Claims

1. A display device comprising: a substrate including a plurality of pixel regions separated from each other and a plurality of transmissive regions located between the pixel regions, wherein each of the pixel regions includes a plurality of sub-pixels; and a plurality of signal lines extending on the substrate along a first direction, wherein the signal lines include a plurality of data lines, wherein the sub-pixels include a plurality of pixel circuits, wherein the signal lines overlap the pixel circuits but do not overlap the transmissive regions, wherein each of the sub-pixels further includes: a first transistor located on a data line from the data lines. Between the circuit and the substrate, the first transistor is electrically connected to the data circuit; a driving transistor is located between the data circuit and the substrate, and is electrically connected to the first transistor; a second transistor is located between the data circuit and the substrate, and is electrically connected to the driving transistor; a storage capacitor is located between the data circuit and the substrate, and is electrically connected to a gate electrode of the driving transistor; and a light-emitting diode is located on the data circuit, and is electrically connected to the driving transistor.

2. The display device as claimed in claim 1 further comprises: a scanning line extending on the substrate along a second direction passing through the pixel regions, the second direction being different from the first direction, wherein each of the sub-pixels in the pixel regions includes a first primary sub-pixel, a second primary sub-pixel, and a third primary sub-pixel located on a first side of the scanning line, and a first redundant sub-pixel, a second redundant sub-pixel, and a third redundant sub-pixel located on a second side of the scanning line, wherein the first primary sub-pixel and the first redundant sub-pixel emit light of a first color, the second primary sub-pixel and the second redundant sub-pixel emit light of a second color, and the third primary sub-pixel and the third redundant sub-pixel emit light of a third color.

3. The display device as claimed in claim 1, wherein the signal lines include a plurality of reference lines.

4. The display device as claimed in claim 3, wherein in one of the pixel regions, the first transistor of a first sub-pixel, the first transistor of a second sub-pixel, and the first transistor of a third sub-pixel are arranged as a straight line along a second direction different from the first direction.

5. The display device as claimed in claim 4, wherein in the single pixel region, a scan line includes a protrusion that projects from the scan line along the first direction and extends at least partially along the second direction, a first transistor of a first primary sub-pixel, a first transistor of a second primary sub-pixel, and a first transistor of a third primary sub-pixel located on a first side of the scan line are located on the protrusion of the scan line, and a first transistor of a first redundant sub-pixel, a first transistor of a second redundant sub-pixel, and a first transistor of a third redundant sub-pixel located on a second side of the scan line are located on the scan line, wherein the first primary sub-pixel and the first redundant sub-pixel are configured to emit light of a first color, the second primary sub-pixel and the second redundant sub-pixel are configured to emit light of a second color, and the third primary sub-pixel and the third redundant sub-pixel are configured to emit light of a third color.

6. The display device as claimed in claim 3, wherein in one of the pixel regions, the second transistor of a first sub-pixel, the second transistor of a second sub-pixel, and the second transistor of a third sub-pixel are arranged as a straight line along the first direction.

7. The display device as claimed in claim 3, wherein in one of the pixel regions, the driving transistor of a first sub-pixel, the driving transistor of a second sub-pixel, and the driving transistor of a third sub-pixel are arranged as a straight line along the first direction.

8. The display device as claimed in claim 3, wherein in one of the pixel regions, the light-emitting diode of a first sub-pixel, the light-emitting diode of a second sub-pixel, and the light-emitting diode of a third sub-pixel are arranged as a straight line along the first direction.

9. The display device as claimed in claim 3, wherein the signal lines are located on and overlap the driving transistor and the storage capacitor.

10. The display device as claimed in claim 3, further comprising: a buffer layer located between the substrate and the driving transistor; a gate insulating layer located on the buffer layer, the gate insulating layer being located between a driving active layer and a driving gate electrode of the driving transistor; a first interlayer insulating layer covering the driving transistor; and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer, wherein the signal lines are located on the one or more insulating layers, and the thickness of the one or more insulating layers is greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

11. The display device as claimed in claim 3 further comprises: a power line located between the storage capacitor and the signal lines, the power line overlapping the signal lines.

12. The display device as claimed in claim 11, wherein the power line comprises a low-potential power line or a high-potential power line.

13. The display device as claimed in claim 11, wherein the power line overlaps the driving transistor and the storage capacitor.

14. The display device as claimed in claim 12, wherein a driving active layer of the driving transistor and a first active layer of the first transistor are located below the power line, a driving drain electrode of the driving transistor and a first source electrode of the first transistor are located on the power line, and the power line includes a plurality of openings overlapping contact holes for connecting the driving active layer and the driving drain electrode and contact holes for connecting the first active layer and the first source electrode.

15. The display device as claimed in claim 3, wherein the reference lines are electrically connected to the second transistor, and the reference lines and the data lines are disposed at the same level.

16. The display device as claimed in claim 15, wherein the reference lines are integrally formed with a second drain electrode of the second transistor.

17. The display device as claimed in claim 1, wherein the sub-pixels comprise: a first sub-pixel having a rectangular shape in a plan view of the display device; a second sub-pixel having two adjacent sides of four sides surrounding the first sub-pixel in the plan view; and a third sub-pixel having an outer portion surrounding the second sub-pixel in the plan view, and wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel together form a rectangular shape.

18. A display device comprising: a substrate including a pixel region and a light-transmitting region that is more transparent than the pixel region; a driving transistor located in the pixel region; a power line located in the pixel region on the driving transistor; a signal line located in the pixel region on the power line; and a light-emitting element located in the pixel region, the light-emitting element being electrically connected to the driving transistor.

19. The display device as claimed in claim 18, wherein in a cross-sectional view, the signal line is located between the driving transistor and the power line, and overlaps the driving transistor and the power line.

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