Wafer structure and chip structure

Abstract

A wafer structure includes a substrate, dicing channels, a wafer wiring pattern, and a peripheral metal pattern. The dicing channels define wafer cells on the substrate. The wafer wiring pattern is disposed in a central region of the wafer cell. The peripheral metal pattern is disposed in a peripheral region of the wafer cell, surrounding the central region. The peripheral metal pattern includes a sealing ring pattern surrounding the central region and an alignment pattern disposed between the dicing channels and the sealing ring pattern.

Description

Technical Field

[0001] This disclosure relates to a wafer structure and a chip structure. Prior Technology

[0002] Generally, integrated circuits consist of multiple layers with different patterns, each formed through a photolithography process. Furthermore, features on successive patterned layers are spatially related to other features. Therefore, during fabrication, each patterned layer must be aligned with the previous patterned layer. To achieve this, the substrate or dielectric layer formed thereon typically has multiple alignment marks (also called alignment targets) to determine the position of previously exposed patterns using the positions of these alignment marks.

[0003] Traditional pattern alignment technology typically involves forming alignment (or identification) marks on the dicing track of each die. However, in order to increase production capacity, the dicing tracks on the wafer are gradually reduced to increase the number of dies per wafer. But this approach can easily lead to the alignment marks being cut into the dicing track during wafer dicing, resulting in the metal layer of the alignment marks being exposed and affecting the appearance. Summary of the Invention

[0004] This disclosure provides a wafer structure in which the position of the alignment pattern does not affect the appearance of the product after the dicing process, and can effectively reduce the dicing width of the wafer, thereby increasing the wafer production capacity of each wafer.

[0005] This disclosure discloses a wafer structure including a substrate, dicing channels, a wafer wiring pattern, and a peripheral metal pattern. The dicing channels define wafer cells on the substrate. The wafer wiring pattern is disposed in the central region of the wafer cell. The peripheral metal pattern is disposed in the peripheral region of the wafer cell, surrounding the central region. The peripheral metal pattern includes a sealing ring pattern surrounding the central region and an alignment pattern disposed between the dicing channels and the sealing ring pattern.

[0006] In one embodiment of this disclosure, the sealing ring pattern includes a chamfer to create a corner area in the wafer cell, and the alignment pattern is disposed within the corner area created by the chamfer.

[0007] In one embodiment of this disclosure, the alignment pattern and the sealing ring pattern are spaced apart by a first distance.

[0008] In one embodiment of this disclosure, the outer edge of the alignment pattern is spaced a second distance from the inner edge of the cutting path.

[0009] In one embodiment of this disclosure, the peripheral metal pattern further includes a plurality of dummy metal pads, evenly distributed between the sealing ring pattern and the alignment pattern.

[0010] In one embodiment of this disclosure, the outer edge of the alignment pattern is substantially collinear with the outer edge of the corresponding sealing ring pattern.

[0011] In one embodiment of this disclosure, viewed from the top view, the alignment pattern does not overlap with the cutting path.

[0012] In one embodiment of this disclosure, the alignment pattern and the sealing ring pattern are disposed on the same plane.

[0013] In one embodiment of this disclosure, the wafer circuit pattern is electrically insulated from the surrounding metal pattern.

[0014] In one embodiment of this disclosure, the alignment pattern is L-shaped, square-shaped, cross-shaped, Z-shaped, or hourglass-shaped.

[0015] In one embodiment of this disclosure, the sealing ring pattern comprises a plurality of sealing ring pattern layers disposed on the substrate in an overlapping manner.

[0016] In one embodiment of this disclosure, the alignment pattern includes a plurality of alignment pattern layers stacked on the substrate, and each layer is disposed in the same layer as the corresponding plurality of sealing ring pattern layers.

[0017] In one embodiment of this disclosure, the sealing ring pattern includes an inner sealing ring pattern surrounding the central region and an outer sealing ring pattern surrounding the inner sealing ring pattern.

[0018] In one embodiment of this disclosure, the alignment pattern is disposed between the cutting channel and the outer sealing ring pattern.

[0019] This disclosure discloses a wafer structure including a substrate, a wafer circuit pattern, and a peripheral metal pattern. The substrate includes a central region and a peripheral region surrounding the central region. The wafer circuit pattern is disposed in the central region. The peripheral metal pattern is disposed in the peripheral region and includes a sealing ring pattern surrounding the wafer circuit pattern and an alignment pattern disposed outside the closed area enclosed by the sealing ring pattern.

[0020] In one embodiment of this disclosure, the alignment pattern is disposed between the outer edge of the wafer structure and the sealing ring pattern.

[0021] In one embodiment of this disclosure, the sealing ring pattern has a chamfer at the corner corresponding to the substrate, and the alignment pattern is disposed at the corner where the chamfer is vacated.

[0022] This disclosure discloses a wafer structure including a substrate, dicing channels, a wafer, a sealing ring, and alignment marks. The dicing channels define wafer cells on the substrate. Wafers are disposed within the wafer cells. The sealing ring surrounds the wafer and is located between the dicing channels and the wafer. Alignment marks are disposed between the dicing channels and the sealing ring.

[0023] Based on the above, the wafer structure disclosed herein places the alignment pattern within the area enclosed by the dicing kerf and outside the closed area enclosed by the sealing ring pattern. This avoids the problem of the metal layer being exposed and affecting the wafer's appearance when the alignment pattern on the dicing kerf is cut during the wafer dicing process. Furthermore, since there is no need to worry about cutting the alignment pattern during the wafer dicing process, the width of the dicing kerf can be further reduced, allowing for a denser arrangement of wafer cells on the wafer, thereby increasing the number of diced dies and increasing the wafer throughput per wafer. Simple Explanation of the Diagram

[0024] Figure 1 is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 2 is a partially enlarged schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 3A is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 3B is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 4 is a partially enlarged schematic diagram of a wafer cell of a wafer structure according to an embodiment of the present disclosure. Figure 5 is a top view schematic diagram of the alignment pattern of a wafer structure according to an embodiment of the present disclosure. Figure 6 is a top view schematic diagram of the alignment pattern of a wafer structure according to different embodiments of the present disclosure. Figure 7A is a partial cross-sectional schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 7B is a partial cross-sectional schematic diagram of a wafer structure according to an embodiment of the present disclosure. Implementation

[0025] The foregoing descriptions and other technical contents, features, and effects of this invention will be clearly presented in the following detailed descriptions of various embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "up," "down," "front," "back," "left," and "right," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention. Furthermore, in the following embodiments, the same or similar elements will be represented by the same or similar reference numerals.

[0026] Figure 1 is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 2 is a partially enlarged schematic diagram of a wafer structure according to an embodiment of the present disclosure. Figure 3A is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Referring to Figures 1 to 3A, in some embodiments, the wafer structure 100 includes a substrate 110. The substrate 110 may be formed of silicon, germanium (Ge), or other suitable semiconductor materials. In some embodiments, the substrate 110 may be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium gallium phosphide (InP). In some embodiments, the substrate 110 is made of a compound semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide. In some other embodiments, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some examples, substrate 110 may include a doped epitaxial layer. In some examples, the silicon substrate may include a multilayer composite semiconductor structure. Alternatively, wafer structure 100 may include a non-semiconductor material, such as a glass substrate, quartz, or a suitable material like calcium fluoride. In some embodiments, the thickness of substrate 110 may be greater than about 500 micrometers (μm).

[0027] In some embodiments, the wafer structure 100 may include a substrate 110, dicing 130, wafer wiring patterns 122, and peripheral metal patterns 124. The substrate 110 has a front surface and a back surface opposite to the front surface, and the dicing 130 defines a plurality of wafer cells 120 on the substrate 110. Specifically, as shown in Figures 1 and 2, the plurality of wafer cells 120 are defined on the front surface of the substrate 110 via the dicing 130. Generally, the wafer structure 100 serves as a manufacturing carrier during wafer production. After the semiconductor process is completed, a plurality of wafer cells 120 are formed on the wafer structure 100. Subsequently, these wafer cells 120 are separated by a wafer dicing or monolithization process to form a plurality of separate wafer structures 120 (the diced wafer structures 120 may be as shown in Figure 3A). The monolithization process may include mechanical dicing or laser dicing to cut the area between the individual wafer cells 120 along the dicing 130. That is, the dicing 130 is the area between adjacent wafer cells 120. In some embodiments, the cut channel 130 does not have any functional means. In some embodiments, the cut channel 130 does not contain metal; for example, the cut channel 130 does not include any metal layer or metal structure. In some embodiments, the cut channel 130 may include a plurality of test pads (not shown) for testing purposes.

[0028] Figure 3A is a top view of a wafer cell according to an embodiment of the present disclosure. Figure 4 is a partially enlarged view of a wafer cell according to an embodiment of the present disclosure. Referring simultaneously to Figures 3A and 4, in some embodiments, the wafer cell 120 may include a central region C1 and a peripheral region P1 surrounding the central region C1. A wafer wiring pattern 122 is disposed in the central region C1, while a peripheral metal pattern 124 is disposed in the peripheral region P1 to surround the wafer wiring pattern 122, and the wafer wiring pattern 122 and the peripheral metal pattern 124 are electrically insulated from each other. It should be noted that the above-mentioned orientation terms, such as central region C1 and peripheral region P1, are relative terms, and the central region C1 is not necessarily located at the center of the wafer cell 120. The elements of the present disclosure can be positioned in many different orientations. Therefore, the orientation terms are for illustrative purposes and are not restrictive in any way.

[0029] In some embodiments, the central region C1 may also be referred to as the active region of the wafer, which may consist of multiple elements, such as active and passive elements located on the substrate 110. The central region C1 includes most of the high-density active circuitry of the wafer unit 120, namely the wafer circuit pattern 122. Specifically, the wafer circuit pattern 122 may include multiple layers, such as an active layer for defining the active region of the integrated circuit, a polysilicon layer for defining the gate region of the integrated circuit, a contact layer for defining the contact between the active region and the polysilicon region, an implantation layer, a metal layer, and / or other suitable layers. The multilayer wafer circuit pattern 122 can form various elements, including passive elements such as resistors, capacitors, and inductors, active elements such as MOSFETs, CMOS, high-voltage transistors, and / or high-frequency transistors, other suitable elements, and / or combinations of the above elements. Initially, these elements formed on the substrate 110 can be isolated from each other, and then interconnected through a multilayer metal interconnect structure to form a functional circuit. Typical interconnect structures include lateral interconnects (such as metal wires or conductors) and vertical interconnects (such as vias and contacts).

[0030] Figure 3B is a top view schematic diagram of a wafer structure according to an embodiment of the present disclosure. Referring to Figures 2 and 3B, in this embodiment, from a structural perspective, a dicing 130 defines a plurality of wafer units 120 on the wafer structure, wherein each wafer unit 120 includes a wafer 121, a sealing ring (i.e., a sealing ring pattern) 1241, and an alignment mark (i.e., an alignment pattern) 1242. Specifically, the plurality of wafer units 120 are defined on the front surface of the substrate 110 via the dicing 130. Generally, the wafer structure 100 serves as a manufacturing carrier during wafer production. After the semiconductor process is completed, a plurality of wafer units 120 are formed on the wafer structure 100. That is, the dicing 130 is the region between adjacent wafer units 120. Wafers 121 are respectively formed within the wafer units 120 defined by the dicing 130, and each wafer 121 includes the aforementioned wafer line pattern 122. In some embodiments, wafer 121 may include multiple components, such as active and passive components located on substrate 110. Specifically, wafer 121 may include a multilayer wafer pattern 122, such as an active layer defining the active region of an integrated circuit, a polysilicon layer defining the gate region of an integrated circuit, a contact layer defining the contact between the active region and the polysilicon region, an implantation layer, a metal layer, and / or other suitable layers. The multilayer wafer pattern 122 can form various components, including passive components such as resistors, capacitors, and inductors, active components such as MOSFETs, CMOSs, high-voltage transistors, and / or high-frequency transistors, other suitable components, and / or combinations of the above components. Initially, these components formed on substrate 110 may be isolated from each other, and then interconnected through a multilayer metal interconnect structure to form a functional circuit. Typical interconnect structures include lateral interconnects (e.g., metal lines or wires) and vertical interconnects (e.g., vias and contacts). A sealing ring 1241 surrounds the wafer 121 and is located between the dicing channel 130 and the wafer 121, while an alignment pattern 1242 is disposed between the dicing channel 130 and the sealing ring 1241.

[0031] In some embodiments, as shown in FIG4, the peripheral metal pattern 124 of the wafer unit 120 includes a sealing ring pattern 1241 surrounding the central region C1 and an alignment pattern 1242 disposed between the dicing channel 130 and the sealing ring pattern 1241. Specifically, the alignment pattern 1242 is disposed within the area enclosed by the dicing channel 130 and outside the closed area enclosed by the sealing ring pattern 1241. Therefore, viewed from the top view direction shown in FIG4, the alignment pattern 1242 does not overlap with the dicing channel 130. It should be noted that since the dicing channel 130 is removed during the wafer dicing process, for the diced wafer structure 120 (as shown in FIG3A), the alignment pattern 1242 is disposed in the area outside the closed area enclosed by the sealing ring pattern 1241. In other words, the alignment pattern 1242 is disposed between the outer edge of the wafer structure 120 and the sealing ring pattern 1241.

[0032] In this embodiment, the top layer of the wafer circuit pattern 122 may include multiple pads, which may include multiple active metal pads and multiple dummy metal pads. The dummy metal pads have no electrical function. The active metal pads are electrically connected to active components on the substrate via pad vias and interconnect structures. The dummy metal pads are electrically insulated from the components in the wafer structure 120. That is, the dummy metal pads may be electrically floating. In some embodiments, the active metal pads and dummy metal pads have the same top view shape, size, and / or contain the same material. Furthermore, the active metal pads and dummy metal pads are formed simultaneously. In alternative embodiments, the active metal pads and dummy metal pads have different top view shapes and / or different top view sizes.

[0033] As shown in Figure 3A, a sealing ring pattern 1241 surrounds the edge of the wafer wiring pattern 122. The sealing ring pattern 1241 forms a barrier against moisture, corrosive gases, and chemicals entering the wafer wiring pattern 122, and protects it from damage caused by cracking, stress, etc., induced by cutting tools. The sealing ring pattern 1241 can typically be formed of a conductive material similar to pads (active metal pads and dummy metal pads), such as aluminum (Al), aluminum-copper (Al-Cu) alloys, or aluminum-copper-silicon (Al-Cu-Si) alloys. In some embodiments, the width of the sealing ring pattern 1241 in the top view is approximately 10 μm, but this disclosure is not limited thereto.

[0034] In some embodiments, the sealing ring pattern 1241 includes a chamfer A1 to create a corner area R1 in the wafer unit 120, and the alignment pattern 1242 is disposed within the corner area R1 created by the chamfer A1. For example, viewed from the top view, the wafer unit 120 may be a rectangle with four corners, and the sealing ring pattern 1241 may have chamfers A1 corresponding to these four corners, making it an octagon as shown in FIG. 3A, to create four corners of the wafer unit 120, and the alignment pattern 1242 may be disposed correspondingly at the four corners created by the chamfer A1. Of course, this disclosure does not limit the shape of the wafer unit and the sealing ring pattern, as long as the number and position of the chamfers of the sealing ring pattern correspond to the number and position of the corners of the wafer unit.

[0035] In this structural configuration, the alignment pattern 1242 is positioned within the area enclosed by the dicing 130 and outside the closed area enclosed by the sealing ring pattern 1241. This avoids the problem of the metal layer being exposed and affecting the wafer appearance due to the alignment pattern being cut during the wafer dicing process. Furthermore, since there is no need to worry about cutting the alignment pattern during the wafer dicing process, the width of the dicing 1242 can be further reduced, allowing for a denser arrangement of wafer cells on the wafer. This increases the number of dies per wafer and improves the wafer throughput per wafer. In one embodiment, the dicing 130 can be reduced to between 60 micrometers and 80 micrometers, but this disclosure is not limited to this.

[0036] In one embodiment, the alignment pattern 1242 and the sealing ring pattern 1241 are electrically insulated from each other and spaced apart by a first distance d1. For example, the first distance d1 is approximately greater than 1 micrometer. In one embodiment, the outer edge of the alignment pattern 1242 is spaced apart from the inner edge of the dicing track 130 by a second distance d2 to further prevent the alignment pattern 1242 from being cut during the wafer dicing process. In this embodiment, the second distance d2 is approximately greater than 1 micrometer. In this embodiment, the sealing ring pattern 1241 includes an inner sealing ring pattern 1241b surrounding the central region C1 and an outer sealing ring pattern 1241a surrounding the inner sealing ring pattern 1241b, and the outer sealing ring pattern 1241a and the inner sealing ring pattern 1241b are electrically insulated from each other. In this embodiment, the alignment pattern 1242 is disposed between the dicing track 130 and the outer sealing ring pattern 1241a.

[0037] In some embodiments, the peripheral metal pattern 124 may further include a plurality of dummy metal pads 1243, which are uniformly distributed between the sealing ring pattern 1241 and the alignment pattern 1242. The dummy metal pads 1243 may be electrically insulated from the sealing ring pattern 1241, the alignment pattern 1242, and the wafer wiring pattern 122. That is, the dummy metal pads 1243 may be electrically floating. The dummy metal pads 1243 may be uniformly distributed in the wiring gaps in the wafer cell 120 to provide a more uniform pattern density, so that the wafer cell 120 can obtain a flatter surface after undergoing a planarization process (e.g., CMP process).

[0038] Figure 5 is a top view schematic diagram of an alignment pattern of a wafer structure according to an embodiment of the present disclosure. Referring simultaneously to Figures 4 and 5, in this embodiment, the outer edge of the alignment pattern 1242 is substantially collinear with the outer edge of the corresponding sealing ring pattern 1241. Specifically, in this embodiment, viewed from the top view direction, the alignment pattern 1242 is L-shaped, having two substantially perpendicular outer edges (outer sides), which are respectively collinear with the outer edges of the corresponding sealing ring pattern 1241 and are parallel to the two sides of the corner of the wafer unit 120. The term "substantially perpendicular" here means that the included angle between the two substantially perpendicular outer edges of the L-shaped alignment pattern 1242 is approximately between 85 and 95 degrees. In this embodiment, the lengths L1 and L2 of the substantially perpendicular two sides of the alignment pattern 1242 can be greater than or approximately equal to 10 micrometers, and the width of these two sides can be greater than or approximately equal to 2 micrometers. Of course, this embodiment is only for illustration and the present disclosure is not limited thereto.

[0039] Figure 6 is a top view schematic diagram of the alignment pattern of a wafer structure according to different embodiments of the present disclosure. Referring to Figure 6, viewed from the top view direction, the shape of the alignment pattern 1242, in addition to the L-shape shown in Figure 4, can also be other suitable shapes. For example, the alignment pattern 1242a can be a square shape, the alignment pattern 1242b can be a cross shape, the alignment pattern 1242c can be a Z-shape, or the alignment pattern 1242d can be an hourglass shape, etc. Each wafer structure can have multiple alignment patterns, and their shapes can be one of the alignment patterns 1242, 1242a, 1242b, 1242c, and 1242d, or a combination of the above shapes. Of course, the present disclosure only lists a few possible shapes of alignment patterns, and the present disclosure is not limited thereto. In one embodiment, the overall length and width dimensions of the alignment pattern can be greater than or approximately equal to 10 micrometers, and the width of the pattern can be greater than or approximately equal to 2 micrometers, so as to facilitate recognition by the image sensor.

[0040] Figure 7A is a partial cross-sectional schematic diagram of a wafer structure according to an embodiment of the present disclosure. Referring to Figure 7A, in this embodiment, the alignment pattern 1242 and the sealing ring pattern 1241 are disposed on the same plane and can be formed using the same photoresist pattern and through the same photolithography process. Specifically, the sealing ring pattern 1241 includes multiple sealing ring pattern layers stacked on the substrate 110, while the alignment pattern 1242 includes multiple alignment pattern layers stacked on the substrate 220. Each alignment pattern layer can be disposed on the same layer as a corresponding sealing ring pattern layer, and each alignment pattern layer and sealing ring pattern layer can be formed using the same photoresist pattern and through the same photolithography process. In this embodiment, the sealing ring pattern 1241 may include an outer sealing ring pattern 1241a and an inner sealing ring pattern 1241b separated from each other by a dielectric material.

[0041] In one embodiment, the sealing ring pattern 1241 may further include a pad layer 1244, which may be the uppermost layer among a plurality of sealing ring pattern layers. In this embodiment, the pad layer 1244 is disposed on the uppermost layer of the outer sealing ring pattern 1241a, but this disclosure is not limited thereto. In one embodiment, the passivation layer 140 conformally covers the sealing ring pattern 1241, the pad layer 1244, and the alignment pattern 1242 as shown in FIG7A, to provide protection for electrical components such as the underlying pad layer 1244, helping to prevent or reduce moisture damage, mechanical damage, and radiation damage, while absorbing or releasing heat and / or mechanical stress during wafer dicing and packaging processes.

[0042] In some embodiments, the outer sealing ring pattern 1241a is formed by stacking multiple wiring layers 125a and through-wire vias 126a. Similarly, the inner sealing ring pattern 1241b is formed by stacking multiple wiring layers 125b and through-wire vias 126b. In one embodiment, the sealing ring pattern 1241 may be connected to the element 112 of the substrate 110; in other embodiments, the sealing ring pattern 1241 may be electrically insulated from the element of the substrate 110. The alignment pattern 1242 is disposed outside the outer sealing ring pattern 1241a and is formed by stacking multiple wiring layers 127 and through-wire vias 128. In this embodiment, the wiring layer 127 of each alignment pattern 1242 and the wiring layers 125a and 125b of each sealing ring pattern 1241a and 1241b are all disposed on the same plane and can be formed simultaneously using a photolithography process.

[0043] Figure 7A is a partial cross-sectional schematic diagram of a wafer structure according to an embodiment of the present disclosure. It must be noted that the wafer structure 100 of this embodiment is similar to the wafer structure of the aforementioned embodiments. Therefore, this embodiment uses the component reference numerals and some content from the aforementioned embodiments, where the same reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For descriptions of the omitted parts, please refer to the aforementioned embodiments; this embodiment will not repeat them. Referring to Figure 7A, in some embodiments, the alignment pattern 1242 is formed by stacking multiple wiring layers 127 and through-holes 128 between conductors. The wiring layers 127 of the multi-layer alignment pattern 1242 can be disposed on the same plane as the wiring layers 125a and 125b of the multi-layer sealing ring patterns 1241a and 1241b, respectively, and can be formed simultaneously using a photolithography process. In this embodiment, unlike the sealing ring patterns 1241a and 1241b, the alignment pattern 1242 may not be stacked from the substrate 110 upwards. That is, the alignment pattern 1242 may not be connected to the substrate 110, but may be formed on any dielectric layer above the substrate 110, and then stacked layer by layer from there. Furthermore, in this embodiment, the alignment pattern 1242 is not connected to the element 112 of the substrate 110 through vias; that is, the alignment pattern 1242 does not include vias connected to the element 112 of the substrate 110. Of course, this embodiment is only used for illustration, and this disclosure does not limit the stacking method of the alignment pattern 1242.

[0044] In summary, the wafer structure disclosed herein places the alignment pattern within the area enclosed by the dicing kerf and outside the closed area enclosed by the sealing ring pattern. This avoids the problem of the alignment pattern on the dicing kerf being cut during the wafer dicing process, which could expose the metal layer and affect the wafer's appearance. Furthermore, since there is no need to worry about cutting the alignment pattern during the wafer dicing process, the width of the dicing kerf can be further reduced, allowing for a denser arrangement of wafer cells on the wafer. This, in turn, increases the number of diced dies per wafer and increases the wafer throughput per wafer.

[0045] 100: Wafer Structure 110:Substrate 112: Components 120: Chip unit, chip structure 121: Chip 122: Chip Circuit Pattern 124: Peripheral Metal Pattern 1241: Sealing ring pattern, sealing ring 1241a: Outer sealing ring pattern, sealing ring pattern 1241b: Inner sealing ring pattern, sealing ring pattern 1242, 1242a, 1242b, 1242c, 1242d: Alignment patterns, alignment marks 1243: Virtual Metal Pad 1244: Substrate layer 125a, 125b, 127: Wiring layers 126a, 126b, 128: Through-holes between conductors 130: Cutting Track 140: Passivation layer A1: Chamfer C1: Central Area d1: First distance d2: Second distance P1: Surrounding Area R1: Corner Area

Claims

1. A wafer structure comprising: substrate; A dicing channel defines a wafer unit on the substrate; a wafer circuit pattern is disposed in the central region of the wafer unit; The peripheral metal pattern is disposed in the peripheral area of ​​the wafer unit, surrounding the central area, wherein the peripheral metal pattern includes a sealing ring pattern surrounding the central area and an alignment pattern disposed between the dicing channel and the sealing ring pattern, and the alignment pattern is electrically insulated from the wafer circuit pattern.

2. The wafer structure as claimed in claim 1, wherein the sealing ring pattern includes a chamfer to create a corner area in the wafer cell, and the alignment pattern is disposed within the corner area created by the chamfer.

3. The wafer structure as claimed in claim 1, wherein the peripheral metal pattern further comprises a plurality of dummy metal pads uniformly distributed between the sealing ring pattern and the alignment pattern.

4. The wafer structure as claimed in claim 1, wherein the outer edge of the alignment pattern is substantially collinear with the outer edge of the corresponding sealing ring pattern.

5. The wafer structure as claimed in claim 1, wherein, viewed from the top view direction, the alignment pattern does not overlap with the dicing ridge.

6. The wafer structure as claimed in claim 1, wherein the wafer circuit pattern is electrically insulated from the peripheral metal pattern.

7. The wafer structure as claimed in claim 1, wherein the alignment pattern is L-shaped, square-shaped, cross-shaped, Z-shaped, or hourglass-shaped.

8. The wafer structure as claimed in claim 1, wherein the sealing ring pattern comprises a plurality of sealing ring pattern layers disposed on the substrate in an overlapping manner.

9. The wafer structure as claimed in claim 1, wherein the alignment pattern comprises a plurality of alignment pattern layers disposed on the substrate in an overlapping manner, and respectively disposed in the same layer as the corresponding plurality of sealing ring pattern layers.

10. The wafer structure as claimed in claim 1, wherein the sealing ring pattern comprises an inner sealing ring pattern surrounding the central region and an outer sealing ring pattern surrounding the inner sealing ring pattern.

11. The wafer structure as claimed in claim 10, wherein the alignment pattern is disposed between the dicing path and the outer sealing ring pattern.

12. A chip structure, comprising: A substrate, including a central region and a peripheral region surrounding the central region; a wafer circuit pattern, disposed in the central region; The surrounding metal pattern is disposed in the surrounding area and includes a sealing ring pattern surrounding the wafer circuit pattern and an alignment pattern disposed outside the closed area enclosed by the sealing ring pattern, wherein the alignment pattern is electrically insulated from the wafer circuit pattern.

13. The wafer structure as claimed in claim 12, wherein the alignment pattern is disposed between the outer edge of the wafer structure and the sealing ring pattern.

14. The wafer structure of claim 12, wherein the sealing ring pattern has a chamfer at a corner corresponding to the substrate, and the alignment pattern is disposed at the corner vacated by the chamfer.

15. A wafer structure comprising: substrate; A dicing channel defines a wafer unit on the substrate; a wafer is disposed in the wafer unit; and a sealing ring surrounding the wafer and located between the dicing track and the wafer; and an alignment mark disposed between the dicing track and the sealing ring, wherein the sealing ring includes a chamfer to create a corner area in the wafer cell, and the alignment mark is disposed within the corner created by the chamfer.

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