Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a functional circuit, an antenna circuit, and a first isolation circuit. The functional circuit is used to receive a first reference voltage signal and a second reference voltage signal. The antenna circuit is used to receive the first reference voltage signal to share charge with the functional circuit. The first isolation circuit is placed between the functional circuit and the antenna circuit and is used to receive the second reference voltage signal to isolate the functional circuit and the antenna circuit from each other.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Prior Technology

[0002] Semiconductor devices may include antenna elements to protect the semiconductor device from additional charges. However, when the voltage difference between the antenna element and other parts of the semiconductor device is high, unwanted leakage current can be induced between the antenna element and other parts of the semiconductor device. Summary of the Invention

[0003] Some embodiments of this disclosure include a semiconductor device comprising a functional circuit for receiving a first reference voltage signal and a second reference voltage signal, an antenna circuit for receiving the first reference voltage signal to share a plurality of charges with the functional circuit, and a first isolation circuit placed between the functional circuit and the antenna circuit and for receiving the second reference voltage signal to isolate the functional circuit and the antenna circuit from each other.

[0004] Some embodiments of this disclosure include a semiconductor device including a first gate structure and a second gate structure for receiving a first reference voltage signal, a first gate portion disposed along a first direction between the first gate structure and the second gate structure for receiving the first reference voltage signal, a second gate portion separated from the first gate portion, and a first source / drain structure and a second source / drain structure coupled together for receiving the first reference voltage signal, wherein the first source / drain structure, the second gate structure, the second source / drain structure and the first gate structure are sequentially arranged along the first direction.

[0005] Some embodiments of this disclosure include a method of manufacturing a semiconductor device, comprising forming a first source / drain structure, a second source / drain structure, and a third source / drain structure sequentially arranged along a first direction; forming a first gate structure between the first source / drain structure and the second source / drain structure; cutting the first gate structure into a first gate portion and a second gate portion, wherein the second gate portion is aligned with and separated from the first gate portion along a second direction different from the first direction; and forming a first conductive segment extending along the first direction, wherein the first source / drain structure is coupled to the second gate portion, the third source / drain structure is coupled to the first conductive segment, and the second source / drain structure and the third source / drain structure serve as two terminals of a first transistor. Simple Explanation of the Diagram

[0006] The various aspects of some embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1A is a circuit diagram of a portion of a semiconductor device according to some embodiments of the present disclosure. Figure 1B is a layout diagram of a portion of a semiconductor device according to some embodiments of the present disclosure. Figure 2A is a circuit diagram of a portion of a semiconductor device corresponding to the semiconductor device shown in Figure 1A, according to some embodiments of the present disclosure. Figure 2B is a layout diagram of a portion of a semiconductor device corresponding to the semiconductor device shown in Figure 1B, according to some embodiments of the present disclosure. Figure 2C is a cross-sectional view of a portion of the semiconductor device shown in Figure 2B according to some embodiments of the present disclosure. Figure 2D is a cross-sectional view of a portion of the semiconductor device shown in Figure 2B according to some embodiments of the present disclosure. Figure 3A is a circuit diagram of a portion of a semiconductor device corresponding to the semiconductor device shown in Figure 1A, according to some embodiments of the present disclosure. Figure 3B is a layout diagram of a portion of a semiconductor device corresponding to the semiconductor device shown in Figure 1B, according to some embodiments of the present disclosure. Figure 3C is a schematic diagram corresponding to a side view of a portion of the semiconductor device shown in Figure 3B, according to some embodiments of the present disclosure. Figure 3D is a schematic diagram corresponding to a side view of a portion of the semiconductor device shown in Figure 3B, based on some embodiments of the present disclosure. Figure 3E is a schematic diagram corresponding to a side view of a portion of the semiconductor device shown in Figure 3B, based on some embodiments of the present disclosure. Figure 3F is a schematic diagram corresponding to a side view of a portion of the semiconductor device shown in Figure 3B, based on some embodiments of the present disclosure. Figure 4 is a flowchart of a method for manufacturing the semiconductor device shown in Figures 2B to 2D or the semiconductor device shown in Figures 3B to 3F, according to some embodiments of the present disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements, materials, values, steps, configurations, or the like are described below to simplify some embodiments of this disclosure. These are, of course, merely examples and are not intended to be limiting. Other elements, materials, values, steps, configurations, or the like are contemplated. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, some embodiments of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “nearly,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “nearly,” or “substantially” may be speculative unless explicitly specified. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the specification are merely examples and may decrease or vary as integrated circuits shrink.

[0009] The terms used throughout the following description and the scope of the claims generally have their common meaning as clearly established in the art or in the specific context in which each term is used. Those skilled in the art will understand that elements or processes may be referred to by different names. The many different embodiments detailed in this specification are merely illustrative and do not in any way limit the scope and spirit of the embodiments disclosed herein or any illustrative terms.

[0010] It is worth noting that terms such as "first" and "second" used herein to describe various components or processes are intended to distinguish one component or process from another. However, components, processes, and their order should not be limited by these terms. For example, without departing from the scope of some embodiments of this disclosure, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component.

[0011] In the following discussion and the scope of the patent application, the terms "comprising," "including," "containing," "having," "involving," and the like shall be understood as open-ended, that is, interpreted as including but not limited to. As used herein, the term "and / or" includes any of the associated listed items and all combinations of one or more of the associated listed items, and is not mutually exclusive.

[0012] Figure 1A is a circuit diagram of a portion of a semiconductor device 100A according to some embodiments of the present disclosure. As illustrated in Figure 1A, the semiconductor device 100A includes functional circuit FC11, antenna circuit AC11, and isolation circuits BC11 and BC12.

[0013] In some embodiments, the functional circuit FC11 operates according to reference voltage signals VDD and VSS. In some embodiments, the functional circuit FC11 is implemented by a standard cell (such as a logic cell containing logic circuitry including AND, OR, NOT AND, multiplexing, flip-flops, latches, buffers, inverters, or any other type of logic circuitry). In some embodiments, the voltage level of the reference voltage signal VDD is higher than the voltage level of the reference voltage signal VSS. For example, the reference voltage signal VDD is implemented by a power signal, while the reference voltage signal VSS is implemented by a ground signal.

[0014] In some embodiments, antenna circuit AC11 is used to receive input signal IS11 from functional circuit FC11 at node N10, so as to share charge with functional circuit FC11. In some embodiments, input signal IS11 is a reference voltage signal VDD. Isolation circuits BC11 and BC12 are used to isolate antenna circuit AC11 from functional circuits (such as functional circuit FC11) in semiconductor device 100A, so as to reduce leakage current between antenna circuit AC11 and functional circuits.

[0015] As illustrated in Figure 1A, the antenna circuit AC11 includes transistors TN11-TN13 and TP11-TP13. Each of the control terminals of transistors TN11-TN13 and TP11-TP13 is coupled to node N10. One terminal of transistor TP11 is coupled to node N13, and the other terminal of transistor TP11 is coupled to node N14. One terminal of transistor TP12 is coupled to node N14, and the other terminal of transistor TP12 is coupled to node N15. One terminal of transistor TP13 is coupled to node N15, and the other terminal of transistor TP13 is coupled to node N16. In other words, transistors TP11-TP13 are connected in series between nodes N13 and N16. In various embodiments, various numbers of transistors are connected in series between nodes N13 and N16, wherein each of the control terminals of the transistors is coupled to node N10.

[0016] As illustrated in Figure 1A, each of the two terminals of transistor TN11 is coupled to node N10. Each of the two terminals of transistor TN12 is coupled to node N10. Each of the two terminals of transistor TN13 is coupled to node N10. In various embodiments, antenna circuit AC11 includes various numbers of transistors coupled between transistors TN11 and TN12, with both terminals coupled to node N10.

[0017] As illustrated in Figure 1A, the isolation circuit BC11 includes transistors TN14, TP14, and TP15. Each of the control terminals of transistors TN14, TP14, and TP15 is coupled to node N10. One terminal of transistor TN14 is coupled to node N19, and the other terminal of transistor TN14 is used to receive a reference voltage signal VSS at node N112. One terminal of transistor TP14 is coupled to node N11, and the other terminal of transistor TP14 is coupled to node N12. One terminal of transistor TP15 is coupled to node N12, and the other terminal of transistor TP15 is coupled to node N13. In some embodiments, each of nodes N11 and N19 is floating.

[0018] As illustrated in Figure 1A, the isolation circuit BC12 includes transistors TN15, TP16, and TP17. Each of the control terminals of transistors TN15, TP16, and TP17 is coupled to node N10. One terminal of transistor TN15 is coupled to node N111, and the other terminal of transistor TN15 is used to receive a reference voltage signal VSS at node N113. One terminal of transistor TP17 is coupled to node N18, and the other terminal of transistor TP17 is coupled to node N17. One terminal of transistor TP16 is coupled to node N17, and the other terminal of transistor TP16 is coupled to node N16. In some embodiments, each of nodes N111 and N18 is floating.

[0019] In some embodiments, isolation circuits BC11 and BC12 operate as decoupling capacitor circuits. The decoupling capacitor circuits are configured as fundamental elements of the power supply voltage in standard cell circuits for stabilizing integrated circuits operating at high speeds. In some embodiments, the decoupling capacitor circuits are inserted near functional circuits with high transistor activity (such as functional circuit FC11) such that their IR voltage drop can be suppressed.

[0020] In some embodiments, the conductivity type of transistors TP11-TP17 is different from that of transistors TN11-TN15. For example, each of transistors TP11-TP17 is implemented by a P-type metal-oxide-semiconductor (PMOS) transistor, while each of transistors TN11-TN15 is implemented by an N-type metal-oxide-semiconductor (NMOS) transistor.

[0021] Figure 1B is a layout diagram of a portion of a semiconductor device 100B according to some embodiments of the present disclosure. As illustrated in Figure 1B, the semiconductor device 100B includes a functional circuit FC12, an antenna circuit AC12, and isolation circuits BC13 and BC14. Isolation circuit BC13, antenna circuit AC12, isolation circuit BC14, and functional circuit FC12 are arranged sequentially along the X direction. Referring to Figures 1A and 1B, functional circuit FC12, antenna circuit AC12, and isolation circuits BC13 and BC14 are embodiments of functional circuit FC11, antenna circuit AC11, and isolation circuits BC11 and BC12, respectively.

[0022] As illustrated in Figure 1B, the semiconductor device 100B includes gate structures GS11~GS17, gate portions GP11~GP14, source / drain structures AA11~AA18, AB11~AB18, and conductive segments CS11~CS15, MP11~MP18, and MN11~MN18 for forming functional circuit FC12, antenna circuit AC12, and isolation circuits BC13 and BC14.

[0023] As illustrated in Figure 1B, conductive segments MP11~MP18 and MN11~MN18 cross and couple to source / drain structures AA11~AA18 and AB11~AB18, respectively. In other words, along the Z direction, conductive segments MP11~MP18 and MN11~MN18 overlap with source / drain structures AA11~AA18 and AB11~AB18, respectively.

[0024] Along the X direction, the gate structure GS11, source / drain structure AA11, gate structure GS12, source / drain structure AA12, gate portion GP11, source / drain structure AA13, gate structure GS13, source / drain structure AA14, gate structure GS14, source / drain structure AA15, gate structure GS15, source / drain structure AA16, gate portion GP13, source / drain structure AA17, gate structure GS16, source / drain structure AA18, and gate structure GS17 are arranged in sequence.

[0025] Similarly, along the X direction, the gate structure GS11, source / drain structure AB11, gate structure GS12, source / drain structure AB12, gate portion GP12, source / drain structure AB13, gate structure GS13, source / drain structure AB14, gate structure GS14, source / drain structure AB15, gate structure GS15, source / drain structure AB16, gate portion GP14, source / drain structure AB17, gate structure GS16, source / drain structure AB18, and gate structure GS17 are arranged in sequence.

[0026] In some embodiments, gate portions GP11 and GP12 are formed by cutting a gate structure extending along the Y direction using a separating spacer CP01. Gate portions GP13 and GP14 are formed by cutting another gate structure extending along the Y direction using a separating spacer CP02. Thus, along the Y direction, gate portions GP11 and GP12 are aligned and separated from each other, while gate portions GP13 and GP14 are aligned and separated from each other. In some embodiments, the X, Y, and Z directions are perpendicular to each other.

[0027] In some embodiments, spacer CP01 is configured to isolate electrical signals transmitted via gate portions GP11 and GP12. Spacer CP02 is configured to isolate electrical signals transmitted via gate portions GP13 and GP14. For illustrative purposes, spacer CP01 is placed between gate portions GP11 and GP12, and spacer CP02 is placed between gate portions GP13 and GP14. Using spacers CP01 and CP02, electrical signals transmitted via gate portion GP11 are isolated from gate portion GP12, and electrical signals transmitted via gate portion GP13 are isolated from gate portion GP14. In some embodiments, at least one of spacers CP01 and CP02 is formed of a dielectric material. In some embodiments, spacers CP01 and CP02 are polycrystalline dicing layers, which are intermediate products during the semiconductor manufacturing process and are not present in the final product of the semiconductor circuit.

[0028] In some embodiments, each of the gate portions GP12 and GP14 is operated as a dummy gate. In other words, neither of the gate portions GP12 nor GP14 operates as a control terminal of the transistor. In some embodiments, the dummy gate is a continuous polysilicon on oxide diffusion edge (CPODE) layout pattern.

[0029] As illustrated in Figure 1B, each of the conductive segments CS11 to CS14 extends along the X direction. Conductive segments CS12, CS14, CS13, and CS11 are separated from each other and arranged sequentially along the Y direction. Each of the conductive segments MN11 and MN18 extends along the Y direction to couple to conductive segment CS12. In some embodiments, the length of each of the conductive segments MN11 and MN18 is greater than the length of each of the conductive segments MN12 to MN17 along the Y direction.

[0030] As illustrated in Figure 1B, conductive segment CS13 spans gate structures GS12-GS16, conductive segments MP12-MP17, gate portions GP11 and GP13, and source / drain structures AA12-AA17. Conductive segment CS13 is coupled to gate structures GS12-GS16 and gate portions GP11 and GP13 via corresponding vias. Each via coupled to conductive segment CS13 is inserted along the X direction between corresponding pairs in source / drain structures AA11-AA18.

[0031] As illustrated in Figure 1B, conductive segment CS14 spans gate structures GS13-GS15, conductive segments MN13-MN16, and source / drain structures AB13-AB16. Conductive segment CS14 is coupled to source / drain structures AB13-AB16 via corresponding vias. Conductive segment CS15 spans conductive segments CS13 and CS14 and is coupled to conductive segments CS13 and CS14 via corresponding vias.

[0032] In some embodiments, the conductivity type of the source / drain structures AB11-AB18 is different from that of the source / drain structures AA11-AA18. For example, the source / drain structures AB11-AB18 are implemented using N-type oxide diffusion (OD) material, while the source / drain structures AA11-AA18 are implemented using P-type OD material. In some embodiments, the gate structures GS11-GS17 and the gate portions GP11-GP14 are implemented using polycrystalline silicon. In some embodiments, the conductive segments CS11-CS14 are placed in the zero metal (MO) layer, while the conductive segment CS15 is placed in the first metal (M1) layer above the MO layer.

[0033] Referring to Figures 1A and 1B, in some embodiments, transistor TN14 is implemented by a gate structure GS12 and source / drain structures AB11 and AB12. Transistor TP14 is implemented by a gate structure GS12 and source / drain structures AA11 and AA12. Transistor TP15 is implemented by a gate portion GP11 and source / drain structures AA13 and AA12.

[0034] In some embodiments, transistor TN11 is implemented by gate structure GS13 and source / drain structures AB13 and AB14. Transistor TP11 is implemented by gate structure GS13 and source / drain structures AA13 and AA14. Transistor TN12 is implemented by gate structure GS14 and source / drain structures AB14 and AB15. Transistor TP12 is implemented by gate structure GS14 and source / drain structures AA14 and AA15. Transistor TN13 is implemented by gate structure GS15 and source / drain structures AB15 and AB16. Transistor TP13 is implemented by gate structure GS15 and source / drain structures AA15 and AA16.

[0035] In some embodiments, transistor TN15 is implemented by gate structure GS16 and source / drain structures AB17 and AB18. Transistor TP17 is implemented by gate structure GS16 and source / drain structures AA17 and AA18. Transistor TP16 is implemented by gate portion GP13 and source / drain structures AA17 and AA16.

[0036] In some embodiments, conductive segment CS11 is used to transmit the reference voltage signal VDD, while conductive segment CS12 is used to transmit the reference voltage signal VSS to the source / drain structures AB11 and AB18 via conductive segments MN11 and MN18. In some embodiments, conductive segment CS15 is used to transmit the reference voltage signal VDD from the higher metal layer through conductive segments CS13 and CS14 to gate structures GS12~GS16, gate portions GP11, GP13, and source / drain structures AB13~AB16. In some embodiments, functional circuitry is used to receive the reference voltage signal VDD from conductive segment CS11 and to receive the reference voltage signal VSS from conductive segment CS12.

[0037] Referring to Figures 1A and 1B, nodes N11-N113 correspond to conductive segments MP11-MP18, MN11, CS15, MN17, MN12, and MN18, respectively. Conductive segments MN13-MN16, gate structures GS12-GS16, and gate portions GP11 and GP13 are coupled to node N10 to share the charge of the reference voltage signal VDD. Each of nodes N19 and N111 is floating and has a logic potential corresponding to the reference voltage signal VSS. Therefore, the protection function circuit FC12 is protected from the charge corresponding to the reference voltage signal VDD. Therefore, functional circuits (such as functional circuit FC12) are isolated from antenna circuit AC12 by isolation circuits BC13 and BC14.

[0038] In some methods, filler is inserted between the antenna circuitry and the functional circuitry to reduce leakage current between them. However, additional space is required to form the filler.

[0039] Compared to the methods described above, in some embodiments disclosed herein, the isolation circuit BC14 is used to share charge via the gate structure GS16 and also to isolate the antenna circuit AC12 and the functional circuit FC12, thereby reducing leakage current between the antenna circuit AC12 and the functional circuit FC12. Therefore, no additional area is required to isolate the antenna circuit AC12 and the functional circuit FC12.

[0040] Figure 2A is a circuit diagram of a portion of semiconductor device 200A corresponding to semiconductor device 100A shown in Figure 1A, according to some embodiments of this disclosure. Referring to Figures 2A and 1A, semiconductor device 200A is an alternative embodiment of semiconductor device 100A. Figure 2A follows a labeling convention similar to that of Figure 1A. For the sake of brevity, the discussion will focus more on the differences between Figure 2A and Figure 1A than on their similarities.

[0041] Compared to semiconductor device 100A, semiconductor device 200A includes isolation circuits BC21 and BC22, but not isolation circuits BC11 and BC12. Compared to isolation circuit BC11, isolation circuit BC21 includes transistor TN21, but not transistor TN14. Compared to isolation circuit BC12, isolation circuit BC22 includes transistor TN22, but not transistor TN15.

[0042] As illustrated in Figure 2A, the control terminal of transistor TN21 is coupled to node N10, and the two terminals of transistor TN21 are coupled to each other at node N21. The control terminal of transistor TN22 is coupled to node N10, and the two terminals of transistor TN22 are coupled to each other at node N22. In some embodiments, each of nodes N21 and N22 is floating.

[0043] Figure 2B is a layout diagram of a portion of semiconductor device 200B corresponding to semiconductor device 100B shown in Figure 1B, according to some embodiments of this disclosure. Referring to Figures 2B and 1B, semiconductor device 200B is an alternative embodiment of semiconductor device 100B. Figure 2B follows a labeling convention similar to that of Figure 1B. For the sake of brevity, the discussion will focus more on the differences between Figure 2B and Figure 1B than on their similarities.

[0044] Compared to semiconductor device 100B, semiconductor device 200B includes isolation circuits BC23 and BC24, but not isolation circuits BC13 and BC14. Referring to Figures 2A and 2B, isolation circuits BC23 and BC24 are embodiments of isolation circuits BC21 and BC22, respectively.

[0045] Furthermore, compared to semiconductor device 100B, semiconductor device 200B includes conductive segments MN21 and MN22, but non-conductive segments MN11 and MN18. Conductive segments MN21 and MN22 are used to form part of isolation circuits BC23 and BC24, respectively.

[0046] As illustrated in Figure 2B, conductive segments MN21 and MN22 span and couple to source / drain structures AB11 and AB18, respectively. Along the X-direction, conductive segment MN21 is positioned between gate structures GS11 and GS12, while conductive segment MN22 is positioned between gate structures GS16 and GS17. Along the Y-direction, the length of conductive segment MN21 is the same as the length of each of conductive segments MN12 through MN17.

[0047] Referring to Figures 2B and 1B, compared to semiconductor device 100B, semiconductor device 200B further includes conductive segments CS21 and CS22. Each of conductive segments CS21 and CS22 extends along the X direction. Conductive segment CS21 spans conductive segments MN21 and MN12 and the gate structure GS12 and is coupled to conductive segments MN21 and MN12 via corresponding vias. Conductive segment CS22 spans conductive segments MN22 and MN17 and the gate structure GS16 and is coupled to conductive segments MN22 and MN17 via corresponding vias.

[0048] Referring to Figures 2B and 2A, in some embodiments, transistor TN21 is implemented by gate structure GS12 and source / drain structures AB11 and AB12. Transistor TN22 is implemented by gate structure GS16 and source / drain structures AB17 and AB18. Nodes N21 and N22 correspond to conductive segments CS21 and CS22, respectively.

[0049] In some embodiments, isolation circuits BC23 and BC24 isolate the functional circuitry (such as functional circuitry FC12) of the semiconductor device 200B from the antenna circuitry AC11. Therefore, leakage current between the antenna circuitry AC11 and the functional circuitry is reduced.

[0050] Figure 2C is a cross-sectional view of a portion of the semiconductor device 200B shown in Figure 2B according to some embodiments of the present disclosure. Referring to Figures 2B and 2C, the cross-sectional view shown in Figure 2C corresponds to line L21 shown in Figure 2B.

[0051] As illustrated in Figure 2C, the semiconductor device 200B further includes a substrate SB21. In some embodiments, the substrate SB21 is made of a P-type material. Each of the source / drain structures AB11 and AB12 is embedded in the substrate SB21. Conductive segments MN21 and MN12 are in contact with the source / drain structures AB11 and AB12, respectively. Conductive segment CS21 is coupled to conductive segments MN21 and MN12 via corresponding vias and is separated from the gate structure GS12 along the Z-direction.

[0052] Figure 2D is a cross-sectional view of a portion of the semiconductor device 200B shown in Figure 2B according to some embodiments of the present disclosure. Referring to Figures 2B and 2D, the cross-sectional view shown in Figure 2D corresponds to line L22 shown in Figure 2B.

[0053] As illustrated in Figure 2D, each of the source / drain structures AB17 and AB18 is embedded in the substrate SB21. Conductive segments MN22 and MN17 are in contact with the source / drain structures AB18 and AB17, respectively. Conductive segment CS22 is coupled to conductive segments MN21 and MN12 via corresponding vias and is separated from the gate structure GS16 along the Z-direction.

[0054] Figure 3A is a circuit diagram of a portion of semiconductor device 300A corresponding to semiconductor device 100A shown in Figure 1A, according to some embodiments of this disclosure. Referring to Figures 3A and 1A, semiconductor device 300A is an alternative embodiment of semiconductor device 100A. Figure 3A follows a labeling convention similar to that of Figure 1A. For the sake of brevity, the discussion will focus more on the differences between Figure 3A and Figure 1A than on their similarities.

[0055] Compared to semiconductor device 100A, semiconductor device 300A includes isolation circuits BC31 and BC32, but not isolation circuits BC11 and BC12. Compared to isolation circuit BC11, isolation circuit BC31 includes transistors TN31 and TP31, but not transistors TN14 and TP14. Compared to isolation circuit BC12, isolation circuit BC32 includes transistors TN32 and TP32, but not transistors TN15 and TP17. Furthermore, transistors TP15 and TP16 are coupled to nodes N31 and N35, respectively, but not to transistors TP14 and TP17.

[0056] As illustrated in Figure 3A, the control terminal of transistor TN31 is coupled to node N33, one terminal of transistor TN31 is coupled to node N32, and the other terminal of transistor TN31 is used to receive the reference voltage signal VSS at node N34. The control terminal of transistor TP31 is coupled to node N32, one terminal of transistor TP31 is coupled to node N33, and the other terminal of transistor TP31 is used to receive the reference voltage signal VDD at node N31. The control terminal of transistor TN32 is coupled to node N37, one terminal of transistor TN32 is coupled to node N36, and the other terminal of transistor TN32 is used to receive the reference voltage signal VSS at node N38. The control terminal of transistor TP32 is coupled to node N36, one terminal of transistor TP32 is coupled to node N37, and the other terminal of transistor TP32 is used to receive the reference voltage signal VDD at node N35.

[0057] During operation, each of transistors TN31, TN32, TP31, and TP23 is turned on. Each of nodes N32 and N36 has a reference voltage signal VSS at a voltage level. Each of nodes N33 and N37 has a reference voltage signal VDD at a voltage level. Therefore, antenna circuit AC11 is isolated from functional circuits (such as functional circuit FC11) in semiconductor device 300A by isolation circuits BC31 and BC32.

[0058] Figure 3B is a layout diagram of a portion of semiconductor device 300B corresponding to semiconductor device 100B shown in Figure 1B, according to some embodiments of this disclosure. Referring to Figures 3B and 1B, semiconductor device 300B is an alternative embodiment of semiconductor device 100B. Figure 3B follows a labeling convention similar to that of Figure 1B. For the sake of brevity, the discussion will focus more on the differences between Figure 2B and Figure 1B than on the similarities.

[0059] Compared to semiconductor device 100B, semiconductor device 300B includes isolation circuits BC33 and BC34, but not isolation circuits BC13 and BC14. Referring to Figures 3A and 3B, isolation circuits BC33 and BC34 are embodiments of isolation circuits BC31 and BC32, respectively.

[0060] Furthermore, compared to semiconductor device 100B, semiconductor device 300B includes conductive segments MP31, MP32, CS31~CS39, CZ31~CZ34 and gate portions GP31~GP34, and non-conductive segments MP12, MP17, CS13 and gate structures GS12, GS16.

[0061] As illustrated in Figure 3B, conductive segments MP31 and MP32 span and are coupled to source / drain structures AA12 and AA17, respectively. Each of conductive segments MP31 and MP32 is coupled to conductive segment CS11 and has a length along the Y direction that is longer than that of each of conductive segments MP11 to MP18.

[0062] As illustrated in Figure 3B, along the X direction, gate portion GP31 is placed between source / drain structures AA11 and AA12, gate portion GP32 is placed between source / drain structures AB11 and AB12, gate portion GP33 is placed between source / drain structures AA17 and AA18, and gate portion GP34 is placed between source / drain structures AB17 and AB18.

[0063] As illustrated in Figure 3B, conductive segment CS31 spans conductive segment MP11. Conductive segment CS32 spans gate portion GP31 and conductive segment MP31. Conductive segment CS33 spans gate portions GP11, GP13 and gate structures GS13~GS15. Conductive segment CS34 spans gate portion GP33 and conductive segment MP32. Conductive segment CS35 spans conductive segment MP18.

[0064] In some embodiments, conductive segment CS31 is coupled to conductive segment MP11 via a corresponding via. Conductive segment CS32 is coupled to gate portion GP31 via a corresponding via and is separated from conductive segment MP31 along the Z direction. Conductive segment CS33 is coupled to gate portions GP11, GP13 and gate structures GS13~GS15 via corresponding vias. Each of the vias coupled to conductive segment CS33 is inserted along the X direction between corresponding pairs in source / drain structures AA12~AA17.

[0065] In some embodiments, conductive segment CS34 is coupled to gate portion GP33 via a corresponding through-hole and is separated from conductive segment MP32 along the Z direction. Conductive segment CS35 is coupled to conductive segment MP18 via a corresponding through-hole.

[0066] As illustrated in Figure 3B, conductive segment CS36 crosses gate portion GP32 and conductive segment MN11. Conductive segment CS37 crosses conductive segment MN12. Conductive segment CS38 crosses conductive segment MN17. Conductive segment CS39 crosses gate portion GP34 and conductive segment MN18.

[0067] In some embodiments, conductive segment CS37 is coupled to conductive segment MN12 via a corresponding via. Conductive segment CS36 is coupled to gate portion GP32 via a corresponding via and is separated from conductive segment MN11 along the Z direction. Conductive segment CS39 is coupled to gate portion GP34 via a corresponding via and is separated from conductive segment MN18 along the Z direction. Conductive segment CS38 is coupled to conductive segment MN17 via a corresponding via.

[0068] In some embodiments, gate portions GP31 and GP32 are formed by cutting a gate structure extending along the Y direction, and gate portions GP33 and GP34 are formed by cutting another gate structure extending along the Y direction. Thus, along the Y direction, gate portions GP31 and GP32 are aligned and separated from each other, while gate portions GP33 and GP34 are aligned and separated from each other.

[0069] As illustrated in Figure 3B, conductive segment CZ31 spans and is coupled to each of conductive segments CS31 and CS36. Conductive segment CZ32 spans and is coupled to each of conductive segments CS32 and CS37. Conductive segment CZ33 spans and is coupled to each of conductive segments CS34 and CS38. Conductive segment CZ34 spans and is coupled to each of conductive segments CS35 and CS39. In some embodiments, conductive segments CS31-CS39 are placed in layer M0, while conductive segments CZ31-CZ34 are placed in layer M1.

[0070] Referring to Figures 3B and 3A, in some embodiments, transistor TN31 is implemented by a gate portion GP32 and source / drain structures AB11 and AB12. Transistor TP31 is implemented by a gate portion GP31 and source / drain structures AA11 and AA12. Transistor TN32 is implemented by a gate portion GP34 and source / drain structures AB17 and AB18. Transistor TP32 is implemented by a gate portion GP33 and source / drain structures AA17 and AA18. Nodes N31 to N38 correspond to conductive segments MP31, CZ32, CZ31, MN11, MP32, CZ33, CZ34, and MN18, respectively.

[0071] In some embodiments, isolation circuits BC33 and BC34 isolate the functional circuitry (such as functional circuitry FC12) of the semiconductor device 300B from the antenna circuitry AC11. Therefore, leakage current between the antenna circuitry AC11 and the functional circuitry is reduced.

[0072] Figure 3C is a schematic diagram corresponding to a portion of the semiconductor device 300B shown in Figure 3B, according to some embodiments of the present disclosure. Referring to Figures 3B and 3C, the schematic diagram shown in Figure 3C corresponds to the isolation circuit BC33 shown in Figure 3B.

[0073] As illustrated in Figure 3C, the semiconductor device 300B further includes a substrate SB31. In some embodiments, the substrate SB31 is made of a P-type material. Each of the source / drain structures AB11 and AB12 is embedded in the substrate SB31. Conductive segments MN11 and MN12 are in contact with the source / drain structures AB11 and AB12, respectively.

[0074] As illustrated in Figure 3C, conductive segment CS12 is coupled to conductive segment MN11 via a corresponding via and is separated from conductive segment CZ31 along the Z direction. Conductive segment CS36 is coupled to gate portion GP32 and conductive segment CZ31 via a corresponding via. Conductive segment CS37 is coupled to conductive segments CZ32 and MN12 via a corresponding via.

[0075] Figure 3D is a schematic diagram corresponding to a portion of the semiconductor device 300B shown in Figure 3B, based on some embodiments of the present disclosure. Referring to Figures 3B and 3D, the schematic diagram shown in Figure 3D corresponds to the isolation circuit BC33 shown in Figure 3B.

[0076] As illustrated in Figure 3D, the semiconductor device 300B further includes a well NW31. In some embodiments, the well NW31 is implemented of an N-type material. Each of the source / drain structures AA11 and AA12 is embedded in the well NW31. Conductive segments MP11 and MP31 are in contact with the source / drain structures AA11 and AA12, respectively.

[0077] As illustrated in Figure 3D, conductive segment CS11 is coupled to conductive segment MP31 via a corresponding via and is separated from conductive segment CZ32 along the Z direction. Conductive segment CS32 is coupled to gate portion GP31 and conductive segment CZ32 via a corresponding via. Conductive segment CS31 is coupled to conductive segment CZ31 and MP11 via a corresponding via.

[0078] Figure 3E is a schematic diagram corresponding to a portion of the semiconductor device 300B shown in Figure 3B, according to some embodiments of the present disclosure. Referring to Figures 3B and 3E, the schematic diagram shown in Figure 3E corresponds to the isolation circuit BC34 shown in Figure 3B.

[0079] As illustrated in Figure 3E, each of the source / drain structures AB17 and AB18 is embedded in the substrate SB31. Conductive segments MN17 and MN18 are in contact with the source / drain structures AB17 and AB18, respectively.

[0080] As illustrated in Figure 3E, conductive segment CS12 is coupled to conductive segment MN18 via a corresponding via and is separated from conductive segment CZ34 along the Z direction. Conductive segment CS39 is coupled to gate portion GP34 and conductive segment CZ34 via a corresponding via. Conductive segment CS38 is coupled to conductive segments CZ33 and MN17 via a corresponding via.

[0081] Figure 3F is a schematic diagram corresponding to a portion of the semiconductor device 300B shown in Figure 3B, according to some embodiments of the present disclosure. Referring to Figures 3B and 3F, the schematic diagram shown in Figure 3F corresponds to the isolation circuit BC34 shown in Figure 3B.

[0082] As illustrated in Figure 3F, the semiconductor device 300B further includes a well NW32. In some embodiments, the well NW32 is implemented of an N-type material. Each of the source / drain structures AA17 and AA18 is embedded in the well NW32. Conductive segments MP17 and MP38 are in contact with the source / drain structures AA17 and AA18, respectively.

[0083] As illustrated in Figure 3F, conductive segment CS11 is coupled to conductive segment MP37 via a corresponding via and is separated from conductive segment CZ33 along the Z direction. Conductive segment CS34 is coupled to gate portion GP33 and conductive segment CZ33 via a corresponding via. Conductive segment CS35 is coupled to conductive segment CZ34 and MP18 via a corresponding via.

[0084] In some embodiments, at least one of semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B is formed by a semiconductor manufacturing system. The semiconductor manufacturing system is configured to receive information associated with at least one of semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B. In some embodiments, the semiconductor manufacturing system includes manufacturing tools for fabricating integrated circuits using a set of masks fabricated based on one or more layout designs of at least one of semiconductor devices 100A, 100B, 200A, 200B, 300A, and 300B.

[0085] Figure 4 is a flowchart of a method 400 for manufacturing the semiconductor device 200B shown in Figures 2B to 2D or the semiconductor device 300B shown in Figures 3B to 3F, according to some embodiments of the present disclosure. As illustrated in Figure 4, method 400 includes operations OP41 to OP47. In some embodiments, operations OP41 to OP47 are performed sequentially.

[0086] In operation OP41, substrate SB21 is formed.

[0087] In operation OP42, the source / drain structures AA11~AA18 and AB11~AB18 are formed and embedded in the substrate SB21.

[0088] In operation OP43, gate structures GS11~GS17 and gate structures corresponding to gate portions GP11~GP14 are formed above the substrate SB21.

[0089] In operation OP44, the gate structure corresponding to the gate portions GP11~GP14 is cut into gate portions GP11~GP14.

[0090] In operation OP45, conductive segments MP11~MP17, MN12~MN17, MN21 and MN22 are formed above the corresponding source / drain structures AA11~AA18 and AB11~AB18.

[0091] In operation OP46, conductive segments CS11~CS14 and CS21~CS22 are formed above the corresponding gate structures GS11~GS17, the corresponding gate portions GP11~GP14, and the corresponding conductive segments MP11~MP17, MN12~MN17, MN21, and MN22.

[0092] In operation OP47, conductive segment CS15 is formed above conductive segments CS11~CS14 and CS21~CS22, and conductive segment CS15 spans conductive segments CS13 and CS14.

[0093] A semiconductor device is also disclosed. The semiconductor device includes a functional circuit, an antenna circuit, and a first isolation circuit. The functional circuit receives a first reference voltage signal and a second reference voltage signal. The antenna circuit receives the first reference voltage signal to share charge with the functional circuit. The first isolation circuit is placed between the functional circuit and the antenna circuit and receives the second reference voltage signal to isolate the functional circuit and the antenna circuit from each other. In some embodiments, the first isolation circuit includes a first gate structure corresponding to a first transistor of the first isolation circuit and used to receive the first reference voltage signal, and a first source / drain structure corresponding to the first transistor and used to receive the second reference voltage signal. In some embodiments, the semiconductor device further includes a first conductive segment spanning and coupled to the first source / drain structure and used to transmit the second reference voltage signal to the first source / drain structure, and a second conductive segment corresponding to the first transistor, wherein the first gate structure is placed between the first conductive segment and the second conductive segment, and the first conductive segment is longer than the second conductive segment. In some embodiments, the semiconductor device further includes a first conductive segment, a plurality of source / drain terminals of a plurality of transistors coupled to an antenna circuit, and a second conductive segment, each of a plurality of gate terminals of the transistors coupled to the antenna circuit, and a first gate structure, wherein the second conductive segment is longer than the first conductive segment along a direction, and a first isolation circuit is disposed between the functional circuit and the antenna circuit along a direction. In some embodiments, the semiconductor device further includes a second isolation circuit for isolating the antenna circuit, a first conductive segment for transmitting a second reference voltage signal to the first isolation circuit, and a second conductive segment for transmitting the second reference voltage signal to the second isolation circuit, wherein the antenna circuit is disposed between the first conductive segment and the second conductive segment. In some embodiments, the first isolation circuit includes a first gate structure for receiving the first reference voltage signal, the second isolation circuit includes a second gate structure for receiving the first reference voltage signal, and the second conductive segment, the second gate structure, the first gate structure, and the first conductive segment are arranged sequentially. In some embodiments, the first isolation circuit includes a first gate portion corresponding to a first transistor of the first isolation circuit, a first source / drain structure corresponding to the first transistor and used to receive a second reference voltage signal, a second gate portion corresponding to a second transistor of the first isolation circuit and separated from the first gate portion, and a second source / drain structure corresponding to the second transistor and used to receive the first reference voltage signal. In some embodiments, the first isolation circuit includes a third source / drain structure corresponding to the first transistor and coupled to the second gate portion, and a fourth source / drain structure corresponding to the second transistor and coupled to the second gate portion.In some embodiments, the semiconductor device further includes a second isolation circuit for isolating the antenna circuit. The second isolation circuit includes a third gate portion, a third transistor corresponding to the second isolation circuit, a third source / drain structure corresponding to the third transistor and used to receive a second reference voltage signal, a fourth gate portion, a fourth transistor corresponding to the second isolation circuit and separate from the third gate portion, and a fourth source / drain structure corresponding to the fourth transistor and used to receive a first reference voltage signal, wherein the fourth gate portion, the fourth source / drain structure, the antenna circuit, the second source / drain structure, and the second gate portion are arranged sequentially.

[0094] A semiconductor device is also disclosed. The semiconductor device includes a first gate structure, a first gate portion, a second gate portion, and a first source / drain structure. The first gate structure and the second gate structure are used to receive a first reference voltage signal. The first gate portion is disposed between the first gate structure and the second gate structure along a first direction and is used to receive the first reference voltage signal. The second gate portion is separated from the first gate portion. The first source / drain structure and the second source / drain structure are coupled together and are used to receive the first reference voltage signal. The first source / drain structure, the second gate structure, the second source / drain structure, and the first gate structure are sequentially arranged along the first direction. In some embodiments, the semiconductor device further includes a first conductive segment spanning and coupled to each of the first gate structure, the second gate structure, and the first gate portion, and a second conductive segment spanning and coupled to each of the first source / drain structure and the second source / drain structure, wherein the first conductive segment is longer than the second conductive segment along the first direction. In some embodiments, the semiconductor device further includes a third source / drain structure disposed between the first gate structure and the second gate portion, a fourth source / drain structure for operation as a first transistor together with the third source / drain structure and the first gate structure, and a first conductive segment spanning the first gate structure and coupled to each of the third source / drain structure and the fourth source / drain structure. In some embodiments, the semiconductor device further includes a third gate structure coupled to the first gate structure, a fifth source / drain structure disposed between the third gate structure and the first source / drain structure, and a sixth source / drain structure for operation as a second transistor together with the third gate structure and the fifth source / drain structure, wherein the third gate structure is disposed between the fifth source / drain structure and the sixth source / drain structure, and the sixth source / drain structure is coupled to the fifth source / drain structure. In some embodiments, the semiconductor device further includes a third source / drain structure disposed between the first gate structure and the second gate portion, a fourth source / drain structure for operating as a first transistor together with the third source / drain structure and the first gate structure, a first conductive segment spanning the fourth source / drain structure and for transmitting a first reference voltage signal to the fourth source / drain structure, and a second conductive segment spanning and coupled to the third source / drain structure, wherein the first conductive segment is longer than the second conductive segment along a second direction different from the first direction. In some embodiments, the semiconductor device further includes a third gate structure coupled to the first gate structure and operating as a control terminal of the second transistor, a third conductive segment operating as a first terminal of the second transistor, a fourth conductive segment operating as a second terminal of the second transistor, and a fifth conductive segment extending along a first direction to be coupled to each of the first conductive segment and the third conductive segment.

[0095] A method for manufacturing a semiconductor device is also disclosed. The method includes: forming a first source / drain structure, a second source / drain structure, and a third source / drain structure sequentially arranged along a first direction; forming a first gate portion between the first source / drain structure and the second source / drain structure; forming a first gate structure between the first source / drain structure and the second source / drain structure; cutting the first gate structure into a first gate portion and a second gate portion, wherein the second gate portion is aligned with and separated from the first gate portion along a second direction different from the first direction; and forming a first conductive segment extending along the first direction. The first source / drain structure is coupled to the second gate portion, the third source / drain structure is coupled to the first conductive segment, and the second source / drain structure and the third source / drain structure serve as two terminals of a first transistor. In some embodiments, the method further includes forming a fourth source / drain structure and a fifth source / drain structure sequentially arranged along a first direction, forming a third gate portion next to the fifth source / drain structure along the first direction, and forming a fourth gate portion aligned with and separated from the third gate portion along a second direction, wherein the fourth source / drain structure is coupled to a first conductive segment, the fourth gate portion is coupled to a second gate portion, and the fourth source / drain structure and the fifth source / drain structure serve as two terminals of a second transistor. In some embodiments, the method further includes forming a second conductive segment, a third conductive segment, a fourth conductive segment, and a fifth conductive segment respectively coupled to the fourth source / drain structure, the fifth source / drain structure, the second source / drain structure, and the third source / drain structure, wherein each of the second conductive segment and the fifth conductive segment is coupled to the first conductive segment, and each of the third conductive segment and the fourth conductive segment is separated from the first conductive segment along the second direction. In some embodiments, the method further includes forming a fourth source / drain structure and a fifth source / drain structure sequentially arranged along a first direction, forming a third gate portion between the fourth source / drain structure and the fifth source / drain structure, and forming a fourth gate portion aligned with and separated from the third gate portion along a second direction, wherein the fourth gate portion is coupled to the fifth source / drain structure, and the third gate portion is coupled to the second source / drain structure. In some embodiments, the method further includes forming a second conductive segment extending along the first direction and coupled to the fourth source / drain structure.

[0096] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of some embodiments disclosed herein. Those skilled in the art should understand that they can readily use some embodiments of this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of some embodiments of this disclosure.

[0097] 100A, 100B, 200A, 200B, 300A, 300B: Semiconductor devices 400: Method AA11~AA18, AB11~AB18: Source / Drain structure AC11, AC12: Antenna circuit BC11, BC12, BC13, BC14, BC21, BC22, BC23, BC24, BC31, BC32, BC33, BC34: Isolation circuits CP01, CP02: Separating spacers CS11~CS15, CS21, CS22, CS31~CS39, CZ31~CZ34, MN11~MN18, MN21, MN22, MP11~MP18, MP31, MP32: Conductive segments FC11, FC12: Functional Circuits GP11~GP14, GP31~GP34: Gate section GS11~GS17: Gate structure IS11: Input signal L21, L22: Lines N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N21, N22, N31, N32, N33, N34, N35, N36, N37, N38, N111, N112, N113: Nodes NW31, NW32: Wells OP41~OP47: Operation SB21, SB31: base plate TN11~TN13, TN14, TN15, TN21, TN22, TN31, TN32, TP11~TP13, TP14, TP15, TP16, TP17, TP31, TP32: Transistors VDD, VSS: Reference voltage signals

[0098] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: A functional circuit for receiving a first reference voltage signal and a second reference voltage signal; An antenna circuit for receiving the first reference voltage signal to share multiple charges with the functional circuit; and a first isolation circuit placed between the functional circuit and the antenna circuit, and for receiving the second reference voltage signal to isolate the functional circuit and the antenna circuit from each other, wherein the first isolation circuit includes: a first gate portion corresponding to a first transistor of the first isolation circuit; and a first source / drain structure corresponding to the first transistor and used to receive the second reference voltage signal.

2. The semiconductor device as claimed in claim 1, wherein the first gate portion is configured to receive the first reference voltage signal.

3. The semiconductor device as described in claim 2, further comprising: A first conductive segment spans and is coupled to the first source / drain structure, and is used to transmit the second reference voltage signal to the first source / drain structure; and a second conductive segment corresponding to the first transistor, wherein the first gate portion is placed between the first conductive segment and the second conductive segment, and the first conductive segment is longer than the second conductive segment.

4. The semiconductor device as claimed in claim 1, wherein the first isolation circuit further comprises: A second gate portion, corresponding to a second transistor of the first isolation circuit and separated from the first gate portion; and a second source / drain structure corresponding to the second transistor and used to receive the first reference voltage signal.

5. A semiconductor device, comprising: A first gate structure and a second gate structure are used to receive a first reference voltage signal; A first gate portion is placed between the first gate structure and the second gate structure along a first direction and is used to receive the first reference voltage signal; a second gate portion is separated from the first gate portion; and a first source / drain structure and a second source / drain structure are coupled together and are used to receive the first reference voltage signal, wherein the first source / drain structure, the second gate structure, the second source / drain structure and the first gate structure are arranged sequentially along the first direction.

6. The semiconductor device as described in claim 5, further comprising: A first conductive segment spans and is coupled to each of the first gate structure, the second gate structure, and the first gate portion; and a second conductive segment, spanning and coupled to each of the first source / drain structure and the second source / drain structure, wherein the first conductive segment is longer than the second conductive segment along the first direction.

7. The semiconductor device as described in claim 5, further comprising: A third source / drain structure is placed between the first gate structure and the second gate portion; A fourth source / drain structure for operation as a first transistor together with the third source / drain structure and the first gate structure; and a first conductive segment spanning the first gate structure and coupled to each of the third source / drain structure and the fourth source / drain structure.

8. The semiconductor device as described in claim 5, further comprising: A third source / drain structure is placed between the first gate structure and the second gate portion; A fourth source / drain structure for operating as a first transistor together with the third source / drain structure and the first gate structure; a first conductive segment spanning the fourth source / drain structure and for transmitting a second reference voltage signal to the fourth source / drain structure; and a second conductive segment spanning and coupled to the third source / drain structure, wherein the first conductive segment is longer than the second conductive segment along a second direction different from the first direction.

9. A method for manufacturing a semiconductor device, comprising: A first source / drain structure, a second source / drain structure, and a third source / drain structure are sequentially arranged along a first direction; A first gate structure is formed between the first source / drain structure and the second source / drain structure; the first gate structure is cut into a first gate portion and a second gate portion, wherein the second gate portion is aligned with and separated from the first gate portion along a second direction different from the first direction; and a first conductive segment is formed extending along the first direction, wherein the first source / drain structure is coupled to the second gate portion, the third source / drain structure is coupled to the first conductive segment, and the second source / drain structure and the third source / drain structure are used as two terminals of a first transistor.

10. The method as described in claim 9, further comprising: A fourth source / drain structure and a fifth source / drain structure are sequentially arranged along the first direction; A third gate portion is formed along the first direction next to the fifth source / drain structure; and a fourth gate portion is formed along the second direction aligned with and separated from the third gate portion, wherein the fourth source / drain structure is coupled to the first conductive segment, the fourth gate portion is coupled to the second gate portion, and the fourth source / drain structure and the fifth source / drain structure serve as two terminals of a second transistor.

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