Low warpage chip

Abstract

This invention, as a low-warpage chip, includes a chip body, a plurality of signal contacts, and a warpage limiting layer. The chip body includes a back surface and an active surface, and a circuit layer is formed inside the chip body. The plurality of signal contacts are disposed on the active surface and electrically connected to the circuit layer. The warpage limiting layer covers at least a portion of the back surface, and the coefficient of thermal expansion of the warpage limiting layer is greater than the coefficient of thermal expansion of the chip body. When this invention undergoes a thermal processing operation, the warpage limiting layer can reduce the warpage of the chip body, keeping the chip body in a relatively flat state.

Description

Technical Field

[0001] This invention relates to a semiconductor chip, specifically a chip that can reduce warpage. Prior Technology

[0002] When a multi-chip package (MCP) structure uses flip-chip technology to accommodate a larger number of chips, the chip thickness needs to be reduced as much as possible. Referring to Figure 13, the structure of chip 200 typically includes a silicon layer 201, a circuit layer 202, and multiple signal contacts 203. The circuit layer 202 is primarily made of conductive metal and is used to electrically connect these multiple signal contacts. To reduce the overall height of chip 200, the thickness of the silicon layer 201 is typically thinned during chip fabrication to ensure the overall height of chip 200 meets requirements. Conversely, because the thickness of the silicon layer 201 is reduced, the proportion of the thickness of the circuit layer 202 relative to the overall height of chip 200 also increases.

[0003] However, in the subsequent packaging process, as shown in Figure 14, when the chip 200 is electrically connected to a circuit substrate P and undergoes a thermal process, the circuit layer 202 and the silicon layer 201 have different coefficients of thermal expansion. This causes the entire chip 200 to warp after being heated, making it difficult to control the height of the chip 200. Furthermore, it may lead to poor electrical connection between the chip 200 and the circuit substrate P. Therefore, it is necessary to further improve the existing chip. Summary of the Invention

[0004] In view of the aforementioned existing chip's tendency to warp, the main purpose of this invention is to provide a low-warp chip to overcome this warping problem.

[0005] To achieve the above objectives, the technical means employed in this invention is to make the low-warpage chip include:

[0006] A wafer body includes a back surface, an active surface, and a plurality of sidewalls, the back surface being opposite to the active surface, and each of the sidewalls being connected between the back surface and the active surface, forming a circuit layer inside the wafer body;

[0007] Multiple signal contacts are disposed on the active surface of the chip body and electrically connected to the circuit layer;

[0008] A warp-limiting layer covers a local area of ​​the back side and does not extend to the plurality of sidewalls, wherein the coefficient of thermal expansion of the warp-limiting layer is greater than the coefficient of thermal expansion of the wafer body.

[0009] This invention, based on the warp location and amplitude of the chip itself, distributes a warp limiting layer at an appropriate position on the back of the chip. Because the coefficient of thermal expansion of the warp limiting layer is greater than that of the chip itself, when the chip undergoes a thermal process, the expansion deformation of the warp limiting layer can appropriately offset the expansion deformation of the chip itself, keeping the chip itself in a relatively flat state and improving the warp problem. In this way, the overall height of the low-warp chip of this invention is easier to control, and when the low-warp chip is connected to a circuit board, it can reduce electrical connection problems caused by warp, ensuring a more reliable electrical connection. Simple Explanation of the Diagram

[0010] Figure 1: Appearance of the first embodiment of the low warp chip of this invention. Figure 2: Side cross-sectional view of the first embodiment of the low warp wafer of this invention. Figure 3: Top view of the first embodiment of the low warp chip of this invention. Figures 4A-4D: Schematic diagrams of the manufacturing process of one embodiment of the low-warp chip of this invention. Figure 5: Schematic diagram of the second embodiment of the low warp chip of this invention. Figures 6A-6B: Schematic diagrams of the third embodiment of the low-warpage chip of this invention. Figures 7A-7B: Schematic diagrams of the fourth embodiment of the low-warp chip of this invention. Figure 8: Schematic diagram of the fifth embodiment of the low warp chip of this invention. Figure 9: Schematic diagram of the sixth embodiment of the low warp chip of this invention. Figures 10A-10C: Schematic diagrams of the seventh embodiment of the low-warp chip of this invention. Figures 11A-11B: Schematic diagrams of the eighth embodiment of the low-warp wafer of this invention. Figure 12: Schematic diagram of the low warp chip of this invention connected to a circuit board. Figure 13: Schematic diagram of an existing chip. Figure 14: Schematic diagram of existing wafer warping problems. Implementation

[0011] Please refer to Figures 1-3, which are schematic diagrams of the first embodiment of the low-warpage chip 100 of this invention. The chip includes a chip body 10, a plurality of signal contacts 20, and a warpage limiting layer 30.

[0012] The wafer body 10 has two opposing surfaces and a plurality of sidewalls. The two opposing surfaces are a back surface 11 and an active surface 12, and each sidewall is connected between the back surface 11 and the active surface 12. The wafer body 10 is based on a semiconductor material (such as a silicon substrate), and a circuit layer 13 made of conductive metal is formed inside the substrate. The circuit layer 13 can be a redistribution layer (RDL) made of copper material, and has a multilayer wiring structure.

[0013] The multiple signal contacts 20 are disposed on the active surface 12 of the wafer body 10, and each signal contact 20 is made of conductive material and electrically connected to the circuit layer 13.

[0014] The warpage limiting layer 30 does not completely cover the back surface 11 of the wafer body 10, nor does it extend to cover the sidewalls of the wafer body 10. The coefficient of thermal expansion (CTE) of the warpage limiting layer 30 is greater than that of the wafer body 10; a larger CTE value indicates a more significant thermal expansion effect. The distribution position, area, and shape of the warpage limiting layer 30 are adjusted according to the warpage direction and degree of warpage of the wafer body 10 to compensate for the warpage generated by the wafer body 10 after heating, so that the wafer body 10 can maintain a flat shape as much as possible.

[0015] In the first embodiment, the warpage limiting layer 30 is distributed at each corner of the back surface 11, and the edge of the warpage limiting layer 30 is flush with the edge of the back surface 11, but the warpage limiting layer 30 does not extend to cover the sidewalls of the wafer body 10. As shown in FIG3, the back surface 11 of the wafer body 10 can be defined into a plurality of equal-sized unit regions 111, in which insulating material is coated. The insulating material in each unit region 111 is called a coating block 32, and the plurality of coating blocks 32 together constitute the warpage limiting layer 30. The warpage limiting layer 30 is symmetrically distributed on both sides of a bisecting reference line L on the wafer body 10. The bisecting reference line L refers to a reference line that divides the back surface 11 of the wafer body 10 into two reference lines of the same area. For example, in FIG3, the bisecting reference line L passes through the center of the two opposite edges of the back surface 11; in other embodiments, the bisecting reference line L may also be a diagonal line passing through the two opposite corners of the back surface 11.

[0016] Regarding the fabrication method of one embodiment of the low-warpage chip 100 of this invention, please refer to Figures 4A to 4D. As shown in Figure 4A, a wafer W is first prepared, which includes a fabricated circuit layer 13 and multiple signal contacts 20. As shown in Figure 4B, the back surface of the wafer W is ground to reduce the thickness of the wafer W to achieve a preset target thickness. As shown in Figure 4C, one or more layers of insulating material are coated on the back surface of the wafer W. The insulating material is, for example, a combination of benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), or similar materials. The insulating material is attached to the back surface of the wafer W using a spin coating process or a similar method, or it is coated on the back surface by screen printing. Referring to Figure 4D, the insulating material is patterned to obtain the warpage limiting layer 30. Finally, the wafer is cut (as shown by the dotted line) to obtain a plurality of low warpage wafers 100, wherein the back side 11 of each low warpage wafer 100 has the warpage limiting layer 30 made of the aforementioned insulating material.

[0017] In addition to the first embodiment described above, this invention can flexibly adjust the distribution position of the warp restriction layer 30 based on the warp state of the wafer body 10, and will be further described below with different embodiments.

[0018] Referring to Figure 5, the warpage limiting layer 30 includes a plurality of rectangular coating blocks 32, which are concentrated in a central region of the back surface 11. These coating blocks 32 can be separated from each other or interconnected. In this embodiment, a plurality of equal-sized unit regions 111 are defined on the back surface 11 of the wafer body 10. The unit regions 111 that do not border the edge of the back surface 11 collectively form a central region of the back surface 11. In this embodiment, the warpage limiting layer 30 is symmetrically distributed along both sides of a bisecting reference line L. In other embodiments, the coating blocks 32 are distributed in unit regions 111 that border at least a portion of the edge of the back surface 11, i.e., distributed in the peripheral region of the back surface 11.

[0019] Please refer to Figures 6A and 6B, which illustrate a third embodiment of this invention. The warpage limiting layer 30 includes coating blocks 32 of different materials. A first coating block 32A made of a first insulating material is located in the central region of the back surface 11. Second coating blocks 32B made of a second insulating material are further disposed around these first coating blocks 32A. The first and second insulating materials are different materials with different coefficients of thermal expansion. In this embodiment, this invention can provide warpage limiting layers 30 composed of different insulating materials on the same wafer body 10 according to the warpage amplitude differences at different locations of the wafer body 10, thereby more effectively reducing the warpage problem of the wafer body 10.

[0020] Please refer to Figures 7A and 7B, which illustrate the fourth embodiment of this invention. The warpage limiting layer 30 includes coating blocks 32A and 32B of different materials. First coating blocks 32A, made of a first insulating material, are distributed in the central region of the back surface 11, while second coating blocks 32B, made of a second insulating material, are distributed at the four corners of the back surface 11. The first and second insulating materials are different and have different coefficients of thermal expansion. In this embodiment, the thickness of each first coating block 32A and the thickness of each second coating block 32B are different on the back surface 11; for example, the thickness of the first coating block 32A is less than the thickness of the second coating block 32B. Furthermore, the first coating blocks 32A and the second coating blocks 32B also have different shapes. By using different insulating materials, thicknesses, or shapes, the warpage of the wafer body 10 is reduced.

[0021] Please refer to Figure 8. According to the fifth embodiment of this invention, the warpage limiting layer 30 is made of different insulating materials. A plurality of second coating blocks 32B made of a second insulating material are dispersed at the corners of the back surface 11. In addition, a first coating block 32A made of a first insulating material covers each of the second coating blocks 32B and fills the remaining area of ​​the back surface 11. In this embodiment, the first coating block 32A is epoxy molding compound (EMC). The side surfaces of the first coating block 32A and the second coating block 32B are flush with the side surfaces of the wafer body 10 and do not cover the side surfaces of the wafer body 10.

[0022] Figure 9 shows the sixth embodiment of this invention. The difference from Figure 8 is that the first coating block 32A, made of epoxy molding compound (EMC), only covers other areas of the back surface 11 of the wafer body 10, that is, the other areas where the second coating block 32B is not provided. The first coating block 32A does not cover the top of each of the second coating blocks 32B, and the first coating block 32A and the second coating block 32B are coplanar on the back surface 11.

[0023] Please refer to Figures 10A-10C, which represent the seventh embodiment of this invention. A first coating block 32A is distributed along two diagonals on the back surface 11 of the wafer body 10, and this first coating block 32A presents an "X" pattern on the back surface 11. A second coating block 32B is distributed along the periphery of the back surface 11, overlapping a portion of the first coating block 32A. Figure 10C is a cross-sectional view shown along direction AA of Figure 10B. The insulating material will have a higher thickness in the overlapping area. Because of the overlapping insulating material, the overall thickness of the second coating block 32B is greater than the thickness of the first coating block 32A where there is no overlapping insulating material. In this embodiment, the first coating block 32A and the second coating block 32B are made of the same material. However, in other embodiments, the first coating block 32A and the second coating block 32B can be made of different insulating materials.

[0024] Please refer to Figures 11A and 11B, which represent the eighth embodiment of this invention. The back surface 11 of the wafer body 10 is divided into a first region A1 and a second region A2 along a bisecting reference line L. The first region A1 and the second region A2 have the same area. The wafer body 10 has signal contacts 20 with a higher density in the first region A1 and signal contacts 20 with a lower density in the second region A2. Considering the different distribution densities of the signal contacts 20, this embodiment asymmetrically distributes the first coating block 32A and the second coating block 32B along both sides of the bisecting reference line L. The first coating block 32A is distributed in the first region A1, where the insulating material has a larger total area; the second coating block 32B is distributed in the second region A2, where the insulating material has a smaller total area. Because of the difference in the distribution density or number of signal contacts 20, the chip body 10 may produce different warpage amplitudes at different locations. In this embodiment, by adjusting the coverage area of ​​the warpage limiting layer 30 in different regions, the warpage amplitude at different locations of the chip body 10 can be adaptively compensated.

[0025] Please refer to Figure 12, which is a schematic diagram of the packaging structure of this invention. The low-warpage chip 100 disclosed in any of the foregoing embodiments can be connected to the surface of a circuit substrate P through flip-chip technology. The signal contacts 20 of the low-warpage chip 100 are electrically connected to the surface of the circuit substrate P, forming a flip-chip package structure. A thermal process is performed during the flip-chip process. In this invention, a warpage limiting layer 30 is provided on the back side 11 of the chip body 10. The coefficient of thermal expansion of the warpage limiting layer 30 is greater than that of the chip body 10. Therefore, the low-warpage chip 100 can maintain a relatively flat state even when heated, improving the warpage problem. The overall height of the low-warpage chip 100 is easier to control, and there is no separation problem between it and the circuit substrate P, ensuring a more reliable electrical connection between the two.

[0026] Although the present invention has been disclosed using the above preferred embodiments, it is not intended to limit the present invention. Any modifications, alterations or combinations made by those skilled in the art relative to the above embodiments without departing from the spirit and scope of the present invention shall still fall within the scope of the technology protected by the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0027] 100: Low warp wafer 10: Chip body 11: Back 111: Cell Region 12: Proactive Face 13: Line Layer 20: Signal contact 30: Warp confinement layer 32: Coating Block 32A: First coating block 32B: Second coating block W: Wafer L: Bisects the baseline A1: First Area A2: Second Area P: Circuit board 200: Chip 201: Silicon Crystal Layer 202: Line Layer 203: Signal contact

Claims

1. A low-warpage wafer, comprising: a wafer body including a back surface, an active surface, and a plurality of sidewalls, wherein the back surface is opposite to the active surface, and each of the sidewalls is connected between the back surface and the active surface, the back surface of the wafer body being divided into a plurality of unit regions of equal area; a plurality of signal contacts disposed on the active surface of the wafer body; a warpage limiting layer covering at least a portion of the back surface and not extending to the plurality of sidewalls, the coefficient of thermal expansion of the warpage limiting layer being greater than the coefficient of thermal expansion of the wafer body, and the warpage limiting layer being made of an insulating material, the warpage limiting layer comprising a plurality of coating blocks distributed on the back surface, the plurality of coating blocks being distributed in at least a portion of the unit regions adjacent to the edge of the back surface.

2. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks includes at least one first coating block and a plurality of second coating blocks, wherein the first coating block and the second coating block are made of different materials and have different coefficients of thermal expansion.

3. The low-warpage wafer as described in claim 2, wherein, The first coating block overlaps and covers each of the second coating blocks.

4. The low-warpage wafer as described in claim 2, wherein, The first coating block and each of the second coating blocks are coplanar on the back side.

5. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks of the warp limiting layer include a plurality of first coating blocks and a plurality of second coating blocks, the first coating blocks and the second coating blocks having different thicknesses on the back side.

6. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks of the warp limiting layer include a plurality of first coating blocks and a plurality of second coating blocks, wherein the first coating blocks and the second coating blocks at least partially overlap on the back side.

7. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks of the warp-limiting layer include a plurality of first coating blocks and a plurality of second coating blocks, the first coating blocks and the second coating blocks having different shapes.

8. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks includes a plurality of first coating blocks and a plurality of second coating blocks; the back surface is divided into two regions of equal area along a bisecting baseline, and the plurality of first coating blocks and the plurality of second coating blocks are symmetrically distributed on both sides of the bisecting baseline.

9. The low-warpage wafer as described in claim 1, wherein, The plurality of coating blocks includes a plurality of first coating blocks and a plurality of second coating blocks; the back surface is divided into two regions of equal area along a bisecting baseline, and the plurality of first coating blocks and the plurality of second coating blocks are asymmetrically distributed along both sides of the bisecting baseline.

10. The low-warpage wafer as claimed in claim 9, wherein the bisecting reference line divides the back surface into a first region and a second region; the number of signal contacts in the first region is greater than the number of signal contacts in the second region; the plurality of first coating blocks are located in the first region, and the plurality of second coating blocks are located in the second region, wherein, The total area of ​​the plurality of first coating blocks is greater than the total area of ​​the plurality of second coating blocks.

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