Display device

Abstract

This invention improves the reliability of display devices using transistors comprising oxide semiconductors. The display device of this invention comprises a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction. Each of the plurality of pixels has: a transistor comprising an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer and extending in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer disposed on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer disposed on the second insulating layer and having an opening; and a second inorganic layer disposed on the first inorganic layer and in contact with the second insulating layer at the opening; wherein the coverage of the first inorganic layer over the second insulating layer is 85% or more relative to the area of ​​the pixel.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor comprising an oxide semiconductor. Furthermore, one embodiment of the present invention relates to a method for manufacturing a display device. Prior Technology

[0002] In recent years, the development of transistors using oxide semiconductors for channels has made continuous progress, replacing amorphous silicon, low-temperature polycrystalline silicon, and monocrystalline silicon (see, for example, Patent Documents 1 and 2). Similar to transistors using amorphous silicon for channels, transistor systems using oxide semiconductors for channels are formed with a simple structure and through low-temperature processes. It is known that, compared to transistors using amorphous silicon for channels, transistors using oxide semiconductors for channels have higher mobility and very low off-state current. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2014-146819 [Patent Document 2] Japanese Patent Application Publication No. 2015-159315 Summary of the Invention

[0004] [The problem the invention aims to solve] It is known that the properties of transistors containing oxide semiconductors can change due to the infiltration of moisture into the oxide semiconductor. Furthermore, in display devices, a planarization film containing an organic resin layer is provided to mitigate the unevenness formed by the transistor. Since the organic resin layer contains a large amount of moisture, if hydrogen contained in the organic resin layer infiltrates into the oxide semiconductor, it may cause changes in the transistor's properties, reducing the reliability of the display device.

[0005] In one embodiment of the present invention, one objective is to improve the reliability of display devices using transistors comprising oxide semiconductors. [Technical means to solve the problem]

[0006] A display device according to one embodiment of the present invention includes a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction. Each of the plurality of pixels has: a transistor having an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer and extending in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer disposed on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer disposed on the second insulating layer and having an opening; and a second inorganic layer disposed on the first inorganic layer and in contact with the second insulating layer at the opening; wherein the coverage of the first inorganic layer over the second insulating layer is 85% or more relative to the area of ​​the pixel. Simple Explanation of the Diagram

[0007] Figure 1 is a top view showing an outline of a display device according to one embodiment of the present invention. Figure 2 is a block diagram showing the circuit configuration of a display device according to one embodiment of the present invention. Figure 3 is a circuit diagram showing the pixel circuit of a pixel in a display device according to one embodiment of the present invention. Figure 4 is a cross-sectional view showing the configuration of a display device according to one embodiment of the present invention. Figure 5 is a top view showing the configuration of a display device according to one embodiment of the present invention. Figure 6 is a top view showing the configuration of a display device according to one embodiment of the present invention. Figure 7 is a sequence diagram illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 8 is a sequence diagram illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 9 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 10 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 11 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 12 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 13 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 14 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 15 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 16 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 17 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 18 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. Figure 19 is a cross-sectional view showing the configuration of a display device according to another embodiment of the present invention. Figure 20 is a cross-sectional view showing the configuration of a display device according to another embodiment of the present invention. Figure 21 is a cross-sectional view showing the configuration of a display device according to another embodiment of the present invention. Figure 22 is a cross-sectional view showing the configuration of a display device according to another embodiment of the present invention. Implementation

[0008] Hereinafter, various embodiments of the present invention will be described with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art while maintaining the spirit of the invention through appropriate changes in the configuration of the embodiments are, of course, included within the scope of the present invention. To make the description clearer, the width, film thickness, shape, etc. of each part are sometimes shown in a patterned manner in the drawings compared to the actual form. However, the shapes shown in the drawings are merely examples and are not intended to limit the interpretation of the present invention. In this specification and in the drawings, configurations that are the same as those described in the drawings above are labeled with the same symbols, and detailed descriptions are sometimes appropriately omitted.

[0009] "Display device" refers to a structure that displays images using an optoelectronic layer. For example, the term "display device" sometimes refers to a display panel containing an optoelectronic layer, or sometimes it refers to a structure obtained by mounting other optical components (e.g., polarizing components, backlights, touch panels, etc.) to a display unit. As long as there is no technical inconsistency, the "optoelectronic layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, in the following embodiments, a liquid crystal display device containing a liquid crystal layer is described as an example of a display device, but the structure in this embodiment can be applied to display devices containing the other optoelectronic layers mentioned above.

[0010] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for ease of explanation, the terms "up" or "below" are used, but for example, the vertical relationship between the substrate and the oxide semiconductor layer may be configured in a different orientation than shown in the figure. In the following description, for example, the expression of the oxide semiconductor layer on the substrate only illustrates the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may also be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking sequence of a structure with multiple layers. When expressed as a pixel electrode above a transistor, it may refer to the positional relationship where the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, when expressed as a pixel electrode vertically above a transistor, it refers to the positional relationship where the transistor and the pixel electrode overlap when viewed from above.

[0011] Unless otherwise expressly stated, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one of the groups selected from A, B, and C" in this specification do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the possibility that α includes other elements.

[0012] Furthermore, as long as no technical contradictions arise, the following implementation methods can be combined with each other.

[0013] [First Implementation] [1. Overview of Display Device 10] A summary of a display device 10 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a top view showing a summary of a display device 10 according to one embodiment of the present invention. In this embodiment, the configuration of a liquid crystal display device as the display device 10 will be described.

[0014] As shown in Figure 1, the display device 10 includes an array substrate 300, a sealing portion 400, a counter substrate 500, a flexible printed circuit board (FPC) 600, and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the sealing portion 400. In the liquid crystal region 22 surrounded by the sealing portion 400, a plurality of pixels 310 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The plurality of pixels 310 includes red pixels R, green pixels G, and blue pixels B corresponding to the color filters disposed on the counter substrate. Each of the red pixels R, green pixels G, and blue pixels B is also referred to as a sub-pixel. The first direction D1 and the second direction D2 may be orthogonal. The liquid crystal region 22 is the region that overlaps with the liquid crystal element 410 described below when viewed from above. Furthermore, hereafter, the region containing the plurality of pixels in the liquid crystal region 22 is sometimes referred to as the image display region or the active region.

[0015] Furthermore, the display device 10 has a backlight unit on the back of the array substrate 300. When the light emitted from the backlight unit passes through the image display area, the image is displayed by modulating the transmitted light in each pixel.

[0016] The sealing region 24, where the sealing portion 400 is provided, is the area surrounding the liquid crystal region 22. The FPC 600 is disposed on the terminal region 26. The terminal region 26 is the area of ​​the array substrate 300 exposed from the opposing substrate 500, and is disposed outside the sealing region 24. Furthermore, "outside the sealing region 24" refers to the area where the sealing portion 400 is provided and the area surrounded by the sealing portion 400. The IC chip 700 is disposed on the FPC 600. The IC chip 700 supplies signals for driving the pixel circuits of each pixel 310. Furthermore, hereinafter, the sealing region 24, the area outside the sealing region 24, and the terminal region 26 (excluding the image display area) are sometimes collectively referred to as the peripheral region.

[0017] [2. Circuit configuration of display device 10] Figure 2 is a block diagram showing the circuit configuration of a display device 10 according to one embodiment of the present invention. As shown in Figure 2, a gate driver circuit 330 is provided adjacent to the liquid crystal region 22 where the pixel 310 is disposed in the first direction D1, and a source driver circuit 320 is provided adjacent to the liquid crystal region 22 in the second direction D2. The source driver circuit 320 and the gate driver circuit 330 are disposed in the aforementioned sealed region 24. However, the region for which the source driver circuit 320 and the gate driver circuit 330 are disposed is not limited to the sealed region 24, and can be any region outside the region where the pixel circuit of the pixel 310 is disposed.

[0018] Gate wiring 331 extends from gate driver circuit 330 in the first direction D1 and is connected to the pixel circuit of a plurality of pixels 310 arranged in the first direction D1. Source wiring 321 extends from source driver circuit 320 in the second direction D2 and is connected to the pixel circuit of a plurality of pixels 310 arranged in the second direction D2.

[0019] A terminal section 333 is provided in the terminal area 26. The terminal section 333 is connected to the source driver circuit 320 via a connection cable 341. Similarly, the terminal section 333 is connected to the gate driver circuit 330 via a connection cable 342. By connecting the FPC 600 to the terminal section 333, an external machine to which the FPC 600 is connected is connected to the display device 10, and the pixel circuits included in each pixel 310 of the display device 10 are driven by signals from the external machine.

[0020] [3. Pixel circuit of display device 10 pixels 310] Figure 3 is a circuit diagram showing the pixel circuit of the pixel 310 of the display device 10 according to one embodiment of the present invention. As shown in Figure 3, the pixel circuit includes components such as a transistor 800, a holding capacitor 890, and a liquid crystal element 410. One electrode of the holding capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO, details of which will be described below. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a gate electrode 810, a source electrode 830, and a drain electrode 840. The gate electrode 810 is connected to the gate wiring 331. The source electrode 830 is connected to the source wiring 321. The drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. Furthermore, in this embodiment, for ease of explanation, 830 is referred to as the source electrode and 840 as the drain electrode, but the functions of each electrode as a source and as a drain can be interchanged.

[0021] [4. Composition of the display device 10] The details of the configuration of a display device 10 according to one embodiment of the present invention will be described with reference to Figures 4 to 6. Figure 4 is a cross-sectional view showing the configuration of the display device 10 according to one embodiment of the present invention. Figures 5 and 6 are top views showing the configuration of the display device 10 according to one embodiment of the present invention. Furthermore, the cross-sectional view in Figure 4 is used to illustrate the layer structure of the display device 10, corresponding to the view seen from the direction of the arrow along the dotted line in Figure 6. In fact, the pixel circuit is disposed in the image display area. In particular, in the pixel circuit in Figure 4, mainly the periphery of the contact hole in the pixel area is shown, while only a portion of the transmission area (aperture area) that facilitates display is shown. The liquid crystal layer and the opposing substrate are omitted in Figure 4. Figure 4 shows a liquid crystal display device of FFS (Fringe Field Switching) mode, but it may also be a liquid crystal display device of IPS (In Plane Switching) mode.

[0022] As shown in Figure 4, the display device 10 is disposed above the substrate SUB. The display device 10 includes a transistor Tr, wiring W1, connecting electrode ZTCO, pixel electrode PTCO, common auxiliary electrode CMTL, and common electrode CTCO. TCO is short for Transparent Conductive Oxide. The transistor Tr is the transistor included in the pixel circuit of the pixel 310 of the display device 10.

[0023] [5. Composition of transistor Tr] A transistor Tr is disposed on a light-shielding layer LS and a first insulating layer IL1 disposed on a substrate SUB. The transistor Tr has an oxide semiconductor layer OS, a second insulating layer IL2, and a gate wiring GL (corresponding to the gate electrode 810 and gate wiring 331 shown in FIG. 3). Furthermore, the transistor Tr may have a metal oxide layer MO1 disposed between the oxide semiconductor layer OS and the first insulating layer IL1. The gate wiring GL faces the oxide semiconductor layer OS. The second insulating layer IL2 is disposed between the oxide semiconductor layer OS and the gate wiring GL. In this embodiment, a top-gate transistor with the oxide semiconductor layer OS disposed closer to the substrate SUB than the gate wiring GL is illustrated; however, a bottom-gate transistor with the gate wiring GL and the oxide semiconductor layer OS in the opposite positional relationship may also be used.

[0024] The oxide semiconductor layer OS comprises a channel region CA, a source region SA, and a drain region DA. The channel region CA is the area of ​​the oxide semiconductor layer that overlaps with the gate wiring GL when viewed from above. The channel region CA switches between a conducting and a non-conducting state depending on the voltage supplied to the gate wiring GL. The source region SA and drain region DA are regions with lower resistance than the channel region. For example, the source region SA and drain region DA are regions obtained by doping the oxide semiconductor layer OS with impurities to reduce its resistance.

[0025] The gate wiring GL is configured along the first direction D1. The oxide semiconductor layer OS is configured to cross relative to the gate wiring GL. The region in the gate wiring GL that overlaps with the oxide semiconductor layer OS functions as a gate electrode.

[0026] A third insulating layer IL3 is provided above the gate wiring GL. A wiring W1 (corresponding to source electrode 830 and source wiring 321 in Figure 3) is provided above the third insulating layer IL3. Wiring W1 is arranged along the second direction D2. Wiring W1 is connected to the source region SA via contact holes WCON provided in the second insulating layer IL2 and the third insulating layer IL3. Data signals related to the grayscale of the pixel are transmitted to wiring W1. A fourth insulating layer IL4 is provided above the third insulating layer IL3 and wiring W1. A connecting electrode ZTCO (corresponding to drain electrode 840 in Figure 3) is provided above the fourth insulating layer IL4. Connecting electrode ZTCO is connected to the drain region DA via contact holes ZCON provided in the second insulating layer IL2 to the fourth insulating layer IL4. The bottom of the connecting electrode ZTCO is in contact with the drain region DA. Connecting electrode ZTCO is a transparent conductive layer.

[0027] The area where the connecting electrode ZTCO connects to the drain region DA is called the first contact area CON1. ​​The common electrode CTCO, in the first contact area CON1 which does not overlap with the gate wiring GL and wiring W1 when viewed from above, connects to the drain region DA; details will be described below. When viewed from above, the first contact area CON1 is included within the display area of ​​the pixel.

[0028] A fifth insulating layer IL5 is disposed above the connecting electrode ZTCO. The fifth insulating layer IL5 mitigates the step difference formed by the structure disposed on a lower layer than the fifth insulating layer IL5. The fifth insulating layer IL5 is sometimes referred to as a planarization film. Furthermore, the fifth insulating layer contains an organic resin. A pixel electrode PTCO is disposed above the fifth insulating layer IL5. The pixel electrode PTCO is connected to the connecting electrode ZTCO via a contact hole PCON disposed in the fifth insulating layer IL5. The area where the connecting electrode ZTCO and the pixel electrode PTCO are in contact is called the second contact area CON2. In top view, the second contact area CON2 overlaps with the gate wiring GL. The pixel electrode PTCO is a transparent conductive layer.

[0029] A sixth insulating layer IL6 is disposed above the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are disposed above the sixth insulating layer IL6. The common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns, details of which will be described below. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL is lower than that of the common electrode CTCO. Furthermore, the common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. A spacer SP is disposed above the common electrode CTCO.

[0030] From a top view, the common auxiliary electrode CMTL is arranged in a grid pattern. The common auxiliary electrode CMTL is configured to traverse the contact hole PCON in the first direction D1 and overlap with the wiring W1 in the second direction D2. An opening COP is provided on the common auxiliary electrode CMTL. The opening COP corresponds to the opening of a pixel. The common electrode CTCO is disposed on the common auxiliary electrode CMTL and is configured to cover the entire image display area. A slit pattern is provided in the area of ​​the common electrode CTCO that overlaps with the opening COP and the pixel electrode PTCO. This slit pattern also overlaps with the pixel electrode PTCO. Furthermore, an opening IOP is provided in the sixth insulating layer IL6, which will be described in detail below.

[0031] Spacers SP are provided for a subset of pixels. For example, spacers SP can be provided for any one of the red pixel R, green pixel G, and blue pixel B. However, spacers SP can also be provided for all pixels. The height of the spacer SP is half the height of the cell gap. Spacers are also provided on the opposing substrate, and the spacers on the opposing substrate overlap with the aforementioned spacers SP in a top view. Furthermore, a configuration in which the height of the spacers SP is equivalent to the cell gap can also be used. Also, as shown in FIG4, the spacers fill the contact hole PCON and protrude toward the opposing substrate side, but a configuration in which only a filler is used to fill the contact hole can also be used.

[0032] A light-shielding layer LS is provided between the transistor Tr and the substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as light-shielding layers LS. However, the light-shielding layer LS may also be formed only by light-shielding layer LS1 or only by light-shielding layer LS2. In top view, the light-shielding layer LS is disposed along the first direction D1 and is disposed in the region overlapping with the gate wiring GL. Furthermore, the light-shielding layer LS is disposed to intersect with the oxide semiconductor layer OS. That is, in top view, the light-shielding layer LS is disposed in the region overlapping with the channel region. The light-shielding layer LS suppresses light incident from the substrate SUB side from reaching the channel region. When a conductive layer is used as the light-shielding layer LS, a voltage can also be applied to the light-shielding layer LS to control the channel region. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL can be connected in the peripheral region of the pixel circuit. In top view, the aforementioned first contact region CON1 is disposed in the region that does not overlap with the light-shielding layer LS.

[0033] It is known that the properties of transistors containing oxide semiconductors can change due to the infiltration of moisture into the oxide semiconductor. Furthermore, in display devices, a planarization film containing organic resin is provided to mitigate the unevenness formed by the transistor. Since organic resin contains a large amount of moisture, if hydrogen from the organic resin infiltrates into the oxide semiconductor, it may cause changes in the transistor's properties, reducing the reliability of the display device.

[0034] In display devices using transistors containing oxide semiconductors, it is necessary to fully release the moisture contained in the organic resin layer disposed on the transistor. Even if annealing is performed in the manufacturing process with the organic resin layer exposed, moisture will be reabsorbed from the surface of the exposed organic resin layer in subsequent processes.

[0035] For example, in the case of liquid crystal display devices, inorganic layers such as pixel electrodes, common electrodes, auxiliary electrodes, or inorganic insulating layers are disposed on an organic resin layer. Compared to the organic resin layer, the inorganic layer has the function of inhibiting moisture permeation. Even if annealing is performed with pixel electrodes formed on an organic resin layer, moisture may still be absorbed from the outside because the surface of the organic resin layer is exposed from the pixel electrodes, causing changes in the characteristics of the transistors. Similarly, even if annealing is performed with common electrodes formed on an organic resin layer, moisture may still be absorbed from the outside because the surface of the organic resin layer is exposed from the common electrodes, causing changes in the characteristics of the transistors. As the resolution of display devices increases, the area of ​​pixels and the area occupied by transistors decrease. Therefore, changes in the characteristics of transistors have a significant impact on the display quality of the display device.

[0036] Therefore, in order to suppress the characteristic changes of transistors containing oxide semiconductors, it is important to release the moisture contained in the organic resin layer to the outside and to prevent the moisture from being drawn back into the organic resin layer from the outside in subsequent processes.

[0037] In one embodiment of the present invention, a first inorganic layer is disposed on an organic resin layer, and an opening IOP is provided in the first inorganic layer. The coverage of the organic resin layer by the first inorganic layer is 85% or more relative to the area of ​​the pixel. A second inorganic layer is disposed on the first inorganic layer, and the second inorganic layer is in contact with the organic resin layer at the opening. That is, the opening IOP disposed on the first inorganic layer is blocked by the second inorganic layer disposed on the first inorganic layer.

[0038] In the manufacturing process of the display device 10, after forming the opening IOP in the first inorganic layer, an annealing process is performed. Here, moisture contained in the organic resin layer is released to the outside through the opening IOP in the first inorganic layer. At this time, since the coverage of the organic resin layer by the first inorganic layer is 85% or more relative to the pixel area, moisture is concentrated and released from the opening IOP. Furthermore, it is possible to suppress moisture from seeping into the organic resin layer from the outside of the first inorganic layer. Moreover, by using a second inorganic layer disposed on top of the first inorganic layer to block the opening IOP, it is possible to further suppress moisture from seeping into the organic resin layer from the outside.

[0039] In a display device 10 according to one embodiment of the present invention, by using a second inorganic layer to block the opening IOP provided in the first inorganic layer, moisture can be prevented from seeping into the organic resin layer not only during the manufacturing process but also when the display device is in use. Therefore, moisture contained in the organic resin layer can be prevented from seeping back into the oxide semiconductor. This suppresses changes in transistor characteristics, thereby improving the reliability of the display device.

[0040] In this specification, the area of ​​a subpixel can be calculated using the following formula. Active region / resolution = area of ​​subpixels Furthermore, depending on the display device, the areas of the red pixel R, green pixel G, and blue pixel B may differ. In this case, the area of ​​the three sub-pixels can be calculated as the area of ​​one pixel. Similarly, the coverage rate of the organic resin layer covering the first inorganic layer can also be calculated using the area of ​​the three sub-pixels as the area of ​​one pixel.

[0041] For example, when the active region (mm²) is 38.4 mm × 38.4 mm and the resolution is 1600 (RGB) × 1600, the area of ​​each sub-pixel is 192 μm². Therefore, as long as the first inorganic layer in the sub-pixel is coated with an organic resin layer of 163.2 μm² or more, the moisture contained in the organic resin layer can be released from the opening (IOP) of the first inorganic layer, and the reabsorption of moisture into the organic resin layer can be prevented in subsequent processes.

[0042] Each of the first and second inorganic layers is formed of a conductive layer, a transparent conductive layer, and an inorganic insulating layer. Each of the first and second inorganic layers can be a single layer or a multilayer structure. In the case of a multilayer structure, for example, it can be a multilayer structure of a transparent conductive layer and an inorganic insulating layer, or a multilayer structure with multiple inorganic insulating layers. The thickness of each of the first and second inorganic layers is not particularly limited, but it is preferably at least 30 nm and 50 nm to 200 nm. When the thickness of the first inorganic layer is less than 30 nm, the blocking effect against external moisture may be weakened. In this case, a second inorganic layer, thicker than the first inorganic layer, can be disposed on top of the first inorganic layer to fill the opening (IOP) disposed in the first inorganic layer. Furthermore, as long as it does not affect the driving of the liquid crystal element, the thickness of the second inorganic layer can be above 200 nm.

[0043] The area of ​​the opening IOP provided in the sixth insulating layer IL6 can be smaller than the area of ​​the contact hole provided in the fifth insulating layer IL5. In other words, the coverage of the organic resin layer coated on the first inorganic layer is 85% or more, preferably 95% or more, and more preferably 98% or more relative to the pixel area. When the area of ​​the opening IOP is large, even if moisture is released from the organic resin layer to the outside through the opening IOP, moisture may still be drawn back into the outside through the opening IOP during the annealing process. By making the area of ​​the opening IOP smaller than the area of ​​the contact hole, it is possible to prevent the moisture released from the organic resin layer from being drawn back in.

[0044] In the structure of the display device 10 shown in Figures 4-6, the first inorganic layer is the pixel electrode PTCO and the sixth insulating layer IL6, and the second inorganic layer is the common electrode CTCO. An opening IOP is provided in the sixth insulating layer IL6. The common electrode CTCO is connected to the fifth insulating layer IL5 at the opening IOP. The common electrode CTCO, located within the pixel at the opening IOP, is not connected to other conductive layers. Furthermore, the coverage of the sixth insulating layer IL6 over the fifth insulating layer IL5 is 85% or more relative to the pixel area.

[0045] Furthermore, the opening IOP disposed in the sixth insulating layer IL6 is preferably disposed in the region overlapping with the oxide semiconductor layer OS. By disposing the opening IOP near the oxide semiconductor layer OS, the influence of moisture contained in the organic resin layer can be reduced. The opening IOP is more preferably configured to overlap with the gate wiring overlap region in the oxide semiconductor layer OS.

[0046] As explained above, in a display device according to one embodiment of the present invention, after the moisture contained in the organic resin layer disposed on the transistor is released, it is possible to prevent the reabsorption of moisture from the outside into the organic resin layer. By suppressing the penetration of moisture from the organic resin layer into the oxide semiconductor layer, changes in the characteristics of the transistor can be suppressed. Therefore, the reliability of the display device can be improved.

[0047] [6. Manufacturing method of display device] A method for manufacturing a display device 10 according to one embodiment of the present invention will be described. Figures 7 and 8 are sequence diagrams illustrating the method for manufacturing a display device 10 according to one embodiment of the present invention. Figures 9 to 18 are cross-sectional views illustrating the method for manufacturing a display device 10 according to one embodiment of the present invention.

[0048] First, light-shielding layers LS1 and LS2 are formed on the substrate SUB as light-shielding layer LS (refer to step S1001 "LS formation" in Figure 7 and Figure 9).

[0049] As a substrate SUB, rigid substrates with light transmittance, such as glass substrates, quartz substrates, and sapphire substrates, can be used. When the substrate SUB needs to be flexible, polyimide substrates, acrylic resin substrates, silicone alkyl boards, fluoropolymer substrates, or substrates containing organic resins can be used as the substrate SUB. When using a substrate containing organic resin as the substrate SUB, impurity elements can be introduced into the aforementioned organic resin to improve the heat resistance of the substrate SUB.

[0050] The light-shielding layer LS is formed, for example, by processing a conductive layer that has been formed by sputtering. The light-shielding layer LS can be made of common metallic materials. Examples of materials that can be used as the light-shielding layer LS include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. As shown in FIG9, after forming the light-shielding layer LS1, the light-shielding layer LS2 is formed by covering the light-shielding layer LS1. In this embodiment, the case of formation by stacking the light-shielding layers LS1 and LS2 is described, but it can also be formed as a single layer.

[0051] Next, a first insulating layer IL1 is formed on the light-shielding layer LS as a base layer (refer to step S1002 "IL1 film formation" in Figure 7 and Figure 9).

[0052] The first insulating layer IL1 is formed by CVD (Chemical Vapor Deposition) or sputtering. The first insulating layer IL1 can be made of common insulating materials. For example, inorganic insulating materials such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), and aluminum nitride (AlNx) can be used as the first insulating layer IL1.

[0053] The aforementioned SiOxNy and AlOxNy are silicon and aluminum compounds containing a smaller ratio of nitrogen (N) than oxygen (O) (x>y). SiNxOy and AlNxOy are silicon and aluminum compounds containing a smaller ratio of oxygen (x>y) than nitrogen.

[0054] The first insulating layer IL1 is formed from a single layer or a multilayer structure. When the first insulating layer IL1 is a multilayer structure, it is preferable to sequentially form a nitrogen-containing insulating material and an oxygen-containing insulating material from the substrate SUB. By using a nitrogen-containing insulating material, for example, impurities diffusing from the substrate SUB towards the oxide semiconductor layer OS can be blocked. Furthermore, by using an oxygen-containing insulating material, oxygen can be released by heat treatment. The heat treatment temperature for releasing oxygen from the oxygen-containing insulating material is, for example, 600°C or below, 500°C or below, 450°C or below, or 400°C or below. That is, the oxygen-containing insulating material releases oxygen, for example, at the heat treatment temperature performed in the manufacturing process of the display device when a glass substrate is used as the substrate SUB. In this embodiment, silicon nitride is formed as an example of the nitrogen-containing insulating material. Silicon oxide is formed as an example of the oxygen-containing insulating material.

[0055] Subsequently, a metal oxide layer MO1 with aluminum as the main component is formed on the first insulating layer IL1 (refer to the "MO1 film formation" in step S1003 shown in Figure 7 and Figure 10).

[0056] The metal oxide layer MO1 is formed by sputtering. For example, aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), and aluminum nitride (AlNx) are inorganic insulating layers. "Aluminum-based metal oxide layer" means that the aluminum content in the metal oxide layer MO1 is 1% or more of the total metal oxide layer MO1. The aluminum content in the metal oxide layer MO1 can be 5% to 70%, 10% to 60%, or 30% to 50% of the total metal oxide layer MO1. These ratios can be either mass ratios or weight ratios.

[0057] The thickness of the metal oxide layer MO1 is, for example, 2 nm to 100 nm, 2 nm to 50 nm, 2 nm to 30 nm, or 2 nm to 15 nm. In this embodiment, alumina is used as the metal oxide layer MO1. Alumina has high gas barrier properties.

[0058] Subsequently, an oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (refer to step S1004 "OS film formation" in Figure 7 and Figure 10).

[0059] The oxide semiconductor layer (AOS) is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor layer (AOS) is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0060] As an oxide semiconductor layer (AOS), metal oxides with semiconductor properties can be used.

[0061] When forming an oxide semiconductor layer (AOS) by sputtering, the temperature of the object to be formed (substrate SUB and the structures formed thereon) is controlled while forming the oxide semiconductor layer (AOS).

[0062] If a film is formed on an object by sputtering, ions generated in the plasma and atoms recoiled by the sputtering target will collide with the object, causing the temperature of the object to rise during the film formation process. As described above, in order to control the temperature of the object, film formation can be performed while the object is being cooled. For example, the object can be cooled from the side opposite to the film-forming surface to reduce the temperature of that film-forming surface (hereinafter referred to as the "film formation temperature") to below 100°C, below 70°C, below 50°C, or below 30°C.

[0063] Next, a pattern of the oxide semiconductor layer AOS is formed ("OS pattern formation" in step S1005 shown in Figure 7). Although not illustrated, a photoresist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the photoresist mask. The etching of the oxide semiconductor layer AOS can be performed using either wet etching or dry etching. For wet etching, an acidic etchant can be used. Examples of etchants include oxalic acid or hydrofluoric acid.

[0064] It is preferable that the oxide semiconductor layer AOS is patterned before OS annealing. Furthermore, even if the oxide semiconductor layer AOS is damaged by etching, the damage can be repaired by OS annealing, which is therefore preferable.

[0065] After the oxide semiconductor layer AOS is patterned, it undergoes heat treatment (OS annealing) (step S1006 "OS annealing" shown in Figure 7 and Figure 11). In the OS annealing process, the oxide semiconductor layer AOS is held at a specified extreme temperature for a specified time. The specified extreme temperature is 300°C to 500°C, preferably 350°C to 450°C. Furthermore, the holding time at the extreme temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. The oxide semiconductor layer OS is thus formed.

[0066] Subsequently, a second insulating layer IL2 is formed on the oxide semiconductor layer OS ("IL2 film formation" in step S1008 shown in Figure 7 and Figure 13).

[0067] The method for forming the second insulating layer IL2 and the insulating material are the same as those for the first insulating layer IL1. Furthermore, the film thickness of the second insulating layer IL2 is, for example, 50 nm to 150 nm.

[0068] As the second insulating layer IL2, it is preferable to use an insulating material containing oxygen. Furthermore, as the second insulating layer IL2, it is preferable to use an insulating layer with fewer defects. For example, when comparing the oxygen composition ratio in the second insulating layer IL2 with the oxygen composition ratio in an insulating layer with the same composition as the second insulating layer IL2 (hereinafter referred to as "other insulating layers"), the oxygen composition ratio in the second insulating layer IL2 is closer to the stoichiometry of that insulating layer than the oxygen composition ratio in the other insulating layer. For example, when both the second insulating layer IL2 and the third insulating layer IL3 are made of silicon oxide (SiOx), the oxygen composition ratio in the silicon oxide used as the second insulating layer IL2 is closer to the stoichiometry of silicon oxide than the oxygen composition ratio in the silicon oxide used as the third insulating layer IL3. For example, a layer in which no defects were observed when evaluated by electron spin resonance (ESR) can be used as the second insulating layer IL2.

[0069] To form a second insulating layer IL2 with fewer defects, the second insulating layer IL2 can be formed at a film-forming temperature of 350°C or higher. Furthermore, after forming the second insulating layer IL2, a process of implanting oxygen into a portion of the second insulating layer IL2 can be performed. In this embodiment, silicon oxide is formed at a film-forming temperature of 350°C or higher to form the second insulating layer IL2 with fewer defects.

[0070] Subsequently, a metal oxide layer MO2 with aluminum as the main component is formed on the second insulating layer IL2 ("MO2 film formation" in step S1009 shown in Figure 7 and Figure 13).

[0071] The method for forming the metal oxide layer MO2 and the insulating material are the same as those described for the metal oxide layer MO1. Oxygen is injected into the second insulating layer IL2 by forming the metal oxide layer MO2. The film thickness of the metal oxide layer MO2 is, for example, 2 nm to 100 nm, 2 nm to 50 nm, 2 nm to 30 nm, or 2 nm to 15 nm. In this embodiment, alumina can be used as the metal oxide layer MO2. Alumina has high gas barrier properties. In this embodiment, the alumina used as the metal oxide layer MO2 suppresses the outward diffusion of oxygen injected into the second insulating layer IL2 during the formation of the metal oxide layer MO2.

[0072] For example, when a metal oxide layer MO2 is formed by sputtering, the processing gas used in sputtering may remain in the MO2 film. For instance, when Ar is used as the processing gas for sputtering, Ar may sometimes remain in the MO2 film. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the MO2 metal oxide layer.

[0073] With a second insulating layer IL2 formed on the oxide semiconductor layer OS and a metal oxide layer MO2 formed on the second insulating layer IL2, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer OS (the "oxidation annealing" in step S1010 shown in Figure 7 and Figure 13).

[0074] During the process from the formation of the oxide semiconductor layer OS to the formation of the second insulating layer IL2 on the oxide semiconductor layer OS, a large number of oxygen defects are generated on the surface and side surfaces of the oxide semiconductor layer OS. By means of the above-mentioned oxidation annealing treatment, the oxygen released from the first insulating layer IL1 is supplied to the surface and side surfaces of the oxide semiconductor layer OS, and the oxygen defects are repaired.

[0075] In the aforementioned oxidation annealing process, the oxygen injected into the second insulating layer IL2 is blocked by the metal oxide layer MO2, thus suppressing its release into the atmosphere. Therefore, through this oxidation annealing process, the oxygen is efficiently supplied to the oxide semiconductor layer OS, and oxygen defects are repaired.

[0076] Subsequently, after oxidation annealing, the metal oxide layer MO2 is etched (removed) ("MO2 removal" in step S1011 shown in Figure 7 and Figure 14). The etching of the metal oxide layer MO2 can be performed using either wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) can be used for wet etching. By this etching, the metal oxide layer MO2 formed over the entire surface is removed. In other words, the metal oxide layer MO2 is removed without using a mask. Furthermore, by this etching, at least the area of ​​the metal oxide layer MO2 overlapping with the oxide semiconductor layer OS formed in a certain pattern, viewed from above, is completely removed.

[0077] Subsequently, the gate wiring GL is formed on the second insulating layer IL2 ("GL formation" in step S1012 shown in Figure 7 and Figure 15). The film formation method and insulating material of the gate wiring GL can be referred to the description of the light-shielding layer LS. The gate wiring GL is arranged along the first direction D1.

[0078] Next, impurities are added to the oxide semiconductor layer OS using the gate wiring GL as a mask ("SA, DA formation" in step S1013 shown in FIG. 7 and FIG. 15). In this embodiment, the case of impurity addition by ion implantation is described, but it can also be performed by ion doping.

[0079] Specifically, impurity elements are added to the oxide semiconductor layer OS through the second insulating layer IL2 using ion implantation, thereby forming the source region SA and the drain region DA. For example, argon (Ar), phosphorus (P), or boron (B) can be used as the impurity element. Furthermore, when adding boron (B) using ion implantation, the acceleration energy is set to 20 keV or higher and 40 keV or lower, and the boron (B) implantation amount is set to 1 × 10¹⁴ cm⁻² or higher and 1 × 10¹⁶ cm⁻² or lower.

[0080] When the determination is performed using SIMS (secondary ion mass spectrometry), the concentration of impurity elements in the source region SA and drain region DA is preferably 1×10¹⁸ cm⁻³ to 1×10²¹ cm⁻³. Furthermore, if the source region SA and drain region DA contain impurity elements at concentrations of 1×10¹⁸ cm⁻³ to 1×10²¹ cm⁻³, it is presumed that the impurity elements were intentionally added via ion implantation or doping.

[0081] Subsequently, a third insulating layer IL3 is formed on the second insulating layer IL2 and the gate wiring GL ("IL3 film formation" in step S1014 shown in Figure 7 and Figure 16). The film formation method and insulating material of the third insulating layer IL3 can be referred to the description of the first insulating layer IL1.

[0082] Next, a contact hole WCON is formed on the third insulating layer IL3, extending to the source region SA. Then, a wiring W1 is formed on the third insulating layer IL3, and the wiring W1 is connected to the source region SA via the contact hole ZCON ("W1 formation" in step S1015 shown in FIG. 7 and FIG. 16). The film formation method and insulating material for the wiring W1 are described in the description of the light-shielding layer LS. The wiring W1 is arranged along the second direction D2.

[0083] Subsequently, a fourth insulating layer IL4 is formed on the third insulating layer IL3 and the wiring W1 ("IL4 film formation" in step S1016 shown in Figure 8 and Figure 16). The film formation method and insulating material of the fourth insulating layer IL4 can be referred to the description of the first insulating layer IL1.

[0084] Subsequently, a contact hole ZCON is formed on the fourth insulating layer IL4, extending to the drain region DA. Then, a connecting electrode ZTCO is formed on the fourth insulating layer IL4 and the connecting electrode ZTCO is connected to the drain region DA via the contact hole ZCON (ZTCO formation in step S1017 shown in FIG8 and FIG16).

[0085] The ZTCO electrode is formed by processing a transparent oxide conductive layer (also known as a transparent conductive layer) that is sputtered. This oxide conductive layer can be made of transparent conductive materials such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO). Other transparent conductive materials can also be used as the oxide conductive layer.

[0086] Subsequently, a fifth insulating layer IL5 is formed on the fourth insulating layer IL4 and the connecting electrode ZTCO ("IL5 film formation" in step S1018 shown in Figure 8 and Figure 17).

[0087] The fifth insulating layer is formed by coating an organic insulating material and baking it. The organic insulating material may be polyimide resin, acrylic resin, epoxy resin, silicone resin, fluoropolymer resin, or silicone resin. Subsequently, a portion of the fifth insulating layer is exposed and removed to form the contact hole PCON, which exposes the ZTCO connecting electrode.

[0088] Next, a pixel electrode PTCO is formed on the fifth insulating layer IL5, and the pixel electrode PTCO is connected to the connecting electrode ZTCO via the contact hole PCON (PTCO formation in step S1019 shown in Figure 8 and Figure 17). The method for forming the pixel electrode PTCO and the transparent conductive material can be found in the description of the connecting electrode ZTCO.

[0089] Subsequently, a sixth insulating layer IL6 is formed on the pixel electrode PTCO ("IL6 film formation" in step S1020 shown in Figure 8 and Figure 17).

[0090] The method for forming the sixth insulating layer IL6 and the insulating material are the same as those described for the first insulating layer IL1. The sixth insulating layer IL6 functions as a dielectric for forming a capacitor. Furthermore, the sixth insulating layer IL6 functions as the first inorganic layer. The film thickness of the sixth insulating layer IL6 is at least 30 nm and at least 50 nm and less than 200 nm. In this embodiment, the sixth insulating layer IL6 is formed using silicon nitride.

[0091] Next, an opening IOP is formed in the sixth insulating layer IL6 ("IOP formation" in step S1021 shown in FIG8 and FIG17). As described above, the opening IOP is provided to allow moisture contained in the fifth insulating layer IL5 to be released.

[0092] The area of ​​the IOP (Installation Opening) is preferably formed such that it does not exceed 15% of the pixel area. In other words, the coverage of the 6th insulating layer IL6 over the 5th insulating layer IL5 is 85% or more, preferably 90% or more, and even more preferably 95% or more, relative to the pixel area. There is not limited to one IOP per pixel; there can be multiple IOPs. Furthermore, when multiple IOPs are provided in each pixel, the total area of ​​the multiple IOPs only needs to be less than 15% of the pixel area. The IOP is preferably located in the region overlapping with the oxide semiconductor layer OS. More preferably, the IOP is located in the region overlapping with the gate wiring overlap region (i.e., the channel region CA) in the oxide semiconductor layer OS. By placing the opening IOP in a region overlapping with the oxide semiconductor layer OS or the channel region CA of the oxide semiconductor layer OS, the moisture contained in the organic resin layer can be released to the outside by the annealing process described later, and the penetration of moisture contained in the organic resin layer into the oxide semiconductor layer OS can be suppressed. However, the location of the opening IOP is not limited to the above-mentioned location; for example, it can also be placed in a location overlapping with the wiring W1, or in a location that does not overlap with the oxide semiconductor layer OS.

[0093] Subsequently, annealing is performed with the 6th insulating layer IL6 covering the 5th insulating layer IL5 ("annealing" in step S1022 shown in FIG. 8 and FIG. 17). The annealing temperature is, for example, 150°C to 300°C. By performing annealing, the moisture contained in the 5th insulating layer IL5 can be released.

[0094] Subsequently, a common auxiliary electrode CMTL is formed on the sixth insulating layer IL6 (CMTL formation in step S1023 shown in Figure 8 and Figure 18).

[0095] The deposition method and conductive materials for the common auxiliary electrode CMTL can be found in the description of the light-shielding layer LS. The common auxiliary electrode CMTL is formed in a lattice shape by overlapping with the gate wiring GL and wiring W1.

[0096] Subsequently, a common electrode CTCO is formed on the sixth insulating layer IL6 and the common auxiliary electrode CMTL ("CTCO formation" in step S1024 shown in Figure 8 and Figure 18). The film formation method and transparent conductive material for the common electrode CTCO are the same as those for the connecting electrode ZTCO. The common electrode CTCO functions as the second inorganic layer. The film thickness of the common electrode CTCO only needs to be at least 30 nm and between 50 nm and 200 nm. By forming the common electrode CTCO, the common electrode CTCO is connected to the fifth insulating layer IL5 at the opening IOP. That is, the common electrode CTCO can block the opening IOP provided in the sixth insulating layer IL6. This prevents moisture from being drawn into the fifth insulating layer IL5 from the outside through the opening IOP.

[0097] Next, spacers SP are formed on the common electrode CTCO ("SP formation" in step S1025 shown in Figure 8). The spacers SP are formed in the contact hole PCON. Finally, the array substrate manufactured as described above and the opposing substrate with the color filter and spacers formed thereon are bonded together with a sealing material and a liquid crystal layer.

[0098] Through the above processes, a display device 10 according to one embodiment of the present invention can be manufactured.

[0099] Typically, in FFS (Freeform-Self) liquid crystal display devices, pixel electrodes, capacitor insulating layers, and common electrodes are deposited on an organic resin layer, or vice versa. When pixel electrodes are disposed on the organic resin layer, to suppress capacitive coupling between the pixel electrodes and wiring, the pixel electrodes are often configured not to overlap with source wiring. Furthermore, slit patterns are sometimes provided on the pixel electrodes. Therefore, the pixel electrode coverage relative to the pixel area is less than 85%. Also, when common electrodes are disposed on the organic resin layer, slit patterns are sometimes provided on the common electrodes, or an opening is provided above the transistor. Therefore, the common electrode coverage relative to the pixel area is less than 85%. Therefore, even when annealing is performed with pixel electrodes or common electrodes disposed on the organic resin layer, moisture can be released from the organic resin layer, but will be reabsorbed during subsequent processing. Moisture contained in the organic resin layer seeping into the oxide semiconductor layer causes changes in the transistor's characteristics.

[0100] Furthermore, in FFS-type liquid crystal display devices, a capacitor insulating layer is formed over the entire surface of the pixel electrode or common electrode above the organic resin layer, covering the active area. Even if annealing is performed with this capacitor insulating layer formed over the entire surface, the moisture contained in the organic resin layer will be blocked by the capacitor insulating layer and the pixel electrode, preventing the moisture from being released from the organic resin layer. Therefore, excess moisture remaining in the organic resin layer will cause moisture to seep into the oxide semiconductor layer, thus altering the characteristics of the transistor.

[0101] In a method for manufacturing a display device according to one embodiment of the present invention, after the moisture contained in the fifth insulating layer IL5, which contains organic resin, is sufficiently released from the opening IOP formed in the first inorganic layer by an annealing process, the opening IOP is blocked by the second inorganic layer. This maintains a state where the amount of moisture contained in the organic resin layer decreases. Therefore, it is possible to suppress the penetration of moisture contained in the organic resin layer into the oxide semiconductor layer. This suppresses changes in transistor characteristics, thereby improving the reliability of the display device.

[0102] In the transistor Tr formation process, the formation of the metal oxide layer MO1 disposed under the oxide semiconductor layer OS can also be omitted. In this case, steps S1003 and S1007 shown in FIG7 can also be omitted. Furthermore, in the transistor Tr formation process, the annealing process after forming the metal oxide layer MO2 on the second insulating layer IL2 can also be omitted. In this case, steps S1009 and S1011 shown in FIG7 can also be omitted.

[0103] Preferably, annealing is performed while the first inorganic layer, disposed on the fifth insulating layer IL5 containing organic resin, has openings, allowing moisture contained in the organic resin layer to be released from the openings. Subsequently, by forming a second inorganic layer to seal the openings, moisture can be prevented from being drawn into the organic resin layer from the outside, thereby suppressing changes in transistor characteristics. This improves the reliability of the display device.

[0104] [8. Variation Example 1] In Variation Example 1, a display device 10A that differs from the display device shown in FIG4 will be described with reference to FIG19. FIG19 shows a structure in which the opening IOP provided in the 6th insulating layer IL6 is blocked by the 7th insulating layer IL7.

[0105] In the display device 10A shown in Figure 19, a sixth insulating layer IL6 and a seventh insulating layer IL7 are provided between the pixel electrode PTCO and the common electrode CTCO. The common electrode CTCO has a slit pattern in the area overlapping with the pixel electrode PTCO. The film formation method and insulating material of the seventh insulating layer IL7 can be referred to the description of the first insulating layer IL1. The thickness of the sixth insulating layer IL6 and the seventh insulating layer IL7 can be appropriately set according to the capacitance of the holding capacitor 890. The thickness of the seventh insulating layer IL7 can be less than the thickness of the sixth insulating layer IL6. The common electrode CTCO is provided on the seventh insulating layer IL7. As long as the thickness of the seventh insulating layer IL7 and the common electrode CTCO is at least 30 nm and 50 nm and 200 nm respectively, the absorption of moisture from the outside can be suppressed. In Variation Example 1, as the first inorganic layer, it is sufficient to include at least the sixth insulating layer IL6, and as the second inorganic layer, it is sufficient to include at least the seventh insulating layer IL7.

[0106] [9. Variation Example 2] In Variation Example 2, a display device 10B that differs from the display device 10 shown in FIG. 4 will be described with reference to FIG. 20. FIG. 20 shows a structure in which the opening IOP provided in the sixth insulating layer IL6 is blocked by a common auxiliary electrode CMTL. Furthermore, a color filter CF is provided between the fourth insulating layer IL4 and the fifth insulating layer IL5.

[0107] In the display device 10B shown in Figure 20, the opening IOP of the sixth insulating layer IL6 is disposed on the wiring W1. In this embodiment, a common auxiliary electrode CMTL is disposed above the wiring W1. Therefore, the opening IOP can also be blocked by the common auxiliary electrode CMTL. Furthermore, a common electrode CTCO is disposed on the sixth insulating layer IL6 and the common auxiliary electrode CMTL. As long as the thickness of the common auxiliary electrode CMTL is at least 30 nm or more, and 50 nm or more and 200 nm or less, the absorption of moisture from the outside can be suppressed. In Variation 2, as the first inorganic layer, it is sufficient to include at least the sixth insulating layer IL6, and as the second inorganic layer, it is sufficient to include at least the common auxiliary electrode CMTL. In this way, the absorption of moisture from the opening IOP and the outside can be suppressed.

[0108] In liquid crystal display devices, when a color filter is provided on the opposing substrate, positional misalignment may occur when the array substrate, on which transistors are formed, is bonded to the opposing substrate. In high-resolution liquid crystal display devices such as VR, even a slight positional misalignment between the pixels of the array substrate and the color filter of the opposing substrate can lead to a decrease in display quality. Therefore, by forming a color filter CF between the fourth insulating layer IL4 and the fifth insulating layer IL5, positional misalignment between the array substrate and the color filter during bonding of the array substrate and the opposing substrate can be suppressed. Furthermore, since the color filter CF is also formed of organic resin, it contains moisture. By annealing, the moisture contained in the color filter CF and the moisture contained in the fifth insulating layer IL5 are released from the opening IOP formed in the sixth insulating layer IL6. The opening IOP is then blocked by the common auxiliary electrode CMTL, thereby preventing the re-absorption of moisture from the outside into the opening IOP, the fifth insulating layer IL5, and the color filter CF.

[0109] Furthermore, although not illustrated, the configuration in which a color filter CF is disposed between the fourth insulating layer IL4 and the fifth insulating layer IL5 can also be applied to the display devices shown in Figures 4 and 19, and the display devices shown in Figures 21 and 22, which will be described later.

[0110] [10. Variation Example 3] In Variation Example 3, a display device 10C that differs from the display device 10 shown in FIG. 4 will be described with reference to FIG. 21. FIG. 21 shows a configuration in which a capacitor electrode CTCO1 is disposed on the fifth insulating layer IL5.

[0111] In the display device 10C shown in Figure 21, a capacitor electrode CTCO1 is disposed on the fifth insulating layer IL5. A holding capacitor is formed by the capacitor electrode CTCO1, the sixth insulating layer IL6, and the pixel electrode PTCO, and a holding capacitor is also formed by the pixel electrode PTCO, the seventh insulating layer IL7, and the common electrode CTCO2. Since the sixth insulating layer IL6 is disposed on the capacitor electrode CTCO1, the coverage of the capacitor electrode CTCO1 with the fifth insulating layer IL5 can reach 85% relative to the pixel area. An opening may also be provided on the capacitor electrode CTCO1.

[0112] A sixth insulating layer IL6 is provided on the capacitor electrode CTCO1. The coverage of the fifth insulating layer IL5 by the sixth insulating layer IL6 is preferably 85% or more relative to the pixel area. Furthermore, the opening IOP may overlap with the opening provided on the capacitor electrode CTCO1. A seventh insulating layer IL7 is provided on the sixth insulating layer IL6. The seventh insulating layer IL7 is provided in such a way that it blocks both the opening IOP and the opening provided on the capacitor electrode CTCO1. Therefore, the seventh insulating layer IL7 is in contact with the fifth insulating layer IL5 at the opening.

[0113] Furthermore, a common electrode CTCO2 is disposed on the 7th insulating layer IL7. Figure 21 shows an example where the opening of the capacitor electrode CTCO1 overlaps with the opening IOP, but this is not a limitation. Alternatively, the opening may not be formed on the capacitor electrode CTCO1, but rather on the 6th insulating layer IL6. In variation 3, the first inorganic layer only needs to include at least the 6th insulating layer IL6, and the second inorganic layer only needs to include at least the 7th insulating layer IL7.

[0114] Furthermore, the film thickness of the 7th insulating layer IL7 only needs to be at least 30 nm and between 50 nm and 200 nm. Also, the film formation methods and transparent conductive materials for the capacitor electrode CTCO1 and the common electrode CTCO2 only need to refer to the instructions for the connecting electrode ZTCO. The film thickness of the capacitor electrode CTCO1 and the common electrode CTCO2 only needs to be at least 30 nm and between 50 nm and 200 nm.

[0115] [11. Variation Example 4] In Variation Example 4, a display device 10D that differs from the display device 10 shown in FIG. 4 will be described with reference to FIG. 22. In the display device 10, the configuration in which the wiring W1 and the connecting electrode ZTCO, which functions as a drain electrode, are disposed on different insulating layers has been described, but the wiring W1 and the connecting electrode ZTCO may also be disposed on the same insulating layer.

[0116] In the display device 10D shown in Figure 22, a structure is illustrated where the fourth insulating layer IL4 is omitted and a wiring W1 and a drain electrode DE are disposed on the third insulating layer IL3. A fifth insulating layer IL5 is disposed on the wiring W1 and the drain electrode DE, and a contact hole PCON is formed in the fifth insulating layer IL5. A pixel electrode PTCO is disposed on the fifth insulating layer IL5, and the pixel electrode PTCO is connected to the drain electrode DE via the contact hole PCON. A sixth insulating layer IL6 is disposed on the fifth insulating layer IL5 and the pixel electrode PTCO. An opening IOP is provided in the sixth insulating layer IL6. The opening IOP is blocked by a common electrode CTCO disposed on the sixth insulating layer IL6. In Variation 4, as the first inorganic layer, it is sufficient to include at least the sixth insulating layer IL6; as the second inorganic layer, it is sufficient to include the common electrode CTCO.

[0117] The above-described embodiments, which are implementations of the present invention, can be appropriately combined to implement them as long as they do not contradict each other. Furthermore, any display device based on the various embodiments, obtained by adding, deleting, or designing constituent elements, or by adding, omitting, or changing processes or conditions, is included within the scope of the present invention as long as it possesses the spirit of the present invention.

[0118] Even if there are other effects that are different from those brought about by the above-described embodiments, it should be understood that those that are obvious from the description in this specification or that can be easily predicted by a practitioner are naturally brought about by the present invention.

[0119] 10, 10A~10D: Display devices 22: LCD area 24: Sealed area 26: Terminal area 300: Array substrate 310: pixels 320: Source driver circuit 321: Source wiring 330: Gate driver circuit 331: Gate wiring 333: Terminal section 341: Wiring connection 342: Wiring connection 400: Sealing part 410: Liquid Crystal Components 500: Opposing substrate 600: Flexible Printed Circuit Board 700: IC chip 800: Transistor 810: Gate electrode 830: Source electrode 840: Drain electrode 890: Holding Capacitor AOS: Oxide Semiconductor Layer CA: Channel Area CF: Color Filter CMTL: Common Auxiliary Electrode CON1: First Contact Area CON2: Second contact area COP: Opening CTCO: Common Electrode CTCO1: Capacitive electrode CTCO2: Common Electrode D1: Direction 1 D2: Second Direction DA: Drainage Region DE: Drain electrode GL: Gate wiring IL1: First insulating layer IL2: Second insulating layer IL3: Third insulating layer IL4: Fourth insulating layer IL5: Fifth Insulation Layer IL6: Sixth Insulation Layer IL7: 7th Insulation Layer IOP: Opening LS: Light-shielding layer LS1: Light-shielding layer LS2: Light-shielding layer MO1, MO2: Metal oxide layers OS: Oxide semiconductor layer PCON: Contact Hole OS: Oxide semiconductor layer PTCO: Pixel Electrode S1001: Steps S1002: Steps S1003: Steps S1004: Steps S1005: Steps S1006: Steps S1007: Steps S1008: Steps S1009: Steps S1010: Steps S1011: Steps S1012: Steps S1013: Steps S1014: Steps S1015: Steps S1016: Steps S1017: Steps S1018: Steps S1019: Steps S1020: Steps S1021: Steps S1022: Steps S1023: Steps S1024: Steps S1025: Steps SA: Source Region SP: Spacer SUB:Substrate Tr: transistor W1: Wiring WCON: Contact Hole ZCON: Contact Hole ZTCO: Connecting Electrode

Claims

1. A display device comprising a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels having: a transistor having an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer and extending in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer disposed on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer disposed on the second insulating layer and having an opening; and a second inorganic layer disposed on the first inorganic layer and in contact with the second insulating layer at the opening; wherein the coverage of the first inorganic layer over the second insulating layer is 85% or more relative to the area of ​​the pixel. The first inorganic layer has a second transparent conductive layer and a first inorganic insulating layer disposed on the second transparent conductive layer. The second transparent conductive layer is connected to the first conductive layer, and the opening is provided in the first inorganic insulating layer.

2. The display device of claim 1, wherein the second inorganic layer includes a third transparent conductive layer, the third transparent conductive layer is in contact with the second insulating layer at the opening, and has a slit pattern in the area overlapping with the second transparent conductive layer.

3. The display device of claim 1, wherein the second inorganic layer comprises a second inorganic insulating layer, and the second inorganic insulating layer is in contact with the second insulating layer at the opening.

4. The display device of claim 3, wherein the second inorganic layer further includes a fourth transparent conductive layer disposed on the second inorganic insulating layer, the fourth transparent conductive layer having a slit pattern in the area overlapping with the second transparent conductive layer.

5. The display device of claim 1, wherein the second inorganic layer comprises a metal layer, and the metal layer is in contact with the second insulating layer at the opening.

6. The display device of claim 1 further includes a first wiring disposed between the transistor and the first conductive layer and connected to the oxide semiconductor layer, wherein the first conductive layer is transparent.

7. The display device of claim 1 further includes a first wiring disposed on the first insulating layer and connected to the oxide semiconductor layer, the first wiring being disposed along the second direction.

8. The display device of claim 1, wherein the opening is provided in the region overlapping with the oxide semiconductor layer.

9. The display device of claim 1, wherein the opening is disposed in a region that overlaps with the gate wiring overlap region in the oxide semiconductor layer.

10. The display device of claim 1, wherein an aluminum oxide layer is further provided between the gate insulating layer and the oxide semiconductor layer.

11. A display device comprising a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels having: a transistor having an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer and extending in the first direction, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer disposed on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer disposed on the second insulating layer and having an opening; and a second inorganic layer disposed on the first inorganic layer and in contact with the second insulating layer at the opening; wherein the coverage of the first inorganic layer over the second insulating layer is 85% or more relative to the area of ​​the pixel. The first inorganic layer includes a first inorganic insulating layer and a second transparent conductive layer disposed on the first inorganic insulating layer. The second transparent conductive layer is connected to the first conductive layer through a contact hole disposed on the first inorganic insulating layer, and the opening is provided in the first inorganic insulating layer.

12. The display device of claim 11, wherein the second inorganic layer comprises a second inorganic insulating layer, and the second inorganic insulating layer is in contact with the second insulating layer at the opening.

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