Semiconductor structure and method of forming the same

Abstract

The semiconductor structure includes laterally spaced bitline structures on a substrate, embedded contacts located between the bitline structures, and landing pads on the embedded contacts. The embedded contacts include a first conductive layer and a second conductive layer on the first conductive layer. The second conductive layer includes a main portion and a protruding portion extending from the main portion into the first conductive layer. A method for forming the semiconductor structure is also disclosed.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. In particular, this disclosure relates to a dynamic random-access memory (DRAM) and a method for forming the same. Prior Technology

[0002] With advancements in technology, the spacing between semiconductor structures in dynamic random access memory (DRAM) has decreased and the integration density has increased to improve DRAM performance. The closer the components are in a semiconductor device, the more difficult it becomes to deposit components within such a reduced distance; for example, forming holes. These holes can increase resistance and reduce the operating speed of DRAM.

[0003] Therefore, in the fabrication of semiconductor devices, it is important to improve the performance of dynamic random access memory and reduce contact resistance. Summary of the Invention

[0004] This disclosure provides a semiconductor structure. The semiconductor structure includes laterally spaced bit line structures on a substrate, embedded contacts located between the bit line structures, and landing pads on the embedded contacts. The embedded contacts further include a first conductive layer and a second conductive layer on the first conductive layer. The second conductive layer includes a main portion and a protruding portion extending from the main portion into the first conductive layer.

[0005] This disclosure provides a method for forming a semiconductor structure. The method includes forming a bit line structure on a substrate, forming trenches between the bit line structures, forming a first conductive layer within the trenches, and forming a second conductive layer on the first conductive layer. The material of the first conductive layer is different from the material of the second conductive layer. The second conductive layer further includes a main portion and a protruding portion, the protruding portion extending from the main portion into the first conductive layer.

[0006] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the claimed invention. Simple Explanation of the Diagram

[0007] A more complete understanding of the present invention can be obtained by reading the following detailed description of the embodiments and the accompanying drawings: Figures 1 through 6 are cross-sectional views of various formation stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure. Implementation

[0008] Embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0009] It should be understood that while the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0010] Additionally, relative terms such as "below" or "bottom" and "above" or "top" are used herein to describe the relationship between an element and another element as shown in the figures. It should be understood that these relative terms are intended to cover different orientations of the device, in addition to those shown in the figures. For example, if a device in a figure is flipped, an element that was originally located "below" another element will be oriented to be located "above" another element. The illustrative term "below" can encompass both "below" and "above" orientations depending on the specific orientation of the figure. Similarly, if a device in a figure is flipped, an element that was originally located "below" or "under" another element will be oriented to be located "above" another element. The illustrative term "below" or "under" can encompass both "above" and "below".

[0011] The terms "about," "approximately," or "roughly" as used in this document generally refer to approximately 20 percent of a given value or range, preferably approximately 10 percent, and more preferably approximately 5 percent. Unless otherwise specified, all values ​​mentioned are considered approximate, i.e., the error or range indicated by "about," "approximately," or "roughly."

[0012] Figures 1 through 6 are cross-sectional views of various formation stages of a method for forming a semiconductor structure 10 according to some embodiments of the present disclosure.

[0013] Referring to Figure 1, the method begins with step S10. A bit line structure 110 is formed on a substrate 100. The semiconductor structure 10 includes the substrate 100. The substrate 100 further includes an active region 102 and an isolation region 104 separating the active region 102. An isolation layer 106 is formed on the substrate 100 and covers the top surfaces of the active region 102 and the isolation region 104 for isolating subsequently formed components from the substrate 100. The bit line structures 110 are laterally spaced from each other on the substrate 100. In some embodiments, each bit line structure 110 may include a conductive stack 112 and an insulating layer 114 on the conductive stack 112 in a direction perpendicular to the substrate 100.

[0014] The substrate 100 may comprise silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 100 may comprise an elemental semiconductor, an alloy semiconductor, a compound semiconductor, or other suitable materials. Additionally, the substrate 100 may optionally comprise a semiconductor-on-insulator (SOI) structure.

[0015] An ion implantation process can be performed on the substrate 100 to dope it with n-type or p-type doping. In some embodiments, source / drain regions (not shown in Figure 1) are formed by doping the active region 102 of the substrate 100 with n-type or p-type doping.

[0016] The isolation region 104 may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. The isolation region 104 may be a single layer or multiple layers. In some embodiments, the isolation region 104 may be formed by a shallow trench isolation (STI) process.

[0017] The insulating layer 106 can be formed of any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) oxide, un-doped silicate glass (USG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), other suitable materials, or combinations thereof.

[0018] Bit line structures 110 are disposed on substrate 100. In some embodiments, according to Figure 1, each bit line structure 110 protrudes in the vertical direction of substrate 100 and has a linear structure that extends along a direction parallel to substrate 100.

[0019] Referring to Figure 2, the method proceeds to step S20. A trench 108 is formed between the bit line structures 110 on the substrate 100. The trench 108 extends through the isolation layer 106 to expose a portion of the active region 102 of the substrate 100.

[0020] The trench 108 is disposed along a direction perpendicular to the substrate 100. In some embodiments, the bottom surface of the trench 108 is below the insulating layer 106. The trench 108 may expose a portion of the active region 102 for electrically connecting elements (such as subsequently formed embedded contacts 116) to the active region 102.

[0021] Referring to Figure 3, the method proceeds to step S30. After forming trench 108, a first conductive layer 118 is formed in trench 108. It should be noted that while depositing material into the first conductive layer 118 in trench 108, holes 120 are formed within the first conductive layer 118. Therefore, each first conductive layer 118 further includes a hole 120. Due to advancements in semiconductor structures, their dimensions have become smaller, resulting in trenches with higher aspect ratios than in the past. Depositing material in trenches with such high aspect ratios easily leads to the formation of holes. It is worth mentioning that the formation of holes can increase the contact resistance of the semiconductor structure and further reduce the operating speed of DRAM. Generally, holes should be avoided in the formation of semiconductor structures.

[0022] The material of the first conductive layer 118 is filled into portions of each trench 108 between the bit line structures 110. The top of the first conductive layer 118 on the isolation layer 106 is surrounded by the bit line structures 110. In some embodiments, the top surface of the first conductive layer 118 is higher than the top surface of the conductive stack 112, but lower than the top surface of the bit line structures 110.

[0023] In some embodiments, the material of the first conductive layer 118 can be deposited by any suitable operation, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. Furthermore, the material of the first conductive layer 118 can be any suitable conductive material, such as polycrystalline silicon.

[0024] An elongated hole 120 is formed within the first conductive layer 118 along the direction of the trench 108. In some embodiments, the two ends of each hole 120 may be pointed, rounded, or blunt, etc. Each hole 120 is surrounded by each first conductive layer 118. A portion of each first conductive layer 118 covers the top of each hole 120. In this way, the hole 120 is not exposed to air. To avoid the presence of the hole 120, the top of the material of the first conductive layer 118 is removed to expose the hole 120, and then a second conductive layer 122 is formed on the first conductive layer 118, referring to Figures 4 and 5.

[0025] Referring to Figure 4, the method proceeds to step S40. After forming the first conductive layer 118, the top of the first conductive layer 118 is removed to form the first conductive layer 118' and expose the hole 120'.

[0026] The hole 120' is exposed and surrounded only by the first conductive layer 118'. In some embodiments, the top surface of the first conductive layer 118' is lower than the top surface of the conductive stack 112. In some embodiments, the top of the material from which the first conductive layer 118 is removed may contain any suitable etching process, such as dry etching and / or wet etching, etc.

[0027] Referring to Figure 5, the method proceeds to step S50. After removing the top of the material of the first conductive layer 118, a second conductive layer 122 is formed on the first conductive layer 118'. To eliminate the voids 120 and improve contact resistance, the second conductive layer 122 is disposed on the first conductive layer 118' and further fills the voids 120' (as shown in Figure 4). In some embodiments, the voids 120' are completely filled with the second conductive layer 122 without any gaps.

[0028] Each second conductive layer 122 further includes a main portion 124 and a protrusion 126, the protrusion 126 extending from the main portion 124 into each first conductive layer 118'. The main portion 124 covers the first conductive layer 118'. In some embodiments, the top surface of the main portion 124 is coplanar with the top surface of the conductive stack 112. The protrusion 126 is formed by filling the second conductive layer 122 into the holes 120'. The protrusion 126 is surrounded by and in contact with the first conductive layer 118'. For example, each main portion 124 has a vertical thickness T1 in the direction perpendicular to the substrate 100. The vertical thickness T1 of the main portion 124 is between about 5 nm and about 10 nm. Each protrusion 126 has a vertical length L1 in the direction perpendicular to the substrate 100. The vertical length L1 of the protrusion 126 is between about 20 nm and about 50 nm. Furthermore, each first conductive layer 118' has a diameter D1 in a plane parallel to the substrate 100. The vertical length L1 of the protrusion 126 is approximately 0.6 to approximately 1.5 times the diameter D1 of the first conductive layer 118'.

[0029] The material of the first conductive layer 118' can be the same as or different from the material of the second conductive layer 122. In some embodiments, the material of the first conductive layer 118' is the same as the material of the second conductive layer 122 (e.g., polysilicon). Although eliminating the voids 120' by filling with the same material will still result in a higher contact resistance. In some embodiments, the material of the first conductive layer 118' is different from the material of the second conductive layer 122. For example, the first conductive layer 118' may include polysilicon, and the second conductive layer 122 may include cobalt. The resistance of the material of the second conductive layer 122 is lower than the resistance of the material of the first conductive layer 118'. That is, the resistance of the second conductive layer 122 is lower than the resistance of the first conductive layer 118'. Thus, by depositing the material of the second conductive layer 122, which has lower resistance, into the voids 120' instead of the same material as the first conductive layer 118', the contact resistance can be further reduced due to the presence of more conductive material. Therefore, the operating speed of the DRAM can be improved. In some embodiments, the material of the second conductive layer 122 can be deposited using other suitable methods, such as CVD, ALD, PVD, etc.

[0030] Referring to Figure 6, the method proceeds to step S60. After forming the second conductive layer 122, a landing pad 128 is formed on the second conductive layer 122 located between the bit line structures 110 and covers part of the bit line structures 110.

[0031] A landing pad 128 is deposited to fill the remaining trenches 108' located between the bit line structures 110. The top surface of the landing pad 128 is higher than the top surface of the bit line structure 110. The bottom surface of the landing pad 128 contacts the top surface of the second conductive layer 122. The sidewalls of the landing pad 128 in the trenches 108' contact the sidewalls of the bit line structure 110.

[0032] In some embodiments, the material of the landing pad 128 may include a conductive material, such as tungsten, copper, aluminum, alloys, or other suitable conductive materials. The material of the landing pad 128 may be deposited as a blanket layer. The deposition operation may include any suitable deposition operation, such as CVD, PVD, ALD, etc.

[0033] In Figure 6, a semiconductor structure 10 is formed by a method for forming a semiconductor structure. The semiconductor structure 10 includes a substrate 100, which includes an active region 102 and an isolation region 104 separating the active region 102. An isolation layer 106 is deposited on the top surface of the active region 102 and the isolation region 104. Bit line structures 110 are laterally disposed on the isolation layer 106 on the substrate 100 and spaced apart from each other. Buried contacts 116 are disposed between the bit line structures 110, and landing pads 128 are formed on the buried contacts 116, covering a portion of the bit line structures 110.

[0034] According to Figure 6, each bitline structure 110 includes a conductive stack 112 and an insulating layer 114 on the conductive stack 112 in a plane perpendicular to the substrate 100. The bottom of the embedded contact 116 is embedded in the substrate 100 and partially contacts the active region 102.

[0035] Each embedded contact 116, in a cross-sectional view on a plane perpendicular to the substrate 100, further includes a first conductive layer 118' and a second conductive layer 122 on the first conductive layer 118'. The first conductive layer 118' includes a hole 120' extending from the top surface of the first conductive layer 118'. To eliminate the hole 120', the second conductive layer 122 is disposed on and fills the first conductive layer 118'. The presence of the hole 120 increases the contact resistance of the semiconductor structure 10. Each second conductive layer 122 further includes a main portion 124 and a protrusion 126. The protrusion 126 extends from the main portion 124 and enters into the first conductive layer 118'. That is, the bottom surface of the main portion 124 contacts the top surface of the first conductive layer 118'. The protrusion 126 is surrounded by and contacts the first conductive layer 118'. In some embodiments, the top surface of the main portion 124 and the top surface of the conductive stack 112 are coplanar.

[0036] In the plane of the vertical substrate 100, each main portion 124 has a vertical thickness T1 and each protrusion 126 has a vertical length L1. In some embodiments, the vertical thickness T1 of the main portion 124 is between about 5 nm and about 10 nm. The vertical length L1 of the protrusion 126 is between about 20 nm and about 50 nm. Furthermore, in the plane of the parallel substrate 100, each first conductive layer 118' has a diameter D1 in a cross-sectional view. In some embodiments, the diameter D1 along the embedded contact 116 is uniform. The vertical length L1 of the protrusion 126 is about 0.6 to about 1.5 times the diameter D1 of the first conductive layer 118'.

[0037] The material of the second conductive layer 122 can be disposed on the first conductive layer 118'. Furthermore, the material of the second conductive layer 122 can be the same as or different from the material of the first conductive layer 118'. In some embodiments, the material of the first conductive layer 118' can be selected from polysilicon, and the material of the second conductive layer 122 can be selected from cobalt, such that the resistance of the second conductive layer 122 is lower than the resistance of the first conductive layer 118'. Using a lower-resistance material for the second conductive layer 122 can reduce contact resistance, thereby further improving the operating speed of the DRAM.

[0038] Landing pad 128 is disposed on embedded contact 116, as shown in Figure 6. Landing pad 128 is electrically connected to embedded contact 116 and further connects the storage node / capacitor of bottom electrode (not shown) to active region 102. In other words, the storage node / capacitor of bottom electrode (not shown) is electrically connected to active region 102 through embedded contact 116.

[0039] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0040] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of the invention. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims.

[0041] S10, S20, S30, S40, S50, S60: Steps 10: Semiconductor Structure 100:Substrate 102: Active Region 104: Isolation Area 106: Isolation layer 108,108': Groove 110: Bitline Structure 112: Conductive Stack 114: Insulation layer 116: Embedded contact element 118, 118': First conductive layer 120,120': Hole 122: Second conductive layer 124: Main Part 126: Highlighted parts 128: Landing mat T1: Thickness L1: Length D1: Diameter

[0042] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure, comprising: A complex number of unit line structures are laterally separated on a substrate; An embedded contact is located between the bitline structures, wherein the embedded contact includes: a first conductive layer; and a second conductive layer located on the first conductive layer, the second conductive layer comprising cobalt, wherein the second conductive layer includes: a main portion; and a protrusion extending from the main portion into the first conductive layer and the protrusion directly contacting the first conductive layer; and a landing pad located on the embedded contact.

2. The semiconductor structure as described in claim 1, wherein the first conductive layer surrounds and contacts the protrusion.

3. The semiconductor structure as described in claim 1, wherein the resistance of the second conductive layer is less than the resistance of the first conductive layer.

4. The semiconductor structure as claimed in claim 1, wherein the first conductive layer comprises polysilicon.

5. The semiconductor structure as described in claim 1, wherein the vertical thickness of the main portion is between 5 nm and 10 nm.

6. The semiconductor structure as described in claim 1, wherein the vertical length of the protrusion is between 20 nm and 50 nm.

7. The semiconductor structure as claimed in claim 1, wherein the vertical length of the protrusion is 0.6 to 1.5 times the diameter of the first conductive layer.

8. The semiconductor structure as claimed in claim 1, wherein the substrate includes an active region and the embedded contact is partially embedded in the substrate and contacts the active region.

9. The semiconductor structure as claimed in claim 1, wherein each bit line structure includes a conductive stack and an insulating layer, the insulating layer being located on the conductive stack, and a top surface of the conductive stack and a top surface of the second conductive layer being substantially coplanar.

10. A method for forming a semiconductor structure, comprising: A complex number of unit line structures are formed on a substrate; A trench is formed in the substrate and located between the bit line structures; Forming a first conductive layer in the trench includes: depositing a material of the first conductive layer in the trench, wherein a hole is formed within the material of the first conductive layer; removing a top of the material of the first conductive layer to expose the hole; and forming a second conductive layer on the first conductive layer, wherein the second conductive layer comprises cobalt, wherein a material of the second conductive layer covers the first conductive layer and completely fills the hole, and the material of the first conductive layer is different from the material of the second conductive layer, and the second conductive layer includes: a main portion; and a protrusion extending from the main portion into the first conductive layer, wherein the protrusion directly contacts the first conductive layer.

11. The method as described in claim 10, wherein removing the top of the material of the first conductive layer to expose the hole is performed by dry etching.

12. The method as described in claim 10, wherein the resistance of the second conductive layer is less than the resistance of the first conductive layer.

13. The method as described in claim 10 further includes forming a landing pad on the second conductive layer.

14. The method of claim 10, wherein forming the trench in the substrate and located between the bit line structures comprises: The substrate is etched to form the trench between the bit line structures and to expose an active region of the substrate.

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