Buffer and inverter transistors embedded in interconnect metal layers

Abstract

This invention describes an integrated circuit arrangement having a buffer transistor or inverter transistor formed between top-side BEOL (back end of line) metal layers. The buffer or inverter transistor includes an active region and source / drain electrodes that can be formed in the space between the top-side metal layers. In some cases, the transistor is formed between the metal layers furthest from the substrate. The transistor is connected to wiring above or below it to buffer and / or invert signals passing through that wiring. For example, the transistor may include an active region positioned between a power wiring and a ground wiring, and connected to signal wiring between the power wiring and the ground wiring to boost and / or invert signals propagating along the signal wiring. In various cases, the active region of the transistor is formed of a thin-channel material.

Description

Technical Field

[0001] The embodiments described herein relate to signal wiring in semiconductor devices. More specifically, the embodiments described herein relate to implementations of buffer or inverter transistors for buffering signals in interconnect layers. Prior Technology

[0002] Massive integration of integrated circuits (such as very-large scale integration (VLSI)) can involve signals that travel globally across several circuits or circuit blocks. In some cases, these signals may travel long distances across several circuits or circuit blocks. In such cases, the signal may need to be boosted (e.g., amplified or buffered) at one or more points along its path to maintain signal strength and an acceptable signal-to-noise ratio. In current embodiments, buffering or inversion is generally implemented by placing the buffer or inverter circuitry in the transistor region of the device (e.g., at the silicon / CMOS level of the device). However, placing the buffer or inverter circuitry in the transistor region requires the signal to travel along vias between the transistor region and a global signal routing layer, typically located in the top metal layer of the device.

[0003] This causes the buffer or inverter circuitry to occupy valuable silicon footprint in the transistor region, resulting in long travel paths for signals as they travel up / down between the transistor region and the top metal layer. Furthermore, the buffer or inverter circuitry and its associated vias to the top metal layer create path congestion that needs to be accommodated in the device design. For example, complex or undesirable paths may be required to route signals around path congestion caused by the buffer or inverter circuitry and its associated vias. Therefore, there are both electrical (e.g., high resistance over long travel paths) and mechanical (e.g., footprint and path congestion) problems associated with buffer or inverter circuitry located in the transistor region. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood by referring to the following detailed description of the currently preferred but illustrative embodiments according to this disclosure, together with the accompanying drawings, wherein: [Figure 1] A top view depicting a contemplated device having a buffer transistor between top-side metal layers according to some embodiments. [Figure 2] is a cross-sectional side view showing a device of a buffer transistor along line 2-2 in Figure 1 according to some embodiments. [Figure 3] is a cross-sectional side view showing a device of a buffer transistor along line 3-3 in Figure 1 according to some embodiments. [Figure 4] depicts a three-dimensional perspective view of a buffer transistor according to some embodiments. [Figure 5] A schematic representation of a buffer transistor according to some embodiments. [Figure 6] depicts a three-dimensional perspective view of another buffer transistor according to some embodiments. [Figure 7] A schematic representation depicting another buffer transistor according to some embodiments. [Figure 8] A top plan view depicting various layouts of the display buffer transistors according to some embodiments. [Figure 9] is a block diagram of an embodiment of the example system.

[0006] While the embodiments disclosed herein may be subject to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to encompass all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined in the appended claims. Implementation

[0007] [Priority Claim] This application claims priority to U.S. Provisional Patent Application No. 63 / 585,402, filed September 26, 2023, entitled "Buffer Transistors Embedded in Interconnect Metal Layers," the disclosure of which is incorporated herein by reference in its entirety.

[0008] This disclosure relates to embodiments of transistors (such as buffer transistors) located above transistor regions (e.g., top-side metal layers) in an integrated circuit device, between metal layers. In various embodiments, such top-side metal layers may be referred to as BEOL ("back end of line") metal layers. Top-side metal layers provide wiring (e.g., paths) for control signals and / or power signals. Many current designs of cells provide connections and wiring for power or signals to transistors or other structures in the region above the transistors. For example, connections and wiring for power or signals may be provided in the top-side layer of the device. As used herein, the term "topside" refers to a region in the device that is vertically above the active layer of the device (e.g., above the transistor regions of the device when viewed in a general cross-sectional view). For example, topside may refer to components (such as contacts or layers) above the transistor regions in a vertical dimension, as depicted in the figures and described herein. In some cases, the term "frontside" may be used interchangeably with the term "topside".

[0009] As used herein, the term "routing" refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / wiring between two structures. Additional embodiments are conceivable where the metal in the "routing" is replaced by a conductive material. For example, the metal in the "routing" could be replaced by a superconductor, a semiconductor, or a non-metallic conductor.

[0010] As indicated above, placing buffers or inverter transistors in the transistor region of a large-scale integrated circuit device can lead to electrical (e.g., high resistance) and mechanical (e.g., occupancy / area utilization and path congestion) problems. This disclosure recognizes that these problems can be mitigated by placing buffers or inverter transistors in locations between top-side winding layers (e.g., top-side metal winding layers) rather than in the transistor region of the integrated circuit device. Placing buffers or inverter transistors in such locations allows for short-distance connections between the buffer or inverter transistor and its associated signal route. For example, a buffer or inverter transistor can be coupled to a signal route in a top-side metal layer directly above or below the buffer or inverter transistor. These shorter connection distances reduce the resistance of the connection between the buffer or inverter transistor and the signal route, which improves the electrical properties of signal transmission. In some cases, by implementing these shorter connection paths, the number of buffers or inverter transistors required for global signal transmission across the device can be reduced. Reducing the number of buffer or inverter transistors can increase the flexibility in the design or manufacture of such devices.

[0011] By placing the transistor between the top metal layers, the buffer or inverter transistor is moved out of the transistor region of the device, freeing up occupied space within the transistor region. For example, this freed-up space can be used to increase the number of other types of transistors or circuit elements, allowing for more complex or powerful devices. Additionally, moving the buffer or inverter transistor out of the device's transistor region eliminates potential transistor blockage. Freeing up occupied space and removing blockages allows for greater flexibility in the design or manufacture of integrated circuit devices. For example, integrated circuit design can include more optimized routing strategies for signals within the device, where occupied space is freed up and blockages are removed. In some cases, manufacturing may also be more efficient through optimized design strategies.

[0012] Some embodiments disclosed herein have three generalized elements: 1) a transistor region; 2) a first metal layer and a second metal layer in a top-side metal layer above the transistor region, wherein one or more of these metal layers include signal wiring, power supply wiring, and ground supply wiring; and 3) a transistor circuit positioned between the first metal layer and the second metal layer. In various embodiments, the transistor circuit includes an active region, a gate, a signal input coupled to the gate (a portion of the signal wiring), a voltage supply input coupled to the power supply wiring, a ground supply input coupled to the ground supply wiring, and a signal output coupled to another portion of the signal wiring. In some embodiments, the signal wiring, the power supply wiring, and the ground supply wiring are located in the same top-side metal layer (e.g., the first metal layer or the second metal layer). In some contemplated embodiments, the transistor circuit is a two-stage or one-stage inverter circuit, wherein the active region includes a p-type active region and an n-type active region.

[0013] Various illustrations of embodiments having such generalized elements are now described in this disclosure. It should be noted that the embodiments illustrated in this disclosure depict a design template for a device having a buffer transistor positioned between top-side metal layers. Those skilled in the art will recognize that the embodiments illustrated in this disclosure can also be design templates for inverter transistors or combinations of buffer and inverter transistors positioned between top-side metal layers. Therefore, the design templates depicted in this disclosure provide basic building blocks from which many different types of wiring schemes and logic functions (such as NAND and NOR) of the device can be constructed based on the transistor connection schemes in the design template. Additional embodiments using more metal traces in the first or second metal layer, along with variations in the size and / or width of the active area, are conceivable.

[0014] Figure 1 depicts a top view representation of a contemplated device having a buffer transistor between top-side metal layers according to some embodiments. In the illustrated embodiment, two top-side metal layers 110 and 120 of device 100 are shown. Top-side metal layers 110 and 120 may be, for example, BEOL metal layers perpendicular to the transistor region of device 100. In some embodiments, metal layer 110 is a metal layer perpendicularly closer to the transistor region of device 100 (e.g., metal layer 110 is a lower metal layer, and metal layer 120 is a top metal layer, as shown in Figures 2 and 3).

[0015] In various embodiments, metal layer 110 includes wirings 112A to 112F and metal layer 120 includes wirings 122A to 122F. Since metal layers 110 and 120 are adjacent metal layers in the top-side metal layers, wirings 112A to 112F and 122A to 122F can run perpendicular to each other, as shown in FIG3. Wirings 112A to 112F and 122A to 122F may include signal wiring, power supply wiring, or ground supply wiring. In some embodiments, one or more of wirings 112 and 122 are global wirings. Global wiring can be, for example, wiring that carries signals over long distances and attempts to avoid path detours when passing over unconnected transistor regions.

[0016] In some embodiments, device 100 includes one or more buffer transistors vertically positioned in the space between metal layers 110 and 120. In the illustrated embodiment, device 100 includes buffer transistors 130 and 140. Dashed lines represent the horizontal area occupied by buffer transistors 130 and 140. Buffer transistor 130 includes an active region 132 positioned parallel to wiring 112 and perpendicular to wiring 122. Buffer transistor 140 includes an active region 142 positioned parallel to wiring 122 and perpendicular to wiring 112. Active regions 132 may intersect below wiring 122, while active regions 142 may intersect above wiring 112. In various embodiments, active regions 132A and 132B are complementary active regions (e.g., one is a PMOS active region and the other is an NMOS active region). Active regions 142A and 142B may similarly be complementary active regions.

[0017] Figure 2 is a cross-sectional side view of a device 100 including a buffer transistor 130 along line 2-2 in Figure 1 according to some embodiments. Note that only a portion of the device 100 including the buffer transistor 130 along line 2-2 is shown in Figure 2. Additionally, for illustrative purposes, the elements in the device 100 (such as, but not limited to, the substrate 200, the transistor region 210, and the dielectric 220) along with their dimensions and spacing relative to each other are shown illustratively. In the illustrated embodiment, the device 100 includes a substrate 200, with the transistor region 210 situated above the substrate.

[0018] In various embodiments, metal layers 110 and 120 (e.g., top-side / BEOL metal layers) are positioned above transistor region 210. In some embodiments, metal layers 110 and 120 are higher metal layers. For example, metal layers 110 and 120 may be metal layers that are vertically further away from transistor region 210 than other metal layers (e.g., there are additional metal layers between transistor region 210 and metal layer 110). However, metal layers 110 and 120 may be any pair of adjacent (e.g., vertically adjacent) metal layers positioned above transistor region 210. For example, embodiments in which metal layers 110 and 120 are the two metal layers vertically closest to transistor region 210 are conceivable.

[0019] In some embodiments, the dielectric 220 layer is positioned between metal layers 110 and 120. The dielectric 220 may include any suitable dielectric material for providing electrical insulation and mechanical support between metal layers 110 and 120. For example, the dielectric 220 may include silicon oxide. A buffer transistor 130, including active regions 132A / 132B, may be formed between metal layers 110 and 120 and at least partially surrounded by the dielectric 220. In various embodiments, as shown in FIG2, active regions 132A, 132B and wirings 112C to 112E are parallel and extend into / out of the page, while wiring 122B runs horizontally along the page.

[0020] Figure 3 is a cross-sectional side view of a device 100 including a buffer transistor 140 along line 3-3 in Figure 1 according to some embodiments. Note that only a portion of the device 100 including the buffer transistor 140 along line 3-3 is shown in Figure 3. Additionally, together with Figure 2, for illustrative purposes, the elements in the device 100 (such as, but not limited to, the substrate 200, the transistor region 210, and the dielectric 220) along with their dimensions and spacing relative to each other are shown illustratively.

[0021] In various embodiments, a buffer transistor 140, including active regions 142A / 142B, is formed between metal layers 110 and 120 and is at least partially surrounded by dielectric 220. In some embodiments, as shown in FIG3, active regions 142A, 142B and wirings 112D to 112F are parallel and extend into / out of the page, while wiring 112B extends horizontally along the page. As shown in FIGS. 2 and 3, a buffer transistor (e.g., buffer transistor 130 or buffer transistor 140) may be formed in the vertical space between two adjacent metal layers (e.g., metal layers 110 and 120) located above the transistor region 210 of device 100 (e.g., on the top side of the transistor region).

[0022] In some embodiments, the active regions 132 of buffer transistor 130 and 142 of buffer transistor 140 are active regions made of thin channel material. For example, the channel material may be about tens or fewer atomic layers. Thin channel materials may include, but are not limited to, 2D (two-dimensional) materials, CNTs (carbon nanotubes), and oxide semiconductors (e.g., indium gallium zinc oxide and tungsten-doped indium oxide). Examples of 2D materials include, but are not limited to, graphene, silicon, BNNS (boron nitride nanosheets), TMDC (transition metal dichalcogenide), phosphorene, and metal oxide nanosheets. Using materials of this type allows for achieving silicon-like active region characteristics in several layers that can be positioned between existing top-side metal layers in a device layout. As described herein, buffer transistors having active regions of this type and positioned between top-side metal layers can be implemented in various device designs, wherein buffer transistors are placed at various locations in a device (such as device 100) to provide buffering for signals propagating across the device.

[0023] Figures 4 through 7 illustrate contemplated embodiments of a buffer transistor design that can be implemented in the space between top-side metal layers as described herein. Figure 4 depicts a three-dimensional perspective view of a buffer transistor 130 according to some embodiments. In the illustrated embodiment, the buffer transistor 130 is a two-stage inverter circuit, wherein active regions 132A and 132B are complementary active regions. In some embodiments, active region 132A is a p-type active region and active region 132B is an n-type active region.

[0024] In various embodiments, the buffer transistor 130 utilizes connections to wirings 112C to 112E in the metal layer 110 to increase the strength of the signal input to the buffer transistor. In the illustrated embodiment, wiring 112D is a signal wiring, wiring 112C is a power supply wiring, and wiring 112E is a ground supply wiring. A voltage supply input 430 for the buffer transistor 130 is provided by connecting wiring 112C (e.g., a power supply wiring) to source line 432 using via 434. Source line 432 then extends over and connects to the source region of active region 132A to provide a voltage supply input for the buffer transistor 130. A ground supply input 440 for the buffer transistor 130 is provided by connecting wiring 112E (e.g., a ground supply wiring) to source line 442 (above metal layer 110) using via 444. Next, source line 442 extends over and connects to the source region of active region 132B to provide a ground supply input for buffer transistor 130. Power supply wiring (e.g., wiring 112C) and ground supply wiring (e.g., wiring 112E) also provide electrical shielding for buffer transistor 130 because the wiring (e.g., rails) is positioned along the outer periphery of the buffer transistor.

[0025] In some embodiments, wiring 112D includes an input wiring 112D' connected to the signal input 410 of the buffer transistor 130 and an output wiring 112D'' connected to the signal output 420 of the buffer transistor. The input wiring 112D' and output wiring 112D'' may be portions of wiring 112D that are physically separated (e.g., cut) within a region of the buffer transistor 130. Embodiments of establishing the input wiring 112D' and output wiring 112D'' by inserting electrical isolation within the wiring 112D are conceivable.

[0026] In some embodiments, the signal input 410 to the buffer transistor 130 is provided by connecting the input wiring 112D' to the gate line 412 using a via 414. The gate line 412 then extends over the active regions 132A and 132B to form the gate of the first stage of the buffer transistor 130 (e.g., the first stage of a two-stage inverter circuit). The gate line 412 may, for example, extend over the channel region of either active region 132A or active region 132B. The gate line 412 may be connected to the channel region of either active region 132A or active region 132B to provide input to the first stage.

[0027] The output from the first stage is provided through stage output line 416, which extends over and connects to the drain regions of both active regions 132A and 132B. To route the output of the first stage on stage output line 416 to the input of the second stage of the buffer transistor 130, a local interconnect 418 may be connected to stage output line 416. In various embodiments, local interconnect 418 may be a C-shaped line connected to the end of stage output line 416 and then routed over and connected to the channel regions of both active regions 132A and 132B to provide input to the second stage of the buffer transistor 130. Therefore, local interconnect 418 provides a same-layer connection for routing signals from the output of the first stage of the buffer transistor 130 to the input of the second stage.

[0028] In various embodiments, local interconnect 418 is permitted to have its wiring if there is sufficient space between metal layer 110 and metal layer 120. For example, in a higher metal layer (e.g., a metal layer further away from the transistor region), the dielectric between the metal layer and the like can be larger and therefore have more space to accommodate local interconnect 418. Accommodating local interconnect 418 may include allowing the local interconnect to be wired without causing the local interconnect to electrically interfere with other wiring or components, or without causing the local interconnect to violate any design rules or guidelines. In a lower metal layer (e.g., a metal layer closer to the transistor region), the height of local interconnect 418 may have to be limited. In some embodiments, local interconnect 418 may be formed by using a portion of the metal layer above buffer transistor 130 (e.g., a portion of metal layer 120). For example, vias may be added to connect stage output line 416 to local interconnect 418 located in metal layer 120 above buffer transistor 130.

[0029] After the signal is routed to the input of the second stage of the buffer circuit 130 via local interconnect 418, the output of the second stage (e.g., the final signal output stage) is provided by stage output line 422. Stage output line 422 may be positioned above and connected to the drain regions of both active regions 132A and 132B. Stage output line 422 (above metal layer 110) is then connected to wiring 112D'' using via 424 to provide signal output 420 for the buffer transistor 130. After passing through the two-stage inverter circuit of the buffer transistor 130 described above, the output signal at signal output 420 has an increased strength relative to the input signal at signal input 410.

[0030] Figure 5 depicts a perspective view of a buffer transistor 130 according to some embodiments. In the illustrated embodiment, the buffer transistor 130 includes a first-stage inverter 510 and a second-stage inverter 520. In various embodiments, wiring 112C carries VDD 506 (e.g., a voltage supply input). Wiring 112C is connected via source line 432 to the source of the p-type region (e.g., active region 132A) in the first-stage inverter 510 and the second-stage inverter 520. Wiring 112E carries VSS 508 (e.g., a ground supply input) and is connected via source line 442 to the source of the n-type region (e.g., active region 132B) in the first-stage inverter 510 and the second-stage inverter 520. These connections to VDD 506 and VSS 508 provide operating power to the first-stage inverter 510 and the second-stage inverter 520.

[0031] In some embodiments, the first-stage inverter 510 receives an input signal 502 provided on wiring 112D'. The output of the first-stage inverter 510 is then connected to the input of the second-stage inverter 520 via a combination of stage output line 416 and local interconnect line 418. An output signal 504 is then output from the second-stage inverter 520 on wiring 112D''.

[0032] Figure 6 depicts a three-dimensional perspective view of a buffer transistor 140 according to some embodiments. In the illustrated embodiment, the buffer transistor 140 is a two-stage inverter circuit, wherein active regions 132A and 132B are complementary active regions. In some embodiments, active region 142A is a p-type active region and active region 142B is an n-type active region.

[0033] In various embodiments, buffer transistor 140 is structurally similar to buffer transistor 130, wherein it is connected to metal layer 120 instead of metal layer 110. For example, buffer transistor 140 may utilize connections to wirings 122D to 122F in metal layer 120 to increase the strength of the signal input to the buffer transistor. In the illustrated embodiment, wiring 122D is a power supply wiring, and wiring 122F is a ground supply wiring. A voltage supply input 630 for buffer transistor 140 is provided by connecting wiring 122D (e.g., the power supply wiring) to source line 632 using via 634. Source line 632 then extends over and connects to the source region of active region 142A to provide a voltage supply input for buffer transistor 140. A ground supply input 640 for buffer transistor 140 is provided by connecting wiring 122F (e.g., the ground supply wiring) to source line 642 (below metal layer 120) using via 644. Next, source line 642 extends over and connects to the source region of active region 142B to provide a ground supply input for buffer transistor 140. Power supply wiring (e.g., wiring 122D) and ground supply wiring (e.g., wiring 122F) also provide electrical shielding for buffer transistor 140 because the wiring (e.g., rails) is positioned along the outer periphery of the buffer transistor.

[0034] In some embodiments, wiring 122E is a signal wiring. Wiring 122E may include an input wiring 122E' connected to the signal input 610 of the buffer transistor 140 and an output wiring 122E'' connected to the signal output 620 of the buffer transistor. The input wiring 122E' and the output wiring 122E'' may be portions of wiring 122E that are physically separated (e.g., cut) in the region of the buffer transistor 140. Embodiments of establishing the input wiring 122E' and the output wiring 122E'' by inserting electrical isolation in the wiring 122E are conceivable.

[0035] In some embodiments, the signal input 610 to the buffer transistor 140 is provided by connecting the input wiring 122E' to the gate line 612 (below the metal layer 120) using a via 614. The gate line 612 extends over the channel regions of both active regions 142A and 142B to form the gate of the first stage of the buffer transistor 140 (e.g., the first stage of a two-stage inverter circuit). The gate line 612 can be connected to the channel regions of both active regions 142A and 142B to provide input to the first stage of the buffer transistor 140.

[0036] The output from the first stage is provided through stage output line 616, which extends over and connects to the drain regions of both active regions 142A and 142B. The output of the first stage on stage output line 616 is routed to the input of the second stage of the buffer transistor 140 by connecting local interconnect 618 to stage output line 616. In various embodiments, local interconnect 618 may be a C-shaped line that connects to the end of stage output line 616 and then routes over and connects to the channel regions of both active regions 142A and 142B to provide input to the second stage of the buffer transistor 140. Therefore, local interconnect 618 provides a same-layer connection for routing signals from the output of the first stage of the buffer transistor 140 to the input of the second stage.

[0037] In various embodiments, if sufficient space exists between metal layers 110 and 120, local interconnects 618, similar to local interconnect 418, are permitted to have their wiring. Furthermore, accommodating local interconnect 618 may include wiring that allows the local interconnect to have wiring that does not electrically interfere with other wiring or components, or violate any design rules or guidelines. In lower metal layers (e.g., metal layers closer to the transistor region), the height of local interconnect 618 may have to be limited. Due to this limitation, in some embodiments, local interconnect 618 may be formed by using a portion of the metal layer below the buffer transistor 140 (e.g., a portion of metal layer 110). For example, vias may be added to connect stage output lines 616 to local interconnect 618 located in metal layer 110 below the buffer transistor 140.

[0038] After local interconnect 618 routes the signal to the input of the second stage of buffer circuit 140, the output of the second stage (e.g., the final signal output stage) is provided by stage output line 622. Stage output line 622 may be positioned above and connected to the drain regions of both active regions 142A and 142B. Stage output line 622 is connected to wiring 122E'' using via 624 to provide signal output 620 for buffer transistor 140. After passing through the two-stage inverter circuit of buffer transistor 140 described herein, the output signal on signal output 620 has an increased strength relative to the input signal on signal input 610.

[0039] Figure 7 depicts a schematic representation of a buffer transistor 140 according to some embodiments. In the illustrated embodiment, the buffer transistor 140 includes a first-stage inverter 710 and a second-stage inverter 720. In various embodiments, wiring 122D carries VDD 706 (e.g., a voltage supply input). Wiring 122D is connected via source line 632 to the source of the p-type region (e.g., active region 142A) in the first-stage inverter 710 and the second-stage inverter 720. Wiring 122F carries VSS 708 (e.g., a ground supply input) and is connected via source line 642 to the source of the n-type region (e.g., active region 142B) in the first-stage inverter 710 and the second-stage inverter 720. These connections to VDD 706 and VSS 708 provide operating power to the first-stage inverter 710 and the second-stage inverter 720.

[0040] In some embodiments, the first-stage inverter 710 receives the input signal 702 provided on wiring 122E'. The output of the first-stage inverter 710 is then connected to the input of the second-stage inverter 720 via a combination of stage output line 616 and local interconnect line 618. The output signal 704 is then output from the second-stage inverter 720 on wiring 122E''. As described above, both buffer transistors 130 and 140 are two-stage inverter circuits capable of providing output signals (e.g., output signals 504 and 704) with increased strength relative to the input signals (e.g., input signals 502 and 702). Because the buffer transistors are positioned between two metal layers (e.g., metal layers 110 and 120, as shown in Figures 2 and 3), they can provide this buffering (e.g., amplification) of signals propagating through the device 100 without any increase in the device's occupied area or area, since the buffer transistors are positioned within the space already present in the device.

[0041] The number and arrangement (e.g., placement) of the buffer transistors (e.g., buffer transistor 130 or buffer transistor 140) described herein can vary based on the design or operational requirements of the device implementing the buffer transistors. For example, embodiments in which multiple buffer transistors are stacked together across multiple rows or columns of wiring in the device (e.g., across multiple wirings in metal layer 110 or metal layer 120) are conceivable. In some embodiments, the stacked buffer transistors may share a common ground supply wiring among them. In such embodiments, the stacked buffer transistors may be stacked aligned (e.g., if the width of the active area is limited) or stacked in an interleaved pattern to allow for a larger active area width.

[0042] Figure 8 depicts a top plan view representation of a contemplated device with various layouts of a display buffer transistor according to some embodiments. In the illustrated embodiment, device 800 includes a metal layer 110 with wirings 112A to 112J and a metal layer 120 with wirings 122A to 122K. Wirings 112B and 112F may be power supply wirings (e.g., VDD), while wiring 112D is a ground supply wiring. Wirings 112C and 112E may be signal wirings.

[0043] The pairing of buffer transistors 130A (having active regions 132A and 132B) and 130B (having active regions 132A' and 132B') represents a pair of buffer transistors aligned and stacked. Note that the complementary pair of active regions is flipped between buffer transistors 130A and 130B to allow the buffer transistors to share a ground supply wiring (wiring 112D). Therefore, active region 132B of buffer transistor 130A is adjacent active region 132B' of buffer transistor 130B. Although buffer transistors 130A and 130B share a common ground supply wiring, the buffer transistors have separate power supply wirings (e.g., wiring 112B and wiring 112F, respectively) and also operate to buffer (e.g., amplify) different signals on different signal wirings (e.g., wiring 112C and wiring 112E, respectively).

[0044] Because buffer transistors 130A and 130B are aligned (e.g., the left and right edges of the buffer transistors are aligned in the illustration), the width of the active region 132 is limited and cannot be increased (note that the width of the active region is vertical in the illustration). Interleaving the buffer transistors (as shown by buffer transistors 130C and 130D in Figure 8) allows the width of the active region 132 to be increased. In the illustrated embodiment, buffer transistor 130C includes active regions 132A'' and 132B'', while buffer transistor 130D includes active regions 13A''' and 132B'''.

[0045] Similar to the pairing of buffer transistors 130A and 130B, complementary active regions are inverted between buffer transistors 130C and 130D to allow the buffer transistors to share a ground supply wiring (wiring 112D). However, with the interleaving of buffer transistors 130C and 130D, the widths of active regions 132A'', 132B'', 13A'', and 132B'' can be increased because there are no restrictions on the size of adjacent buffer transistors. For example, the size of active regions 132A'' and 132B'' in buffer transistor 130C is not limited by the placement of buffer transistor 130D, and vice versa. Accordingly, the interleaving of buffer transistors 130C and 130D allows for the implementation of wider active regions in device 800. These wider active regions can be used to increase the amplification strength of the buffer transistors. For example, the signal strength increase provided by buffer transistors 130C / 130D can be greater than the signal strength increase provided by buffer transistors 130A / 130B. When the active region is rotated 90 degrees in a horizontal dimension parallel to the substrate, the stacked buffer transistors can also be stacked in an aligned manner (e.g., if the width of the active region is limited) or stacked in an interlaced pattern using metal layer 120 as wiring (e.g., 122A to 122K).

[0046] Although the buffer transistors described above are logically and readily apparent to those skilled in the art, it is logical to construct other logic functions and logic gate systems using the concepts and ideas described. For example, an inverter can be constructed using only the second stage of the buffer. In another instance, other logic gates (such as NAND and NOR) can be constructed with the freedom to adjust the size and width of the active region by using more wiring metal tracks in metal layer 110 or metal layer 120. Example computer system

[0047] Turning to Figure 9, a block diagram of one embodiment of system 900 is shown, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 900 includes at least one instance of a system-on-chip (SoC) 906, which may include various types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, communication mesh architecture and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 906 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 906 is coupled to external memory 902, peripheral devices 904, and a power supply 908.

[0048] A power supply 908 is also provided, which supplies supply voltage to the SoC 906 and one or more supply voltages to memory 902 and / or peripheral devices 904. In various embodiments, the power supply 908 represents a battery pack (e.g., a rechargeable battery pack in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 906 is included (and more than one external memory 902 is also included).

[0049] Memory 902 refers to any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3, and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices are mounted using a SoC or integrated circuit in a chip-on-chip configuration, package-on-package configuration, or multi-chip module configuration.

[0050] Depending on the type of system 900, peripheral device 904 may include any desired circuitry. For example, in one embodiment, peripheral device 904 may include means for various types of wireless communication (such as WiFi, Bluetooth, cellular, GPS, etc.). In some embodiments, peripheral device 904 may also include additional storage, including RAM, solid-state storage, or disk storage. Peripheral device 904 may include user interface devices such as a display screen (including a touch screen or multi-touch screen), a keyboard or other input device, a microphone, a speaker, etc.

[0051] As illustrated, system 900 is shown to have applications in a wide range of fields. For example, system 900 can be used as part of a chip, circuit system, component, etc., of a desktop computer 910, laptop computer 920, tablet computer 930, cellular or mobile phone 940, or television 950 (or a set-top box coupled to a television). A smartwatch and health monitoring device 960 are also illustrated. In some embodiments, the smartwatch may include a variety of general computing-related functions. For example, the smartwatch may provide email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track a user's proximity to other users for the purpose of social distancing during an epidemic, contact tracing, and provide communication to emergency services in the event of a health crisis. Epidemiological functions (such as contact tracing), providing communication to emergency medical services, etc. In various embodiments, the smartwatches mentioned above may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0052] System 900 can be further used as part of (multiple) cloud-based services 970. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 900 can be used in one or more devices in a home 980, different from those previously mentioned. For example, appliances in the home can monitor and detect conditions of concern. For example, various devices in the home (e.g., refrigerators, air conditioning systems, etc.) can monitor the status of the devices and provide alerts to the homeowner when specific events are detected (or, for example, repair facilities). Alternatively, a thermostat can monitor the temperature in the home and automatically adjust the heating / cooling system based on the homeowner's historical responses to various conditions. Figure 9 also illustrates the application of System 900 to various transportation modes 990. For example, system 900 can be used in the control and / or entertainment systems of airplanes, trains, buses, taxis, private cars, surface vessels ranging from private boats to cruise ships, locomotives (for rental or personal use), etc. In various cases, system 900 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, and other aspects. Many other embodiments are possible and contemplated. It should be noted that the apparatus and applications illustrated in Figure 9 are illustrative only and are not intended to be limiting. Other apparatuses are possible and contemplated. ***

[0053] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiment" or "various embodiments"). An embodiment is a different implementation or example of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," and the like do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives falling within the spirit or scope of this disclosure.

[0054] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all embodiments of these embodiments will necessarily exhibit any or all of the potential advantages. Whether the advantages realized for a particular embodiment depend on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why embodiments falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure (in conjunction with one of the disclosed embodiments) that renders one or more of the disclosed advantages ineffective or diminished. Furthermore, suboptimal design implementation of a particular embodiment (e.g., the embodiment's technology or tooling) may also render the disclosed advantages ineffective or diminished. Even assuming a skilled embodiment, the realization of advantages may still depend on other factors, such as the environmental conditions in which the embodiment is deployed. For example, the input supplied to a particular embodiment may prevent one or more problems addressed in this disclosure from arising in a particular context, resulting in the inability to achieve the benefits of its solution. Given the existence of possible factors outside this disclosure, it is expressly intended that any potential advantages described herein not be construed as requiring compliance with the claims to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the (multiple) types of improvements available to designers who have the benefits of this disclosure. Such advantages described permissibly (e.g., stating that a particular advantage "may cause") are not intended to convey any doubt about whether such advantages are actually achievable, but rather to acknowledge that the technical reality of achieving such advantages often depends on additional factors.

[0055] Unless otherwise stated, the embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of the draft claims based on this disclosure, even if only a single instance with respect to a particular feature is described. The disclosed embodiments are intended to be illustrative and not limiting, and there is no statement to the contrary in this disclosure. Therefore, this application is intended to allow the scope of the claims to cover the disclosed embodiments and such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to which this disclosure pertains.

[0056] For example, the features in this application can be combined in any suitable manner. Accordingly, during the examination of this application (or the application claiming priority), a new claim may be made for any such combination of features. Specifically, referring to the claims of the accompanying patent application, features from independent claims may be combined with features from other independent claims, including, where appropriate, claims attached to other subsidiary claims. Similarly, features from individual subsidiary claims may be combined, where appropriate.

[0057] Accordingly, while the accompanying subsidiary claims may be drafted such that each is dependent on a single other claim, additional dependencies are also contemplated. Any combination of features of the subsidiary claims consistent with this disclosure is contemplated and may be claimed in this application or another application. In short, combinations are not limited to those specifically enumerated in the scope of the appended patent application.

[0058] Where appropriate, it is also envisioned that a request drafted in one format or statutory type (e.g., device) is intended to support a corresponding request in another format or statutory type (e.g., method). ***

[0059] Because this disclosure is a legal document, all terms and phrases used are subject to administrative and judicial interpretation. The following paragraphs and the definitions provided throughout this disclosure are intended to determine how to interpret the scope of any patent application drafted based on this disclosure.

[0060] Unless the context explicitly specifies otherwise, the singular form of an item (i.e., a noun or noun phrase preceded by "a / an" or "the") is intended to mean "one or more" (or "one or more"). Therefore, mentioning "an item" in a claim does not exclude additional instances of that item without accompanying context. "Plurality" refers to a set of one of two or more items.

[0061] In this article, the word "may" is used in the sense of permission (i.e., having the possibility or ability to) and not in the sense of mandatory (i.e., being required to).

[0062] The terms “comprising” and “including” and their forms are open-ended, meaning “including, but not limited to”.

[0063] When the term "or" is used in this disclosure with respect to a list of options, it is generally understood to be used in an inclusive sense unless the context otherwise provides. Therefore, the statement "x or y" is equivalent to "x or y, or both," thus: 1) covering x but not y; 2) covering y but not x; and 3) covering both x and y. On the other hand, phrases such as "either x or y, but not both" clearly indicate that "or" is used in an exclusive sense.

[0064] The statements "w, x, y, or z, or any combination thereof" or "... at least one of ... w, x, y, and z" are intended to cover all possibilities involving a single element or at most a total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element of the set (e.g., w but not x, y, or z)), any two elements (e.g., w and x, but not y or z)), any three elements (e.g., w, x, and y, but not z)), and all four elements. Therefore, the phrase "...w, x, y, and z at least one" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase is not interpreted as requiring at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0065] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for a feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of that feature. Additionally, unless otherwise stated, the labels "first," "second," and "third," when applied to a feature, do not imply any type of order (e.g., spatial, temporal, logical, etc.).

[0066] The phrase "based on" is used to describe one or more factors that influence a decision. This term does not preclude the possibility that additional factors may influence the decision. That is, a decision may be based solely on a particular factor, or on that particular factor and other unspecified factors. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A, or that B influences the decision of A. This phrase does not preclude the possibility that A may also be determined based on other factors, such as C. This phrase is also intended to encompass an embodiment where A is determined solely based on B. As used herein, the term "based on" is synonymous with the term "based at least in part on."

[0067] The phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independently of any of the specified factors. That is, an effect may be a response to these factors alone, or it may be a response to these specified factors and other unspecified factors. Consider the phrase "perform A in response to B." This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude the possibility that A may also be performed in response to another factor (such as C). This phrase also does not exclude the possibility that A may be performed in conjunction with responses to B and C. This phrase is also intended to cover instances where A is performed in response to B alone. As used herein, the phrase "responsive to" is synonymous with the phrase "responsive at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "at least in part in response to". ***

[0068] In this disclosure, different entities (which may be referred to differently as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This notation ("entity" configured to "perform one or more tasks") is used herein to refer to a structure (i.e., a physical object). Specifically, this notation indicates that the structure is configured to perform the one or more tasks during operation. Even if a structure is not currently being operated, it may still be said that the structure is "configured to" perform a task. Therefore, an entity described or stated as being "configured to" perform a task refers to a physical object, such as a device, circuit, system with a processing unit, or memory storing executable program instructions to perform that task. This phrase is not used herein to refer to intangible things.

[0069] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform such tasks / operations, even if not specifically mentioned.

[0070] The term "configured to" does not imply "configurable to". For example, an unprogrammed FPGA will not be considered "configured to" performing a specific function. However, this unprogrammed FPGA may be "configurable to" performing that function. After proper programming, the FPGA can then claim to be "configured to" performing a specific function.

[0071] For the purposes of this disclosed U.S. patent application, it is expressly intended that a structure be described in a claim as being "configured to" perform one or more tasks. [Not] invoke 35 USC § 112(f) to interpret the claim element. If the applicant intends to invoke section 112(f) during the examination of a U.S. patent application based on this disclosure, the claim element will be stated using the phrase "a component for 'performing a function'".

[0072] Different “circuit” may be described in this disclosure. These circuits or “circuitry” constitute hardware comprising various types of circuit elements, such as combinational logic, time-controlled storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuit systems may be custom-designed or taken from standard libraries. In various implementations, circuit systems may include digital components, analog components, or a combination of both, as needed. Certain types of circuits are often referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit systems.

[0073] Therefore, the disclosed circuits / units / components and other elements illustrated herein include hardware elements, such as those described in the preceding paragraphs. In many instances, the internal configuration of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" can be described as having the function of "processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units," meaning that the decoder unit is "configured to" perform this function. This description of function is sufficient for those skilled in the art of computer science to indicate a feasible set of structures for that circuit.

[0074] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements defined by the functions or operations implemented therefrom through configuration, this configuration, and the manner in which such circuits / units / components interact with each other, form a micro-level definition of hardware, which is ultimately manufactured in integrated circuits or programmed into an FPGA to form a physical implementation of the micro-level definition. Therefore, this micro-level definition is a structure from which many physical implementations are recognized by those skilled in the art, all of which fall within the broad structure described by the micro-level definition. That is, those skilled in the art who propose the micro-level definition provided according to this disclosure can implement this structure without excessive experimentation and by using common techniques, by encoding the description of the circuits / units / components in a hardware description language (HDL) (such as Verilog or VHDL). HDL descriptions are often expressed in a functional manner. However, for those with ordinary knowledge in the relevant technical field, this HDL description is used to transform the structure of a circuit, unit, or component into the details of a next-level implementation. This HDL description can take the form of behavioral code (which is generally not synthesizable), register transfer language (RTL) code (which is generally synthesizable, as opposed to behavioral code), or structured code (e.g., a wiring lookup table specifying logic gates and their connections). Subsequently, the HDL description can be synthesized based on a component library designed for a given integrated circuit manufacturing technique, and can be modified for timing, power, and other reasons to produce a final design database, which is transferred to a manufacturing plant to create a mask, ultimately producing the integrated circuit. Some hardware circuitry or portions thereof can also be customized in a schematic editor and transferred to the integrated circuit design along with the synthesized circuit system. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement hardware circuitry, and / or discrete components may be used in some embodiments. Alternatively, HDL designs may be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA. The decoupling between the design of this group of circuits and subsequent lower-level implementations of these circuits typically results in a situation where, when this process is executed at a different stage of the circuit implementation, the circuit or logic designer never specifies a particular set of structures for the lower-level implementation that goes beyond the description of the actions the circuit is configured to perform.

[0075] In fact, many different lower-level combinations of circuit elements can be used to implement circuits of the same specifications, resulting in a large number of equivalent structures. As mentioned, these lower-level circuit implementations can vary depending on changes in manufacturing technology, the choice of manufacturer to produce integrated circuits, and the component library provided for a particular project. In many cases, the choice of different design tools or methodologies to produce these different implementations can be arbitrary.

[0076] Furthermore, for a single implementation of a circuit with a specific functional specification, it is common to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete description of the underlying structure for implementing a single embodiment, let alone an equivalent feasible implementation of a massive array. For this reason, this disclosure describes circuit structures using functional shorthand commonly used in the industry.

[0077] 100: Device 110: Top side metal layer; metal layer 112, 112A, 112B, 112C, 112D, 112E, 112F, 112G, 112H, 112I, 112J, 112J: Wiring 112D': Input wiring; wiring 112D'': Output wiring; wiring 120: Top side metal layer; metal layer 122, 122A, 122B, 122C, 122D, 122E, 122F, 122G, 122H, 122I, 122J, 122K: Wiring 122E': Input wiring; wiring 122E'': Output wiring; wiring 130, 130A, 130B, 130C, 130D: Buffer transistors 132, 132, 132A, 132A', 132A'', 132A''', 132B, 132B', 132B'', 132B'': Active region 140: Buffer transistor; Buffer circuit 142, 142A, 142B: Active Regions 200: Substrate 210: Transistor Region 220: Dielectric 410: Signal Input 412: Gate line 416: Stage Output Line 418: Local interconnects 420: Signal Output 422: Stage Output Line 424: Through hole 430: Voltage supply input 432: Source line 434: Through hole 440: Grounding supply input 442: Source line 444: Through hole 502: Input signal 506:VDD 508:VSS 510: First-stage inverter 520: Second-stage inverter 610: Signal Input 612: Gate line 614: Through hole 616: Stage Output Line 618: Local interconnects 620: Signal Output 622: Stage Output Line 630: Voltage supply input 632: Source Line 634: Through hole 640: Grounding supply input 642: Source Line 644: Through hole 704: Output signal 706:VDD 708:VSS 710: First-stage inverter 720: Second-stage inverter 800: Device 900: System 902: External memory; memory 904: Peripheral Equipment 906: System-on-a-Chip (SoC) 908: Power Supply 910: Desktop computer 920: Laptop 930: Tablet PC 940: Cellular or mobile phone 950: Television 960: Smartwatches and health monitoring devices 970: Cloud-based services 980: Home 990: Transportation Mode

Claims

1. A semiconductor device comprising: a transistor region of an integrated circuit, the transistor region being above the substrate in a vertical dimension perpendicular to the substrate; a first metal layer being located above the transistor region in the vertical dimension; a second metal layer being located above the first metal layer in the vertical dimension; wherein at least one of the first metal layer and the second metal layer includes power supply wiring, ground supply wiring, and signal wiring; and a transistor circuit positioned between the first metal layer and the second metal layer in the vertical dimension, wherein the transistor circuit includes: A pair of active regions, positioned in a horizontal dimension parallel to the substrate between the power supply wiring and the grounding supply wiring; A gate positioned above two active regions in the vertical dimension; a signal input coupled to the gate and a portion of the signal wiring; a voltage supply input coupled to the active region of the power supply wiring; A ground supply input for coupling to the active area of ​​the ground supply cabling; and a signal output for coupling to an additional portion of the signal cabling.

2. The semiconductor device of claim 1, wherein the transistor circuit is a buffer transistor circuit configured to increase the strength of a signal received at the signal input.

3. The semiconductor device of claim 1, wherein the transistor circuit is an inverter transistor circuit, and the pair of active regions includes a p-type active region and an n-type active region.

4. The semiconductor device of claim 3, wherein the transistor circuit further includes a partial via between one or more of the gate, the voltage supply input, the ground supply input, and the signal output and one or both of the first metal layer and the second metal layer.

5. The semiconductor device of claim 3, wherein the transistor circuit further includes a local interconnect positioned in the vertical dimension between the first metal layer and the second metal layer and between the drain region and the gate region of the active region.

6. The semiconductor device of claim 1, wherein the power supply wiring, the ground supply wiring, and the signal wiring are oriented parallel to each other in the horizontal dimension, and wherein the signal wiring is positioned between the pair of active regions in the horizontal dimension.

7. The semiconductor device of claim 1, further comprising an additional transistor circuit positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the additional transistor circuit includes a pair of additional active regions.

8. The semiconductor device of claim 7, wherein the pair of additional active regions is orthogonal to the orientation of the pair of active regions in the horizontal dimension.

9. The semiconductor device of claim 1, wherein the transistor circuit is positioned in a dielectric layer between the first metal layer and the second metal layer.

10. The semiconductor device of claim 1, wherein the pair of active regions is formed by a thin channel material positioned between the first metal layer and the second metal layer.

11. A semiconductor device comprising: a transistor circuit positioned over a transistor region of an integrated circuit in a vertical dimension perpendicular to a substrate; a first metal layer positioned over the transistor region in the vertical dimension; a second metal layer positioned over the transistor region in the vertical dimension; wherein at least one of the first and second metal layers includes power supply wiring, ground supply wiring, and signal wiring, wherein a portion of the signal wiring is coupled to the transistor circuit; and a buffer transistor circuit positioned between the first and second metal layers in the vertical dimension, wherein the buffer transistor circuit includes: One-p type active region; Type 1n active region; A gate input, which is coupled to the portion of the signal wiring that is coupled to the transistor circuit; A voltage supply input coupled to a source region in the p-type active region and the power supply wiring; a ground supply input coupled to a source region in the n-type active region and the ground supply wiring; and a gate output coupled to an additional portion of the signal wiring.

12. The semiconductor device of claim 11, wherein the power supply wiring, the ground supply wiring, and the signal wiring are oriented parallel to each other along a first direction in a horizontal dimension parallel to the substrate.

13. The semiconductor device of claim 12, wherein the p-type active region and the n-type active region are oriented parallel to each other along the first direction in the horizontal dimension.

14. The semiconductor device of claim 12, wherein the buffer transistor circuit includes a gate line oriented along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, and wherein the gate line is positioned in the vertical dimension between the first metal layer and the second metal layer and extends in the vertical dimension above both the p-type active region and the n-type active region.

15. The semiconductor device of claim 11, wherein the voltage supply input includes: A metal wire positioned in the vertical dimension between the first metal layer and the second metal layer and at least partially positioned above the source region in the p-type active region; and a via coupled between the metal wire and the power supply wiring.

16. The semiconductor device of claim 11, wherein the ground supply input includes: A metal wire positioned in the vertical dimension between the first metal layer and the second metal layer and at least partially positioned above the source region in the n-type active region; and a via coupled between the metal wire and the ground supply wiring.

17. The semiconductor device of claim 11, wherein the buffer transistor circuit includes: A first gate line oriented along a direction in a horizontal dimension, wherein the gate line is at least partially positioned above the channel regions of both the p-type active region and the n-type active region in the vertical dimension; a first-stage output line oriented along the direction, wherein the first-stage output line is at least partially positioned above the drain regions of both the p-type active region and the n-type active region in the vertical dimension; and a local interconnect line connected to both ends of the first-stage output line, wherein at least a portion of the local interconnect line is positioned above the channel regions of both the p-type active region and the n-type active region in the vertical dimension.

18. The semiconductor device of claim 17, wherein the gate output includes a second-stage output line oriented along a second direction, wherein the second-stage output line is at least partially positioned above the drain regions of both the p-type active region and the n-type active region in the vertical dimension.

19. The semiconductor device of claim 11, wherein the buffer transistor circuit is located in a dielectric layer between the first metal layer and the second metal layer.

20. A semiconductor device comprising: a transistor region of an integrated circuit, the transistor region being above a substrate in a vertical dimension perpendicular to the substrate; a first metal layer being located above the transistor region in the vertical dimension, wherein the first metal layer includes a first power supply wiring, a first ground supply wiring, and a first signal wiring; a second metal layer being located above the first metal layer in the vertical dimension, wherein the second metal layer includes a second power supply wiring, a second ground supply wiring, and a second signal wiring; and a first buffer transistor circuit being positioned between the first metal layer and the second metal layer in the vertical dimension, wherein the first buffer transistor circuit includes: The first p-type active region; The first type n active region; A first gate input, which is coupled to a portion of the first signal wiring; The system comprises: a first voltage supply input coupled to a first source region of the first p-type active region and the first power supply wiring; a first ground supply input coupled to a first source region of the first n-type active region and the first ground supply wiring; a first gate output coupled to an additional portion of the first signal wiring; and a second buffer transistor circuit positioned in the vertical dimension between the first metal layer and the second metal layer, wherein the second buffer transistor circuit includes: a second p-type active region; a second n-type active region; a second gate input coupled to a portion of the second signal wiring; a second voltage supply input coupled to a second source region of the second p-type active region and the second power supply wiring; a second ground supply input coupled to a second source region of the second n-type active region and the second ground supply wiring; and a second gate output coupled to an additional portion of the second signal wiring.

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