Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, a gate dielectric layer, a dipole layer, a gate, a source region, and a drain region. The gate dielectric layer is located above the substrate. The dipole layer is located above the gate dielectric layer, wherein the dipole layer is an oxide-containing layer, and the width of the dipole layer is smaller than the width of the gate dielectric layer. The gate is located above the dipole layer and the gate dielectric layer. The source region is located in the substrate. The drain region is located in the substrate, wherein the source region and the drain region are located on opposite sides of the gate dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] In traditional planar metal-oxide-semiconductor (MOSFET) field-effect transistors, the saturation current is determined by the inversion charge density. Therefore, increasing the inversion charge density can increase the saturation current. Common methods to increase the inversion charge density include adjusting the placement conditions and reducing the gate oxide layer thickness to lower the threshold voltage. However, this approach introduces side effects such as increased off-state current and gate leakage current. For example, precise control of the placement area profile becomes more difficult, leading to unacceptable levels of off-state leakage current. A thinner gate oxide layer may also result in greater gate leakage. Summary of the Invention

[0003] Some embodiments of this disclosure provide a semiconductor device including a substrate, a gate dielectric layer, a dipole layer, a gate, a source region, and a drain region. The gate dielectric layer is located above the substrate. The dipole layer is located above the gate dielectric layer, wherein the dipole layer is an oxide-containing layer, and the width of the dipole layer is smaller than the width of the gate dielectric layer. The gate is located above the dipole layer and the gate dielectric layer. The source region is located in the substrate. The drain region is located in the substrate, wherein the source region and the drain region are located on opposite sides of the gate dielectric layer.

[0004] In some embodiments, the sidewall of the dipole layer near the source region is aligned with the sidewall of the gate dielectric layer near the source region.

[0005] In some embodiments, the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the gate dielectric layer near the drain region.

[0006] In some embodiments, the semiconductor device further includes a high-k gate dielectric layer located between the gate dielectric layer and the dipole layer, wherein the dielectric constant of the high-k gate dielectric layer is higher than the dielectric constant of the gate dielectric layer.

[0007] In some embodiments, a high-k gate dielectric layer contacts the gate.

[0008] In some embodiments, the width of the dipole layer is smaller than the width of the high-k gate dielectric layer.

[0009] In some embodiments, the sidewall of the dipole layer near the source region is aligned with the sidewall of the high-k gate dielectric layer near the source region.

[0010] In some embodiments, the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the high-k gate dielectric layer near the drain region.

[0011] In some embodiments, the sidewall of the dipole layer near the drain region is aligned with the sidewall of the gate dielectric layer near the drain region.

[0012] In some embodiments, the sidewall of the dipole layer near the source region is laterally offset from the sidewall of the gate dielectric layer near the source region.

[0013] Some embodiments of this disclosure provide a method for manufacturing a semiconductor device, including the following steps: forming a gate dielectric layer over a substrate; forming a dipole layer over the gate dielectric layer, wherein the dipole layer covers a portion of the gate dielectric layer; forming a gate over the dipole layer and the gate dielectric layer; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are located on opposite sides of the gate dielectric layer.

[0014] In some embodiments, after the source region and drain region are formed, the sidewall of the dipole layer near the source region is aligned with the sidewall of the gate dielectric layer near the source region.

[0015] In some embodiments, after the source region and drain region are formed, the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the gate dielectric layer near the drain region.

[0016] In some embodiments, after the source region and drain region are formed, the gate contact near the drain region is a gate dielectric layer near the drain region.

[0017] In some embodiments, the thickness of the gate near the source region is less than the thickness of the gate near the drain region.

[0018] In some embodiments, the manufacturing method further includes the step of forming a high-k gate dielectric layer over a gate dielectric layer before forming a dipole layer, wherein after forming the dipole layer, a portion of the high-k gate dielectric layer is exposed by the dipole layer.

[0019] In some embodiments, after the source region and drain region are formed, the gate near the drain region contacts the high-k gate dielectric layer near the drain region.

[0020] In some embodiments, after the source and drain regions are formed, the sidewall of the dipole layer near the source region is aligned with the sidewall of the high-k gate dielectric layer near the source region.

[0021] In some embodiments, after the source region and drain region are formed, the sidewall of the dipole layer near the drain region is aligned with the sidewall of the gate dielectric layer near the drain region.

[0022] In some embodiments, after the source region and drain region are formed, the sidewall of the dipole layer near the source region is laterally offset from the sidewall of the gate dielectric layer near the source region.

[0023] It should be understood that the foregoing general description and the following detailed description are provided by way of examples and are intended to provide further explanation of the content disclosed in the claim. Simple Explanation of the Diagram

[0024] This disclosure can be more fully understood by referring to the accompanying drawings and by reading the following detailed description of the embodiments: Figures 1 through 7 are cross-sectional views illustrating methods of manufacturing a semiconductor device according to some embodiments of this disclosure. Figure 8 illustrates a semiconductor device in some other embodiments of this disclosure. Figure 9 illustrates a semiconductor device in some other embodiments of this disclosure. Figure 10 illustrates a semiconductor device in some other embodiments of this disclosure. Implementation

[0025] Some embodiments disclosed herein relate to an asymmetric metal-oxide-semiconductor field-effect transistor (MOSFET) including a dipole layer. The dipole layer is designed to be close to one of the source or drain terminals of the MOSFET and far from the other. The dipole layer is used to adjust the threshold voltage of the MOSFET and suppress off-state current to enhance the switching ratio of the semiconductor device.

[0026] Figures 1 through 7 illustrate cross-sectional views of a method for manufacturing a semiconductor device according to some embodiments of this disclosure. Referring to Figure 1, a substrate 100 is provided. The substrate 100 is a doped semiconductor substrate. For an NMOS (N-type MOSFET), the substrate 100 is a P-type substrate, and for a PMOS (P-type MOSFET), the substrate 100 is an N-type substrate. In some embodiments, the substrate 100 may be formed of, for example, silicon, germanium, silicon-germanium, silicon-carbon, silicon-germanium-carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials.

[0027] Referring to Figure 2, a gate dielectric layer 110 is formed over the substrate 100. In some embodiments, the gate dielectric layer 110 is made of silicon oxide.

[0028] Referring to Figure 3, a high-k gate dielectric layer 120 is formed above the gate dielectric layer 110, and the dielectric constant of the high-k gate dielectric layer 120 is higher than that of the gate dielectric layer 110. In some embodiments, the high-k gate dielectric layer 120 may be made of hafnium oxide (HfO 2), zirconium oxide (ZrO 2), titanium oxide (TiO 2), aluminum oxide (Al 2O 3), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or combinations thereof. In some embodiments, the high-k gate dielectric layer 120 may be omitted in the semiconductor device.

[0029] Referring to Figure 4, a dipole layer 130 is formed above the gate dielectric layer 110 and the high-k gate dielectric layer 120. The dipole layer 130 is used to adjust the threshold layer of the semiconductor device by means of oxygen atom exchange between the gate dielectric layer 110 and the dipole layer 130. Therefore, the oxygen concentration of the gate dielectric layer 110 and the oxygen concentration of the dipole layer 130 are different. The material of the dipole layer 130 is different from the material of the high-k gate dielectric layer 120. In some embodiments, the dipole layer 130 is an oxygen-containing layer, for example, made of Al₂O₃, TiO₂, ZrO₂, MgO, Y₂O₃, Lu₂O₃, La₂O₃, or SrO, or combinations thereof. In some embodiments, the thickness of the dipole layer 130 is in the range of 1 Å to 50 Å. In some embodiments, the dipole layer 130 may also be made of silicon oxide. The dipole layer 130 and the gate dielectric layer 110 can be formed separately by adjusting the oxygen ratio of the process gas, thereby forming the dipole layer 130 and the gate dielectric layer 110 in the same process cavity. Therefore, the oxygen concentration of the dipole layer 130 is different from that of the gate dielectric layer 110.

[0030] Referring to Figure 5, the dipole layer 130 is patterned such that a portion of the high-k gate dielectric layer 120 is exposed. In some embodiments, the dipole layer 130 can be patterned by etching the dipole layer 130 with a hard mask layer above it until the high-k gate dielectric layer 120 is exposed.

[0031] Referring to Figure 6, a gate 140 is formed over a dipole layer 130, a high-k gate dielectric layer 120, and a gate dielectric layer 110. In some embodiments, the gate 140 can be formed by depositing a conductive material over the dipole layer 130, the high-k gate dielectric layer 120, and the gate dielectric layer 110, and then planarizing the conductive material. Since the dipole layer 130 exposes the high-k gate dielectric layer 120, the high-k gate dielectric layer 120 contacts the gate 140 and the dipole layer 130. After the planarization process, the thickness of the gate 140 in contact with the high-k gate dielectric layer 120 is greater than the thickness of the gate 140 in contact with the dipole layer 130. In some other embodiments, the conductive material is not planarized after deposition. Therefore, the gate 140 can have a uniform thickness over the dipole layer 130 and the high-k gate dielectric layer 120.

[0032] Referring to Figure 7, the gate dielectric layer 110, high-k gate dielectric layer 120, dipole layer 130, and gate 140 are patterned to expose a portion of the substrate 100. Subsequently, the gate dielectric layer 110, high-k gate dielectric layer 120, dipole layer 130, and gate 140 are used as masks to form a source region 102 and a drain region 104 in the substrate 100. The source region 102 and drain region 104 are located on opposite sides of the gate dielectric layer 110. The source region 102 and drain region 104 are doped regions with a conductor type different from that of the substrate 100. For NMOS, the source region 102 and drain region 104 are N-type doped regions, and for PMOS, they are P-type doped regions. After forming the source region 102 and the drain region 104, a dielectric layer 150 and a contact 160 are formed on the substrate 100. The dielectric layer 150 separates the gate 140 from the contact 160. One sidewall S1 of the dipole layer 130 contacts the dielectric layer 150, and the other sidewall S2 of the dipole layer 130 contacts the gate 140.

[0033] The resulting semiconductor device is shown in Figure 7. The semiconductor device includes a substrate 100, a gate dielectric layer 110, a dipole layer 130, a gate 140, a source region 102, a drain region 104, a dielectric layer 150, and contacts 160. The gate dielectric layer 110 is located above the substrate 100. The dipole layer 130 is located above the gate dielectric layer 110, wherein the width W1 of the dipole layer 130 is smaller than the width W2 of the gate dielectric layer 110. The gate 140 is located above the dipole layer 130 and the gate dielectric layer 110. The dielectric layer 150 is located above the source region 102 and the drain region 104. Contacts 160 are located in the dielectric layer 150, and each contact 160 is located above either the source region 102 or the drain region 104. The source region 102 and the drain region 104 are located on opposite sides of the gate dielectric layer 110. If the semiconductor device is a PMOS, a voltage VDD (the highest voltage in the circuit) is applied to the source region 102, and the voltages applied to the gate 140 and drain region 104 are both less than the voltage applied to the source region 102 (i.e., VGS < 0 and VDS < 0). If the semiconductor device is an NMOS, a ground voltage is applied to the source region 102, and the voltages applied to the gate 140 and drain region 104 are both greater than the voltage applied to the source region 102 (i.e., VGS > 0 and VDS > 0).

[0034] The semiconductor device has an asymmetric structure because the dipole layer 130 is located closer to the source region 102 than to the drain region 104. Specifically, the sidewall of the dipole layer 130 near the source region 102 is aligned with the sidewall of the gate dielectric layer 110 near the source region 102, while the sidewall of the dipole layer 130 near the drain region 104 is laterally offset from the sidewall of the gate dielectric layer 110 near the drain region 104. The thickness of the gate 140 near the source region 102 is less than the thickness of the gate 140 near the drain region 104. The dipole layer 130 is used to reduce the threshold voltage of the semiconductor device to increase the reverse charge density. The reverse charge density is the charge density of the reverse layer in the substrate 100 below the gate 140, and increasing the reverse charge density increases the saturation current of the semiconductor device. The reduction of the threshold voltage of the semiconductor device can be achieved by the exchange of oxygen atoms between the gate dielectric layer 110 and the dipole layer 130 near the source region 102. If the dipole layer 130 near the source region 102 has the following oxygen concentration, the thickness of the inversion layer increases, resulting in an increase in the saturation current of the semiconductor device. In some embodiments, when the dipole layer 130 is near the source region 102, for NMOS, the oxygen concentration of the dipole layer 130 is lower than the oxygen concentration of the gate dielectric layer 110, and for PMOS, the oxygen concentration of the dipole layer 130 is higher than the oxygen concentration of the gate dielectric layer 110. Since the dipole layer 130 near the drain region 104 is removed, oxygen atom exchange does not occur near the drain region 104, thereby suppressing the cutoff state current.

[0035] The semiconductor device further includes a high-k gate dielectric layer 120 located between a gate dielectric layer 110 and a dipole layer 130, wherein the dielectric constant of the high-k gate dielectric layer 120 is higher than that of the gate dielectric layer 110. The high-k gate dielectric layer 120 contacts a gate 140. The width W1 of the dipole layer 130 is smaller than the width W2 of the high-k gate dielectric layer 120. The sidewall of the dipole layer 130 near the source region 102 is aligned with the sidewall of the high-k gate dielectric layer 120 near the source region 102. The sidewall of the dipole layer 130 near the drain region 104 is laterally offset from the sidewall of the high-k gate dielectric layer 120 near the drain region 104. The gate 140 near the drain region 104 contacts the high-k gate dielectric layer 120 near the drain region 104.

[0036] Figure 8 illustrates a semiconductor device in some other embodiments of this disclosure. The semiconductor device in Figure 8 is similar to that in Figure 7, except that the dipole layer 130 in Figure 8 is closer to the drain region 104 than to the source region 102. The sidewall of the dipole layer 130 near the drain region 104 is aligned with the sidewall of the gate dielectric layer 110 near the drain region 104. The sidewall of the dipole layer 130 near the source region 102 is laterally offset from the sidewall of the gate dielectric layer 110 near the source region 102. The gate 140 near the source region 102 contacts the high-k gate dielectric layer 120 near the source region 102. The thickness of the gate 140 near the drain region 104 is less than the thickness of the gate 140 near the source region 102. The dipole layer 130 is used to increase the threshold voltage of the semiconductor device to reduce the reverse charge density. The threshold voltage of the semiconductor device can be increased by oxygen atom exchange between the gate dielectric layer 110 and the dipole layer 130 near the drain region 104. If the dipole layer 130 near the drain region 104 has the following oxygen concentration, the thickness of the inversion layer will decrease, resulting in a decrease in the saturation current of the semiconductor device. In some embodiments, when the dipole layer 130 is near the drain region 104, for NMOS, the oxygen concentration of the dipole layer 130 is higher than that of the gate dielectric layer 110, and for PMOS, the oxygen concentration of the dipole layer 130 is lower than that of the gate dielectric layer 110. Since the dipole layer 130 near the source region 102 is removed, no oxygen atom exchange occurs near the source region 102, thereby maintaining the on-state current. Therefore, the switching ratio of the semiconductor device is also enhanced.

[0037] Figure 9 illustrates a semiconductor device in some other embodiments of this disclosure. The semiconductor device in Figure 9 is similar to that in Figure 7, except that a high-k gate dielectric layer 120 is not provided in the semiconductor device in Figure 9. The dipole layer 130 contacts the gate dielectric layer 110, and the gate 140 near the drain region 104 also contacts the gate dielectric layer 110.

[0038] Figure 10 illustrates a semiconductor device in some other embodiments of this disclosure. The semiconductor device in Figure 10 is similar to that in Figure 8, except that a high-k gate dielectric layer 120 is not provided in the semiconductor device in Figure 10. The dipole layer 130 contacts the gate dielectric layer 110, and the gate 140 near the source region 102 also contacts the gate dielectric layer 110.

[0039] As described above, some embodiments of the semiconductor device disclosed herein include a dipole layer for simultaneously adjusting a threshold voltage and suppressing the off-state current of the semiconductor device. The width of the dipole layer is smaller than the width of the gate dielectric layer, and the position of the dipole layer can adjust the threshold voltage of the semiconductor device. For example, if the dipole layer is close to the source region, it can be used to lower the threshold voltage, and if the dipole layer is close to the drain region, it can be used to increase the threshold voltage. The other side of the dipole layer is removed to suppress the off-state current or maintain the on-state current. Therefore, the switching ratio of the semiconductor device can be improved.

[0040] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the description of the embodiments contained herein.

[0041] Those skilled in the art will understand that various modifications and changes can be made to the structure of this disclosure without departing from its scope or spirit. In summary, this disclosure is intended to cover modifications and changes to this disclosure, provided such modifications and changes fall within the scope of the invention application.

[0042] 100:Substrate 102: Source Region 104: Drainage Zone 110: Gate dielectric layer 120: High-k gate dielectric layer 130: Dipole layer 140: Gate 150: Dielectric layer 160: Contact S1, S2: Sidewalls W1, W2: Width

[0043] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a substrate; a gate dielectric layer located above the substrate; a dipole layer located above the gate dielectric layer, wherein the dipole layer is an oxide layer and a width of the dipole layer is smaller than a width of the gate dielectric layer; a gate located above the dipole layer and the gate dielectric layer; a source region located in the substrate; and a drain region located in the substrate, wherein the source region and the drain region are located on opposite sides of the gate dielectric layer, and a sidewall of the dipole layer near the source region is aligned with a sidewall of the gate dielectric layer near the source region.

2. The semiconductor device as claimed in claim 1, wherein the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the gate dielectric layer near the drain region.

3. The semiconductor device as claimed in claim 1, further comprising: a high-k gate dielectric layer located between the gate dielectric layer and the dipole layer, wherein a dielectric constant of the high-k gate dielectric layer is higher than a dielectric constant of the gate dielectric layer.

4. The semiconductor device as claimed in claim 3, wherein the high-k gate dielectric layer is aligned with the gate.

5. The semiconductor device as claimed in claim 3, wherein the width of the dipole layer is smaller than the width of the high-k gate dielectric layer.

6. The semiconductor device as claimed in claim 3, wherein the sidewall of the dipole layer near the source region is aligned with the sidewall of the high-k gate dielectric layer near the source region.

7. The semiconductor device as claimed in claim 3, wherein the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the high-k gate dielectric layer near the drain region.

8. A semiconductor device comprising: a substrate; a gate dielectric layer located above the substrate; a dipole layer located above the gate dielectric layer, wherein the dipole layer is an oxide layer and a width of the dipole layer is smaller than a width of the gate dielectric layer; a gate located above the dipole layer and the gate dielectric layer; a source region located in the substrate; and a drain region located in the substrate, wherein the source region and the drain region are located on opposite sides of the gate dielectric layer, and a sidewall of the dipole layer near the drain region is aligned with a sidewall of the gate dielectric layer near the drain region.

9. The semiconductor device as claimed in claim 8, wherein the sidewall of the dipole layer near the source region is laterally offset from the sidewall of the gate dielectric layer near the source region.

10. A method of manufacturing a semiconductor device, comprising: forming a gate dielectric layer over a substrate; forming a dipole layer over the gate dielectric layer, wherein the dipole layer covers a portion of the gate dielectric layer; forming a gate over the dipole layer and the gate dielectric layer; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are located on opposite sides of a gate dielectric layer, and a sidewall of the dipole layer near the source region is aligned with a sidewall of the gate dielectric layer near the source region.

11. The method as described in claim 10, wherein after the source region and the drain region are formed, the sidewall of the dipole layer near the drain region is laterally offset from the sidewall of the gate dielectric layer near the drain region.

12. The method as described in claim 10, wherein after the source region and the drain region are formed, the gate near the drain region contacts the gate dielectric layer near the drain region.

13. The method as described in claim 10, wherein the thickness of the gate near the source region is less than the thickness of the gate near the drain region.

14. The method of claim 10 further comprises: forming a high-k gate dielectric layer over the gate dielectric layer prior to forming the dipole layer, wherein after forming the dipole layer, the dipole layer exposes a portion of the high-k gate dielectric layer.

15. The method as described in claim 14, wherein after the source region and the drain region are formed, the gate near the drain region contacts the high-k gate dielectric layer near the drain region.

16. The method as described in claim 14, wherein after the source region and the drain region are formed, the sidewall of the dipole layer near the source region is aligned with the sidewall of the high-k gate dielectric layer near the source region.

17. A method of manufacturing a semiconductor device, comprising: forming a gate dielectric layer over a substrate; forming a dipole layer over the gate dielectric layer, wherein the dipole layer covers a portion of the gate dielectric layer; forming a gate over the dipole layer and the gate dielectric layer; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are located on opposite sides of a gate dielectric layer, and after forming the source region and the drain region, a sidewall of the dipole layer near the drain region is aligned with a sidewall of the gate dielectric layer near the drain region.

18. The method as described in claim 17, wherein after the source region and the drain region are formed, the sidewall of the dipole layer near the source region is laterally offset from the sidewall of the gate dielectric layer near the source region.

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