Systems and methods for improving efficiency in a power converter using cascode power stages

Abstract

A circuit. In one embodiment, the circuit includes: a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal; and a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal.

Description

Technical Field

[0001] The described embodiments generally relate to power converters, and more specifically, the embodiments of the present invention relate to systems and methods for improving the efficiency of power converters using cascaded power stages. Prior Technology

[0002] Today's consumers have access to a wide variety of electronic devices. Many of these devices have integrated circuits powered by regulated low-voltage DC power supplies. These low-voltage power supplies are often generated by dedicated power converter circuits that use a higher voltage input from a battery or another power source. In some applications, the dedicated power converter circuit can be one of the most power-dissipating components of an electronic device, and sometimes it can consume more space than the integrated circuits it powers. As electronic devices become more complex and compact, there is a need for more efficient power converter circuits. Summary of the Invention

[0003] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes: a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal; a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal; an input terminal coupled to a first terminal of an impedance element; an output terminal coupled to a second terminal of the impedance element and the first drain terminal and the third drain terminal; and a control circuit configured to couple the first gate terminal to a DC bias voltage during a first state and to couple the first gate terminal to the first source terminal during a second state.

[0004] In some embodiments, the first power stage and the second power stage control the power transfer from the input terminal to the output terminal.

[0005] In some embodiments, the first state is a full load condition, wherein the first power stage and the second power stage transfer power from the input terminal to the output terminal.

[0006] In some embodiments, the second state is a light load condition, wherein the second power stage transfers power from the input terminal to the output terminal.

[0007] In some embodiments, the control circuitry is configured to connect the second gate terminal to the second source terminal during the second state.

[0008] In some embodiments, the first power stage and the second power stage are configured to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

[0009] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes: providing a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal; providing a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal; providing an input terminal coupled to a first terminal of an impedance element; providing an output terminal coupled to a second terminal of the impedance element and the first drain terminal and the third drain terminal; and using control circuitry to couple the first gate terminal to a DC bias voltage during a first state and to the first source terminal during a second state.

[0010] In some embodiments, the method further includes using a first power stage and a second power stage to control power transfer from the input terminal to the output terminal.

[0011] In some embodiments, the first state is a full load condition, wherein the first power stage and the second power stage transfer power from the input terminal to the output terminal.

[0012] In some embodiments, the second state is a light load condition, wherein the second power stage transfers power from the input terminal to the output terminal.

[0013] In some embodiments, the method further includes using control circuitry to connect the second gate terminal to the second source terminal during the second state.

[0014] In some embodiments, the method further includes using a first power stage and a second power stage to generate an output voltage at the output terminal that is lower than the voltage at the input terminal.

[0015] In some embodiments, a circuit is disclosed. The circuit includes: a first power stage including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal; a second power stage including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal; an input terminal coupled to a first terminal of a transistor; an output terminal coupled to a second terminal of a transistor and the first drain terminal and the third drain terminal; and a control circuit configured to couple the first gate terminal to a DC bias voltage during a first state and to couple the first gate terminal to the first source terminal during a second state.

[0016] In some embodiments, the fourth gate terminal is configured to receive a pulse width modulation (PWM) signal.

[0017] In some embodiments, in response to receiving a PWM signal, a fourth switch is configured to control the transfer of power from the input terminal to the output terminal in a second state. Simple Explanation of the Diagram

[0018] Figure 1 illustrates a DC-DC power converter circuit using a cascaded power stage according to one embodiment of this disclosure; and

[0019] Figure 2 illustrates the equivalent circuit for a segment of the circuit in Figure 1, showing the parasitic capacitance during light-load operation according to certain embodiments. Implementation

[0020] Cross-reference to related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 292,359, filed December 21, 2021, entitled "Systems and Methods for Improving Efficiency in a Power Converter Using Cascode Power Stages," which is incorporated herein by reference in its entirety for all purposes.

[0021] The circuits and related techniques disclosed herein are generally related to power converters. More specifically, the circuits, apparatuses, and related techniques disclosed herein relate to systems and methods for improving the efficiency of power converters using cascaded power stages. In some embodiments, a power converter, such as a DC-DC converter, may include cascaded switches, wherein each switch may be formed of multiple segments, and a portion of one segment may be deactivated (or unloaded) to improve the efficiency of the power converter across the load current range. In various embodiments, the disclosed methods enable the use of offloading techniques in power converters having cascaded power stages. In some embodiments, methods for offloading portions of a switch segment can reduce the maximum voltage applied to the switch, thereby keeping the switch within its safe operating area (SOA) and improving reliability. The various inventive embodiments described herein include methods, processes, systems, apparatuses, and the like.

[0022] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form a part of this invention. The following description is merely illustrative and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the subsequent description of the embodiments will provide illustrative descriptions for implementing one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the function and configuration of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments may be practiced without such specific details. The drawings and descriptions are not intended to be limiting. The terms “example” or “illustrative” are used herein to mean “serving as an example, illustration, or description.” No embodiment or design described herein as “illustrative” or “example” should be construed as superior or more advantageous than other embodiments or designs.

[0023] Figure 1 illustrates a DC-DC power converter circuit 100 using cascaded power stages according to one embodiment of the present disclosure. As shown in Figure 1, the DC-DC power converter circuit 100 may include a first segment power stage 102 and a second segment power stage 104 coupled in parallel. In various embodiments, the circuit 100 may include three or more parallel segments coupled in parallel. The first segment power stage 102 may be coupled to the second segment power stage 104 at node 143 and at node 141, respectively. Each of the first segment 102 and the second segment 104 may respectively include a top switch 105 and a top switch 115, and a bottom switch 110 and a bottom switch 120. The top switch 105 may have a gate terminal 190, a drain terminal 191, and a source terminal 193. The top switch 115 may have a gate terminal 171, a drain terminal 173, and a source terminal 177. Bottom switch 110 may have a gate terminal 111, a drain terminal 117, and a source terminal 119. Bottom switch 120 has a gate terminal 163, a drain terminal 167, and a source terminal 169.

[0024] Top switch 105 can be cascaded to bottom switch 110. Top switch 115 can be cascaded to bottom switch 120. In some embodiments, top switches 105 and 115 may be identical in size and other electrical characteristics, and bottom switches 110 and 120 may be identical in size and other electrical characteristics. In various embodiments, the top and bottom switches may have different sizes and different electrical characteristics. Power converter circuit 100 may include input terminal 135 and output terminal 145. Input terminal 135 may be configured to have a power supply Vdd. In some embodiments, output terminal 145 may be coupled to an inductor. Node 143 may be coupled to power supply Vdd via impedance element 130. In some embodiments, node 143 may be coupled to power supply Vdd via a switch such as, but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET). In various embodiments, impedance element 130 may be a resistor. Node 141 may be coupled to ground 140. Circuit 100 may provide an output voltage (Vout) at output terminal 145. Circuit 100 may further include a first control circuit 106 coupled to the top switch 105 and a second control circuit 108 coupled to the bottom switch 110. In some embodiments, the first control circuit 106 and the second control circuit 108 may be integrated to form a single control circuit. Switch 185 may be coupled to gate terminal 190. Switch 185 may be controlled by the signal High_Load 122 and may be configured to connect gate terminal 190 to node 170 or node 189. Node 170 may have a DC bias voltage. Node 189 may be coupled to node 125 connected to source terminal 193.

[0025] During full-load operation, the power converter circuit 100 can use both the first power stage 102 and the second power stage 104 to generate power at the output terminal 145. Full-load operation can also be referred to as high-load operation. During light-load operation, the power converter circuit 100 can offload (or deactivate) one of the first power stage 102 and the second power stage 104 to improve efficiency. This is because during light-load operation, most power loss is attributed to switching losses of switches 105, 110, 115, and 120. When a segment is offloaded during light-load operation, switching losses are reduced, thereby improving the efficiency of the power converter 100. In the first power stage 102, the top switch 105 and the bottom switch 110 can be cascaded. In this way, the top switch 105 and the bottom switch 110 can be coupled in series, allowing each switch to support a portion of the power supply voltage across its drain terminal to source terminal. The sum of the voltages across the drain and source terminals can exceed the voltage that any single switch can withstand; that is, the sum of the voltages across the drain and source terminals can be outside the safe operating area (SOA) of each switch. Extended operation outside the SOA can lead to reliability issues and switch damage. Similarly, in the second power stage 104, the top switch 115 and the bottom switch 120 are configured in a cascade configuration, such that each switch supports a portion of the power supply voltage across its drain and source terminals.

[0026] Switch 185 can be controlled by a High_Load signal 122. The High_Load signal 122 can be high when the power converter operates under high load and low when the power converter operates under light load. Under high load operation, gate terminal 190 can be connected to node 170 and has a DC bias voltage. Gate terminal 171 can be connected to node 170 and has a DC bias voltage. Therefore, both gate terminals of the top switch can be connected to a DC bias voltage. The gate of the bottom switch 110 can be connected to the output node of the AND gate 150, wherein the first input node 155 of the AND gate 150 can be configured to receive a switching signal 118, and the second input node 160 of the AND gate 150 can be configured to receive the High_Load signal 122. In some embodiments, the switching signal 118 can be a pulse width modulation (PWM) signal.

[0027] During high load conditions, signal High_Load 122 can be high. Therefore, AND gate 150 can transmit switching signal 118 to gate terminal 111. Thus, bottom switch 110 can switch during high load conditions. Gate terminal 163 can also be coupled to terminal 165 configured to receive switching signal 118, thereby bottom switch 120 can also switch during high load conditions. Therefore, both bottom switches 110 and 120 can switch during high load conditions. In this way, the effective on-resistance (Rdson) of the bottom switches can be minimized because bottom switches 110 and 120 are configured in parallel. Furthermore, the maximum voltage across each power level segment can be divided between its top and bottom switches, meaning that each of switches 105 / 110 and 115 / 120 will not experience voltages exceeding its rated safe operating area (SOA).

[0028] During light-load operation, the first power stage segment 102 can be unloaded (disabled) to improve the efficiency of the power converter. During light-load operation, the High_Load signal 122 is low, so the switching signal 118 cannot pass through the AND gate 150. With the High_Load signal 122 low, switch 185 can disconnect gate terminal 190 from node 170 and connect gate terminal 190 to node 125 coupled to source terminal 193. Therefore, the first power stage segment 102 can be disabled, while segment 104 can continue to operate. By connecting gate terminal 190 to node 125, gate terminal 190 is connected to a high-impedance node. The voltage Vx at node 125 can be determined by the relative values ​​of the drain-source leakage currents of the top switch 105 and the bottom switch 110. For example, if the drain-to-source leakage current of the top switch 105 is greater than the drain-to-source leakage current of the bottom switch 110, the voltage at node 125 can increase towards the power supply Vdd. When the voltage at node 125 increases, it causes the drain-to-source voltage of the top switch 105 to decrease, which in turn causes a decrease in the drain-to-source leakage current of the top switch 105. Simultaneously, the increase in the drain-to-source voltage of the bottom switch 110 causes an increase in the leakage current of the bottom switch 110. Therefore, the voltage (Vx) at node 125 decreases and moves towards the midpoint through this feedback loop until equilibrium is reached. In this way, the equilibrium voltage (Vx) at node 125 can be below the gate-to-drain breakdown voltages of both the top switch 105 and the bottom switch 110.

[0029] During light load conditions, top switch 105 can be disconnected because its gate terminal is connected to its source. Figure 2 illustrates the equivalent circuit for the first power stage segment 102, showing the parasitic capacitance during light load conditions. As can be seen in Figure 2, during light load conditions, gate terminal 190 can be coupled to node 125, and gate terminal 111 of bottom switch 110 can be connected to its source at ground 140. Since there is no channel forming in top switch 105, the drain-to-gate parasitic capacitance 159 of top switch 105 can be relatively small. In this way, the parasitic capacitance at output terminal 145 can be minimized, thereby improving the efficiency of power converter circuit 100. This is because the parasitic capacitance at output terminal 145 can have a significant effect on the efficiency of power converter circuit 100, as output terminal 145 is charged and discharged as Vout oscillates from track to track. The parasitic capacitance at output terminal 145 locks Vout as it oscillates from rail to rail, charging and discharging. The energy stored in this parasitic capacitance at output terminal 145 is dissipated as heat, directly affecting efficiency. Furthermore, the output voltage Vout at output terminal 145 can repeatedly oscillate from Vdd to ground, and the switch is implemented as a MOSFET device. As Vout moves to ground, node Vx can be clamped to the ground voltage -Vdiode (Vdiode is the voltage across the parasitic diode between the drain and the substrate of the MOSFET), where the substrate is connected to the source. The value of Vdiode can be, for example, 0.7 V. Therefore, the drain-to-gate parasitic capacitance across top switch 105 maintains the voltage Vdiode. As Vout oscillates to Vdd, Vx can move towards the equilibrium point, and the voltage across the gate-to-source capacitance of top switch 105 becomes Vdd-Vx. Therefore, in each switching cycle, the voltage change across the gate-to-source capacitance of top switch 105 is Vdd-Vx-Vdiode.

[0030] As discussed above, in some embodiments, during light load conditions, the gate terminal of the top switch 105 is connected to its source. This prevents channel formation in the top switch 105 and allows the parasitic capacitance of the top switch 105 to be relatively small, thereby improving the efficiency of the power converter 100. Furthermore, the drain-to-source parasitic capacitance 157 of the bottom switch 110 is connected in series with the drain-to-gate parasitic capacitance 159 of the top switch 105, resulting in a smaller overall parasitic capacitance for the combined parasitic capacitance of the top switch 105 and the bottom switch 110. In this way, the parasitic capacitance at the output terminal 145 is minimized.

[0031] Embodiments of this disclosure can also reduce power supply leakage current, thereby improving the efficiency of the power converter. For example, when the bottom switch 110 is open, the leakage current of the power converter can be limited to the maximum leakage current that may occur through the combination of the top switch 105 and the bottom switch 110. In some embodiments, the top switch 105 may be implemented to have a relatively small size, thereby allowing a relatively low leakage current to flow through the top switch 105, thus limiting the leakage current that can flow from the power supply Vdd to ground 140.

[0032] As will be understood by those skilled in the art who benefit from this disclosure, the gate of the top switch 105 may be connected to its source by, for example, a switching element such as a MOSFET, a resistor, a diode, or a diode-connected MOSFET, or other active circuitry such as an amplifier or a follower circuit. In various embodiments, a DC bias voltage may be generated such that it is higher than ground voltage, but not so high that the top switch 105 can be turned on under any circumstances, nor so low that it exceeds the gate-to-drain breakdown voltage of the top switch 105.

[0033] Although the primary application of the disclosed technology has been shown herein as for power stages, the technology is applicable to any cascade device that will disconnect with minimal leakage or in a manner that minimizes parasitic capacitance at the drain node of its switch. Furthermore, different sized switches can be used dynamically to vary the gain of the power stage, the switching speed of the power stage, or to allow for low-current standby modes.

[0034] In some embodiments, the described switch may be formed of silicon or any other semiconductor material. In various embodiments, the described switch may be a transistor. In some embodiments, the described switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the MOSFET may not be formed entirely within a single die. In some embodiments, the disclosed power converter may be monolithically integrated onto a single die. In various embodiments, the top switch and bottom switch may be formed on separate individual dies. In some embodiments, the top switch and bottom switch, along with logic and control circuitry and any combination thereof, may be grouped and formed on separate dies. In various embodiments, the top switch and bottom switch, along with logic and control circuitry, may all be integrated into a single electronic package, such as, but not limited to, a quad-flat no-lead (QFN) package, a dual-flat no-lead (DFN) package, or a ball grid array (BGA) package.

[0035] Although this document describes and illustrates systems and methods for improving the efficiency of power converters using cascaded power stages with respect to a particular configuration of a DC-DC power converter circuit, the embodiments disclosed herein are suitable for use with other configurations of power converters. For example, multiphase DC-DC power converter circuits may employ embodiments of this disclosure to offload (disable) sections of the power stage for more efficient operation.

[0036] In the foregoing specification, embodiments of this disclosure have been described with reference to numerous specific details that may vary between implementations. Therefore, the specification and drawings should be viewed in an illustrative rather than limiting sense. The sole and exclusive indication of the scope of this disclosure, and the content that the applicant intends to define as the scope of this disclosure, is the literal and equivalent scope of the set of such claims published from this application in the specific form of the claims, including any subsequent corrections. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0037] Additionally, spatially relative terms such as "bottom" or "top" and similar terms may be used to describe the relationship of one element and / or feature to another element(s) and / or feature(s), as illustrated in, for example, the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device during use and / or operation. For example, if the device in the figures is flipped, the element described as the "bottom" surface may then be oriented "above" other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0038] As used herein, the terms "and," "or," and "one / or" may have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Typically, "or," when used to relate a list such as A, B, or C, is intended to mean A, B, and C (used herein in an inclusive sense), and A, B, or C (used herein in an exclusive sense). Additionally, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in the singular, or to describe a combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and the subject matter claimed is not limited to this example. Furthermore, the term "at least one of" when used to relate a list such as A, B, or C may be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0039] Throughout this specification, references to "one example," "example," "some examples," or "illustrative implementation" mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases "in one example," "example," "in some examples," "in some implementations," or other similar phrases appearing throughout this specification do not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0040] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those skilled in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, but rather may encompass all forms falling within the scope of the appended claims and their equivalents.

[0041] 100: Power converter circuit 102: First section power stage 104: Second Section Power Stage 105: Top switch 106: First control circuit 108: Second control circuit 110: Bottom switch 111: Gate terminal 115: Top switch 117:Drain terminal 118: Switching Signal 119: Source terminal 120: Bottom switch 122:High_Load / signal 125: Node 130: Impedance element 135: Input terminal 140: Grounding 141: Node 143: Node 145: Output terminal 150: AND gate 155: First input node 157: Drain-to-source parasitic capacitance 159: Drain-to-gate parasitic capacitance 160: Second input node 163: Gate terminal 165:Terminal 167:Drain terminal 169: Source terminal 170: Node 171: Gate terminal 173:Drain terminal 177: Source terminal 185: Switch 189: Node 190: Gate terminal 191:Drain terminal 193: Source terminal Vdd: power supply Vout: Output voltage Vx: Voltage

Claims

1. A power converter circuit, comprising: A first power stage including a first switch coupled to a second switch, wherein the first switch has a first gate terminal, a first drain terminal and a first source terminal, and the second switch has a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is directly coupled to the second drain terminal without any other intermediate element between the first source terminal and the second drain terminal; a second power stage including a third switch coupled to a fourth switch, the second power stage being coupled in parallel to the first power stage; an input terminal coupled to the first power stage and the second power stage; an output terminal coupled to the first power stage and the second power stage; and a control circuit coupled to the first power stage and the second power stage and configured to cause the first power stage and the second power stage to generate an output voltage at the output terminal that is lower than a voltage at the input terminal.

2. The power converter circuit of claim 1, wherein the control circuit is further configured to cause the first power stage and the second power stage to control the power transfer from the input terminal to the output terminal.

3. The power converter circuit of claim 1, wherein the third switch includes a third gate terminal, a third drain terminal and a third source terminal, and the fourth switch includes a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the third source terminal is coupled to the fourth drain terminal.

4. The power converter circuit of claim 3, wherein the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal.

5. The power converter circuit of claim 4, wherein the control circuit is configured to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

6. The power converter circuit of claim 5, wherein the first state is a full load condition and the second state is a light load condition.

7. The power converter circuit of claim 6, wherein the control circuit is configured to connect the second gate terminal to the second source terminal during the second state.

8. A method of operating a power converter circuit, the method comprising: providing a first power stage, the first power stage including a first switch coupled to a second switch, wherein the first switch has a first gate terminal, a first drain terminal and a first source terminal, and the second switch has a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is directly coupled to the second drain terminal without any other intermediate element between the first source terminal and the second drain terminal; providing a second power stage, the second power stage including a third switch coupled to a fourth switch, the second power stage being coupled in parallel to the first power stage; providing an input terminal coupled to the first power stage and the second power stage; providing an output terminal coupled to the first power stage and the second power stage; providing a control circuit coupled to the first power stage and the second power stage; and by means of the control circuit causing the first power stage and the second power stage to generate an output voltage at the output terminal that is lower than a voltage at the input terminal.

9. The method of claim 8, further comprising causing the first power stage and the second power stage to control the power transfer from the input terminal to the output terminal by means of the control circuit.

10. The method of claim 8, wherein the third switch comprises a third gate terminal, a third drain terminal and a third source terminal, and the fourth switch comprises a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the third source terminal is coupled to the fourth drain terminal.

11. The method of claim 10, wherein the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal.

12. The method of claim 11, further comprising using the control circuit to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

13. A power converter circuit, comprising: A first power stage comprising a first switch coupled to a second switch, wherein the first switch has a first gate terminal, a first drain terminal, and a first source terminal, and the second switch has a second gate terminal, a second drain terminal, and a second source terminal, wherein the first source terminal is directly coupled to the second drain terminal without any other intermediate element between the first source terminal and the second drain terminal; a second power stage comprising a third switch coupled to a fourth switch, the second power stage being coupled in parallel to the first power stage; an input terminal coupled to the first power stage and the second power stage; an output terminal coupled to the first power stage and the second power stage; and a control circuit coupled to the first power stage and the second power stage and configured to cause the first power stage and the second power stage to control power transfer from the input terminal to the output terminal.

14. The power converter circuit of claim 13, wherein the control circuit is further configured to cause the first power stage and the second power stage to generate an output voltage at the output terminal that is lower than a voltage at the input terminal.

15. The power converter circuit of claim 13, wherein the third switch includes a third gate terminal, a third drain terminal and a third source terminal, and the fourth switch includes a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the third source terminal is coupled to the fourth drain terminal.

16. The power converter circuit of claim 15, wherein the second power stage is coupled in parallel to the first power stage such that the first drain terminal is coupled to the third drain terminal and the second source terminal is connected to the fourth source terminal.

17. The power converter circuit of claim 16, wherein the control circuit is configured to couple the first gate terminal to a DC bias during a first state and to the first source terminal during a second state.

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