Package structure and manufacturing method thereof

Abstract

A packaging structure includes a substrate, an intermediate module, and a chip module. The intermediate module is disposed on the substrate. The intermediate module includes a first insulating layer, a second insulating layer, and a plurality of dummy terminals. The first insulating layer is disposed between the second insulating layer and the substrate. The plurality of dummy terminals directly contact the first insulating layer and the substrate and are electrically insulated therefrom. The chip module is disposed on the intermediate module and is electrically connected to the substrate through the intermediate module. A method for manufacturing the packaging structure is also provided.

Description

Technical Field

[0001] This invention relates to a packaging structure and its manufacturing method. Prior Technology

[0002] With the advancement of technology, the market demands for electronic products are increasing. For example, ensuring that the packaging structure has good quality has become a current research topic. Summary of the Invention

[0003] This invention provides a packaging structure and its manufacturing method, which effectively improves the yield and thus ensures good quality.

[0004] A packaging structure of the present invention includes a substrate, an intermediate module, and a chip module. The intermediate module is disposed on the substrate. The intermediate module includes a first insulating layer, a second insulating layer, and a plurality of dummy terminals. The first insulating layer is disposed between the second insulating layer and the substrate. The plurality of dummy terminals directly contact the first insulating layer and the substrate and are electrically insulated therefrom. The chip module is disposed on the intermediate module and is electrically connected to the substrate through the intermediate module.

[0005] A method for manufacturing a packaging structure according to the present invention includes at least: providing a substrate; providing an intermediate module including a plurality of dummy terminals; disposing the intermediate module on the substrate through the plurality of dummy terminals; providing a wafer module; and disposing the wafer module on the intermediate module, wherein the intermediate module is a single-chip type, and the wafer module is electrically connected to the substrate through the intermediate module.

[0006] In one embodiment of the present invention, after the above-mentioned wafer module is disposed on the intermediate module, the molding process and the cutting process are not performed.

[0007] In one embodiment of the present invention, the above-described manufacturing method further includes: bonding an intermediate module and a substrate through a plurality of first conductive terminals; bonding a wafer module and an intermediate module through a plurality of second conductive terminals; and covering the plurality of first conductive terminals and the plurality of second conductive terminals respectively with a first protective member and a second protective member.

[0008] In one embodiment of the present invention, the first protective member and the second protective member are formed by performing an adhesive dispensing process or a film lamination process, respectively.

[0009] In one embodiment of the present invention, the first protective member and the second protective member are formed in different processes.

[0010] In one embodiment of the present invention, the steps of forming the above-mentioned intermediate module include: providing a first insulating layer; disposing a plurality of bridging chips on the first insulating layer; forming a second insulating layer to encapsulate the plurality of bridging chips; forming a plurality of dummy terminals on the first insulating layer; and performing a chip-cutting process.

[0011] In one embodiment of the present invention, the above-described manufacturing method further includes: forming a plurality of conductive terminals to surround a plurality of dummy terminals.

[0012] Based on the above, since the number of process steps that the chip module goes through can be reduced, the risk of defect rate in the process can be reduced. At the same time, by using the design of dummy terminals, stress in the process can be distributed. Accordingly, the yield of the packaging structure of the present invention is effectively improved, thereby ensuring its good quality.

[0013] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0014] Figures 1A to 1G are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to an embodiment of the present invention. Figures 2, 3, 4, 5, 6, 7, and 8 are partial cross-sectional schematic diagrams of the packaging structure according to some embodiments of the present invention. Implementation

[0015] The directional terms used in this article (e.g., up, down, right, left, front, back, top, bottom) are used for reference only and are not intended to imply absolute orientation.

[0016] Unless otherwise expressly stated, no method described herein is intended to be construed as requiring its steps to be performed in a particular order.

[0017] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or size of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be described again in the following paragraphs.

[0018] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part.

[0019] Unless otherwise stated, the term "between" used in this specification to define numerical ranges is intended to cover the range equal to and between the endpoint values. For example, a size range between a first value and a second value means that the size range can cover the first value, the second value, and any value between the first value and the second value.

[0020] Figures 1A to 1G are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to an embodiment of the present invention. Referring to Figures 1A to 1E, the manufacturing process of the intermediate module 110 may include the following steps. First, a carrier 10 is provided. In some embodiments, the carrier 10 is, for example, a plate made of glass, wafer, metal or other suitable support material, so that the carrier 10 can be used to carry films or components formed thereon.

[0021] In this embodiment, a release layer 11 may optionally be formed on the carrier plate 10 to improve the releaseability of the structure (such as an intermediate structure in the process) and the carrier plate 10 in subsequent processes. For example, the release layer 11 may be a light-to-heat-conversion (LTHC) release layer or other suitable release layer, and the present invention is not limited thereto.

[0022] Next, a layered structure 111 is formed on the carrier substrate 10. In this embodiment, the layered structure 111 is a single-layer structure. For example, the layered structure 111 can be an insulating layer deposited from polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or similar materials. However, the invention is not limited to this. In embodiments not shown, the layered structure 111 can be a suitable redistribution layer (RDL) structure, wherein the top and bottom insulating layers of the RDL structure are insulating layers deposited from polyimide, polybenzoxazole, benzocyclobutene, or similar materials. The top insulating layer is, for example, the film layer furthest from the carrier substrate 10 in the RDL structure, and the bottom insulating layer is, for example, the film layer closest to the carrier substrate 10 in the RDL structure. Furthermore, multiple openings 111a can be formed in the layered structure 111 by a suitable method (such as an etching process). Here, the layered structure 111 is, for example, the first insulating layer.

[0023] Then, as shown in FIG1A, a plurality of bridging chips 112 are disposed on the carrier board 10. In this embodiment, the bridging chip 112 has an active surface AS and a back surface BS opposite to the active surface AS, and the bridging chip 112 is disposed on the layered structure 111 with the active surface AS facing upward. For example, the back surface BS of the bridging chip 112 is disposed on the layered structure 111 by an adhesive layer 12. Furthermore, when the layered structure 111 is a single-layer structure, the adhesive layer 12 can directly contact the top surface of the layered structure 111, and when the layered structure 111 is a multi-layer redistribution structure, the adhesive layer 12 can directly contact the topmost insulating layer of the layered structure 111.

[0024] In one embodiment, the adhesive layer 12 may be a die attach film (DAF). However, the invention is not limited thereto, and in other embodiments, the bridging wafer 112 may be configured on the carrier 10 in other ways. Furthermore, the bridging wafer 112 may be any suitable wafer type.

[0025] After configuring multiple bridging chips 112, a package 113 is formed to encapsulate the multiple bridging chips 112 (e.g., in direct contact with the silicon substrate of the bridging chips 112). In one embodiment, the package 113 may be formed by the following steps. First, a packaging material is formed to cover the conductive bumps 112a of the bridging chips 112, wherein the conductive bumps 112a may be disposed on pads 112b and surrounded by an insulating layer 112c. Next, the packaging material is planarized to form the package 113, so that the top surface of the package 113 may be substantially coplanar with the top surface of the conductive bumps 112a, but the invention is not limited thereto. Here, the package 113 may be, for example, a second insulating layer. Furthermore, the package 113 may be formed by a liquid molding compound or a granule-type solid molding compound through a molding process.

[0026] In Figure 1A, a plurality of conductive connectors 114 may also be formed on the carrier 10, wherein the plurality of conductive connectors 114 may correspond to the plurality of openings 111a of the layered structure 111 and surround the bridging wafer 112, wherein the plurality of conductive connectors 114 and the plurality of openings 111a are arranged, for example, in a one-to-one manner. Furthermore, the top surfaces of the conductive connectors 114, the top surfaces of the package 113, and the top surfaces of the conductive bumps 112a may be substantially coplanar, but the present invention is not limited thereto.

[0027] In some embodiments, the conductive connector 114 may be made of copper, aluminum, nickel, or a combination thereof, and may be a conductive post formed, for example, by lithography, plating, or photoresist stripping. However, the invention is not limited thereto, and the conductive connector 114 may be formed of other suitable materials and forming methods depending on the actual design requirements.

[0028] In one embodiment, the conductive connector 114 is formed before the plurality of bridging wafers 112 are disposed and the package 113 is formed. In another embodiment, the conductive connector 114 is formed after the plurality of bridging wafers 112 are disposed and before the package 113 is formed. In yet another embodiment, the conductive connector 114 is formed after the plurality of bridging wafers 112 are disposed and the package 113 is formed.

[0029] Referring again to Figure 1A, a circuit layer 115 (e.g., in direct contact with the package 113 and conductive connector 114) is formed on the carrier 10, wherein the package 113 is disposed between the circuit layer 115 and the layered structure 111. In this embodiment, the circuit layer 115 can be a multilayer structure. For example, the circuit layer 115 may include multiple dielectric layers 115a stacked on top of each other and multiple patterned conductive layers 115b, wherein the patterned conductive layers 115b can reconfigure the wires for signal transmission used in the package.

[0030] In some embodiments, the material of the dielectric layer 115a may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, benzocyclobutene, and may be formed, for example, by spin-on coating, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0031] In some embodiments, the material of the patterned conductive layer 115b may include copper, aluminum, nickel, gold, silver, tin, or a combination thereof, and may be formed, for example, by sputtering, vapor deposition, electroless plating, or electroplating. However, the invention is not limited thereto, and the dielectric layer 115a and the patterned conductive layer 115b may be formed by other suitable materials and forming methods according to actual design requirements.

[0032] Referring to Figure 1B, after forming the circuit layer 115, another carrier 20 and another release layer 21 are bonded to the circuit layer 115, wherein optionally a portion of the circuit layer 115 can be embedded in the release layer 21. Next, the carrier 10 is removed through the release layer 11 to expose the bottom surface 111b of the layered structure 111 and the bottom surface 114b of the conductive connector 114, wherein the carrier 20 and the release layer 21 are similar to the carrier 10 and the release layer 11, and will not be described again here. Here, exposure to a UV laser can be used to peel the release layer 11 and the carrier 10 away from the layered structure 111 and the conductive connector 114.

[0033] Referring to Figure 1C, flip the structure shown in Figure 1B vertically so that multiple bridging chips 112, packages 113, and conductive connectors 114 are displayed as disposed on / above the circuit layer 115. Then, multiple connection terminals 116 are formed on the bottom surface 114b of the conductive connectors 114 and the bottom surface 111b of the layered structure 111.

[0034] Furthermore, the connection terminal 116 may include a plurality of conductive terminals 116a and a plurality of dummy terminals 116b, wherein the conductive terminals 116a may directly contact and be electrically connected to the conductive connector 114, while the dummy terminals 116b may directly contact and be electrically insulated from the layered structure 111. Here, the dummy terminal 116b can be a dummy bump. By designing these dummy terminals 116b, in embodiments where terminals are manufactured using an electroplating process, the terminals on the entire plane to be electroplated can be distributed more evenly, resulting in a more uniform electroplating current distribution. Consequently, the height of the terminals formed will also be more uniform, thus achieving good terminal co-planarity. Alternatively, the design of these dummy terminals 116b can disperse stress, preventing stress caused by thermal expansion coefficient (CTE) mismatch from acting entirely on the functional conductive terminal 116a in cases of temperature differences during subsequent component operation and / or reliability testing. This effectively improves product lifespan and performance, while also enhancing product performance during reliability testing.

[0035] For example, the dummy terminal 116b can disperse the stress generated during the electroplating process to form the conductive terminal 116a, and can also reduce the probability of the conductive terminal 116a breaking due to the mismatch of the coefficient of thermal expansion (CTE) between the conductive terminal 116a and the substrate 120. However, the present invention is not limited to this, and the dummy terminal 116b can also be used to disperse the stress generated in other processes.

[0036] In some embodiments, the dummy terminal 116b directly contacts the layered structure 111. For example, when the layered structure 111 is a single-layer structure, the dummy terminal 116b can directly contact the bottom surface of the layered structure 111 (relative to the top surface of FIG. 1A), while when the layered structure 111 is a multi-layer rewiring structure, the dummy terminal 116b can directly contact the bottom insulating layer of the layered structure 111 (relative to the top insulating layer of FIG. 1A). In other words, when the layered structure 111 is a single-layer structure, the adhesive layer 12 and the dummy terminal 116b directly contact the opposite surfaces of the layered structure 111, respectively. When the layered structure 111 is a multi-layer rewiring structure, the adhesive layer 12 and the dummy terminal 116b directly contact the insulating layers (top insulating layer and bottom insulating layer) on opposite sides of the multi-layer rewiring structure, respectively.

[0037] Referring to Figure 1D, after the connection terminal 116 is formed, the carrier 20 is removed through the release layer 21 to expose the other surface of the circuit layer 115 opposite to the surface on which the bridging wafer 112 is disposed. Here, exposure to a UV laser can be used to peel the release layer 21 and the carrier 20 off the circuit layer 115.

[0038] Referring to Figure 1E, a singulation process is then performed to obtain multiple intermediate modules 110 (single-segment type), wherein the singulation process can be performed by a rotating blade or a laser beam. After performing the singulation process and before bonding to the substrate 120, inspection and testing steps can be performed on the singled intermediate modules 110 to reduce the probability that poor quality will adversely affect the subsequently bonded wafer modules 130, but the present invention is not limited thereto.

[0039] Referring to FIG1F, a substrate 120 is provided, and an intermediate module 110 (single-chip type) is disposed on the substrate 120. Next, a chip module 130 is disposed on the intermediate module 110, such that the chip module 130 is electrically connected to the substrate 120 through the intermediate module 110. In this embodiment, the chip module 130 is, for example, composed of multiple individual chiplets (FIG. 1F schematically illustrates three chips 131). Here, the three chips 131 may have the same or different functions depending on the actual design requirements; this invention is not limited thereto. For example, the chip 131 may be a logic chip, a memory chip, or a combination thereof.

[0040] In this embodiment, a plurality of external terminals 121 are further formed on the surface of the substrate 120 relative to the intermediate module 110 (such as the bottom surface) to connect with other components in subsequent processes (such as electrical connection or dummy connection).

[0041] In Figure 1F, the intermediate module 110 and the substrate 120 can be connected via multiple conductive terminals 116a and dummy terminals 116b, and the wafer module 130 and the intermediate module 110 can be connected via multiple conductive terminals 130a. The wafer module 130 is electrically connected to the substrate 120 via conductive terminals 130a, the circuit layer 115 in the intermediate module 110, the conductive connector 114 in the intermediate module 110, and the conductive terminals 116a. Here, the conductive terminal 116a is, for example, a first conductive terminal, and the conductive terminal 130a is, for example, a second conductive terminal.

[0042] It should be noted that both the conductive terminal 116a and the dummy terminal 116b are in direct contact with the top metal layer of the substrate 120 to achieve the effect of stress dispersion. The portion of the top metal layer to which the conductive terminal 116a is connected is a functional pad, which allows it to be electrically connected to the functional external terminal 121 below. The portion of the top metal layer to which the dummy terminal 116b is connected is a dummy pad, which prevents it from being electrically connected to the functional external terminal 121 below (electrically insulated), or allows it to be coupled to the dummy external terminal 121 below. That is, the external terminal 121 may include functional components and dummy components, but the present invention is not limited thereto.

[0043] In one embodiment, before bonding the intermediate module 110, an inspection and testing step may be performed on the substrate 120 to reduce the probability that its poor quality will adversely affect the subsequent bonding of the chip module 130 thereon, but the invention is not limited thereto.

[0044] In one embodiment, there is a gap between adjacent wafers 131 in the wafer module 130 and signal transmission can be performed by bridging wafers 112, but the present invention is not limited thereto.

[0045] In some embodiments, substrate 120 may be an ABF substrate or the like. However, it should be noted that the number of dielectric layers and conductive circuit design (such as vias) of substrate 120 in FIG1F are only schematic illustrations. The present invention does not limit the type of substrate 120. As long as substrate 120 can provide the signal transmission function required in the product, it falls within the protection scope of the present invention.

[0046] Referring to Figure 1G, the connecting terminal 116 (including conductive terminal 116a and dummy terminal 116b) is covered by a protective element 151A, and the conductive terminal 130a is covered by a protective element 152A. The protective element 151A can directly contact the top surface 120t of the substrate 120, and the protective element 152A can be separated from the substrate 120 by the intermediate module 110.

[0047] After the above-described process, the fabrication of the packaging structure PKG1 in this embodiment is largely complete. Since the chip module 130 is not initially placed on the wafer-level intermediary module 110, and most of the processes in the packaging structure PKG1 are completed during its placement, the number of process steps traversed by the chip module 130 can be reduced, lowering its yield loss risk during the process. Furthermore, based on the design of the dummy terminal 116a, stress during the process can be distributed. Therefore, the yield of the packaging structure PKG1 in this embodiment is effectively improved, thereby ensuring its good quality. Here, the wafer-level intermediary module 110 is, for example, the uncut intermediary module 110 shown in FIG. 1D.

[0048] Furthermore, when placing wafers on large-scale interposers at the wafer level without wafer dicing, warpage or surface unevenness is likely to occur. On the other hand, the conductive terminals on the wafer may not be effectively aligned with the underlying interposer, resulting in higher process risk and more difficult yield control. However, with the process step design shown in Figures 1A to 1G, the fine-pitch wafer bonding process can be limited to a smaller area (the size of the interposer module 110 in the wafer dicing type), thus providing a wider process tolerance / margin and reducing the probability of the aforementioned problems occurring.

[0049] In one embodiment, the dummy terminal 116b corresponds to the bridging chip 112 in the stacking direction D of the substrate 120, the intermediate module 110 and the chip module 130. For example, the orthographic projection of the dummy terminal 116b on the substrate 120 overlaps with the orthographic projection of the bridging chip 112 on the substrate 120, but the present invention is not limited thereto.

[0050] Furthermore, as shown in Figure 1G, the materials of protective element 151A and protective element 152A are different, and protective elements 151A and 152A are formed in different processes. For example, the material of protective element 151A is selected from capillary underfill material (CUF), while the material of protective element 152A is selected from non-conductive film (NCF). For example, in Figure 1G, since the capillary underfill material is formed by performing a dispensing process, it fills the gap between the connecting terminals 116 by means of the fluidity of the adhesive and capillary phenomenon, and also overflows upward to form on the sidewall of the intermediate module 110. Therefore, protective element 151A has a trapezoidal profile. On the other hand, since the non-conductive film is formed by performing a film lamination process, before the wafer module 130 is bonded to the intermediate module 110, the conductive terminals 130a on the wafer 131 are first attached to the sheet-like dry film material, and then the flip-chip bonding of the wafer 131 is performed by heat and pressure. At the same time, the conductive terminals 130a are protected by the protective member 151A. Therefore, the flip-chip bonding method when using the non-conductive film is thermal compression bond (TCB). The protective member 152A can form an arc-shaped edge caused by the compression of the dry film material, and in this way, it will not cover the sidewall of the wafer 131 (e.g., the upper half). That is, based on the selection of different materials, the protective member 151A and the protective member 152A can have different shapes, but the present invention is not limited to this.

[0051] In one embodiment, the capillary bottom filler material and the non-conductive film can each have their advantages under different circumstances. For example, when the wafers 131 have a high aspect ratio, such as large wafer size and / or small spacing (e.g., 50 micrometers to 150 micrometers) between wafers 131, the capillary bottom filler material is likely to cover the sidewalls between wafers 131 and have a large contact area with the substrate material (e.g., silicon) in the wafers 131. As a result, poor adhesion, trapped voids, and / or insufficient strength of the capillary bottom filler material itself may occur between the capillary bottom filler material and the substrate material, which may lead to adverse effects such as delamination and cracking during reliability testing, reducing product reliability. In this case, the non-conductive film has its advantages because it can avoid the aforementioned risks. On the other hand, since it is difficult for non-conductive films to cover higher conductive terminals, when the height of the conductive terminal 130a after the bonding of the wafer 131 is high (e.g., greater than 40 micrometers), the capillary bottom filling material has its advantages. Therefore, the present invention does not limit the material of the protective component, which can be determined according to the actual design requirements.

[0052] In this embodiment, the use of a non-conductive film between the wafer 131 and the intermediate module 110 can reduce the size of the intermediate module 110. However, the present invention is not limited to this. In other embodiments, when the non-conductive film is used between the intermediate module 110 and the substrate 120, the size of the substrate 120 can be reduced.

[0053] In this embodiment, after the chip module 130 is placed on the intermediate module 110, the molding process and the dicing process are not performed, and the side surface 130s and top surface 130t of the chip 131 in the chip module 130 can be completely exposed, which can significantly improve heat dissipation. In addition, since no molding material is formed subsequently, the gap between the chips 131 in the chip module 130 can be effectively reduced (e.g., less than or equal to 50 micrometers), thereby making the package structure PKG1 more advantageous in miniaturization, but the present invention is not limited to this.

[0054] In one embodiment, the chip module 130 is composed of multiple individual chips 131. Since the cost of chips 131 is relatively high, a probe card test can be performed on the chips 131 before they are placed on the intermediate module 110 to select known good dies (KGD). This avoids the situation where damage to some chips 131 in the chip module 130 causes other chips 131 to malfunction. However, the invention is not limited to this. Here, a known good die can be a semiconductor chip that has been tested, inspected, and passed in terms of functionality and reliability, and is known to achieve all designed properties and operating states after a power supply potential is applied.

[0055] In some embodiments, the conductive bump 112a, the connecting terminal 116, and the conductive terminal 130a may each comprise a conductive post, a conductive plug solder ball, or a combination thereof, made of materials such as copper or the like. The solder balls may be formed by a ball placement process and / or a reflow process, but the invention is not limited thereto. In some alternative embodiments, the conductive bump 112a, the connecting terminal 116, and the conductive terminal 130a may use other possible forms or shapes based on design requirements, and may have the same or different appearances from each other.

[0056] In some embodiments, the encapsulation 113 may be formed of an insulating material such as epoxy resin or other suitable resins, and for example, a molding compound formed by a molding process. However, the invention is not limited thereto, and the encapsulation 113 may be formed of other suitable materials and methods.

[0057] It must be noted that the following embodiments use the component references and some contents of the above embodiments, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiments. The following embodiments will not repeat the description.

[0058] Figures 2, 3, 4, 5, 6, 7, and 8 are partial cross-sectional schematic diagrams of the packaging structure according to some embodiments of the present invention.

[0059] Referring to Figure 2, in this embodiment, the packaging structure PKG2 is similar to the packaging structure PKG1, except that: the protective element 151B is selected from a non-conductive film, while the protective element 152B is selected from a capillary underfill material. Therefore, the protective element 151B has an arc-shaped edge, while the protective element 152B has a trapezoidal contour. Furthermore, in this embodiment, the flip-chip bonding method when using capillary underfill material can be to first place the wafer 131 in the positioning position, then bond it through reflow, and then form the capillary underfill material through a dispensing process. That is, the protective element 152B can be formed after the wafer module 130 is bonded to the intermediate module 110.

[0060] Referring to Figure 3, in this embodiment, the packaging structure PKG3 is similar to the packaging structure PKG2, except that a protective element 152B selected from the capillary bottom filling material is used to simultaneously cover the connecting terminal 116 and the conductive terminal 130a (formed in the same process). In this embodiment, the protective element 152B covers the connecting terminal 116 (including the conductive terminal 116a and the dummy terminal 116b) and the conductive terminal 130a, so that the connecting terminal 116 (including the conductive terminal 116a and the dummy terminal 116b) and the conductive terminal 130a are recessed within the protective element 152B. In this way, the connecting terminal 116 (including the conductive terminal 116a and the dummy terminal 116b) and the conductive terminal 130a can be protected simultaneously, thus significantly reducing material costs. However, the present invention is not limited to this.

[0061] Referring to Figure 4, in this embodiment, the packaging structure PKG4 is similar to the packaging structures PKG1 and PKG2, except that: a protective element 151A selected from the capillary bottom filling material is used to cover the connecting terminal 116, and a protective element 152B selected from the capillary bottom filling material is used to cover the conductive terminal 130a.

[0062] Referring to Figure 5, in this embodiment, the encapsulation structure PKG5 is similar to the encapsulation structures PKG1 and PKG2, except that: a protective element 151B selected from a non-conductive film is used to cover the connecting terminal 116, and a protective element 152A selected from a non-conductive film is used to cover the conductive terminal 130a.

[0063] Referring to Figure 6, in this embodiment, the packaging structure PKG6 is similar to the packaging structure PKG1, except that: since no molding and planarization processes are performed, the multiple chips 131 in the chip module 130 can have different heights. In addition, in this embodiment, the heights of the multiple chips 131 can all be different, as shown in Figure 6, having a first height H1, a second height H2, and a third height H3 that decrease in sequence. However, the present invention is not limited to this. In embodiments not shown, the multiple chips 131 in the chip module 130 may only have partially different heights. For example, two of the three chips 131 have the same height and are different from the other.

[0064] Referring to Figure 7, in this embodiment, the packaging structure PKG7 is similar to the packaging structure PKG1, except that the packaging structure PKG7 further includes a cover 160, wherein the cover 160 at least covers the back side of the chip module 130 relative to the active surface. Therefore, the cover 160 can protect the electronic components in the packaging structure PKG7, and it can also serve as a heat sink to provide additional heat dissipation. In one embodiment, the cover 160 forms multiple cavities in the packaging structure PKG7.

[0065] Furthermore, in this embodiment, when the height difference between the plurality of wafers 131 of the wafer module 130 is large, the cover 160 has a stepped shape in cross-section, wherein the plurality of wafers 131 and the cover 160 can be bonded together by thermal interface (TIM) material 170 of substantially the same thickness, but the present invention is not limited thereto.

[0066] Referring to Figure 8, in this embodiment, the packaging structure PKG8 is similar to the packaging structure PKG7, except that: the cover 160 and each of the plurality of wafers 131 in the wafer module 130 have a different thickness of thermal interface material 170, which is applied to cases where the height difference between the plurality of wafers 131 in the wafer module 130 is low (e.g., less than 100 micrometers).

[0067] In this embodiment, the thicknesses of the multiple thermal interface materials 170 may all be different, as shown in FIG8, having a first thickness T1, a second thickness T2 and a third thickness T3 that increase sequentially. However, the present invention is not limited thereto. In embodiments not shown, the multiple thermal interface materials 170 may only have partially different thicknesses. For example, two of the three thermal interface materials 170 may have the same thickness and be different from the other.

[0068] In the above embodiment, a backside metal (BSM) (not shown) can be further deposited on the backside 130t of the wafer module 130. The backside metal can be pre-deposited on the backside 130t before the wafer module 130 is installed to further improve heat dissipation capabilities, but the present invention is not limited thereto. Here, the material of the backside metal can be any suitable metal material with excellent heat dissipation efficiency, and the present invention is not limited thereto.

[0069] In embodiments not shown, the package structure further includes a metal ring, which may be located on the top surface of the substrate and surround the chip module. Therefore, the metal ring can protect the electronic components in the package structure and can also provide additional support as a reinforcement, but the invention is not limited thereto.

[0070] In summary, by reducing the number of process steps the chip module passes through, the risk of defect rate during the process is reduced. At the same time, the design of dummy terminals can disperse stress during the process. Accordingly, the yield of the packaging structure of the present invention is effectively improved, thereby ensuring its good quality.

[0071] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0072] 10, 20: Carrier board 11, 21: Release layer 12: Adhesive layer 110: Intermediary Module 111: Layered structure 111a: Opening 111b, 114b: Bottom surface 112: Bridge chip 112a: Conductive bump 112b: Connector 112c: Insulation layer 113: Package 114: Conductive connectors 115: Line Layer 115a: Dielectric layer 115b: Patterned conductive layer 116: Connecting terminal 116a, 130a: Conductive terminals 116b: Dummy Terminal 120:Substrate 120t, 130t: Top surface 121: External terminal 130: Chip Module 130s: Side surface 131: Chip 151A, 151B, 152A, 152B: Protective components 160: Capping 170: Thermal interface materials A: Area AS: Active Face BS: Back D: Stacking direction H1, H2, H3: Height T1, T2, T3: Thickness PKG1, PKG2, PKG3, PKG4, PKG5, PKG6, PKG7, PKG8: Package Structure

Claims

1. A packaging structure, comprising: substrate; An intermediate module is disposed on the substrate, wherein: the intermediate module includes a first insulating layer, a second insulating layer, and a plurality of dummy terminals; The first insulating layer is disposed between the second insulating layer and the substrate; and the plurality of dummy terminals directly contact the first insulating layer and the substrate; a wafer module is disposed on the intermediate module and electrically connected to the substrate through the intermediate module; a plurality of external terminals, including a plurality of functional components, wherein the substrate is disposed between the plurality of dummy terminals and the plurality of external terminals, and the plurality of dummy terminals are electrically insulated from the plurality of functional components; and a plurality of conductive terminals, wherein the plurality of conductive terminals are disposed between the intermediate module and the substrate and surround the plurality of dummy terminals.

2. The packaging structure as claimed in claim 1, wherein the intermediate module further includes a plurality of bridging chips, the plurality of bridging chips being disposed on the first insulating layer via an adhesive layer, the second insulating layer encapsulating the plurality of bridging chips, and the plurality of dummy terminals corresponding to the plurality of bridging chips in the stacking direction of the substrate, the intermediate module and the chip module.

3. The packaging structure as claimed in claim 2, wherein the orthographic projection of the plurality of dummy terminals on the substrate overlaps with the orthographic projection of the plurality of bridging chips on the substrate.

4. The packaging structure as described in claim 2, wherein the adhesive layer and the plurality of dummy terminals respectively directly contact the surfaces opposite to the first insulating layer.

5. The packaging structure as claimed in claim 2, wherein the intermediate module includes a multilayer rewiring structure, the first insulating layer is the bottom insulating layer of the multilayer rewiring structure, and the adhesive layer directly contacts the top insulating layer of the multilayer rewiring structure relative to the first insulating layer.

6. The packaging structure as claimed in claim 1, wherein the plurality of dummy terminals are in direct contact with dummy pads on the top of the substrate.

7. The packaging structure as claimed in claim 1, wherein the plurality of external terminals further includes a plurality of dummy components, wherein the plurality of dummy terminals are coupled to the plurality of dummy components.

8. The packaging structure as claimed in claim 1 further includes a cap disposed on the substrate, wherein the cap has a thermal interface material between itself and each of the plurality of wafers in the wafer module.

9. The packaging structure as described in claim 8, wherein the plurality of wafers in the wafer module have different heights.

10. The packaging structure as claimed in claim 9, wherein the cap and each of the plurality of wafers in the wafer module have a thermal interface material of different thicknesses.

11. A method for manufacturing a packaging structure, comprising: Provide substrate; An intermediate module and a plurality of conductive terminals are provided, wherein the plurality of conductive terminals are disposed between the intermediate module and a substrate, the intermediate module being a single-chip type, the intermediate module including a plurality of dummy terminals; the intermediate module is disposed on the substrate through the plurality of dummy terminals and the plurality of conductive terminals, wherein the plurality of dummy terminals and the plurality of conductive terminals directly contact the substrate, and the plurality of conductive terminals surround the plurality of dummy terminals; a wafer module is provided; the wafer module is disposed on the intermediate module, wherein the wafer module is electrically connected to the substrate through the intermediate module; and a plurality of external terminals are formed on the surface of the substrate relative to the intermediate module, wherein the plurality of external terminals include a plurality of functional components, and the plurality of dummy terminals are electrically insulated from the plurality of functional components.

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