Programmable logic block comprising flash memory array to store configuration data for programmable logic

Abstract

In one embodiment, a system includes a programmable logic block, the programmable logic block including programmable logic, and a configuration block for storing configuration data and providing the configuration data to the programmable logic, the configuration block including a flash memory array for storing the configuration data, and the flash memory array including a discrete gate flash memory cell array.

Description

Technical Field

[0001] [Priority Claim] This application claims priority to U.S. Provisional Patent Application No. 63 / 613,008, filed December 20, 2023, entitled "Programmable Logic Block Comprising Flash Memory Array to Configure Programmable Logic", and U.S. Patent Application No. 18 / 435,943, filed February 7, 2024, entitled "Programmable Logic Block Comprising Flash Memory Array to Configure Programmable Logic".

[0002] Numerous embodiments disclose a programmable logic block including a flash memory array for configuring programmable logic. Prior Technology

[0003] Prior art includes non-volatile memory. For example, U.S. Patent 5,029,130 ​​(“130 Patent”), incorporated herein by reference, discloses a discrete-gate non-volatile memory cell array, which is a type of flash memory cell. This memory cell 110 is shown in FIG1. ​​Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source and drain regions. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has: a first portion disposed over and insulated from (and controlling the conductivity of) a second portion of the channel region 18; and a second portion extending upward and over the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. The bit line 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel through the FN from the floating gate 20 through the intermediate insulator to the word line terminal 22.

[0005] The memory cell 110 is programmed by source-side injection (SSI) with hot electrons (where electrons are placed on the floating gate) and by applying a positive voltage to both the word line terminal 22 and the source region 14. Electron current flows from the drain region 16 towards the source region 14. When electrons reach the gap between the word line terminal 22 and the floating gate 20, they accelerate and become heated. Some of these heated electrons are injected through the gate oxide onto the floating gate 20 due to the electrostatic attraction from the floating gate 20.

[0006] Memory cell 110 is read by applying a positive read voltage to drain region 16 and word line terminal 22 (which connects the portion of channel region 18 below the word line terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also connected, and current flows across channel region 18; this is sensed as erased or a "1" state. If floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of channel region below floating gate 20 is mostly or completely turned off, and current does not flow across channel region 18 (or flows very little); this is sensed as programmed or a "0" state.

[0007] Table 1 illustrates the typical voltage and current ranges applicable to the terminals of memory cell 110 during read, erase, and programming operations: Table 1: Operation of Flash Memory Cell 110 in Figure 1 WL BL SL Read 2 to 3 V 0.6 to 2 V 0 V erase ~11 to 13 V 0 V 0 V Programming 1 to 2 V 10.5 to 3 µA 9 to 10 V

[0008] Other discrete-gate memory cell configurations for other types of flash memory cells are known. For example, Figure 2 illustrates a four-gate memory cell 210, which includes a floating gate 20 above a first portion of a source region 14, a drain region 16, a selected gate 22 above a second portion of a channel region 18 (typically coupled to a word line WL), a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning that these gates are electrically connected or can be connected to a voltage source. Programming is performed by injecting energized electrons from the channel region 18 onto the floating gate 20. Erasure is performed by tunneling electrons from the floating gate 20 to the erase gate 30.

[0009] Table 2 illustrates the typical voltage and current ranges applicable to the terminals of memory cell 210 during read, erase, and programming operations: Table 2: Operation of Flash Memory Cell 210 in Figure 2 WL / SG BL CG EG SL Read 1.0 to 2 V 0.6 to 2 V 0 to 2.6 V 0 to 2.6 V 0 V erase -0.5 V / 0 V 0 V 0 V / -8 V 8 to 12 V 0 V Programming 1 V 0.1 to 1 µA 8 to 11 V 4.5 to 9 V 4.5 to 5 V

[0010] Figure 3 illustrates a three-gate memory cell 310 of another type of split-gate flash memory cell. Memory cell 310 is identical to memory cell 210 in Figure 2, except that memory cell 310 does not have a separate control gate. The erase operation (where erasure occurs through the use of the erase gate) and read operation are similar to the erase and read operations in Figure 2, except that there is no applied control gate bias. Programming operations are also performed without a control gate bias, and therefore, a higher voltage is applied to the source line during a programming operation to compensate for the lack of a control gate bias.

[0011] Table 3 illustrates the typical voltage and current ranges applicable to the terminals of memory cell 310 during read, erase, and programming operations: Table 3: Operation of Flash Memory Cell 310 in Figure 3 WL / SG BL EG SL Read 0.7 to 2.2 V 0.6 to 2 V 0 to 2.6 V 0 V erase -0.5 V / 0 V 0 V 11.5 V 0 V Programming 1 V 0.2 to 3 µA 4.5 to 8 V 6 to 9V

[0012] Figure 4 illustrates another type of flash memory cell, stacked gate memory cell 410. Memory cell 410 is similar to memory cell 210 in Figure 1, except that: a floating gate 20 extends over the entire channel region 18 and a control gate 22 (which is coupled to a word line here) extends over the floating gate 20, which is separated from the control gate by an insulating layer. Erasure is performed by tunneling electrons from FG to FN on the substrate; programming is performed by channel hot electron (CHE) injection in the region between channel 18 and drain region 16, by allowing electrons to flow from source region 14 to drain region 16; and read operations are similar to read operations performed on memory cell 210 with a higher control gate voltage.

[0013] Table 4 illustrates the typical voltage range applicable to the terminals of memory cell 410 and substrate 12 during read, erase, and programming operations: Table 4: Operation of Flash Memory Cell 410 (Figure 4) CG BL SL substrate Read 2 to 5 V 0.6 to 2 V 0 V 0 V erase -8 to -10 V / 0 V FLT FLT 8 to 10 V / 15 to 20 V Programming 8 to 12 V 3 to 5 V 0 V 0 V

[0014] Prior art also includes programmable logic devices that, after configuration, can form a digital logic design. Programmable logic devices can be reconfigured multiple times to form different digital logic designs. An embodiment of a programmable logic device includes a programmable array logic (PAL), a programmable logic array (PLA), a complex programmable logic device (CPLD), and a field-programmable gate array (FPGA).

[0015] A programmable logic device is configured before operation, wherein configuration data is provided to the programmable logic device.

[0016] There is a need for improved methods and systems for utilizing flash memory arrays, which include discrete gate flash memory cells for storing configuration data and delivering the configuration data to a programmable logic device. Summary of the Invention

[0017] In the systems and methods described herein, a system includes one or more programmable logic blocks, which may be embedded on the same die. A programmable logic block includes a configuration block and programmable logic. The configuration block includes a flash memory device in which configuration data is stored and delivered from the flash memory device to the programmable logic during configuration operations. The configuration block may include configuration data logic near the flash memory device, wherein there is virtually no delay between the flash memory array and the configuration data logic, and wherein the configuration data logic delivers configuration data from the flash memory device to the programmable logic. Storing configuration data in a flash memory device is a flexible method of storing configuration data because, for example, the configuration data is robust to errors caused by solar radiation and resistant to single-event flip-flop (SEU) or single-event error (SEE) events. Simple Explanation of the Diagram

[0018] Figure 1 illustrates a prior art decoupled gate flash memory cell.

[0019] Figure 2 illustrates another prior art decoupled gate flash memory cell.

[0020] Figure 3 illustrates another prior art decoupled gate flash memory cell.

[0021] Figure 4 illustrates a prior art stacked gate flash memory cell.

[0022] Figure 5 illustrates a system including programmable logic blocks and circuits.

[0023] Figure 6A illustrates one embodiment of a programmable logic block.

[0024] Figure 6B illustrates another embodiment of a programmable logic block.

[0025] Figure 7A illustrates one embodiment of a programmable logic block.

[0026] Figure 7B illustrates another embodiment of a programmable logic block.

[0027] Figure 8A illustrates one embodiment of a programmable logic block.

[0028] Figure 8B illustrates another embodiment of a programmable logic block.

[0029] Figure 9 illustrates another embodiment of a programmable logic block.

[0030] Figure 10 illustrates another embodiment of a programmable logic block.

[0031] Figure 11A illustrates storing one of the configuration data bits with a first value in an adjacent memory cell.

[0032] Figure 11B illustrates storing one of the configuration data bits with a second value in an adjacent memory cell.

[0033] Figure 11C illustrates storing one of the configuration data bits with a first value in an adjacent memory cell.

[0034] Figure 11D illustrates storing one of the configuration data bits with a second value in an adjacent memory cell.

[0035] Figure 12A illustrates storing configuration data bits in adjacent memory cells of a first memory cell architecture.

[0036] Figure 12B illustrates storing configuration data bits in adjacent memory cells of a second memory cell architecture.

[0037] Figure 13 illustrates a single-position quasi-shifter.

[0038] Figure 14 illustrates a current mirror.

[0039] Figure 15 illustrates a current mirror. Implementation

[0040] Figure 5 illustrates system 500, which includes circuitry 501 and programmable logic blocks 502, 503, and 504. This embodiment illustrates three programmable logic blocks, but it should be understood that system 500 includes m programmable logic blocks, where m can range from 1 to any integer value. Programmable logic blocks 502, 503, 504, and any other programmable logic blocks may be the same as or different from one or more of the other programmable logic blocks. Circuitry 501 includes supporting circuitry for operating the m programmable logic blocks, such as routing circuitry, buffers, and other circuitry.

[0041] Figure 6A illustrates a programmable logic block 601, which is an embodiment of one of the m programmable logic blocks in Figure 5 (such as programmable logic blocks 502, 503, and 504). Programmable logic block 601 includes a configuration block 602 and programmable logic 603. Configuration block 602 includes a flash memory device 604, which includes a flash memory array 605 and circuitry for operating the flash memory array 605. Programmable logic 603 may include logic for performing a specific function. The flash memory array 605 is programmed to store configuration data used to configure programmable logic 603 to perform its specific function or multiple functions. The 605 series flash memory array is configured as a column and a row of flash memory cells (such as cells following the architecture of memory cells 110, 210, 310 and 410 in Figures 1, 2, 3 and 4 respectively).

[0042] Figure 6B illustrates a programmable logic block 651, which is an embodiment of one of the m programmable logic blocks (such as programmable logic blocks 502, 503, and 504) in Figure 5. Programmable logic block 651 is similar to programmable logic block 601 in Figure 6A, except that it also includes configuration data logic 656. Programmable logic block 651 includes configuration block 652 and programmable logic 653. Configuration block 652 includes a flash memory device 654, which includes a flash memory array 605 and circuitry for operating the flash memory array 655. The flash memory array 655 is an array of flash memory cells (such as cells following the architecture of memory cells 110, 210, 310, and 410 in Figures 1, 2, 3, and 4, respectively) configured in columns and rows. Programmable logic 653 may include logic for performing a specific function. Flash memory array 655 is programmed to store configuration data used to configure programmable logic 653 to perform its specific function or multiple functions. Configuration data logic 656 receives signals from flash memory device 654 and performs one or more of the following: such as boosting the signal by increasing or decreasing a voltage level of a "1" bit; boosting the signal by providing more functionality to the output, such as supplementary signals or other functional logic signals; and providing the boosted configuration data to programmable logic 653 to configure programmable logic 653.

[0043] Figure 7A illustrates a programmable logic block 701, which is an embodiment of programmable logic block 601 in Figure 6A. Programmable logic block 701 includes configuration blocks 702 and programmable logic 703, which are embodiments of configuration blocks 602 and programmable logic 603 in Figure 6A, respectively. Configuration block 702 includes a flash memory device 704 (an embodiment of flash memory device 604 in Figure 6A), which includes a flash memory array 706 and a row multiplexer 707. The row multiplexer 707 is used for programming or, possibly sensing, selecting bit lines of the flash memory array 706. Circuitry for programming or sensing is not shown. Sensing can be used to verify whether a cell is in a programmed or erased state.

[0044] Flash memory array 706 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 706 further includes word lines coupled to word line terminals of flash memory cells, control gate lines coupled to control gate terminals of flash memory cells, source lines coupled to source line terminals of flash memory cells, erase gate lines coupled to erase gate terminals of flash memory cells, and bit lines coupled to bit line terminals of flash memory cells. In this embodiment, the word lines, control gate lines, source lines, and erase gate lines are horizontal (i.e., configured in a first direction) and the bit lines are vertical (i.e., configured in a second direction perpendicular to the first direction).

[0045] During programming operations of cells in flash memory array 706, a row multiplexer 707 is used by providing a programming current IPROOG to the cell being programmed. The row multiplexer 707 also connects flash memory array 706 to a sense amplifier for use during read or verification operations. During configuration operations of programmable logic 703, configuration data is read from flash memory array 706 and provided to programmable logic 703 via the row multiplexer 707, which is controlled by a controller (not shown).

[0046] Figure 7B illustrates a programmable logic block 751, which is an embodiment of programmable logic block 651 in Figure 6B. Programmable logic block 751 includes configuration blocks 752 and programmable logic 753, which are embodiments of configuration blocks 652 and programmable logic 653 in Figure 6B, respectively. Configuration block 752 includes a flash memory device 754 (an embodiment of flash memory device 654 in Figure 6B), which includes a flash memory array 757, a row multiplexer 758 for all bit lines, and configuration data logic 755 (an embodiment of configuration data logic 656 in Figure 6B).

[0047] Flash memory array 757 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 757 further includes word lines coupled to word line terminals of flash memory cells, control gate lines coupled to control gate terminals of flash memory cells, source lines coupled to source line terminals of flash memory cells, erase gate lines coupled to erase gate terminals of flash memory cells, and bit lines coupled to bit line terminals of flash memory cells. In this embodiment, the word lines, control gate lines, source lines, and erase gate lines are horizontal (i.e., configured in a first direction) and the bit lines are vertical (i.e., configured in a second direction perpendicular to the first direction).

[0048] During programming operations of cells in flash memory array 757, row multiplexer 758 is used by providing a programming current IPROOG to the cell being programmed. Row multiplexer 758 also connects flash memory array 757 to a sense amplifier for use during read or verification operations.

[0049] During one configuration operation of programmable logic 753, a read signal (such as bit line current or voltage corresponding to bit line current) corresponding to the stored configuration data is obtained from flash memory array 757. The read signal is provided to configuration data logic 755. Configuration data logic 755 performs one or more of the following: such as enhancing the read signal by increasing or decreasing the voltage level of a "1" bit; and enhancing the signal by providing more functionality to the output, such as supplementary signals or other functional logic signals; and providing the enhanced configuration data to programmable logic 753. In one embodiment, configuration data logic 755 includes a level shifter 756 that receives the voltage output from flash memory array 757 and generates an output voltage at a different level than the received voltage for a "1" (e.g., from 0.7 V to 1.8 V) or, as appropriate, for a "0" (e.g., from 0.0 V to 0.5 V) depending on the programmed or erased state of the memory cell.

[0050] Figure 8A illustrates a programmable logic block 801, which is an embodiment of programmable logic block 601 in Figure 6A. Programmable logic block 801 includes configuration blocks 802 and programmable logic 803, which are embodiments of configuration blocks 602 and programmable logic 603 in Figure 6A, respectively. Configuration block 802 includes a flash memory device 804 (which is an embodiment of flash memory device 604 in Figure 6A), and flash memory device 804 includes a flash memory array 806 and a row multiplexer 807.

[0051] Flash memory array 806 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 806 further includes word lines coupled to word line terminals of the flash memory cells, control gate lines coupled to control gate terminals of the flash memory cells, source lines coupled to source line terminals of the flash memory cells, erase gate lines coupled to erase gate terminals of the flash memory cells, and bit lines coupled to bit line terminals of the flash memory cells. In this embodiment, the word lines, control gate lines, source lines, erase gate lines, and bit lines are arranged in a single direction (which appears vertical on this page).

[0052] During programming operations of cells in flash memory array 806, row multiplexer 807 is used by providing a programming current IPROOG to the cell being programmed. Row multiplexer 807 also connects flash memory array 806 to a sense amplifier for use during read or verify operations. During a configuration operation of programmable logic 803, configuration data is read from flash memory array 806 and provided to programmable logic 803.

[0053] Figure 8B illustrates a programmable logic block 851, which is an embodiment of programmable logic block 651 in Figure 6B. Programmable logic block 851 includes configuration blocks 852 and programmable logic 853, which are embodiments of configuration blocks 652 and programmable logic 653 in Figure 6B, respectively. Configuration block 852 includes a flash memory device 854 (an embodiment of flash memory device 654 in Figure 6B), which includes a flash memory array 857, a row multiplexer 858, and configuration data logic 855 (an embodiment of configuration data logic 656 in Figure 6B).

[0054] Flash memory array 857 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 857 further includes word lines coupled to word line terminals of the flash memory cells, control gate lines coupled to control gate terminals of the flash memory cells, source lines coupled to source line terminals of the flash memory cells, erase gate lines coupled to erase gate terminals of the flash memory cells, and bit lines coupled to bit line terminals of the flash memory cells. In this embodiment, the word lines, control gate lines, source lines, erase gate lines, and bit lines are arranged in a single direction (which appears vertical on this page).

[0055] During programming operations of cells in flash memory array 857, row multiplexer 858 is used by providing a programming current IPROOG to the cell being programmed. Row multiplexer 858 also connects flash memory array 857 to a sense amplifier for use during read or verification operations.

[0056] During one configuration operation of programmable logic 853, a read signal (such as bit line current or a voltage corresponding to the stored configuration data) is obtained from flash memory array 857. The read signal is provided to configuration data logic 855 by line multiplexer 858. Configuration data logic 855 performs one or more of the following: such as enhancing the read signal by increasing or decreasing the voltage level of a "1" bit; and enhancing the signal by providing more functionality to the output, such as supplementary signals or other functional logic signals; and providing the enhanced configuration data to programmable logic 853. In one embodiment, configuration data logic 855 includes a level shifter 856 that receives a voltage output from a sense amplifier (not shown) that has generated such a voltage in response to the read signal (such as bit line current) from flash memory array 857.

[0057] Figure 9 illustrates a programmable logic block 951, which is an embodiment of programmable logic block 651 in Figure 6B. Programmable logic block 951 includes configuration blocks 952 and programmable logic 953, which are embodiments of configuration blocks 652 and programmable logic 653 in Figure 6B, respectively. Configuration block 952 includes a flash memory device 954 (an embodiment of flash memory device 654 in Figure 6B), which includes a flash memory array 957 and, if applicable, a row multiplexer 958 and configuration data logic 955 (an embodiment of configuration data logic 656 in Figure 6B).

[0058] Flash memory array 957 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 957 further includes word lines coupled to word line terminals of flash memory cells, control gate lines coupled to control gate terminals of flash memory cells, source lines coupled to source line terminals of flash memory cells, erase gate lines coupled to erase gate terminals of flash memory cells, and bit lines coupled to bit line terminals of flash memory cells. In this embodiment, the word lines, source lines, and erase gate lines are horizontal (i.e., configured in a first direction), and the control gate lines and bit lines are vertical (i.e., configured in a second direction perpendicular to the first direction).

[0059] During programming operations of cells in the flash memory array 957, a row multiplexer 958 is used by providing a programming current IPROOG to the cell being programmed. The row multiplexer 958 also connects the flash memory array 957 to a sense amplifier for use during read or verification operations.

[0060] During configuration operation of programmable logic 953, a read signal (such as bit line current or voltage corresponding to the stored configuration data) corresponding to the flash memory array 957 is obtained. The read signal is provided to configuration data logic 955 by line multiplexer 958. Configuration data logic 955 performs one or more of the following: enhancing the read signal by increasing or decreasing the voltage level of a "1" bit; enhancing the signal by providing more functionality to the output, such as supplementary signals or other functional logic signals; and providing the enhanced configuration data to programmable logic 953. In one embodiment, configuration data logic 955 includes a level shifter 956 that receives a voltage output from a sense amplifier (not shown) that has generated such a voltage in response to the read signal (such as bit line current) from flash memory array 957.

[0061] Figure 10 illustrates a programmable logic block 1051, which is an embodiment of programmable logic block 651 in Figure 6B. Programmable logic block 1051 includes configuration blocks 1052 and programmable logic 1053, which are embodiments of configuration blocks 652 and programmable logic 653 in Figure 6B, respectively. Configuration block 1052 includes a flash memory device 1054 (an embodiment of flash memory device 654 in Figure 6B), which includes a flash memory array 1057 and, if applicable, a row multiplexer 1058 and configuration data logic 1055 (an embodiment of configuration data logic 656 in Figure 6B).

[0062] Flash memory array 1057 includes a plurality of flash memory cells configured in columns and rows. Flash memory array 1057 further includes word lines coupled to word line terminals of flash memory cells, control gate lines coupled to control gate terminals of flash memory cells, source lines coupled to source line terminals of flash memory cells, erase gate lines coupled to erase gate terminals of flash memory cells, and bit lines coupled to bit line terminals of flash memory cells. In this embodiment, the control gate lines, source lines, and erase gate lines are horizontal (i.e., configured in a first direction), and the word lines and bit lines are vertical (i.e., configured in a second direction perpendicular to the first direction).

[0063] During programming operations of cells in flash memory array 1057, row multiplexer 1058 is used by providing a programming current IPROOG to the cell being programmed. Row multiplexer 1058 also connects flash memory array 1057 to a sense amplifier for use during read or verification operations.

[0064] During one configuration operation of programmable logic 1053, a read signal (such as bit line current or a voltage corresponding to the stored configuration data) is obtained from flash memory array 1057. The read signal is provided to configuration data logic 1055 by line multiplexer 1058. Configuration data logic 1055 performs one or more of the following: enhancing the read signal by increasing or decreasing the voltage level of a "1" bit; enhancing the signal by providing more functionality to the output, such as supplementary signals or other functional logic signals; and providing the enhanced configuration data to programmable logic 1053. In one embodiment, configuration data logic 1055 includes level shifter 1056 that receives a voltage output from a sense amplifier (not shown) that has generated such a voltage in response to the read signal (such as bit line current) from flash memory array 1057.

[0065] Figures 11A and 11B illustrate configurable nonvolatile memory (NVM) bits 1100 configured to store either a "1" or a "0" using adjacent flash memory cells (a pair of cells) sharing a single bit line. Flash memory cells 1101 (a first memory cell) and 1102 (a second memory cell) are adjacent cells in flash memory devices 604, 654, 706, 757, 806, 857, 957, and 1057 in Figures 6A, 6B, 7A, 7B, 8A, 8B, 9, and 10, respectively. Flash memory cell 1101 includes a first erase gate (EG) terminal, a first source line (SL) terminal, a first control gate (CG) terminal, and a first word line (WL) terminal, respectively coupled to a first erase gate line, a first source line, a first control gate line, and a first word line. Flash memory cell 1102 includes a second erase gate (EG) terminal, a second source line (SL) terminal, a second control gate (CG) terminal, and a second word line (WL) terminal, respectively coupled to a second erase gate line, a second source line, a second control gate line, and a second word line. Flash memory cells 1101 and 1102 each have a bit line terminal connected to a common bit line at a common drain terminal of flash memory cells 1101 and 1102.

[0066] In Figure 11A, when flash memory cell 1101 is erased and flash memory cell 1102 is programmed, since memory cell 1101 is in a fully conducting state (high current state, erase state) and memory cell 1102 is in a non-conducting state (no current state, programmed state), the output on the bit line will be "1" during a read operation of one of the two cells. In Figure 11B, when flash memory cell 1101 is programmed and flash memory cell 1102 is erased, since memory cell 1102 is in a fully conducting state (high current state, erase state) and memory cell 1101 is in a non-conducting state (no current state, programmed state), the output on the bit line will be "0" during a read operation of one of the two cells. Because two memory cells (flash memory cells 1101 and 1102) are used to store a single data bit and are always on, the memory is resilient to errors that may be injected by external forces such as solar radiation. For example, if the bit value stored in flash memory cell 1101 or 1102 changes due to an external event, the output will still be valid due to the other flash memory cell. This means that BL will still have a relatively high current to correctly output a "1" or will still have a relatively high current to correctly output a "0". Moreover, because the memory cell is always on, the output state can recover from transient effects.

[0067] Figures 11C and 11D illustrate configurable nonvolatile memory (NVM) bits 1150 in which adjacent flash memory cells (a pair of cells) are used to store either a "1" or a "0", and these adjacent flash memory cells are jointly coupled to a bit line of a common drain terminal. The NVM bit 1150 is similar to the NVM bit 1100 in Figures 11A and 11B, wherein a sense amplifier 1151 is added to sense a signal on the common bit line (BL) to generate a digital output bit. Alternatively, the erase and programming states of flash memory cells 1101 and 1102 can be interchanged. This means that for output = 1, flash memory cell 1101 is programmed and flash memory cell 1102 is erased, and for output = 0, flash memory cell 1101 is erased and flash memory cell 1102 is programmed, wherein the sense amplifier 1151 is modified accordingly.

[0068] Figures 12A and 12B illustrate an embodiment of a nonvolatile memory bit formed by adjacent flash memory cells with different flash memory cell architectures.

[0069] In Figure 12A, the non-volatile memory cell 1200 is formed by adjacent flash memory cells 1201 and 1202 of the type of flash memory cell 310 in Figure 3. A sense amplifier 1251 is coupled to a common bit line. The sense amplifier is used to convert the output signal from the bit line into a low-impedance and potentially shifted voltage level, such as a full power supply level.

[0070] In Figure 12B, the non-volatile memory cell 1210 is formed by adjacent flash memory cells 1211 and 1212 of the type of flash memory cell 110 in Figure 1. Due to the difference in operating voltage used by the two types of flash memory cells, an output "1" will be 1 V in Figure 12A but 1.8 V in Figure 12B.

[0071] Figure 13 illustrates a level shifter 1300 that can be used in any of the level shifters 756, 856, 956, and 1056. Level shifter 1300 includes cross-coupled PMOS transistors 1301 and 1302, NMOS transistors 1303 and 1304, and an inverter 1305. Inverter 1305 receives the INPUT signal, which in this embodiment may be 0 V for a "0" or 0.7 V for a "1". Inverter 1305 inverts INPUT and outputs the inverted value INPUTTB as its output. Inverter 1305 receives VLSSUP as its supply voltage. In one embodiment of VLSSUP, the level is 0.7 V.

[0072] The gate of NMOS transistor 1303 receives INPUT, and the gate of NMOS transistor 1304 receives INPUTB. When INPUT is high, INPUTB will be low, and NMOS transistor 1303 will be turned on while NMOS transistor 1304 will be turned off, causing OUTB to be pulled to ground and become a "0", which is 0V here. PMOS transistor 1302 receives OUTB at its gate and will be turned on, causing OUT to be pulled high to the value of VSUP, which is 1.8V here. PMOS transistor 1301 receives OUT at its gate and will be turned off.

[0073] When INPUT is low, INPUTB will be high, and NMOS transistor 1303 will be off and NMOS transistor 1304 will be on, causing OUT to be pulled to ground and become a "0". PMOS transistor 1301 receives OUT at its gate and will be on, causing OUTB to be pulled high to the value of VSUP, which is 1.8 V in this case. PMOS transistor 1302 receives OUTB at its gate and will be off. Therefore, in this embodiment, level shifter 1300 converts a 0 V input "0" to a 0 V output "0" and a 0.7 V input "1" to a 1.8 V output "1". Both complementary outputs OUT and OUTB can be used by programmable logic (e.g., programmable logic 603, 703, 753, 803, 853, 953, or 1053).

[0074] The voltage VLSSUP is generated by a circuit comprising flash memory cell 1306, flash memory cell 1307, and operational amplifier 1308. Flash memory cell 1306 is erased and flash memory cell 1307 is programmed, resulting in a voltage VLSSUP_REF output on its common bit line. The non-inverting input of operational amplifier 1308 receives VLSSUP_REF, and the inverting input of operational amplifier 1308 is coupled to its output, VLSSUP, a buffered version of VLSSUP_REF. VLSSUP supplies the inputs to level shifter 1300 INPUT and INPUTB. This prevents leakage, such as leakage from inverter 1305, which could occur because the VGS of one of the PMOS transistors in inverter 1305 may not be zero (i.e., the PMOS is not completely off during a turn-off state; for example, the PMOS source may be 1 V, typically the Vdd core voltage, and its gate < 0.8 V (from INPUT), which is a signal from a flash memory array (not shown). Depending on the situation, outputs OUT and OUTB can themselves be used as a voltage source for another circuit.

[0075] Figure 14 illustrates a current mirror 1400 based on a flash memory cell. The current mirror includes a current source 1401 and a first memory cell, namely flash memory cell 1402, in a flash memory array. The word line (WL) terminal of flash memory cell 1402 is connected to a bit line terminal (BL), which is coupled to the output of current source 1401 to generate a desired voltage bias WLBIAS to control the programmable current IPROOG. This voltage bias can be applied to the word lines of a flash memory array for programming, as shown in Figure 15. In Figure 15, a non-volatile memory bit 1500 is formed by flash memory cells 1501 (a third memory cell) and 1502 (a second memory cell). In this embodiment, memory cell 1501 is to be programmed to store a value. A node generating WLBIAS in current mirror 1400 provides word line terminals to memory cell 1502 of non-volatile memory bit 1500 to form a current mirror. Current IPROOG will be drawn through flash memory cell 1502 and through flash memory cell 1501, as these cells are coupled in series. Memory cell 1502 thus acts to provide programming current to the programming memory cell 1501. Alternatively, memory cell 1501 can act as the programming current for memory cell 1502, in which case its word line will be set to equal WLBIAS. Therefore, in a flash memory array (such as flash memory devices 604 and 654 in Figures 6A and 6B, respectively), flash memory cell 1402 itself is used to generate a programming current to program other cells (such as flash memory cell 1501) within the same flash memory array. This eliminates the need for a line multiplexer during a programming operation because the programming current IPROOG is generated by the flash memory array itself and does not need to be directed from an external programming source to the cell being programmed. The programmed cell (such as flash memory cell 1501) can then be used to provide a stored value to configure programmable logic, such as programmable logic 603, 653, 703, 753, 803, 853, 953, and 1053.

[0076] As used herein, the terms "over" and "on" both inclusively include "directly on" (without intermediate material, components, or space between them) and "indirectly on" (with intermediate material, components, or space between them). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate material, components, or space between them) and "indirectly adjacent" (with intermediate material, components, or space between them), "installed to" includes "directly installed to" (without intermediate material, components, or space between them) and "indirectly installed to" (with intermediate material, components, or space between them), and "electrically coupled" includes "directly electrically coupled to" (without intermediate material or components electrically connecting the components together) and "indirectly electrically coupled to" (with intermediate material or components electrically connecting the components together). For example, forming an element "over a substrate" may include: forming the element directly on the substrate without intermediate materials / elements therebetween; and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

[0077] 12: Semiconductor substrate, substrate 14: Source Region 16: Dublin Region 18: Passage area, passage 20: Floating gate 22: Word line terminal, selected gate, control gate 24: Bitline 28: Control gate 30: Remove gate 110: Memory cell, flash memory cell 210: Quad-gate memory cell, memory cell, flash memory cell 310: Three-gate memory cell, memory cell, flash memory cell 410: Stacked gate memory cell, memory cell, flash memory cell 500: System 501: Circuit 502: Programmable Logic Block 503: Programmable Logic Block 504: Programmable Logic Block 601: Programmable Logic Block 602: Configuration Block 603: Programmable Logic 604: Flash memory device 605: Flash Memory Array 651: Programmable Logic Block 652: Configuration Block 653: Programmable Logic 654: Flash Memory Device 655: Flash Memory Array 656: Configuration Data Logic 701: Programmable Logic Block 702: Configuration Block 703: Programmable Logic 704: Flash Memory Device 706: Flash Memory Array 707: Line Multiplexer 751: Programmable Logic Block 752: Configuration Block 753: Programmable Logic 754: Flash Memory Device 755: Configuration Data Logic 756: Level Shifter 757: Flash Memory Array 758: Line Multiplexer 801: Programmable Logic Block 802: Configuration Block 803: Programmable Logic 804: Flash Memory Device 806: Flash Memory Array 807: Line Multiplexer 851: Programmable Logic Block 852: Configuration Block 853: Programmable Logic 854: Flash Memory Device 855: Configuration Data Logic 856: Level Shifter 857: Flash Memory Array 858: Line Multiplexer 951: Programmable Logic Block 952: Configuration Block 953: Programmable Logic 954: Flash Memory Device 955: Configuration Data Logic 956: Level Shifter 957: Flash Memory Array 958: Line Multiplexer 1051: Programmable Logic Block 1052: Configuration Block 1053: Programmable Logic 1054: Flash Memory Device 1055: Configuration Data Logic 1056: Level shifter 1057: Flash Memory Array 1058: Line Multiplexer 1100: Configurable nonvolatile memory modules, nonvolatile memory modules 1101: Flash memory cell, first memory cell, memory cell 1102: Second memory cell, flash memory cell, memory cell 1150: Configurable nonvolatile memory modules, nonvolatile memory modules 1151: Sensing Amplifier 1200: Non-volatile memory loci 1201: Flash Memory Cell 1202: Flash Memory Cell 1210: Non-volatile memory loci 1211: Flash Memory Cell 1212: Flash Memory Cell 1251: Sensing Amplifier 1300: Level Shifter 1301: PMOS transistor 1302: PMOS transistor 1303: NMOS transistor 1304: NMOS transistor 1305: Inverter 1306: Flash Memory Cell 1307: Flash Memory Cell 1308: Operational Amplifier 1400: Current Mirror 1401: Current Source 1402: Flash Memory Cell 1500: Non-volatile memory loci 1501: Flash memory cell, third memory cell, memory cell 1502: Second Memory Cell, Flash Memory Cell, Memory Cell BL: Common bit line, bit line terminal CG: First control gate, second control gate EG: First erase gate, second erase gate INPUT: Signal INPUTB: Inverted value IPROG: Programmed Current, Current OUT: Output OUTB: Output SL: First source line, second source line VLSSUP: Voltage VLSSUP_REF: Voltage WL: letter bar, first letter bar, second letter bar WLBIAS: Voltage bias

Claims

1. A system for configuring programmable logic, comprising: A programmable logic block includes programmable logic and a configuration block for storing configuration data and providing the configuration data to the programmable logic to configure the programmable logic to form a digital logic design. The configuration block includes a flash memory array for storing the configuration data and configuration data logic for receiving signals from the flash memory array, generating enhancement signals by increasing or decreasing a voltage level of a "1" bit, and providing such enhancement signals to the programmable logic. The flash memory array includes a split-gate flash memory cell array.

2. As in the system of request item 1, wherein, A single configuration data bit is stored in a plurality of adjacent memory cells that share a common bit line in the flash memory array.

3. The system as described in request item 2, wherein, The plurality of adjacent memory cells includes a first memory cell and a second memory cell, and when the first memory cell is erased and the second memory cell is programmed, the configuration data bit is "1" and when the first memory cell is programmed and the second memory cell is erased, the configuration data bit is "0".

4. As in request item 1, where, This configuration block includes a row of multiplexers.

5. As in request item 1, where, The flash memory array includes source lines, control gate lines, word lines, and erase gate lines arranged in a first direction, and bit lines arranged in a second direction perpendicular to the first direction.

6. As in request item 1, where, The flash memory array includes source lines, control gate lines, word lines, erase gate lines, and bit lines arranged in a single direction.

7. As in request item 1, where, The flash memory array includes source lines, word lines, and erase gate lines arranged in a first direction, and control gate lines and bit lines arranged in a second direction perpendicular to the first direction.

8. The system as described in request item 1, wherein, The flash memory array includes source lines, control gate lines, and erase gate lines arranged in a first direction, as well as word lines and bit lines arranged in a second direction perpendicular to the first direction.

9. The system as described in Request 1, comprising: A second programmable logic block includes a second programmable logic and a second configuration block for storing second configuration data and providing the second configuration data to the second programmable logic to configure the second programmable logic to form a digital logic design. The second configuration block includes a second flash memory array for storing the second configuration data.

10. The system as described in request item 1, wherein, The cell programming of these discrete gate flash memory is performed by injecting hot electrons from the source electrode side.

11. The system as described in request item 1, wherein, The discrete gate flash memory cells are programmed using a current source.

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