Electrical overstress protection device and communication system

Abstract

This invention provides an overcurrent electrical stress protection device and a communication system. The core circuit receives signals through a communication signal terminal. The overcurrent electrical stress protection device includes an impedance switching element and an overcurrent electrical stress protection element. A first terminal of the impedance switching element is coupled between the communication signal terminal and a switching element of the core circuit. A first terminal of the overcurrent electrical stress protection element is coupled to a second terminal of the impedance switching element. The second terminal of the overcurrent electrical stress protection element is coupled to a reference voltage. During normal operation, the impedance switching element can be controllably provided with a high impedance to cut off. During overcurrent electrical stress discharge operation, the impedance switching element provides a low impedance to conduct, thereby discharging charge through the overcurrent electrical stress protection element to the reference voltage.

Description

Technical Field

[0001] This invention relates to a circuit protection technology, and more particularly to an electrical overstress (EOS) protection device and communication system. Prior Technology

[0002] Electrical overstress (EOS) protection components are used to provide a shunt path for EOS energy (such as static electricity, surges, etc.) and to prevent damage to the internal circuitry (core circuitry) of integrated circuits caused by EOS. EOS protection components are typically positioned between the signal lines (signal lines from the connection port to the core circuitry) and the reference voltage (such as ground voltage GND).

[0003] However, current common EOS protection components involve some design trade-offs. For example, transient voltage suppressors (TVS) may have low trigger voltages, but due to the properties of silicon materials, TVS components introduce relatively large harmonic distortions. On the other hand, polymer ESD suppressors (PES) are less prone to harmonic distortion in the GHz range, but may have high trigger voltages (which are detrimental to EOS protection). Balancing electrical performance and EOS protection design is one of the many technical challenges in this field.

[0004] It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be known to those skilled in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content was known to those skilled in the art prior to this application. Summary of the Invention

[0005] This invention provides an Electrical Overstress (EOS) protection device and communication system to prevent EOS energy from damaging the core circuit.

[0006] In one embodiment of the present invention, the above-described overcurrent electrical stress protection device is used to protect the core circuit. The core circuit receives signals through a communication signal terminal. The overcurrent electrical stress protection device includes an impedance switching element and an overcurrent electrical stress protection element. The impedance switching element includes a first terminal and a second terminal. The first terminal of the impedance switching element is coupled to the core circuit. The overcurrent electrical stress protection element includes a first terminal and a second terminal. The first terminal of the overcurrent electrical stress protection element is coupled to the second terminal of the impedance switching element. The second terminal of the overcurrent electrical stress protection element is coupled to a reference voltage. During normal operation, the impedance switching element can be controllably provided with a high impedance to turn off. During overcurrent electrical stress discharge operation, the impedance switching element provides a low impedance to turn on, so as to discharge the charge through the overcurrent electrical stress protection element to the reference voltage.

[0007] In one embodiment of the present invention, the communication system includes a communication signal terminal, a core circuit, an impedance switching element, and an overcurrent electrical stress protection element. The core circuit includes a switching element and a communication signal venting element. A first terminal of the switching element is coupled to the communication signal terminal. The communication signal venting element is connected across a second terminal of the switching element and a reference voltage. The impedance switching element includes a first terminal and a second terminal. The first terminal of the impedance switching element is coupled to the communication signal terminal. The overcurrent electrical stress protection element is coupled between the second terminal of the impedance switching element and the reference voltage. The overcurrent electrical stress protection element has noise greater than -70 dBm in the frequency range of 10 kHz to 10 GHz. During normal operation, the communication signal venting element is controllably turned on to conduct the communication signal to the reference voltage. During overcurrent electrical stress discharge operation, the impedance switching element provides a low impedance to conduct, thereby venting charge through the overcurrent electrical stress protection element to the reference voltage.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0009] Figure 1 shows a radio frequency system with protection devices. Figure 2 is a schematic diagram of a circuit block of a communication system according to an embodiment of the present invention. Figure 3 is a circuit block diagram of a communication system according to another embodiment of the present invention. Figure 4 is a circuit block diagram of a communication system according to another embodiment of the present invention. Figure 5 is a circuit block diagram illustrating the core circuit, impedance switching element, and overcurrent electrical stress (EOS) protection element according to an embodiment of the present invention. Figure 6 is a circuit block diagram of the core circuit according to another embodiment of the present invention. Figure 7 is a circuit block diagram of an impedance switching element according to an embodiment of the present invention. Figure 8 is a circuit block diagram of an impedance switching element according to another embodiment of the present invention. Figure 9 is a circuit block diagram of an impedance switching element according to another embodiment of the present invention. Implementation

[0010] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0011] Figure 1 shows a radio frequency (RF) system 100 with protection devices. The RF system 100 includes a communication signal terminal P11, integrated circuitry 110, and an Electrical Overstress (EOS) protection element 120 arranged on a printed circuit board (PCB). A signal line W11 connects the communication signal terminal P11 and the integrated circuitry 110. The EOS protection element 120 is coupled between the signal line W11 and a reference voltage Vref11 (e.g., ground voltage). The EOS protection element 120 is triggered by an EOS event (e.g., an electrostatic discharge event, ESD event). When the EOS protection element 120 is triggered, it provides a low-impedance path between the signal line W11 and the reference voltage Vref11 to prevent EOS energy from damaging the core circuitry of the integrated circuitry 110. However, the EOS protection element 120 may introduce relatively large harmonic distortion.

[0012] Figure 2 is a circuit block diagram of a communication system 200 according to an embodiment of the present invention. The communication system 200 includes a communication signal terminal P21, a core circuit 211, and an Electrical Overstress (EOS) protection device 220. The core circuit 211 is coupled to the communication signal terminal P21 via the input terminal ST21 of the core chip 210 and the signal line W21 to transmit / receive signals. Depending on the application, the communication signal terminal P21 can be coupled to an antenna (not shown), and the core circuit 211 receives signals from the antenna through the communication signal terminal P21. In one embodiment, the signal of the communication signal terminal P21 can be a signal conforming to the Data-Over-Cable Service Interface Specifications (DOCSIS) or other signals. In one embodiment, the core circuit 211 can be a radio frequency switching circuit. The core circuit 211 may include a switching element and a communication signal venting element (the switching element and the communication signal venting element are not shown in Figure 1, but will be illustrated later in Figures 5 and 6). The first terminal of the switching element of the core circuit 211 is coupled to the input terminal ST21 of the core chip 210. The communication signal venting element of the core circuit 211 is connected across the second terminal of the switching element and a reference voltage (e.g., ground voltage).

[0013] EOS protection device 220 is used to protect core circuit 211. EOS protection device 220 is controlled by control signal Sc21 and provides a variable impedance path coupled between signal line W21 and reference voltage Vref21 (e.g., ground voltage). EOS protection device 220 includes two operating states: normal operation and EOS discharge operation. In normal operation, according to control signal Sc21, EOS protection device 220 is in a "high impedance" state to prevent signal leakage to reference voltage Vref21 when transmitting / receiving signals on signal line W21. Furthermore, it isolates harmonic distortion by providing a high impedance path between signal line W21 and the harmonic-rich protection device (e.g., EOS protection element 222) of EOS protection device 220. In EOS discharge operation, EOS protection device 220 is in a "low impedance" state and provides a low impedance path to shunt EOS energy from communication signal terminal P21 to reference voltage Vref21. Therefore, the EOS protection device 220 not only prevents the core circuit 211 from being damaged by the EOS event, but also avoids harmonic distortions of the operating signal of the signal line W21.

[0014] The EOS protection device 220 includes an impedance switching element 221 and an EOS protection element 222. A first terminal of the impedance switching element 221 is coupled to a communication signal terminal P21. A first terminal of the EOS protection element 222 is coupled to a second terminal of the impedance switching element 221. The second terminal of the EOS protection element is coupled to a reference voltage Vref21. In one embodiment, when the EOS protection device 220 is in a "high impedance" state, the impedance switching element 221 is turned off to provide at least... Ohm.

[0015] The EOS protection element 222 can be any type of element. For example, the EOS protection element 222 includes bidirectional protection elements, transient voltage suppressors (TVS), polymer ESD suppressors (PES), silicon TVS diode arrays, thyristors (such as silicon controlled rectifiers (SCRs)), varistors (such as multi-layer varistors (MLVs) and metal oxide varistors (MOVs)), gas discharge tubes (GDTs), or other EOS protection elements. The EOS protection element 222 has noise greater than -70 dBm in the 10 kHz to 10 GHz frequency range. In one embodiment, the EOS protection element 222 has noise greater than -70 dBm in the 5 MHz to 2 GHz frequency range. During normal operation, the communication signal venting element of the core circuit 211 (not shown in Figure 1, but described later) can be controllably turned on to conduct the communication signal to the reference voltage Vref21 (e.g., ground voltage); or the communication signal venting element of the core circuit 211 can be controllably turned off to transmit the communication signal to the core circuit 211 for processing, such as through a path that transmits the communication signal to the core circuit 211. For example, the communication system (e.g., communication systems 200, 300, 400) can be a wired cable signal communication system, and the core circuit 211 can be part of a wired cable signal transceiver. When a wired cable signal (e.g., a DOCSIS-compliant signal) with an operating frequency range of 5MHz to 2GHz is transmitted on signal line W21, the EOS protection element 222 generates noise, for example, a signal strength greater than -70dBm in the frequency range of 10kHz to 10GHz, resulting in nonlinear parasitic effects and thus harmonic distortion.

[0016] The core circuit 211 (or other control circuit, not shown) can provide a control signal Sc21 to control the impedance switching element 221 to turn on or off. During normal operation, the impedance switching element 221 can be controllably provided with a high impedance to turn off. Therefore, the impedance switching element 221 can isolate the nonlinear parasitic effects of the EOS protection element 222, preventing harmonic distortion of the communication signal at the communication signal terminal P21 caused by the EOS protection element 222. During EOS discharge operation, the impedance switching element 221 provides a low impedance to turn on. The EOS protection element 222 is triggered by an EOS event (e.g., an electrostatic discharge event). When the impedance switching element 221 is on, the EOS protection element 222 is triggered by electrostatic discharge at the communication signal terminal P21, thus the charge at the communication signal terminal P21 is immediately discharged to the reference voltage Vref21 through the impedance switching element 221 and the EOS protection element 222. Based on this, the EOS protection device 220 can prevent EOS energy from damaging the core circuit 211.

[0017] The core circuit 211, impedance switching element 221, and EOS protection element 222 described above are implemented in different ways depending on the design and application context. For example, in some embodiments, the core circuit 211 is located on a first chip (core chip 210), the impedance switching element 221 is located on a second chip (different from the core chip 210), and the EOS protection element 222 is located on a third chip (different from the core chip 210 and the second chip). In other embodiments, the core circuit 211 is located on the first chip (core chip 210), while the impedance switching element 221 and the EOS protection element 222 are located on the second chip. In still other embodiments, the core circuit 211 and the impedance switching element 221 are located on the first chip (core chip 210), and the EOS protection element 222 is located on the second chip. Depending on the actual design, these chips are arranged on a printed circuit board (PCB) or other circuit board.

[0018] Figure 3 is a circuit block diagram of a communication system 300 according to another embodiment of the present invention. The communication system 300 shown in Figure 3 includes a communication signal terminal P21, a core circuit 211, and an EOS protection device 220. The core chip 210, core circuit 211, input terminal ST21, signal line W21, communication signal terminal P21, EOS protection device 220, impedance switching element 221, and EOS protection element 222 shown in Figure 3 can be referred to the relevant description in Figure 2, and therefore will not be repeated. In the embodiment shown in Figure 3, the core circuit 211 includes a switching element SW32 for cutting off or enabling the transmission of signals received by the communication signal terminal P21 to the core circuit 211. The first end of the impedance switching element 221 is coupled between the communication signal terminal P21 and the switching element SW32 of the core circuit 211.

[0019] Figure 4 is a circuit block diagram of a communication system 400 according to another embodiment of the present invention. The communication system 400 shown in Figure 4 includes a communication signal terminal P21, a core circuit 211, and an EOS protection device 220. The core chip 210, core circuit 211, input terminal ST21, signal line W21, communication signal terminal P21, EOS protection device 220, impedance switching element 221, and EOS protection element 222 shown in Figure 4 can be referred to in the relevant description in Figure 2, and therefore will not be repeated. In the embodiment shown in Figure 4, the core circuit 211 includes a switching element SW32. The switching element SW32 shown in Figure 4 can be referred to in the relevant description in Figure 3, and therefore will not be repeated. Compared to the embodiment shown in Figure 3, the first end of the switching element SW32 shown in Figure 4 is coupled to the communication signal terminal P21, and the first end of the impedance switching element 221 is coupled to the second end of the switching element SW32.

[0020] In summary, impedance switching element 221 is coupled between the communication signal terminal P21 and the EOS protection element 222. During EOS discharge operation, impedance switching element 221 is turned on to discharge the charge of the communication signal terminal P21 through the EOS protection element 222 to the reference voltage Vref21. Therefore, the EOS protection device 220 and the communication system 200 can prevent EOS energy from damaging the core circuit 211. During normal operation, impedance switching element 221 is turned off. Therefore, impedance switching element 221 can isolate the nonlinear parasitic effects of the EOS protection element 222, avoiding harmonic distortion caused by excessive electrical stress on the protection element from affecting the signal line W21.

[0021] Figure 5 is a circuit block diagram illustrating the core circuit 211, impedance switching element 221, and EOS protection element 222 according to an embodiment of the present invention. The core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 5 can be one of many embodiments of the core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 2. The core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 5 can be one of many embodiments of the core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 4. In the embodiment shown in Figure 5, the impedance switching element 221 includes a switching transistor, and the EOS protection element 222 includes a Zener diode. Based on practical design and application, the impedance switching element 221 can be arranged in the core circuit 211.

[0022] The core circuit 211 receives signals through the communication signal terminal P21. In the embodiment shown in Figure 5, the core circuit 211 includes a radio frequency (RF) switching circuit, which includes switching elements SW31 and SW32, a communication signal venting element SW33, and a communication signal venting element SW34. The communication signal venting elements SW33 and SW34 can function as shunts. In the first phase of normal operation, switching elements SW31 and SW34 are turned on, while switching elements SW32, impedance switching element 221, and SW33 are turned off. At this time, the signal from the communication signal terminal P21 can be transmitted to path RF31 through switching element SW31. When the signal from the communication signal terminal P21 is transmitted to path RF31, switching elements SW32 and impedance switching element 221 are turned off, thus avoiding harmonic distortion caused by the EOS protection element 222. During the second phase of normal operation, switching element SW31, impedance switching element 221, and communication signal venting element SW34 are off, while switching element SW32 and communication signal venting element SW33 are on. At this time, the signal from communication signal terminal P21 can be transmitted to path RF32 via switching element SW32. When the signal from communication signal terminal P21 is transmitted to path RF32, impedance switching element 221 is off, thus avoiding harmonic distortion caused by EOS protection element 222. In one embodiment, the first end of impedance switching element 221 can be coupled between communication signal venting element SW34 and path RF32.

[0023] As described above, during normal operation, impedance switching element 221 remains off in both the first and second phases. In the event of an EOS event, impedance switching element 221 becomes on to discharge charge through EOS protection element 222 to the reference voltage Vref21. Therefore, EOS protection device 220 and communication system 200 can prevent EOS energy from damaging the core circuit 211.

[0024] Figure 6 is a circuit block diagram of the core circuit 211 according to another embodiment of the present invention. The core circuit 211 shown in Figure 6 can be one of many embodiments of the core circuit 211 shown in Figure 2. The core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 6 can be one of many embodiments of the core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 3. The core circuit 211, impedance switching element 221, and EOS protection element 222 shown in Figure 6 can be deduced by referring to the relevant description in Figure 5, and therefore will not be described again. Based on practical design and application, the impedance switching element 221 can be arranged in the core circuit 211. Unlike the embodiment shown in Figure 5, the first end of the impedance switching element 221 shown in Figure 6 is coupled between the communication signal terminal P21 and the switching element SW32 of the core circuit 211.

[0025] During EOS discharge operation, impedance switching element 221 is turned on, and EOS energy (such as ESD charge) is transferred to EOS protection element 222 through impedance switching element 221. At this time, the charge at communication signal terminal P21 is immediately discharged to reference voltage Vref21 through impedance switching element 221 and EOS protection element 222 to prevent EOS energy from damaging core circuit 211. During normal operation, impedance switching element 221 is turned off, thus avoiding harmonic distortion caused by EOS protection element 222.

[0026] Figure 7 is a circuit block diagram of impedance switching element 221 according to an embodiment of the present invention. The impedance switching element 221 shown in Figure 7 can be one of many embodiments of the impedance switching element 221 shown in Figure 2. The core circuit 211, signal line W21, communication signal terminal P21, impedance switching element 221, and EOS protection element 222 shown in Figure 7 can be deduced from the relevant description in Figure 2, and therefore will not be repeated. In the embodiment shown in Figure 7, the impedance switching element 221 includes an impedance switching circuit 510, a switch driver 520, and an EOS detection circuit 530. The first terminal of the impedance switching circuit 510 is coupled to the first terminal of the impedance switching element 221, that is, coupled to the signal line W21. The second terminal of the impedance switching circuit 510 is coupled to the EOS protection element 222. The input terminal of the switch driver 520 is coupled to the core circuit 211 to receive the control signal Sc21. The output terminal of the switch driver 520 is coupled to the control terminal of the impedance switching circuit 510. In one embodiment, the impedance switching element 221 includes only one of the switch driver 520 and the EOS detection circuit 530.

[0027] Impedance switching circuit 510 includes multiple stacked transistors (e.g., multiple transistors Mn5_1~Mn5_m stacked together as shown in FIG. 7). The first terminal of each stacked transistor is coupled to the first terminal of impedance switching element 221, i.e., coupled to signal line W21. The second terminal of each stacked transistor is coupled to EOS protection element 222. The control terminal (e.g., gate) of each transistor in the stacked transistor is coupled to the control terminal of impedance switching circuit 510 via a corresponding resistor (e.g., resistors Rg5_1~Rg5_m shown in FIG. 7), i.e., coupled to the output terminal of switch driver 520. In one application example, the base terminal of each transistor in the stacked transistor is coupled to switch driver 520 via a corresponding resistor (e.g., resistors Rb5_1~Rb5_m shown in FIG. 7). In another application example, the base terminal of each transistor in the stacked transistor is coupled to a reference voltage (e.g., ground voltage) via a corresponding resistor. In one embodiment, at least one of the stacked transistors can be manufactured using the SOI (Silicon On Insulator) process.

[0028] The input of the EOS detection circuit 530 is coupled to the input of the core circuit 211. The output of the EOS detection circuit 530 is coupled to the control terminal of the impedance switching circuit 510. In the embodiment shown in FIG. 7, the EOS detection circuit 530 includes a diode string. The anode of the diode string is coupled to the first terminal of the impedance switching element 221, i.e., coupled to the signal line W21. The cathode of the diode string is coupled to the control terminal of the impedance switching circuit 510. The switch driver 520 is configured to turn the impedance switching circuit 510 on / off according to the control signal Sc21. In one embodiment, the switch driver 520 includes a level shift circuit to provide an appropriate control voltage to resistors Rg5_1~Rg5_m and resistors Rb5_1~Rb5_m to turn transistors Mn5_1~Mn5_m on / off. Under normal operating conditions, the impedance switching circuit 510 is in a "high impedance" state because the switch driver 520 keeps the transistors Mn5_1 to Mn5_m in the off state. Therefore, the impedance switching circuit 510 in the off state can suppress the harmonic effects of the EOS protection element 222.

[0029] During normal operation, the switch driver 520 or the EOS detection circuit 530 cuts off the impedance switch circuit 510. For example, during normal operation, the switch driver 520 cuts off the impedance switch circuit 510 according to the control signal Sc21. In some applications, during EOS discharge operation, the switch driver 520 or the EOS detection circuit 530 turns on the impedance switch circuit 510 to discharge the charge through the impedance switch circuit 510 and the EOS protection element 222 to the reference voltage Vref21. For example, when an EOS positive pulse appears at the communication signal terminal P21, the EOS positive pulse turns on the multi-layer transistors Mn5_1~Mn5_m of the impedance switch circuit 510 through the diode string of the EOS detection circuit 530.

[0030] Figure 8 is a circuit block diagram of impedance switching element 221 according to another embodiment of the present invention. The impedance switching element 221 shown in Figure 8 can be considered as one of many embodiments of the impedance switching element 221 shown in Figure 2. The core circuit 211, signal line W21, communication signal terminal P21, impedance switching element 221, and EOS protection element 222 shown in Figure 8 can be deduced by referring to the relevant description in Figure 2, and therefore will not be repeated. In the embodiment shown in Figure 8, the impedance switching element 221 includes an impedance switching circuit 510, a switch driver 520, and an EOS detection circuit 630. The impedance switching circuit 510, switch driver 520, and EOS detection circuit 630 shown in Figure 8 can be deduced by referring to the relevant description of the impedance switching circuit 510, switch driver 520, and EOS detection circuit 530 shown in Figure 7, and therefore will not be repeated.

[0031] In the embodiment shown in Figure 8, the EOS detection circuit 630 includes a resistor R61 and a capacitor C61. The first end of resistor R61 is coupled to the first end of impedance switching element 221, i.e., coupled to signal line W21. The second end of resistor R61 is coupled to the control terminal of impedance switching circuit 510. The first end of capacitor C61 is coupled to the control terminal of impedance switching circuit 510. The second end of capacitor C61 is coupled to reference voltage Vref21 (e.g., ground voltage).

[0032] During normal operation, the switch driver 520 or the EOS detection circuit 530 shuts off the impedance switch circuit 510. For example, during normal operation, the switch driver 520 shuts off the impedance switch circuit 510 according to the control signal Sc21. In some applications, during EOS discharge operation, the switch driver 520 or the EOS detection circuit 530 shuts off the impedance switch circuit 510, where the impedance switch circuit 510 collapses due to excessive electrical stress, thereby discharging charge through the impedance switch circuit 510 and the EOS protection element 222 to the reference voltage Vref21.

[0033] Figure 9 is a circuit block diagram of impedance switching element 221 according to another embodiment of the present invention. The impedance switching element 221 shown in Figure 9 can be considered as one of many embodiments of the impedance switching element 221 shown in Figure 2. The core circuit 211, signal line W21, communication signal terminal P21, impedance switching element 221, and EOS protection element 222 shown in Figure 9 can be deduced by analogy with the relevant description in Figure 2, and therefore will not be described again. In the embodiment shown in Figure 9, the impedance switching element 221 includes an impedance switching circuit 710, a switch driver 520, and an EOS detection circuit 730. The impedance switching circuit 710, switch driver 520, and EOS detection circuit 730 shown in Figure 9 can be deduced by analogy with the relevant descriptions of the impedance switching circuit 510, switch driver 520, and EOS detection circuit 630 shown in Figure 8, or by analogy with the relevant descriptions of the impedance switching circuit 510, switch driver 520, and EOS detection circuit 530 shown in Figure 7, and therefore will not be described again.

[0034] In the embodiment shown in FIG9, the impedance switching circuit 710 includes multiple stacked transistors (e.g., multiple transistors Mn7_1~Mn7_m stacked together as shown in FIG9). The first terminal of each stacked transistor is coupled to the first terminal of the impedance switching element 221, i.e., coupled to the signal line W21. The second terminal of each stacked transistor is coupled to the EOS protection element 222. The control terminal (e.g., the gate) of each of the stacked transistors is coupled to the control terminal of the impedance switching circuit 510, i.e., coupled to the switch driver 520 and the EOS detection circuit 730. In one application example, the base terminal of each of the stacked transistors Mn7_1~Mn7_m is electrically floating. In another application example, the base terminal of each of the stacked transistors Mn7_1~Mn7_m is coupled to the switch driver 520. In another application example, the base terminal of each of the multiple stacked transistors Mn7_1 to Mn7_m is directly coupled to a reference voltage (e.g., ground voltage).

[0035] During normal operation, the switch driver 520 or the EOS detection circuit 730 shuts off the impedance switch circuit 510. For example, during normal operation, the switch driver 520 shuts off the impedance switch circuit 510 according to the control signal Sc21. In some applications, during EOS discharge operation, the switch driver 520 or the EOS detection circuit 730 turns on the impedance switch circuit 710 to discharge charge through the impedance switch circuit 710 and the EOS protection element 222 to the reference voltage Vref21. In other applications, during EOS discharge operation, the switch driver 520 or the EOS detection circuit 730 shuts off the impedance switch circuit 710, where the impedance switch circuit 710 collapses due to excessive electrical stress, to discharge charge through the impedance switch circuit 710 and the EOS protection element 222 to the reference voltage Vref21.

[0036] In one embodiment, the switch driver 520 is used to receive an output signal from a microcontroller. The switch driver 520 can receive the output signal and maintain the cutoff impedance switch circuit 510 at least during normal operation.

[0037] In one embodiment, the EOS detection circuit 730 is used to detect whether an EOS event has occurred on the signal line W21, so as to turn on the impedance switch circuit, or turn off the impedance switch circuit and cause the impedance switch circuit to fail.

[0038] In summary, impedance switching element 221 is coupled between communication signal terminal P21 and EOS protection element 222. During EOS discharge operation, the impedance switching circuit 710 of impedance switching element 221 is turned on, allowing the charge at communication signal terminal P21 to be discharged to the reference voltage Vref21 through EOS protection element 222. Therefore, EOS protection device 220 and communication system 200 can prevent EOS energy from damaging the core circuit 211. During normal operation, the impedance switching circuit 710 of impedance switching element 221 is turned off. Therefore, the impedance switching circuit 710 of impedance switching element 221 can isolate the nonlinear parasitic effects of EOS protection element 222, preventing harmonic distortion on signal line W21 caused by EOS protection element 222. Therefore, EOS protection device 220 and communication system 200 can avoid harmonic distortion caused by EOS protection element 222.

[0039] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0040] 100: Radio Frequency System 110: Integrated circuits 120: Excess Electrical Stress (EOS) Protection Element 200, 300, 400: Communication System 210: Core chip 211: Core Circuit 220: EOS protection device 221: Impedance switching element 222: EOS protection element 510, 710: Impedance switching circuit 520: Switch driver 530, 630, 730: EOS detection circuit C61: Capacitor Mn5_1, Mn5_m, Mn7_1, Mn7_m: Transistors P11, P21: Communication signal terminals R61: Resistor Rb5_1, Rb5_m, Rg5_1, Rg5_m: Resistors RF31, RF32: Path Sc21: Control signal ST21: Input Terminal SW31, SW32: Switching elements SW33, SW34: Communication signal venting components Vref11, Vref21: Reference voltages W11, W21: Signal lines

Claims

1. An over-electrical stress protection device for protecting a core circuit, wherein the core circuit receives a signal through a communication signal terminal, wherein the core circuit includes a switching element for blocking or enabling the transmission of the signal received by the communication signal terminal to the core circuit, wherein the communication signal terminal is coupled to an antenna, and the core circuit receives the signal from the antenna through the communication signal terminal, the over-electrical stress protection device comprising: An impedance switching element includes a first terminal and a second terminal, wherein the first terminal of the impedance switching element is coupled between the communication signal terminal and the switching element of the core circuit; and an overcurrent electrical stress protection element includes a first terminal and a second terminal, wherein the first terminal of the overcurrent electrical stress protection element is coupled to the second terminal of the impedance switching element, and the second terminal of the overcurrent electrical stress protection element is coupled to a reference voltage, wherein during normal operation, the impedance switching element is controllably provided with a high impedance to cut off; and during overcurrent electrical stress discharge operation, the impedance switching element provides a low impedance to conduct, so as to discharge a charge through the overcurrent electrical stress protection element to the reference voltage.

2. The excessive electrical stress protection device as claimed in claim 1, wherein the core circuit provides a control signal to control the impedance switching element to be turned on or off, the impedance switching element further includes an impedance switching circuit, and the impedance switching element further includes a switch driver or an excessive electrical stress detection circuit; the impedance switching circuit includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the impedance switching circuit is coupled to the first terminal of the impedance switching element, and the second terminal of the impedance switching circuit is coupled to the excessive electrical stress protection element; and the switch driver includes an input terminal and an output terminal, wherein the input terminal of the switch driver is coupled to the core circuit to receive the control signal, and the output terminal of the switch driver is coupled to a control terminal of the impedance switching circuit; or the excessive electrical stress detection circuit includes an input terminal and an output terminal, wherein the input terminal is coupled to the input terminal of the core circuit, and the output terminal is coupled to the control terminal of the impedance switching circuit.

3. The excessive electrical stress protection device as claimed in claim 2, wherein the excessive electrical stress detection circuit comprises: A diode string, wherein one anode of the diode string is coupled to the first terminal of the impedance switching element, and one cathode of the diode string is coupled to the control terminal of the impedance switching circuit.

4. The excessive electrical stress protection device as claimed in claim 2, wherein the excessive electrical stress detection circuit comprises: A resistor, wherein a first end of the resistor is coupled to the first end of the impedance switching element, and a second end of the resistor is coupled to the control terminal of the impedance switching circuit; and a capacitor, wherein a first end of the capacitor is coupled to the control terminal of the impedance switching circuit, and a second end of the capacitor is coupled to the reference voltage.

5. The over-electrical stress protection device as described in claim 2, wherein, During normal operation, the switch driver or the excessive electrical stress detection circuit turns off the impedance switch circuit; and during excessive electrical stress discharge operation, one of the switch driver and the excessive electrical stress detection circuit turns on the impedance switch circuit or turns off and breaks down the impedance switch circuit, so as to discharge the charge through the impedance switch circuit and the excessive electrical stress protection element to the reference voltage.

6. The over-electrical stress protection device as claimed in claim 2, wherein the impedance switching circuit comprises: A multi-layer transistor includes a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the impedance switching element, the second terminal is coupled to the overcurrent electrical stress protection element, and a control terminal of each transistor in the multi-layer transistor is coupled to the control terminal of the impedance switching circuit or the switch driver.

7. The over-electrical stress protection device as claimed in claim 3, wherein the over-electrical stress protection element is a bidirectional protection element.

8. The over-electrical stress protection device as claimed in claim 6, wherein a base terminal of each of the multiple stacked transistors is electrically floating or the base terminal is coupled to the switch driver or the reference voltage.

9. The over-electrical stress protection device as claimed in claim 6, wherein the control terminal of each of the multiple stacked transistors is coupled to the control terminal of the impedance switching circuit or the switch driver via a resistor.

10. The over-electrical stress protection device as claimed in claim 1, wherein the over-electrical stress protection element includes a transient voltage suppressor.

11. The over-electrical stress protection device as claimed in claim 1, wherein the core circuit further includes a communication signal venting element, which, during normal operation, is controllably turned on to conduct the signal received by the core circuit to the reference voltage.

12. The over-electrical stress protection device as claimed in claim 1, wherein the over-electrical stress protection element has noise greater than -70 dBm in the 10 kHz to 10 GHz range.

13. The overcurrent electrical stress protection device as claimed in claim 1, wherein the signal is a wired cable data service interface specification.

14. A communication system for protecting a core circuit, the communication system comprising: a communication signal terminal; the core circuit including a switching element and a communication signal venting element, a first terminal of the switching element coupled to the communication signal terminal, and the communication signal venting element connected across a second terminal of the switching element and a reference voltage, wherein the switching element is used to block or enable the transmission of a signal received by the communication signal terminal to the core circuit, wherein the communication signal terminal is coupled to an antenna, and the core circuit receives the signal from the antenna through the communication signal terminal; An impedance switching element includes a first terminal and a second terminal, wherein the first terminal of the impedance switching element is coupled between a communication signal terminal and a switching element of the core circuit; and an overcurrent electrical stress protection element is coupled between the second terminal of the impedance switching element and a reference voltage, wherein the overcurrent electrical stress protection element has noise greater than -70dBm in the frequency range of 10kHz to 10GHz, wherein during normal operation, the communication signal venting element is controllably turned on to conduct a communication signal to the reference voltage; and during overcurrent electrical stress discharge operation, the impedance switching element provides a low impedance to conduct, so as to vent a charge through the overcurrent electrical stress protection element to the reference voltage.

15. The communication system of claim 14, wherein the core circuit and the impedance switching element are disposed on a first wafer, and the over-electrical stress protection element is disposed on a second wafer; or the core circuit is disposed on a first wafer, the impedance switching element is disposed on a second wafer, and the over-electrical stress protection element is disposed on a third wafer.

16. An over-stress protection device for protecting a core circuit, the core circuit receiving a signal via a communication signal terminal, the over-stress protection device comprising: an impedance switching element including a first terminal and a second terminal, wherein the first terminal of the impedance switching element is coupled to the core circuit; and an over-stress protection element including a first terminal and a second terminal, wherein the first terminal of the over-stress protection element is coupled to the second terminal of the impedance switching element, and the second terminal of the over-stress protection element is coupled to a reference voltage, wherein during normal operation, the impedance switching element is controllably provided with a high impedance to cut off; and during over-stress discharge operation, the impedance switching element provides a low impedance to conduct, so as to discharge a charge through the over-stress protection element to the reference voltage. The core circuit provides a control signal to control the impedance switching element to be turned on or off. The impedance switching element further includes an impedance switching circuit and a switch driver or an excessive electrical stress detection circuit. The impedance switching circuit includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the impedance switching circuit is coupled to the first terminal of the impedance switching element, and the second terminal of the impedance switching circuit is coupled to the excessive electrical stress protection element. The switch driver includes an input terminal and an output terminal, wherein the input terminal of the switch driver is coupled to the core circuit to receive the control signal, and the output terminal of the switch driver is coupled to a control terminal of the impedance switching circuit. Alternatively, the excessive electrical stress detection circuit includes an input terminal and an output terminal, wherein the input terminal is coupled to the input terminal of the core circuit, and the output terminal is coupled to the control terminal of the impedance switching circuit.

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