Package structure and method of forming device structure

Abstract

A packaging structure and a method for forming a device structure are provided. The device structure can be formed by: providing a first redistribution structure; providing a metal crack barrier structure including at least one metal pillar on a peripheral region of the first redistribution structure; attaching a connecting die to a central region of the first redistribution structure; forming a packaging frame around the connecting die and the metal crack barrier structure; and forming a second redistribution structure on the connecting die, the metal crack barrier structure, and the packaging frame.

Description

Technical Field

[0001] The embodiments of the present invention relate to a packaging structure and a method for forming an apparatus structure. Prior Technology

[0002] Composite interposers, which include different types of materials such as molding compounds and redistributed dielectric layers, may develop cracks. To improve the reliability of composite interposers, it is necessary to suppress the formation of such cracks. Summary of the Invention

[0003] An embodiment of the present invention provides a method for forming an apparatus structure, comprising: providing a first redistribution structure, the first redistribution structure including a first redistribution line connector formed within a first redistribution dielectric layer; disposing a metal crack-blocking structure including at least one metal pillar above a peripheral region of the first redistribution structure; attaching a connecting die to a central region of the first redistribution structure; forming an encapsulation frame around the connecting die and the metal crack-blocking structure; and forming a second redistribution structure above the connecting die, the metal crack-blocking structure, and the encapsulation frame, the second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer.

[0004] An embodiment of the present invention provides a method for forming an apparatus structure, comprising: forming a composite grain, the composite grain comprising at least one semiconductor grain and a first molding compound matrix; forming a first redistribution structure on the composite grain, wherein the first redistribution structure comprises a first redistribution line connector formed within a first redistribution dielectric layer and electrically connected to a metal interconnect structure within the at least one semiconductor grain; disposing a metal crack barrier structure comprising at least one metal pillar above a peripheral region of the first redistribution structure; attaching a connecting grain to a central region of the first redistribution structure; and forming an encapsulation frame around the connecting grain and the metal crack barrier structure.

[0005] An embodiment of the present invention provides a packaging structure comprising: a first redistribution structure including a first redistribution line connector formed within a first redistribution dielectric layer; a metal crack-resistant structure including at least one metal pillar disposed above a peripheral region of the first redistribution structure; a connecting die attached to a central region of the first redistribution structure; a packaging frame encapsulating the connecting die and the metal crack-resistant structure; and a second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer and located above the connecting die, the metal crack-resistant structure, and the packaging frame. Simple Explanation of the Diagram

[0006] The best understanding of this disclosure is achieved by reading it in conjunction with the accompanying drawings, and by the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a vertical cross-sectional view of an example structure after semiconductor dies and dummy dies have been attached to a first carrier wafer, according to an embodiment of the present disclosure. Figure 2 is a vertical cross-sectional view of an example structure after forming a molded compound grain framework, according to an embodiment of the present disclosure. Figure 3 is a vertical cross-sectional view of an example structure after the formation of the first redistribution structure, according to an embodiment of the present disclosure. Figure 4 is a vertical cross-sectional view of an example structure after a through-intermediate via (TIV) structure is provided on the first redistribution structure according to an embodiment of the present disclosure. Figure 5 is a vertical cross-sectional view of an example structure after a metal crack-blocking structure is provided on the first redistribution structure according to an embodiment of the present disclosure. Figure 6 is a vertical cross-sectional view of an example structure after the connecting grains are attached to the central region of the first redistribution structure, according to an embodiment of the present disclosure. Figures 7A-7J are top views of the example structure after the processing steps in Figure 6, showing various settings. Figure 8 is a vertical cross-sectional view of an example structure after applying an adhesive material between the first redistribution structure and the connecting grains, according to an embodiment of the present disclosure. Figure 9 is a vertical cross-sectional view of an example structure after the encapsulation frame has been formed, according to an embodiment of the present disclosure. Figure 10 is a vertical cross-sectional view of an example structure after the formation of the second redistribution structure according to an embodiment of the present disclosure. Figure 11 is a vertical cross-sectional view of an example structure after attaching the second carrier wafer to the second redistribution structure and separating the first carrier wafer from the composite grain, according to an embodiment of the present disclosure. Figure 12 is an enlarged view of an area of ​​an example structure around a cutting channel during a cutting process, according to an embodiment of the present disclosure. Figure 13 is a vertical cross-sectional view of a composite package formed by cutting a reconstructed wafer of the example structure of Figure 11 according to an embodiment of the present disclosure. Figure 14 is a vertical cross-sectional view of an in-process semiconductor interposer according to an embodiment of the present disclosure, wherein the in-process semiconductor interposer is contained in a wafer of an array of in-process semiconductor interposers. Figure 15 is a vertical cross-sectional view of an assembly comprising a semiconductor interposer, a composite package, and two high-bandwidth memory chips within a wafer cell region according to an embodiment of the present disclosure. Figure 16 is a vertical cross-sectional view of an assembly after forming a molded compound polycrystalline framework, according to an embodiment of the present disclosure. Figure 17 is a vertical cross-sectional view of an assembly after thinning the back side of a wafer and dicing the reconstructed wafer into an integrated semiconductor package, according to an embodiment of the present disclosure. Figure 18 is a first flowchart illustrating the steps of forming the apparatus structure according to an embodiment of the present disclosure. Figure 19 is a second flowchart illustrating the steps of forming the apparatus structure according to an embodiment of the present disclosure. Figure 20 is a third flowchart illustrating the steps of forming the apparatus structure according to an embodiment of the present disclosure. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," "upper part," and similar terms may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0009] Various embodiments disclosed herein relate to a method for forming reliable semiconductor packages compatible with system-on-integrated-chip (SoIC) technology. During die-cutting processes associated with semiconductor manufacturing, cracks often occur in redistribution structures and / or molding compounds, potentially leading to corner chipping, which compromises the integrity of the semiconductor package. These problems are typically due to insufficient edge protection of the interposer backside redistribution structure and the package frame. Embodiments of this disclosure provide a metal crack-resistant structure comprising at least one metal pillar, which can be used to prevent internal cracks in the interposer and enhance the reliability of the semiconductor package.

[0010] According to one aspect of this disclosure, a composite die comprising at least one semiconductor die and a molding compound matrix can be provided. A first redistribution structure having a first redistribution wiring connector formed in a first redistribution dielectric layer can be formed on the composite die. A metal break-barrier structure comprising at least one metal pillar can be formed in a peripheral region of the first redistribution structure. A wiring die can be attached to a central region of the first redistribution structure, and an encapsulation frame can be formed around the wiring die and the metal break-barrier structure. A second redistribution structure can be formed on the wiring die, the metal break-barrier structure, and the encapsulation frame. The second redistribution structure includes a second redistribution wiring connector formed in a second redistribution dielectric layer. An array of metal bump structures can be formed on the second redistribution wiring connector. The metal break-barrier structure can be an electrically inactive structure that remains electrically isolated from the metal bumps.

[0011] In some embodiments, the first redistribution structure may include a first edge sealing ring structure electrically connected to the metal crack barrier structure and continuously extending through all first redistribution dielectric layers. Similarly, the second redistribution structure may include a second edge sealing ring structure electrically connected to the metal crack barrier structure and continuously extending through all second redistribution dielectric layers. The package frame may be formed by applying a molding compound material around the connector die and the metal crack barrier structure, followed by a planarization process to expose the top surfaces of the connector die and the metal crack barrier structure. The connector die may be indirectly bonded to a first bump structure of the first redistribution structure via solder. In some embodiments, a through-intermediate via (TIV) structure may be disposed on a second bump structure of the first redistribution structure and may be formed within the package frame. The TIV structure may be used to provide an electrical connection between the first redistribution line connector and the second redistribution line connector. A composite package may be provided, comprising a composite die including at least one semiconductor die and a molding compound die framework, and a composite intermediary including the first redistribution structure, the connector die, and the metal crack barrier structure and the second redistribution structure formed within the package frame. The metal crack-resistant structure structurally reinforces the encapsulation framework to prevent cracking of the composite interlayer. The accompanying drawings illustrate various aspects of this disclosure in detail.

[0012] Referring to FIG1, an example structure according to an embodiment of the present disclosure is illustrated. This example structure includes a semiconductor die 200 and an optional dummy die 201 that can be attached to the top side of a first carrier 710. In one embodiment, the first carrier 710 may be a wafer formed of a semiconductor material or a transparent material. For example, the first carrier 710 may be a silicon wafer or a glass wafer. In one embodiment, the first carrier 710 may be a panel formed of a dielectric material or a transparent material. For example, the first carrier 710 may be a glass panel. The first carrier 710 may include a two-dimensional array of cell regions UA1, such as a rectangular array of cell regions UA1. In this embodiment, instances of multiple cell regions UA1 may be repeated along a first horizontal direction hd1 at a first spacing and along a second horizontal direction at a second spacing. The illustrated example structure partially corresponds to a region of a single cell region UA1. Typically, a combination of at least one semiconductor die 200 and at least one optional dummy die 201 may be attached to the first carrier wafer 710 in each cell region UA1. In one embodiment, a die bonding film (DAF) 711 may be applied to the top surface of a first carrier 710, and each group of at least one semiconductor die 200 and optionally at least one dummy die 201 may be attached to the DAF 711 by performing a pick and place operation.

[0013] Typically, each semiconductor die 200 can be any type of semiconductor die known to those skilled in the art. For example, each of at least one semiconductor die 200 in cell region UA1 may include a system-on-chip (SoC) die, a logic die, a memory die, or any other type of semiconductor die. In one embodiment, semiconductor die 200 may include a die semiconductor substrate 210, which may include a single-crystal semiconductor substrate. Semiconductor device 220 may be formed on the top surface of die semiconductor substrate 210. Semiconductor device 220 may include a field-effect transistor, resistor, diode, capacitor, inductor, or any other type of semiconductor device known to those skilled in the art.

[0014] Each semiconductor die 200 may include a metal interconnect structure 222 formed in a dielectric material layer 230 and covering the semiconductor device 220. The metal interconnect structure 222 may provide electrical connections between semiconductor devices 220. Die-side bonding pads 224, i.e., bonding pads formed on the semiconductor die 200, may be formed on the top layer of the dielectric material layer 230. The die-side bonding pads 224 are electrically connected to the semiconductor device 220 via the metal interconnect structure 222. In one embodiment, the semiconductor die 200 may be attached to a first carrier 710 such that the die semiconductor substrate 210 is closer to the first carrier 710 than the die-side bonding pads 224. After each semiconductor die 200 is attached to the first carrier 710, the planar horizontal surface of the die-side bonding pads 224 may be physically exposed.

[0015] While this disclosure describes embodiments in which a single semiconductor die 200 and a dummy die 201 are attached to the first carrier 710 within each cell region UA1, embodiments in which two or more semiconductor dies 200 are attached to the first carrier 710 are explicitly contemplated herein. Further embodiments in which no dummy die 201 is used, or in which multiple dummy dies 201 are attached to the first carrier wafer 710 within each cell region UA1, are also explicitly contemplated herein.

[0016] Referring to Figure 2, an encapsulation of, for example, molding compound (MC) material can be applied to the gap between adjacent pairs of grains (200, 201) attached to the first carrier 710. The MC material may include an epoxy-containing compound that can be hardened (i.e., cured) to provide a dielectric portion with sufficient rigidity and mechanical strength. The MC material may include epoxy resin, hardener, silica (as a filler), and other additives. The MC material may be provided in liquid or solid form depending on viscosity and flowability. Liquid MC materials generally offer better workability, good flowability, fewer voids, better filling, and fewer flow marks. Solid MC materials generally offer less curing shrinkage, better isolation, and less grain drift. High filler content (e.g., 85% by weight) within the MC material can shorten molding time, reduce molding shrinkage, and reduce molding warpage. Uniform filler size distribution in the MC material can reduce flow marks and improve flowability.

[0017] The MC material can be cured at a curing temperature to form an MC matrix, referred to herein as the first MC matrix or grain-level MC matrix. The grain-level MC matrix may be a continuous material layer extending across the entire first carrier 710. Each portion of the grain-level MC matrix within the cell region UA1 constitutes a first molding compound framework, referred herein as a molding compound grain framework 205, or MC grain framework 205. Each MC grain framework 205 laterally surrounds a combination of at least one semiconductor die 200 and optionally at least one dummy die 201. A planarization process may be performed to remove portions of MC material covering a horizontal plane including the topmost surface of the semiconductor die 200. The top surfaces of the semiconductor die 200 and the dummy die 201 may be coplanar with the top surface of the grain-level MC matrix. The combination of the semiconductor die 200, the optional dummy die 201, and the grain-level MC matrix constitutes a reconstructed wafer. The reconstructed wafer may include a two-dimensional array of reconstructed dies. Each reconstructed die may be located within its respective cell region UA1 and may include at least one semiconductor die 200, at least one optional dummy die 201, and a molded compound die framework 205.

[0018] The illustrated exemplary structure corresponds to cell region UA1, which is the region comprising a single repeating cell within the reconstructed wafer. The combination of all material portions located within cell region UA1 and covering the die bonding film 711 constitutes composite die 290. Therefore, each composite die 290 includes at least one semiconductor die 200, at least one optional dummy die 201, and a molded compound die framework 205 (which is part of the grain-level MC matrix within cell region UA1).

[0019] Referring to Figure 3, a first redistribution line connector 340 formed in a first redistribution dielectric layer 330 can be formed over a reconstructed wafer including a two-dimensional array of composite grains 290. The first redistribution dielectric layer 330 comprises a respective dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric polymer materials may also be used. Each first redistribution dielectric layer 330 can be formed by spin-coating and drying its respective dielectric polymer material. The thickness of each first redistribution dielectric layer 330 can range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 20 micrometers. Each first redistribution dielectric layer 330 can be patterned, for example, by applying and patterning a respective photoresist layer thereon, and transferring the pattern from the photoresist layer to the first redistribution dielectric layer 330 using an etching process (e.g., anisotropic etching). The photoresist layer can then be removed, for example, by ashing.

[0020] Each first redistribution line connector 340 may be formed by sputtering a metal seed layer, applying and patterning a photoresist layer on the metal seed layer to form an opening pattern through the photoresist layer, electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between portions of the electroplated metal filler material. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness ranging from 50 nanometers to 300 nanometers, and the copper seed layer may have a thickness ranging from 100 nanometers to 500 nanometers. The metal filler material of the first redistribution line connector 340 may include copper, nickel, or a combination of copper and nickel. The thickness of the metal filler material deposited for each first redistribution line connector 340 may range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 10 micrometers, although smaller or larger thicknesses may also be used.

[0021] The topmost first redistribution line connector 340 may have a general shape of a metal pad, with a maximum lateral dimension ranging from 5 micrometers to 50 micrometers, for example from 10 micrometers to 40 micrometers, and / or from 15 micrometers to 30 micrometers, although smaller and larger maximum lateral dimensions may also be used. The lateral dimension of the bottom end of the via portion of the first redistribution line connector 340 may range from 2 micrometers to 10 micrometers, for example from 3 micrometers to 8 micrometers, although smaller and larger lateral dimensions may also be used. The total number of layers of the first redistribution line connector 340 may range from 1 to 20. The combination of the first redistribution line connector 340 and the first redistribution dielectric layer 330 within each unit region UA1 constitutes a redistribution structure, referred to herein as the first redistribution structure 320, for providing the formation of a fan-out bonding structure.

[0022] In one embodiment, the first redistribution structure 320 includes a line layer edge sealing ring structure 340E that laterally surrounds the entire first redistribution line connector 340. The line layer edge sealing ring structure 340E may include at least one rectangular frame-shaped structure without any lateral perforations. As used herein, a rectangular frame-shaped structure refers to a structure that laterally surrounds a volume having a rectangular horizontal cross-sectional shape in a plan view. Therefore, the portion of the first redistribution dielectric layer 330 located inside the line layer edge sealing ring structure 340E does not contact the portion of the first redistribution dielectric layer 330 located outside the line layer edge sealing ring structure 340E, and is laterally spaced from the portion of the first redistribution dielectric layer 330 located outside the line layer edge sealing ring structure 340E. The line layer edge sealing ring structure 340E may extend vertically from the bottom surface of the first redistribution dielectric layer 330 to the top surface of the first redistribution dielectric layer 330.

[0023] A first redistribution bump structure 354 and at least one peripheral bump structure 354E may be formed on the top layer of the first redistribution structure 320 within each unit region UA1. The first redistribution bump structure 354 and at least one peripheral bump structure 354E may be formed by depositing and patterning a metallic bonding material. In one embodiment, the first redistribution bump structure 354 and at least one peripheral bump structure 354E may comprise copper bump structures formed by depositing and patterning copper. In this embodiment, each top surface of the first redistribution bump structure 354 and at least one peripheral bump structure 354E may be formed in the same horizontal plane. The height of the copper bump structure may range from 20 micrometers to 100 micrometers, although smaller and larger heights are also possible.

[0024] At least one peripheral bump structure 354E may be formed directly on the top surface of the line layer edge sealing ring structure 340E. Each peripheral bump structure 354E may include a corresponding rectangular frame shape structure without any lateral perforations. The combination of the line layer edge sealing ring structure 340E and the peripheral bump structure 354E constitutes the first edge sealing ring structure (340E, 354E). The first edge sealing ring structure (340E, 354E) extends continuously in the peripheral region of the first redistribution structure 320 to provide at least one lateral closure structure, which may include multiple nested closure structures. The first edge sealing ring structure (340E, 354E) extends vertically from the bottommost first redistribution dielectric layer 330 to the topmost first redistribution dielectric layer 330. The lateral range of the first edge sealing ring structure (340E, 354E) in the radial direction (i.e., the lateral direction perpendicular to the nearest edge of the unit region UA1) can be between 3 micrometers and 30 micrometers, for example from 6 micrometers to 20 micrometers, although smaller and larger lateral dimensions are also possible.

[0025] The first redistributed bump structure 354 is then used to attach structural elements thereon. In one embodiment, the first redistributed bump structure 354 may include a first bump structure 3541 located in a central region and configured for bonding with a semiconductor die, and a second bump structure 3542 configured for engaging with a through-intermediate via (TIV) structure subsequently disposed thereon. The second bump structure 3542 is laterally offset relative to the first bump structure 3541 and located within the area enclosed by at least one peripheral bump structure 354E. The first bump structure 3541 may be configured for bonding with a semiconductor die. The second bump structure 3542 may be configured for engaging with a through-intermediate via (TIV) structure subsequently disposed thereon. Thus, each top surface of at least one peripheral bump structure 354E, the first bump structure 3541, and the second bump structure 3542 may be formed in the same horizontal plane.

[0026] In one embodiment, each first bump structure 3541 may have a lateral dimension or diameter ranging from 2 micrometers to 20 micrometers, for example from 4 micrometers to 10 micrometers, although smaller and larger diameters may also be used. In one embodiment, each second bump structure 3542 may have a lateral dimension or diameter ranging from 10 micrometers to 100 micrometers, for example from 20 micrometers to 60 micrometers, although smaller and larger diameters may also be used. Each peripheral bump structure 354E may have a width ranging from 10 micrometers to 200 micrometers (measured between the inner and outer sidewalls), for example from 20 micrometers to 100 micrometers, although smaller and larger widths may also be used.

[0027] Referring to FIG4, a through-intermediate via (TIV) structure 350 may be disposed on a second bump structure 3542. In this embodiment, the second bump structure 3542 may have a lateral dimension suitable for accommodating the TIV structure 350 (e.g., a dimension ranging from 10 micrometers to 60 micrometers). Each TIV structure 350 may have a circular or elliptical cylindrical shape. The maximum lateral diameter of each TIV structure 350 may range from 10 micrometers to 100 micrometers, although smaller and larger dimensions may also be used. The height of the TIV structure 350 may range from 30 micrometers to 300 micrometers, although smaller and larger heights may also be used. In one embodiment, the TIV structure 350, when disposed on the second bump structure 3542, is electrically connected to a corresponding one of the first redistribution line connectors 340.

[0028] Referring to Figure 5, a metal fracturing structure 360 ​​may be disposed on the first redistribution structure 320. Specifically, the metal fracturing structure 360 ​​may be directly disposed on the top surface of at least one peripheral bump structure 354E. The metal fracturing structure 360 ​​includes at least one metal pillar. The metal fracturing structure 360 ​​may have the same height as the TIV structure 350. The metal fracturing structure 360 ​​may include, and / or may be essentially composed of transition metals (e.g., W, Ta, Mo, Nb, Co, Ru, Cu, etc.). The metal fracturing structure 360 ​​may include a single metal pillar or multiple metal pillars. The lateral dimension of each metal pillar in the radial direction (i.e., any horizontal direction radiating outward from the geometric center of the first redistribution structure 320) may range from 10 micrometers to 200 micrometers, for example from 20 micrometers to 100 micrometers, although smaller and larger lateral dimensions may also be used.

[0029] In one embodiment, the metal crack-prevention structure 360 ​​may include at least one rectangular frame structure that continuously extends over the top surface of at least one peripheral protrusion structure 354E, covering the peripheral region of the first redistribution structure 320. Each rectangular frame structure may have no lateral openings and may laterally close its respective enclosed volume. In one embodiment, each rectangular frame structure may have the shape of its own rectangular frame, i.e., a frame having a set of inner sidewalls on the inner rectangular side in a plan view and a set of outer sidewalls on the outer rectangular side in a plan view.

[0030] Alternatively, the metal crack-prevention structure 360 ​​may include at least one set of discrete metal pillar structures, which are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320 on the top surface of at least one peripheral bump structure 354E. In this embodiment, each peripheral bump structure 354E may have its own frame shape (e.g., its own rectangular frame shape), and each set of metal pillar structures may be disposed on the top surface of its own peripheral bump structure 354E to substantially enclose the area also enclosed by its own peripheral bump structure 354E. Each metal pillar structure may have its own cylindrical shape. The horizontal cross-sectional shape of each cylinder may be circular, elliptical, rectangular, rounded rectangular, or L-shaped, etc.

[0031] Typically, a metal crack-blocking structure 360, including at least one metal pillar, may be disposed on the peripheral region of the first redistribution structure 320. In one embodiment, the metal crack-blocking structure 360 ​​may directly contact and be electrically connected to the first edge sealing ring structure (340E, 354E). The lateral extension of the metal crack-blocking structure 360 ​​in the radial direction (i.e., the lateral direction perpendicular to the lateral direction closest to the edge of the unit region UA1) may range from 3 micrometers to 30 micrometers, for example from 6 micrometers to 20 micrometers, although smaller and larger lateral dimensions may also be used.

[0032] Referring to Figures 6 and 7A-7J, the connecting grain 100 may be attached to the central region of the first redistribution structure 320 within each unit region UA1. In one embodiment, the connecting grain 100 may include a through-substrate via (TSV) grain, i.e., a TSV grain. As used herein, "through-substrate via grain" or "TSV grain" refers to a grain that includes a through-substrate via extending vertically through the substrate. The substrate through which the through-substrate via extends vertically is referred to herein as a "TSV substrate". The connection die 100 may include a through-substrate via (TSV) structure 120 formed within a TSV substrate 110, a connection die redistribution dielectric layer 150 located on a first side of the TSV substrate 110, a connection die redistribution line connector 160 formed within the connection die redistribution dielectric layer 150, an optional dielectric capping layer 111 located on a second side of the TSV substrate 110, a metal pad 122 contacting the end surface of the through-substrate via structure 120 and contacting the optional dielectric capping layer 111 (if present), and a mirror-patterned connection die bump structure 144 located on the metal pad and having a pattern of a first bump structure 3541. In one embodiment, the TSV substrate 110 may include a semiconductor substrate, such as a silicon substrate, with a thickness ranging from 5 micrometers to 20 micrometers. Tubular insulating spacers (not shown) may be provided around each through-substrate via structure 120. In one embodiment, the connecting die 100 may be temporarily supported by a temporary support substrate 101 structure, which may be bonded to the distal side of the connecting die 100 via an adhesive layer 103. The distal side of the connecting die 100 refers to the side of the connecting die 100 that includes the connecting die bump structure 144.

[0033] In an illustrative example, a two-dimensional array of connecting dies 100 may be formed on a support wafer (e.g., a silicon wafer). In this embodiment, a continuous adhesive layer having the same material composition and thickness as the adhesive layer 103 may be formed on the support wafer. The two-dimensional array of connecting dies 100 may be formed on the continuous adhesive layer, such that an array of connecting die bump structures 144 is formed on top. Solder portions 148 may be attached to the connecting die bump structures 144. The support wafer may be selectively thinned from the back side, for example, by grinding. The support wafer and the two-dimensional array of connecting dies 100 may be cut along a dicing channel to provide a combination of connecting dies 100 and temporary support substrates 101. Each temporary support substrate 101 is a cut portion of the support wafer. The combination of connecting dies 100 and temporary support substrates 101 may be indirectly bonded by solder, i.e., by reflowing and resolidifying the solder portions 148, to the array of first bump structures 3541.

[0034] Typically, the connecting die 100 is attached to the central region of the first redistribution structure 320. In one embodiment, the first redistribution structure 320 includes a first bump structure 3541 in the central region, the connecting die 100 includes a connecting die bump structure 144, and the connecting die 100 is indirectly attached to the first redistribution structure 320 via solder (i.e., through an array of solder portions 148) between the connecting die bump structure 144 and the first bump structure 3541. In one embodiment, the first bump structure 3541 may include copper pillars provided for die connection (C2) bonding, and the connecting die bump structure 144 may include additional copper pillars provided for die connection bonding. In other words, the first bump structure 3541 and the connecting die bump structure 144 may include microbump structures.

[0035] In one embodiment, the heights of the metal fracture-prevention structure 360 ​​and the TIV structure 350 can be selected such that the top surfaces of the metal fracture-prevention structure 360 ​​and the TIV structure 350 are located in or near a horizontal plane including the top surface of the connecting grain 100. The lateral extension of each metal fracture-prevention structure 360 ​​in the radial direction (i.e., the lateral direction perpendicular to the nearest edge of the unit region UA1) can range from 3 micrometers to 30 micrometers, for example from 6 micrometers to 20 micrometers, although smaller and larger lateral dimensions are also possible.

[0036] As described above, the metal crack-prevention structure 360 ​​can be formed in various configurations. For example, the metal crack-prevention structure 360 ​​may include at least one rectangular frame structure that extends continuously on the top surface of at least one peripheral protrusion structure 354E in the peripheral region of the first redistribution structure 320, and / or at least a set of separate metal pillar structures that are laterally spaced from each other and arranged along the top surface of at least one peripheral protrusion structure 354E in the peripheral region of the first redistribution structure 320. Figures 7A-7J are top views of various configurations of the example structure after the process steps of Figure 6.

[0037] Figure 7A illustrates a first example configuration of the metal crack-prevention structure 360, which includes a plurality of metal pillars laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320. Connecting dies 100 (on which a temporary support substrate 101 is disposed) overlap in area with semiconductor dies 200 (including die semiconductor substrate 210) and may or may not overlap in area with dummy dies 201. In one embodiment, each metal pillar may have a respective horizontal cross-sectional shape that is circular, elliptical, rectangular, or rounded rectangular. The sidewalls of the temporary support substrate 101 may be perpendicularly coincident with the sidewalls of the connecting dies 100. The connecting dies 100 are laterally surrounded by the metal crack-prevention structure 360 ​​when attached to the central region of the first redistribution structure 320.

[0038] Figure 7B illustrates a second example configuration of the metal crack-prevention structure 360, wherein the metal crack-prevention structure 360 ​​includes a rectangular metal frame covering the periphery of the first redistribution structure 320. The second example configuration can be derived from the first example configuration by using a single rectangular frame as the metal crack-prevention structure 360, instead of using multiple metal columns spaced laterally from each other.

[0039] Figure 7C illustrates a third example configuration of the metal crack-prevention structure 360, which includes a plurality of metal pillars laterally spaced from each other and arranged along the periphery of the first redistribution structure 320. The third example configuration can be derived from the first example configuration by changing the horizontal cross-sectional shape of the metal pillars to a rectangular or L-shaped shape. Alternatively, the third example configuration can be derived from the second example structure by dividing the rectangular frame shown in Figure 7B into multiple sections, such that each section of the rectangular frame becomes a separate metal pillar.

[0040] Figure 7D illustrates a fourth example configuration of the metal crack-prevention structure 360, which can be derived from the first example configuration by using a plurality of frame-shaped metal pillars. Each frame-shaped arrangement of metal pillars comprises a group of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the respective frame-shaped structures of the plurality of peripheral protrusion structures 354E. The frame-shaped arrangement of the metal pillars can be nested within each other.

[0041] Figure 7E illustrates a fifth example configuration of the metal crack-prevention structure 360, which can be derived from the third example configuration by using a plurality of frame-shaped metal pillars. Each frame-shaped arrangement of metal pillars comprises a group of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the respective frame-shaped structures of the plurality of peripheral protrusion structures 354E. The frame-shaped arrangement of the metal pillars can be nested within each other.

[0042] Figure 7F illustrates a sixth example configuration of the metal crack-prevention structure 360, which can be derived from the first and second example configurations by using the frame-shaped arrangement of metal pillars shown in Figure 7A and the rectangular metal frame shown in Figure 7B. The frame-shaped arrangement of metal pillars comprises groups of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the frame-shaped structure of the plurality of peripheral protrusion structures 354E. The frame-shaped arrangement of metal pillars and the rectangular metal frame can be nested. In the example shown, the frame-shaped arrangement surrounds the rectangular metal frame.

[0043] Figure 7G illustrates a seventh example configuration of the metal crack-prevention structure 360, which can be derived from the first and second example configurations by using the frame-shaped arrangement of metal pillars shown in Figure 7A and the rectangular metal frame shown in Figure 7B. The frame-shaped arrangement of metal pillars comprises groups of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the frame-shaped structure of the plurality of peripheral protrusion structures 354E. The frame-shaped arrangement of metal pillars and the rectangular metal frame can be nested. In the example shown, the rectangular metal frame surrounds the frame-shaped arrangement.

[0044] Figure 7H illustrates an eighth example configuration of the metal crack-prevention structure 360, which can be derived from the second and third example configurations by using the frame-like arrangement of metal pillars shown in Figure 7C and the rectangular metal frame shown in Figure 7B. The frame-like arrangement of metal pillars comprises groups of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the frame-like structure of the plurality of peripheral protrusion structures 354E. The frame-like arrangement of metal pillars and the rectangular metal frame can be nested. In the example shown, the frame-like arrangement surrounds the rectangular metal frame.

[0045] Figure 7I illustrates a ninth example configuration of the metal crack-prevention structure 360, which can be derived from the second and third example configurations by using the frame-shaped arrangement of metal pillars shown in Figure 7C and the rectangular metal frame shown in Figure 7B. The frame-shaped arrangement of metal pillars comprises groups of metal pillars that are laterally spaced from each other and arranged along the peripheral region of the first redistribution structure 320, covering and contacting the frame-shaped structure of the plurality of peripheral protrusion structures 354E. The frame-shaped arrangement of metal pillars and the rectangular metal frame can be nested. In the example shown, the rectangular metal frame surrounds the frame-shaped arrangement.

[0046] Figure 7J illustrates a tenth example setting of the metal crack-resistant structure 360, which can be derived from the second example setting by using multiple rectangular metal frames as multiple metal columns. The rectangular metal frames can be nested within each other.

[0047] Referring to Figure 8, the primer material can be applied to the gap between the connecting grain 100 and the first redistribution structure 320 to form the primer material portion 149.

[0048] Referring to Figure 9, the adhesive layer 103 can be decomposed, for example, by applying heat. In one embodiment, the example structure can be annealed above the decomposition temperature of the adhesive layer 103 material, which can be in the range of 200 to 250 degrees Celsius. The temporary support substrate 101 is separated from the connecting grains 100 in each unit region UA1. A suitable cleaning process can be performed to remove residual material from the substantially exposed top surface of each connecting grain 100.

[0049] Molding compound material can be applied around a two-dimensional array of connecting grains 100, a two-dimensional array of metal fracture-preventing structures 360, and a cluster of TIV structures 350. Molding compound material is applied around each connecting grain 100, each TIV structure 350, and each metal fracture-preventing structure 360. A planarization process can be performed to remove portions of the molding compound material above a planarization level. The planarization level refers to the level at which material is removed from the level above the connecting grains 100, TIV structures 350, and metal fracture-preventing structures 360, for example, by chemical mechanical polishing. The planarization level can be located at or below the lowest level of the level containing the top surface of the connecting grains 100, the top surface of the TIV structures 350, or the top surface of the metal fracture-preventing structures 360. In one embodiment, the top surface of the connecting grain 100, the top surface of the TIV structure 350, and the top surface of the metal crack-resistant structure 360 ​​may be formed in the same horizontal plane during the processing steps described with reference to Figures 4 to 7J, so as to minimize the incidental removal of the upper portions of the connecting grain 100, the TIV structure 350, and the metal crack-resistant structure 360 ​​during the planarization process.

[0050] Following the planarization process, the top surfaces of the connecting die 100, TIV structure 350, and metal crack-resistant structure 360 ​​are substantially exposed at the planarization plane. The remaining portion of the molding compound material comprises a molding compound interlayer matrix. Each portion of the molding compound interlayer matrix located within the cell region UA1 constitutes an encapsulation frame 305. Each encapsulation frame 305 laterally surrounds the corresponding cluster of connecting dies 100, the corresponding cluster of TIV structures 350, and the corresponding metal crack-resistant structure 360 ​​(which may include at least one continuous metal pillar in the shape of a frame and / or at least one arrangement of separate metal pillars in the shape of a frame). The top surfaces of the connecting die 100, TIV structure 350, metal crack-resistant structure 360, and encapsulation frame 305 can all be formed in the same horizontal plane, i.e., the planarization plane.

[0051] Referring to FIG10, a second redistribution structure 390 may be formed over each component of the connecting die 100, TIV structure 350, metal crack-resistant structure 360, and packaging frame 305. The second redistribution structure 390 includes second redistribution line connectors 380 formed in a second redistribution dielectric layer 370. Typically, the processing steps described with reference to FIG3 may be appropriately modified to form the second redistribution structure 390. In one embodiment, the TIV structure 350 may be electrically connected to the corresponding second redistribution line connector 380 during the formation of the second redistribution line connector 380.

[0052] In one embodiment, the second redistribution structure 390 includes a second edge sealing ring structure 380E that laterally encloses the entire second redistribution line connector 380. The second edge sealing ring structure 380E may include at least one rectangular frame-shaped structure without any lateral perforations. Therefore, the portion of the second redistribution dielectric layer 370 located inside the second edge sealing ring structure 380E does not contact the portion of the second redistribution dielectric layer 370 located outside the second edge sealing ring structure 380E and is spaced apart from the portion of the second redistribution dielectric layer 370 laterally located outside the second edge sealing ring structure 380E. The second edge sealing ring structure 380E may extend vertically from the bottom surface of the second redistribution dielectric layer 370 to the top surface of the second redistribution dielectric layer 370. The lateral extension range of the second edge sealing ring structure 380E in the radial direction (i.e., the lateral direction perpendicular to the nearest edge of the cell region UA1) may be between 3 micrometers and 30 micrometers, for example from 6 micrometers to 20 micrometers, although smaller and larger lateral dimensions are also possible. The combination of the first edge sealing ring structure (340E, 354E), the metal crack-blocking structure 360, and the second edge sealing ring structure 380E constitutes the intermediary layer edge protection assembly 365, which is composed of a metal structure and extends continuously around the periphery of the intermediary layer 300 to provide mechanical support to the peripheral area of ​​the intermediary layer 300. The metal crack-blocking structure 360 ​​may or may not have lateral openings, depending on the arrangement of the metal crack-blocking structure 360, i.e., whether the metal crack-blocking structure 360 ​​is formed as a single continuous metal column with a tubular arrangement or as multiple metal columns laterally spaced from each other.

[0053] A second redistribution bump structure 394 may be formed on the top layer of the second redistribution structure 390 within each unit region UA1. The second redistribution bump structure 394 may be formed by depositing and patterning a metallic bonding material. In one embodiment, the second redistribution bump structure 394 may include a copper bump structure formed by depositing and patterning copper. The second redistribution bump structure 394 may be formed as a microbump structure for wafer interconnect (C2) bonding, or as a metallic bonding pad for controlled collapse wafer interconnect (C4) bonding. Solder portions 398 may be attached to the second redistribution bump structure 394.

[0054] Each combination of the first redistribution structure 320, the connecting die 100, the TIV structure 350, the metal crack barrier structure 360, the package frame 305, the second redistribution structure 390, and auxiliary structures (such as solder portion 148 and undercoat material portion 149) located within the cell region UA1 constitutes the interposer layer 300. Each successive combination of the composite die 290 and the interposer layer 300 constitutes a composite package 800, which includes at least one bonding combination of semiconductor die 200 and interposer layer 300. Each group of the second redistribution bump structures 394 located on the interposer layer 300 is subsequently used to attach the interposer layer 300 to another structure. Therefore, the second redistribution bump structure 394 is also referred to as the metal bump structure 394 on the interposer layer.

[0055] Generally, the second redistribution structure 390 includes a second redistribution line connector 380 formed within the second redistribution dielectric layer 370 and located above the connection die 100, the metal break-barrier structure 360, and the encapsulation frame 305. An array of metal bump structures (such as metal bump structure 394 on the interposer) may be formed on the second redistribution line connector 380. The metal break-barrier structure 360 ​​is not an electrically active element and may therefore be electrically isolated from the metal bump structure array (such as metal bump structure 394 on the interposer). In one embodiment, the second redistribution structure 390 includes a second edge sealing ring structure 380E that extends continuously along the peripheral region of the second redistribution structure 390 and vertically extends from the bottommost second redistribution dielectric layer 370 to the topmost second redistribution dielectric layer 370. In one embodiment, the metal break-barrier structure 360 ​​is accessible and electrically connected to the second edge sealing ring structure 380E.

[0056] Referring to Figure 11, an adhesive layer 721 may be applied over the metal bump structure 394 and solder portion 398 on the interposer layer. A second carrier wafer 720 may be attached to a reconstructed wafer comprising a two-dimensional array of composite dies 290 and a two-dimensional array of interposers 300 stacked via the adhesive layer 721. A first carrier wafer 710 may be separated from the reconstructed wafer by inducing the decomposition of the die-attachment film 711. The substantially exposed back side of the composite dies 290 may be thinned, for example, by grinding or polishing. After thinning the composite dies 290, a suitable cleaning process may be performed on the back side of the composite dies 290.

[0057] Referring to Figure 12, the adhesive layer 721 can be decomposed, for example, by applying heat. In one embodiment, the example structure can be annealed above a temperature at which the adhesive layer 721 material decomposes, which can be in the range of 200 to 250 degrees Celsius. The second carrier wafer 720 is separated from the reconstructed wafer containing the two-dimensional array of the composite package 800. A suitable cleaning process can be performed to remove the substantially exposed top surface of the second redistribution structure 390 and residual material around the metal bump structure 394 and solder portion 398 on the interposer layer.

[0058] The reconstructed wafer is diced along the dicing channel DC. Generally, the metal dicing structures 360 are located next to the dicing channel DC within the edge region ER of their respective interposers 300. Therefore, when dicing the reconstructed wafer, each metal dicing structure 360 ​​is located near the sidewall of its respective composite package 800.

[0059] Referring to Figure 13, the diced composite package 800 is illustrated. The actual exposed sidewalls of the various components in the composite package 800 may be vertically coincident (i.e., located in the same vertical plane) because all components of the composite package 800 are provided by dicing and reconstructing the wafer.

[0060] Referring to FIG14, an in-process semiconductor interposer 600' is illustrated, which may be provided in a semiconductor wafer containing an array of in-process semiconductor interposers 600'. As used herein, an "in-process" element refers to an element whose material composition and / or shape is modified in at least one subsequent processing step. The illustrated wafer region corresponds to repeating cell region UA2, in which a single in-process semiconductor interposer 600' is provided. Each in-process semiconductor interposer 600' may be processed into a semiconductor interposer in a subsequent processing step.

[0061] An interposer semiconductor substrate 510 is illustrated, which is a portion of a semiconductor wafer located within a repeating cell region UA2. The repeating cell region UA2 in the semiconductor wafer is larger than the repeating cell region UA1 shown in Figures 1-6 and Figures 8-11. An insulating layer 611 may be formed on the top surface of the interposer semiconductor substrate 510. A combination of insulating spacers (not shown) and an interposer TSV structure 620 may be formed in each via by performing material deposition and planarization processes (e.g., chemical mechanical polishing). A silicon interposer metal bump structure 654 may be formed on the top surface of the interposer TSV structure 620. In one embodiment, a subset of the silicon interposer metal bump structure 654 may have a mirror pattern of the pattern of the metal bump structure 394 on the interposer.

[0062] Referring to Figure 15, the composite package 800 shown in Figure 13 can be bonded to the in-process semiconductor interposer 600' within each cell region UA2 of the semiconductor wafer. Additional semiconductor dies or additional semiconductor packages can be bonded to the in-process semiconductor interposer 600' simultaneously, before, or after bonding the composite package 800 to the in-process semiconductor interposer 600'. For example, at least one memory die 400, such as at least one high-bandwidth memory (HBM) memory die, can be provided. Each HBM memory die may include a vertical stack of memory layers 410 and a base layer 420 including logic circuitry for controlling the operation of the memory array in the memory layers 410. Each memory die 400 may include memory die bump structures 444 for bonding the respective memory die 400 to the in-process semiconductor interposer 600'. A molding compound frame 430 may laterally surround the vertical stack of memory layers 410 and the base layer 420. A combination of a composite package 800, a memory die 400, and a molded compound polydie framework 505 constitutes a polydie assembly 500. The polydie assembly 500 includes a group of at least one logic die (such as at least one semiconductor die 200), at least one memory die 400, and at least one interposer 300, and can be bonded to a semiconductor interposer 600' in the manufacturing process.

[0063] Referring to Figure 16, a base adhesive material portion 515 may be applied between the semiconductor interposer 600' and each of the composite package 800, additional semiconductor dies, and additional semiconductor packages in the process. A packaging material, such as a molding compound (MC) material, may be applied to the gaps between the composite package 800, additional semiconductor dies, and additional semiconductor packages bonded to the array of semiconductor interposers 600' in the process. The packaging material may contain any material suitable for the aforementioned molding compound die frame 205 or package frame 305. A planarization process may be performed to remove portions of the MC material covering the top surface of the composite package 800, additional semiconductor dies, and additional semiconductor packages. The top surfaces of the semiconductor dies 200 and dummy dies 201 may be coplanar with the top surface of the remaining portion of the MC material. The remaining portion of the MC material constitutes the molding compound matrix. Each portion of the molding compound matrix located within the cell region UA2 constitutes a molding compound polycrystal frame 505 laterally surrounding a plurality of semiconductor dies, referred to herein as the molding compound polycrystal frame 505. An array of semiconductor interposers 600', an interposer 300, a memory die 400, and a molding compound matrix constitute a reconstructed wafer. The reconstructed wafer may contain a two-dimensional array of reconstructed dies. Each reconstructed die may be located within its respective cell region UA2 and may contain the semiconductor interposer 600', a composite package 800, at least one memory die 400, and a molding compound polydie framework 505. The portion of the example structure shown corresponds to cell region UA2, i.e., the region containing a single repeating cell within the reconstructed wafer.

[0064] Referring to Figure 17, the reconstructed wafer can be thinned from the back side. Specifically, the back side portion of the semiconductor wafer containing the array of interposer semiconductor substrates 510 can be removed by a thinning process. The thinning process can use a grinding process, a polishing process, anisotropic etching process, and / or isotropic etching process. The thinning process can continue until the back side surface of the interposer TSV structure 620 is exposed. Subsequently, a back-side redistribution structure can be formed on the substantially exposed back side surface of the semiconductor wafer and the interposer TSV structure 620. The back-side redistribution structure may include a back-side redistribution dielectric layer 670 and back-side redistribution interconnects 680.

[0065] A back bump structure 694 may be formed on the last layer of the back-side redistribution line interconnect 680. The back bump structure 694 may include microbump structures or C4 bonding pads. A solder portion 698 may be formed on the back bump structure 694. After semiconductor wafer thinning and the formation of the back-side redistribution structure, the back bump structure 694, and the solder portion 698, the semiconductor interposer 600' in the process is converted into a semiconductor interposer, referred to herein as semiconductor interposer 600.

[0066] The reconstructed wafer can be diced along the dicing channel. Each diced portion of the reconstructed wafer contains a system-in-package structure, which includes a combination of a semiconductor interposer 600, a composite package 800, at least one memory die 400, and a molded compound polydie framework 505.

[0067] Referring to FIG18, a first flowchart illustrates the processing steps for forming an apparatus structure according to an embodiment of the present disclosure.

[0068] Referring to step 1810 and Figures 1 to 3, a first redistribution structure 320 can be provided, which includes a first redistribution line connector 340 formed in a first redistribution dielectric layer 330.

[0069] Referring to step 1820 and Figures 4 and 5, a metal crack-blocking structure 360 ​​containing at least one metal column may be disposed on the peripheral area of ​​the first redistribution structure 320.

[0070] Referring to step 1830 and Figures 6 and 7A to 7J, the connecting grain 100 can be attached to the central region of the first redistribution structure 320.

[0071] Referring to step 1840 and Figures 8 and 9, the encapsulation frame 305 may be formed around the connecting die 100 and the metal crack-resistant structure 360.

[0072] Referring to step 1850 and Figures 10 to 17, a second redistribution structure 390, including a second redistribution line connector 380 formed in the second redistribution dielectric layer 370, may be formed on the connecting die 100, the metal crack-resistant structure 360, and the encapsulation frame 305.

[0073] Referring to FIG19, a second flowchart illustrates the processing steps for forming an apparatus structure according to an embodiment of the present disclosure.

[0074] Referring to step 1910 and Figures 1 and 2, a composite grain 290 comprising at least one semiconductor grain 200 and a molded compound grain framework 205 is formed.

[0075] Referring to step 1920 and Figure 3, a first redistribution structure 320 may be formed on the composite die 290. The first redistribution structure 320 includes a first redistribution line connector 340 formed in a first redistribution dielectric layer 330 and electrically connected to a metal interconnect structure 222 in at least one semiconductor die 200.

[0076] Referring to step 1930 and Figures 4 and 5, a metal crack-blocking structure 360 ​​containing at least one metal column may be disposed on the peripheral area of ​​the first redistribution structure 320.

[0077] Referring to step 1940 and Figures 6 and 7A to 7J, the connecting grain 100 can be attached to the central region of the first redistribution structure 320.

[0078] Referring to step 1950 and Figures 8 to 17, the encapsulation frame 305 may be formed around the connecting die 100 and the metal crack-resistant structure 360.

[0079] Referring to FIG20, the third flowchart illustrates the processing steps for forming an apparatus structure according to an embodiment of the present disclosure.

[0080] Referring to step 2010 and Figures 1 and 2, a composite grain 290 comprising at least one semiconductor grain 200 and a molded compound grain framework 205 is formed.

[0081] Referring to step 2020 and Figure 3, the first redistribution structure 320 can be formed on the composite grain 290.

[0082] Referring to step 2030 and Figures 4 and 5, a metal crack-blocking structure 360 ​​containing at least one metal column may be disposed on the peripheral area of ​​the first redistribution structure 320.

[0083] Referring to step 2040 and Figures 6 and 7A to 7J, the connecting grain 100 can be attached to the central region of the first redistribution structure 320.

[0084] Referring to step 2050 and Figures 8 and 9, the encapsulation frame 305 may be formed around the connecting die 100 and the metal crack-resistant structure 360.

[0085] Referring to step 2060 and Figures 10 to 17, a second redistribution structure 390, including a second redistribution line connector 380 formed in the second redistribution dielectric layer 370, may be formed above the connecting die 100, the metal crack-resistant structure 360, and the encapsulation frame 305.

[0086] An embodiment of the present invention provides a method for forming an apparatus structure, comprising: providing a first redistribution structure, the first redistribution structure including a first redistribution line connector formed within a first redistribution dielectric layer; disposing a metal crack-blocking structure including at least one metal pillar above a peripheral region of the first redistribution structure; attaching a connecting die to a central region of the first redistribution structure; forming an encapsulation frame around the connecting die and the metal crack-blocking structure; and forming a second redistribution structure above the connecting die, the metal crack-blocking structure, and the encapsulation frame, the second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer.

[0087] In some embodiments, the method further includes forming an array of metal bump structures on the second redistribution line connector, wherein the metal crack-blocking structure is electrically isolated from the array of metal bump structures.

[0088] In some embodiments, wherein: the first redistribution structure includes a first edge sealing ring structure that extends continuously in the peripheral region of the first redistribution structure and extends vertically from the bottom layer of the first redistribution dielectric layer to the top layer of the first redistribution dielectric layer; and the metal crack-resistant structure is electrically connected to the first edge sealing ring structure.

[0089] In some embodiments, the second redistribution structure includes a second edge sealing ring structure that extends continuously along the peripheral region of the second redistribution structure and extends vertically from the bottom layer of the second redistribution dielectric layer to the top layer of the second redistribution dielectric layer; and the metal crack-resistant structure is electrically connected to the second edge sealing ring structure.

[0090] In some embodiments, the encapsulation frame is formed by: applying a molding compound material around the connecting grain and the metal crack-resistant structure; and performing a planarization process that removes a portion of the molding compound material above a planarization plane, such that the top surfaces of the connecting grain and the metal crack-resistant structure are substantially exposed on the planarization plane after the planarization process, wherein the remaining portion of the molding compound material comprises the encapsulation frame.

[0091] In some embodiments, wherein: the connecting grain includes a through-substrate via (TSV) grain; the first redistribution structure includes a first bump structure in a central region; the TSV-containing grain includes a connecting grain bump structure; and the TSV-containing grain is indirectly attached to the first redistribution structure via solder between the connecting grain bump structure and the first bump structure.

[0092] In some embodiments, wherein: the first redistribution structure further includes a second bump structure; and the method includes providing a through-intermediate via (TIV) structure on the second bump structure, wherein the encapsulation frame is formed around the TIV structure.

[0093] In some embodiments, wherein: when the TIV structure is disposed on the second bump structure, it is electrically connected to a corresponding one of the first redistribution line connectors; and when the TIV structure is formed in the second redistribution line connector, it is electrically connected to a corresponding one of the second redistribution line connectors.

[0094] An embodiment of the present invention provides a method for forming an apparatus structure, comprising: forming a composite grain, the composite grain comprising at least one semiconductor grain and a first molding compound matrix; forming a first redistribution structure on the composite grain, wherein the first redistribution structure comprises a first redistribution line connector formed within a first redistribution dielectric layer and electrically connected to a metal interconnect structure within the at least one semiconductor grain; disposing a metal crack barrier structure comprising at least one metal pillar above a peripheral region of the first redistribution structure; attaching a connecting grain to a central region of the first redistribution structure; and forming an encapsulation frame around the connecting grain and the metal crack barrier structure.

[0095] In some embodiments, wherein: the first redistribution structure includes a first bump structure located in a central region and at least one peripheral bump structure located in a peripheral region, the at least one peripheral bump structure having the same material composition as the first bump structure; each top surface of the at least one peripheral bump structure and the top surface of the first bump structure are formed in the same horizontal plane; the connecting grains are bonded to the first bump structure via an array of solder portions; and the at least one metal pillar is directly disposed on the at least one peripheral bump structure.

[0096] In some embodiments, wherein: the connecting grains include grains containing through-substrate vias (TSVs); the metal crack-blocking structure includes a plurality of metal pillars spaced laterally from each other; and the TSV-containing grains are laterally surrounded by the metal crack-blocking structure when attached to the central region of the first redistribution structure.

[0097] In some embodiments, the metal crack-blocking structure includes a rectangular frame covering the peripheral area of ​​the first redistribution structure.

[0098] In some embodiments, the invention further includes forming a second redistribution structure, the second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer above the connecting die, the metal crack-resistant structure and the packaging frame.

[0099] Referring to all the drawings and various embodiments disclosed herein, a packaging structure is provided, comprising: a first redistribution structure 320 including a first redistribution line connector 340 formed in a first redistribution dielectric layer 330; a metal crack barrier structure 360 ​​including at least one metal pillar disposed on a peripheral region of the first redistribution structure 320; a connecting die 100 attached to a central region of the first redistribution structure 320; a packaging frame 305 encapsulating the connecting die 100 and the metal crack barrier structure 360; and a second redistribution structure 390 including a second redistribution line connector 380 formed in a second redistribution dielectric layer 370 and located above the connecting die 100, the metal crack barrier structure 360, and the packaging frame 305.

[0100] In one embodiment, the packaging structure further includes an array of metal bump structures (e.g., metal bump structure 394 on the interposer) located on the second redistribution line connector 380, wherein the metal break-resistant structure 360 ​​is electrically isolated from the array of metal bump structures.

[0101] In one embodiment, the first redistribution structure 320 includes a first edge sealing ring structure (340E, 354E) that extends continuously along the peripheral region of the first redistribution structure 320 and extends vertically from the bottom first redistribution dielectric layer 330 to the top first redistribution dielectric layer 330; and the metal crack-resistant structure 360 ​​is electrically connected to the first edge sealing ring structure (340E, 354E).

[0102] In one embodiment, the second redistribution structure 390 includes a second edge sealing ring structure 380E that extends continuously along the peripheral region of the second redistribution structure 390 and extends vertically from the bottom second redistribution dielectric layer 370 to the top second redistribution dielectric layer 370; and the metal crack-resistant structure 360 ​​is electrically connected to the second edge sealing ring structure 380E.

[0103] In one embodiment, the top surface of the encapsulation frame 305, the top surface of the connecting die 100, and the top surface of the metal crack-blocking structure 360 ​​are located in a horizontal plane including the bottom surface of the second redistribution structure 390.

[0104] In one embodiment, the first redistribution structure 320 includes a first bump structure 3541 in the central region; the connecting die 100 includes a connecting die bump structure; and the connecting die 100 is indirectly attached to the first redistribution structure 320 by solder between the connecting die bump structure and the first bump structure 3541.

[0105] In one embodiment, the first redistribution structure 320 further includes a second bump structure 3542; a through-intermediate via (TIV) structure 350 is located on the second bump structure 3542 and embedded in the encapsulation frame 305; the TIV structure is electrically connected to a corresponding one of the first redistribution line connectors 340; and the TIV structure is electrically connected to a corresponding one of the second redistribution line connectors 380.

[0106] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the nature of this disclosure. Each embodiment described using the term "comprising" is also inherently disclosed, and the term "comprising" may be replaced in some embodiments with "substantially constitutes" or "consisting of," unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same or different paragraphs, the disclosure may also imply the inclusion of the Markus group comprising those two or more elements. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation or processing of an element, embodiments in which such an element or processing step is not performed are also explicitly contemplated, provided that the resulting apparatus or device provides an equivalent result. Therefore, when applied to the formation or processing of an element, the auxiliary verb "may" should also be interpreted as "may" or "may," or "may not," provided that omitting the formation of such an element or such processing step provides the same or equivalent result, including slightly better and slightly worse results. The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0107] 100: Connecting grains 101: Temporary support base 103, 721: Adhesive layer 110: TSV substrate 111: Optional dielectric capping layer 120: Through-substrate perforation structure 122: Metal Pad 144: Connecting Grain Bump Structure 148, 698: Solder section 149: Base Rubber Material Section 150: Connecting the grain redistribution dielectric layer 160, 340, 380: Redistribution line connectors 200, 201: Grain size 205: Grain framework 210: Grain semiconductor substrate 220: Semiconductor devices 222: Metal interconnect structure 224: Grain-side bonding pad 230: Dielectric material layer 290: Composite grains 300, 600, 600': Intermediate layer 305: Encapsulation Framework 320, 390: Redistributed Structure 330, 370: Redistributed dielectric layer 340E / 380E: Sealing ring structure 350: TIV structure / through-intermediate via structure 354, 394, 3541, 3542: convex structure 354E: Protrusion structure / Sealing ring structure 360: Metal Crack-Resistant Structure 365: Intermediate Layer Edge Protection Component 398: Solder section 400: Memory chip 410: Memory Layer 420: Grassroots 430: Molded compound framework 500: Polycrystalline module 505: Polycrystalline framework 510: Intermediate semiconductor substrate 611: Insulation layer 620: Intermediate Layer TSV Structure 654: Silicon Intermediate Metal Bump Structure 680: Internal connection of the back-side redistribution line 694: Backside bump structure 710: The First Carrier 711: Diode-to-Filler Film / DAF 720: Second carrier wafer 800: Composite Package DC: Cutting Channel ER: Edge region UA1, UA2: Area hd1: First horizontal direction

Claims

1. A method for forming an apparatus structure, comprising: A first redistribution structure is provided, the first redistribution structure including a first redistribution line connector formed within a first redistribution dielectric layer; a metal crack barrier structure including at least one metal pillar is disposed above a peripheral region of the first redistribution structure; a connector die is attached to a central region of the first redistribution structure; an encapsulation frame is formed around the connector die and the metal crack barrier structure; a second redistribution structure is formed above the connector die, the metal crack barrier structure, and the encapsulation frame, the second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer; and an array of metal bump structures is formed on the second redistribution line connector, wherein the metal crack barrier structure is electrically isolated from the array of metal bump structures.

2. The method as described in request item 1, wherein: The first redistribution structure includes a first edge sealing ring structure that extends continuously in the peripheral region of the first redistribution structure and extends vertically from the bottom layer of the first redistribution dielectric layer to the top layer of the first redistribution dielectric layer; and the metal crack-resistant structure is electrically connected to the first edge sealing ring structure.

3. A method for forming an apparatus structure, comprising: A composite die is formed, the composite die comprising at least one semiconductor die and a first molding compound matrix; a first redistribution structure is formed on the composite die, wherein the first redistribution structure includes a first redistribution line connector formed within a first redistribution dielectric layer and electrically connected to a metal interconnect structure within the at least one semiconductor die; a metal crack barrier structure including at least one metal pillar is disposed above a peripheral region of the first redistribution structure; a connecting die is attached to a central region of the first redistribution structure; and an encapsulation frame is formed around the connecting die and the metal crack barrier structure; a second redistribution structure is formed above the connecting die, the metal crack barrier structure, and the encapsulation frame, the second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer; and an array of metal bump structures is formed on the second redistribution line connector, wherein the metal crack barrier structure is electrically isolated from the array of metal bump structures.

4. The method as described in request item 3, wherein: The first redistribution structure includes a first bump structure located in the central region and at least one peripheral bump structure located in the peripheral region, the at least one peripheral bump structure having the same material composition as the first bump structure; each top surface of the at least one peripheral bump structure and the top surface of the first bump structure are formed in the same horizontal plane; the connecting grains are bonded to the first bump structure through an array of solder portions; And the at least one metal pillar is directly disposed on the at least one peripheral protrusion structure.

5. The method as described in request item 3, wherein: The connecting grains include grains containing through-substrate vias (TSVs); the metal crack-resistant structure includes a plurality of metal pillars spaced laterally from each other; and the TSV-containing grains are laterally surrounded by the metal crack-resistant structure when attached to the central region of the first redistribution structure.

6. The method of claim 3, wherein the metal crack-blocking structure includes a rectangular frame covering the peripheral region of the first redistribution structure.

7. A packaging structure, comprising: The first redistribution structure includes a first redistribution line connector formed within the first redistribution dielectric layer; A metal crack-blocking structure includes at least one metal pillar disposed above the peripheral region of the first redistribution structure; a connecting die attached to the central region of the first redistribution structure; an encapsulation frame encapsulating the connecting die and the metal crack-blocking structure; and a second redistribution structure including a second redistribution line connector formed within a second redistribution dielectric layer and located above the connecting die, the metal crack-blocking structure, and the encapsulation frame; and an array of metal bump structures located on the second redistribution line connector, wherein the metal crack-blocking structure is electrically isolated from the array of metal bump structures.

8. The encapsulation structure as described in claim 7, wherein: The first redistribution structure includes a first edge sealing ring structure that extends continuously along the peripheral region of the first redistribution structure and extends vertically from the bottom layer of the first redistribution dielectric layer to the top layer of the first redistribution dielectric layer; and the metal crack-resistant structure is electrically connected to the first edge sealing ring structure.

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