Display panel and display device including the same

Abstract

The embodiments disclose a display panel and a display device including the display panel. The display panel includes: a plurality of pixels; and gate lines and data lines connected to the plurality of pixels. Each of the plurality of pixels includes: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color. Each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line.

Description

Technical Field

[0001] This specification relates to a display panel and a display device comprising the display panel. Prior Technology

[0002] Organic light-emitting diode (OLED) displays reproduce images by allowing each pixel to emit light in response to an input image signal. OLED displays can have fast response times, high luminous efficiency, high brightness, and wide viewing angles, and can represent black as perfect grayscale, thus possessing excellent contrast ratio and color gamut. Such OLED displays do not require a backlight unit.

[0003] In recent years, microdisplay devices using light-emitting diodes (LEDs) as the light-emitting elements in pixels have attracted increasing attention as next-generation display devices. These LEDs are inorganic light-emitting elements manufactured in tiny sizes of about 100 μm or smaller. LEDs are made of inorganic materials and therefore do not require a separate encapsulation layer to protect organic materials from moisture, and they offer superior reliability and longer lifespan compared to OLEDs. Furthermore, LEDs can be quickly switched on and off, and possess high luminous efficiency and shock resistance.

[0004] The problem with these microdisplay devices is that two LEDs are connected in parallel in a single subpixel, so when one of the LEDs experiences a short circuit and dims, the other LED will also dim. Summary of the Invention

[0005] This specification relates to providing a display panel and a display device including the display panel, wherein the display panel allows another light-emitting element to emit light even when one of the light-emitting elements of a plurality of sub-pixels dims.

[0006] This specification also relates to providing a display panel in which light-emitting elements can be repaired and a display device including the display panel.

[0007] The purpose of this specification is not limited to the purposes described above, and other purposes not described above will be clearly understood from the following description by those skilled in the art.

[0008] According to one aspect of the present invention, a display panel is provided, comprising: a plurality of pixels; and gate lines and data lines connected to the plurality of pixels, wherein each of the plurality of pixels includes: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line. Simple Explanation of the Diagram

[0009] The above and other aspects, features, and advantages of the present invention will become more apparent to those skilled in the art by describing in detail the exemplary embodiments of the invention with reference to the accompanying drawings, wherein: Figure 1 is a block diagram schematically illustrating the configuration of a display device according to one embodiment of this specification; Figure 2 is a partial cross-sectional view illustrating the solder pad electrodes and side lines disposed on the outer periphery of the display panel according to an embodiment of this specification; Figure 3 is a perspective view illustrating a splicing display device according to an embodiment of this specification; Figure 4 is a plan view illustrating the planar structure of a display panel according to an embodiment of this specification; Figure 5 is a cross-sectional view illustrating the cross-sectional structure of a display panel according to one embodiment of this specification; Figure 6 is a diagram illustrating a pixel structure according to an embodiment of this specification; Figure 7 is a diagram illustrating a red sub-pixel according to one embodiment of this specification; Figure 8 is a diagram illustrating a green sub-pixel according to an embodiment of this specification; Figure 9 is a diagram illustrating a blue sub-pixel according to an embodiment of this specification; Figure 10 is a diagram illustrating the cathodes of the red, green, and blue sub-pixels; Figure 11 is a circuit diagram schematically illustrating a pixel circuit according to one embodiment of this specification; Figure 12 is a circuit diagram illustrating a pixel circuit according to another embodiment of this specification; Figure 13 is a waveform diagram of a pixel circuit according to another embodiment of this specification; Figure 14 is a diagram illustrating a pixel with a sub-pixel connected in parallel; Figure 15 is a diagram illustrating the sub-pixels of Figure 14; and Figures 16 and 17 are diagrams illustrating a repair method in a display panel according to an embodiment of this specification. Implementation

[0010] The advantages and features of the invention disclosed in this specification, as well as the methods for achieving such advantages and features, will be more clearly understood from the embodiments described below with reference to the accompanying drawings. The invention is not limited to the embodiments described below, but may be implemented in various different forms. The embodiments are provided merely to complete the invention and to fully provide the scope of the invention to those skilled in the art, and the invention will be defined by the appended claims.

[0011] In describing this invention, detailed descriptions of well-known techniques will be omitted when it is determined that such detailed descriptions may unnecessarily obscure the gist of the invention.

[0012] Terms such as “including,” “containing,” “having,” and “consisting of” used herein are intended to allow for the addition of other elements, unless such terms are used in conjunction with the term “only.” When a component is expressed in the singular, it may be interpreted as plural unless otherwise expressly stated.

[0013] When the location or interconnection between two components is described using terms such as "on," "above," "below," "next to," "connect or couple," "crossing or intersecting," and similar terms, one or more other components may be inserted between the two components, unless such terms are used with the terms "immediately" or "directly."

[0014] When describing temporal relationships using terms such as "after," "subsequent to," "next," "before," and similar terms, discontinuous situations may be included unless the terms "immediately" or "directly" are used.

[0015] Although ordinal numbers such as first, second and the like are used to distinguish components, the function or structure of such components is not limited to the ordinal number preceding the component or component name.

[0016] The following embodiments may be partially or wholly coupled or combined with each other, and may interoperate and be performed in various technical ways. Each of these embodiments may operate independently of each other, and may be implemented together in a related relationship.

[0017] In the embodiments of this specification, the pixel and display panel driving circuit includes a transistor. A transistor is a three-electrode element comprising a gate, a source, and a drain. The source is the electrode that provides carriers to the transistor. Carriers in the transistor begin to flow from the source. The drain is the electrode through which carriers exit the transistor to the outside. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, the carriers are electrons, and therefore the source voltage is lower than the drain voltage, causing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor, the carriers are holes, and therefore the source voltage is higher than the drain voltage, causing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed in position. For example, the source and drain can be interchanged depending on the applied voltage. Therefore, this specification is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0018] The gate signal can oscillate between the gate-on voltage and the gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be the gate-high voltage VGH, and the gate-off voltage can be the gate-low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be the gate-low voltage VGL, and the gate-off voltage can be the gate-high voltage VGH.

[0019] In the embodiments of this specification, the term "line" can be interpreted as wiring to which a signal or voltage is applied.

[0020] Unless otherwise defined and described, the terms (including technical and scientific terms) used in the embodiments of this specification may be interpreted in the meaning commonly understood by one of ordinary skill in the art, and commonly used terms (such as terms defined in a dictionary) may be understood taking into account their meaning in the context of the relevant art.

[0021] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0022] Referring to FIG1, the display device 100 includes: a display panel PN, including a display area AA in which a plurality of pixels are disposed; and a display panel driving circuit configured to drive the pixels.

[0023] The display panel PN can be a panel with a rectangular structure, having length in the X-axis direction, width in the Y-axis direction, and thickness in the Z-axis direction, but this specification is not limited to this. Each pixel contains a plurality of subpixels SP of different colors. The display area AA can be a screen viewed from the front of the display panel PN, on which the input image is displayed in the display panel PN.

[0024] The display panel driving circuit includes: a data driver DD; a gate driver GD; and a timing controller TC configured to control the gate driver GD and the data driver DD.

[0025] The input image is displayed on sub-pixels SP in the display area AA of the display panel PN. Each sub-pixel SP includes: a light-emitting element; and pixel circuitry configured to drive the light-emitting element. The light-emitting element may be a light-emitting diode (LED) or a micro-LED.

[0026] On the display panel PN, a plurality of gate lines SL and a plurality of data lines DL are provided to intersect each other. Each of the sub-pixels SP is connected to the gate line SL and the data line DL. The power lines, omitted from Figure 1, can be connected to each of the sub-pixels SP. In the display panel PN, the non-display area NA can be located outside the display area AA.

[0027] The gate driver GD supplies a gate signal to the gate line SL in response to a gate control signal provided by the timing controller TC. The gate driver GD can be located at least in the non-display area NA of the display panel PN as shown in Figure 1, or it can be located in the display area AA.

[0028] The data driver DD responds to the data control signal provided by the timing controller TC by converting the image data received from the timing controller TC into a gamma-compensated voltage to output a data voltage. The data voltage output from the data driver DD is supplied to the data line DL.

[0029] The timing controller TC aligns the externally input image data and supplies the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals based on timing signals synchronized with the input image signal (such as dot clock signals, data enable signals, and horizontal / vertical sync signals). The timing controller TC supplies the gate control signals and data control signals to the gate driver GD and the data driver DD respectively to control the operating timing of the gate driver GD and the data driver DD.

[0030] The link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA can be located in the non-display area NA. One or more of the gate driver IC integrating the gate driver GD circuitry and the data driver IC integrating the data driver DD circuitry can be located in the non-display area NA. The non-display area NA may include the rear surface of the display panel PN, i.e., the rear surface of the sub-pixels SP are not present there. The non-display area NA can be minimized to the point that it is invisible when an image is displayed on the display panel PN.

[0031] The display panel driving circuit can be connected to the display panel PN in various ways to drive pixels. For example, the gate driver GD can be set in the non-display area NA using the gate-in-panel (GIP) method, or between multiple sub-pixels SP in the display area AA using the gate-in-display area (GIA) method. The data driver DD and timing controller TC can be formed on a separate flexible film and printed circuit board (PCB), and can be electrically connected to the display panel PN by bonding the terminals of the flexible film to the pad electrodes formed in the non-display area NA of the display panel PN. The flexible film bonded to the display panel PN can be connected to the PCB on which circuit elements are mounted and formed into lines.

[0032] Side lines used to connect signal lines on the front surface of the display panel PN to pad electrodes on the rear surface of the display panel PN can be formed on the outer peripheral surface of the display panel PN. The method of electrically connecting the front and rear surfaces of the display panel PN via side lines minimizes the non-display area NA as viewed from the front surface of the display panel PN. In Figure 2, "SRL" represents a side line. When the gate driver GD, data driver DD, and timing controller TC are electrically connected to the display panel PN using the method described above, a virtually borderless screen can be implemented on the display panel PN.

[0033] Referring to Figure 2, a plurality of pad electrodes for transmitting various signals to the sub-pixel SP are disposed in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to the sub-pixel SP can be disposed in the non-display area NA, which is located on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to circuit elements such as flexible films and PCBs is disposed in the non-display area NA, which is located on the rear surface of the display panel PN. The non-display area NA on the outer periphery of the front surface of the display panel PN on which the image is displayed can be minimized in size by providing only the pad area, in which the first pad electrode PAD1 is disposed.

[0034] Various signal lines connected to the sub-pixel SP, such as gate line SL or data line DL, can extend to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0035] The display panel PN may include a side line SRL disposed on the outer peripheral surface of the display panel PN. The side line SRL electrically connects a first pad electrode PAD1 to a second pad electrode PAD2, spanning the side surface of the display panel PN. The first pad electrode is disposed on the outer periphery of the front surface of the display panel PN, and the second pad electrode is disposed on the outer periphery of the rear surface of the display panel PN. Signals output from circuit elements disposed on the rear surface of the display panel PN can be transmitted via the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1 to the sub-pixel SP and gate driver GD in the display area AA. Therefore, the area of ​​the non-display area NA on the front surface of the display panel PN can be minimized by forming signal transmission paths spanning the outer peripheries of the front, side, and rear surfaces of the display panel PN.

[0036] A plurality of display modules can be combined on a plane to implement a large-screen splicing display device. Each of the display modules can be implemented as a single display device, and the combination of the plurality of display modules can be implemented as a large-screen splicing display device. Each of the display modules includes: a display panel PN; a driving circuit for the display panel PN; and circuit elements and module cover components coupled to the rear surface of the display panel PN.

[0037] Referring to Figure 3, the large-screen splicing display device TD includes a plurality of display modules disposed on the XY plane. Each of these display modules includes a display panel PN for reproducing an input image. The large-screen image can be reproduced when the non-display area NA is minimized at the outer periphery of the front surface of each of the display panels PN, wherein there are no visible seams between adjacent display panels PN.

[0038] Display panels PN can be assembled on a plane such that the separation distance D1 between the outermost pixel PX of one display panel PN and the outermost pixel PX of another display panel PN adjacent to it is substantially equal to the separation distance D2 between adjacent pixels PX in the display area AA of the display panel PN. Therefore, the separation distances D1 and D2 between adjacent pixels PX are equal across the large screen display area of ​​the splicing display device TD, thereby ensuring that no seam area is visually discernible.

[0039] In this splicing display device TD, multiple display modules can share a single timing controller TC. The host system can connect to multiple timing controllers TC to transmit and synchronize the video signals to be reproduced on all display panels PN of the large-screen splicing display device TD.

[0040] Figure 4 is a plan view schematically illustrating the planar structure of a display panel according to one embodiment of this specification.

[0041] Referring to Figure 4, the display panel PN includes a substrate SUBS on which a pixel array and gate driver GD circuitry are disposed. The display panel PN can be a panel with a rectangular structure, having a length in the column direction (X-axis direction), a width in the row direction (Y-axis direction), and a thickness in the thickness direction (Z-axis direction), but this specification is not limited thereto.

[0042] A substrate SUBS can be an insulating substrate that supports components disposed on the upper part of a display device. A substrate SUBS can have a structure in which a plurality of substrates are stacked. A substrate SUBS can be made of glass, polymer resin, or plastic substrate.

[0043] On one surface (or front surface) of the substrate SUBS, the display area AA may include: a plurality of pixel areas UPA; a plurality of gate drive areas GA; and a plurality of pad areas PA1 and PA2. One or more pixels PX may be disposed in each of the pixel areas UPA. The pixel areas UPA may be disposed along a plurality of column lines and a plurality of row lines. Each of the pixels PX includes a plurality of subpixels SP of different colors. Each of the subpixels SP includes a light-emitting element and pixel circuitry, and therefore can emit light independently. The subpixels SP may include red subpixels, blue subpixels, green subpixels, and the like, but this specification is not limited thereto.

[0044] A plurality of gate drive regions GA contain circuitry for gate drivers GD. The gate drive regions GA can be formed between a plurality of pixel regions UPA in the column direction and / or row direction. The gate drivers GD formed in the gate drive regions GA can provide gate signals to a plurality of gate lines SL. The gate drive regions GA can be positioned between adjacent pixel regions UPA in the column direction (X-axis direction).

[0045] The first pad area PA1 includes a plurality of first pad electrodes PAD1 disposed on the outer periphery of the front surface of the display panel PN on one side (or the top side). The first pad electrodes PAD1 can transmit various signals to various lines extending in the row direction within the display area AA. The first pad electrodes PAD1 include: a data pad DP, connected to a data line DL to transmit a data voltage output from a data driver DD to the data line DL; and a gate pad GD, connected to a gate driver GD to transmit clock signals, start signals, gate low voltage, gate high voltage, and the like to the gate driver GD to drive the gate driver GD. The clock signals, start signals, gate low voltage, gate high voltage, and the like used to drive the gate driver GD can be generated by a timing controller TC and applied to the gate pad GP via a level shifter and the PCB. The first pad electrodes PAD1 may include a plurality of power lines to which a direct current (DC) voltage (or a constant voltage) is applied.

[0046] The substrate (SUBS) of the display panel PN includes: gate drive lines connected to gate pads (GP) in the row direction; and a plurality of gate drive lines (GVL) extending in the column direction. The gate drive lines in the row direction can be connected to the gate drive lines (GVL) in the column direction via contact holes through an insulating film. The gate drive lines (GVL) transmit signals (such as clock signals, start signals, gate high voltage, gate low voltage, and the like) necessary to drive the gate drivers (GD) distributed in the gate drive regions (GA) to the circuitry of the gate drivers (GD).

[0047] The second pad region PA2 includes a plurality of second pad electrodes PAD2 disposed on the outer periphery of the front surface on the other side (or underside) of the display panel PN. The second pad region PA2 may include a plurality of low-potential power pads VP2.

[0048] The DC voltage applied to the power line can be output from the power circuit (omitted in the diagram) and applied to the power pads VP1 and VP2 connected to the power line via the PCB. The power circuit can be a DC-DC converter, which is disposed on the PCB or control boards CTB1 and CTB2 located on the rear surface of the display panel PN, and converts the DC input voltage output from the main power supply into a DC voltage suitable for driving the display panel PN.

[0049] The power pads VP1 and VP2 connected to the power line may include: a plurality of high-potential power pads VP1 disposed on a first pad area PA1 to transmit high-potential power voltage to high-potential power line VL1; and a plurality of low-potential power pads VP2 disposed on a second pad area PA2 to transmit low-potential power voltage to low-potential power line VL2.

[0050] The data pads DP, which are connected one-to-one to the data line DL, can each have a relatively narrow width, while the power pads VP1 and VP2 and the gate pad GP can each have a relatively wide width. The low-potential power pad VP2 can each have a wider width than each of the high-potential power pads VP1.

[0051] To minimize the outermost non-display area NA of the display panel PN, pixel arrays, lines, and pads are formed on the front surface of the substrate of the display panel PN, and then the outermost portion extending beyond the scribe line SCL indicated by the dashed line is removed, enabling the fabrication of a substrate SUBS with a minimized non-display area NA. After the scribe process, the rough edges on the outer periphery of the substrate SUBS can be ground or laser-trimmed. Short pad electrodes PAD1 and PAD2 are retained on the outer periphery of the front surface of the substrate SUBS, and these short pad electrodes have been correspondingly reduced in size.

[0052] Data lines DL can extend on the substrate SUBS in the row direction (Y direction) and overlap with the pixel region UPA. Data lines DL supply data voltage to the pixel circuitry of each sub-pixel SP. Gate lines SL can extend on the substrate SUBS of the display panel PN in the column direction (X direction) and overlap with the pixel region UPA and the gate drive region GA. Gate lines SL can cross the pixel region UPA and the gate drive region GA and supply the gate signal output from the gate driver GD to the pixel circuitry of each sub-pixel SP.

[0053] A high-potential power line VL1 extends in the row direction (Y direction), and one or more of it are connected in a mesh structure to an auxiliary high-potential power line AVL1 extending in the column direction (X direction). The auxiliary high-potential power line AVL1 is connected to the sub-pixel SP disposed in the column direction (X direction). Therefore, the high-potential power supply voltage applied to the high-potential power line VL1 can be transmitted to the sub-pixel SP via the auxiliary high-potential power line AVL1.

[0054] Low-potential power lines VL2 extend in the row direction (Y direction), and one or more of them are connected in a mesh structure to auxiliary low-potential power lines AVL2 extending in the column direction (X direction). The auxiliary low-potential power lines AVL2 are connected to sub-pixels SP located in the column direction (X direction). Therefore, sub-pixels SP are connected to the auxiliary low-potential power lines AVL2 to which the low-potential power supply voltage is applied.

[0055] Due to the mesh structure of the power cord, the resistance of the power cord can be reduced, which can reduce the voltage drop across high-potential power supply voltages and the variation of power supply voltage within the display area AA.

[0056] The substrate SUBS of the display panel PN may include one or more alignment keys AK1 and AK2 disposed between pixel regions UPA. Alignment keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The first alignment key AK1 may be disposed in the gate drive region GA. The first alignment key AK1 is used to check the alignment position of each of the light-emitting elements. The first alignment key AK1 may be formed in a cross pattern, but this specification is not limited thereto. The second alignment key AK2 may overlap with the high-potential power line HL. The high-potential power line HL may be distinguished from the second alignment key AK2 by including a hole formed at the location where it overlaps with the second alignment key AK2. The second alignment key AK2 is used to align the display panel PN with the donor substrate. The donor substrate is an intermediate medium for mounting light-emitting elements on the substrate SUBS of the display panel PN. A plurality of light-emitting elements manufactured on a semiconductor wafer may be attached and transferred to the donor substrate, and the light-emitting elements attached to the donor substrate may be transferred to the substrate SUBS. The second alignment key AK2 may be formed in a circular or annular pattern, but this specification is not limited thereto.

[0057] Figure 5 is a cross-sectional view illustrating the cross-sectional structure of a display panel according to an embodiment of the present invention.

[0058] Referring to Figure 5, a pixel circuit for driving the light-emitting element ED is disposed in each of the plurality of sub-pixels SP of the first substrate SUBS1. The pixel circuit may include a plurality of thin-film transistors and one or more capacitors. For ease of illustration, the driving element DT, the first capacitor C1, and the second capacitor C2 for the pixel circuit are described, but the display panel PN may further include other circuit elements.

[0059] The pattern of the first metal layer can be disposed on the first substrate SUBS1. The pattern of the first metal layer can include a light blocking layer BSM. The light blocking layer BSM can minimize leakage current by blocking light incident on the active layer ACT of the driving element DT. The light blocking layer BSM can be formed of an opaque conductive material, such as metals such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), alloys of such metals, or multilayer metal layers.

[0060] The buffer layer BUF can be disposed on the light blocking layer BSM. The buffer layer BUF can prevent moisture or impurities from penetrating the first substrate SUBS1. The buffer layer BUF can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple insulating layers.

[0061] The driving element DT, which includes the active layer ACT, gate electrode GE, source electrode SE, and drain electrode DE, can be placed on the buffer layer BUF.

[0062] The active layer ACT can be made of semiconductor materials such as oxide semiconductors, amorphous silicon, or polycrystalline silicon, but the invention is not limited thereto. The gate insulating layer GI electrically insulates the active layer ACT of the driving element DT from the gate electrode GE. The gate insulating layer GI can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer insulating layer.

[0063] The pattern of the second metal layer can be set on the gate insulating layer GI. The pattern of the second metal layer can include the gate electrode GE of the driving element DT. The second metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multiple metal layers.

[0064] First interlayer insulating layer ILD1 and second interlayer insulating layer ILD2 are disposed on the gate electrode GE. Contact holes are formed in first interlayer insulating layer ILD1 and second interlayer insulating layer ILD2 for each of the source electrode SE and drain electrode DE of the driving element DT to connect to the active layer ACT. Each of first interlayer insulating layer ILD1 and second interlayer insulating layer ILD2 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple insulating layers.

[0065] The pattern of the third metal layer can be disposed on the second interlayer insulating layer ILD2. The pattern of the third metal layer can include a source electrode SE and a drain electrode DE, which overlap with the active layer ACT and are connected to the active layer ACT through contact holes passing through the interlayer insulating layers ILD1 and ILD2. The source electrode SE can be connected to capacitors C1 and C2 and the first electrode E1 of the light-emitting element ED. The third metal layer can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multiple metal layers.

[0066] The first capacitor C1 includes: a first capacitor electrode C1a; and a second capacitor electrode C1b. The first capacitor electrode C1a may be formed as a pattern of a second metal layer disposed on the gate insulating layer GI. The second capacitor electrode C1b is formed as a pattern of a fourth metal layer disposed on the first interlayer insulating layer ILD1, and overlaps with the first capacitor electrode C1a, wherein the first interlayer insulating layer ILD1 is interposed between the second capacitor electrode and the first capacitor electrode. The second capacitor electrode C1b may be connected to the source electrode SE of the driving element DT. The fourth metal layer may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multiple metal layers.

[0067] The second capacitor C2 includes a third capacitor electrode C2a that overlaps with the first capacitor electrode C1a, wherein a buffer layer BUF and a gate insulating layer GI are inserted between the first capacitor electrode and the third capacitor electrode. The third capacitor electrode C2a may be formed as a pattern of a first metal layer disposed on the first substrate SUBS1.

[0068] The second capacitor C2 is electrically connected between the source electrode SE of the driving element DT and the light-emitting element ED to increase the capacitance of the light-emitting element ED, which can increase the brightness when the light-emitting element ED emits light.

[0069] The first passivation layer PAS1 covers the pattern of the third metal layer and the second interlayer insulating layer ILD2 so as to overlap with the pattern of the third metal layer. The first passivation layer PAS1 can be formed of silicon oxide (SiOx), silicon nitride (SiNx) or multiple insulating layers.

[0070] A first planarization layer PLN1 is disposed on a first passivation layer PAS1. The first planarization layer PLN1 covers the first passivation layer PAS1 to planarize the surface on which the light-emitting element is disposed. The first planarization layer PLN1 may be a thick, single-layer or multi-layer organic insulating layer made of phenylcyclobutene or acrylic-based organic materials.

[0071] The pattern of the fifth metal layer can be formed on the first planarization layer PLN1. The pattern of the fifth metal layer can include a reflective layer RF. The reflective layer RF reflects light from the light-emitting element ED toward the front surface of the display panel PN to increase light efficiency and can be used as an electrode to connect the light-emitting element ED to the pixel circuit or power line. The reflective layer RF can be electrically connected to the source electrode SE of the driving element DT and the first capacitor C1 through the contact hole CH1 passing through the first planarization layer PLN1 and the first passivation layer PAS1. In addition, the reflective layer RF can be electrically connected to the first electrode E1 of the light-emitting element ED through the anode AND, or the second electrode E2 of the light-emitting element ED can be electrically connected to the high-potential power line HL. The fifth metal layer can be formed of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), a transparent electrode material such as indium tin oxide (ITO), or a multilayer metal layer.

[0072] The second passivation layer PAS2 covers the pattern of the fifth metal layer and the first planarization layer PLN1. The second passivation layer PAS2 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple insulating layers.

[0073] An adhesive layer AD can be disposed on the second passivation layer PAS2 to fix the light-emitting element ED. The adhesive layer AD can be formed of a photocurable resin. The adhesive layer AD can be formed of an acrylic-based material containing a photosensitizer, but the present invention is not limited thereto. The adhesive layer AD can be formed on the entire surface of the first substrate SUBS1, excluding the pad regions PA1 and PA2 where the first pad electrode PAD1 is to be disposed.

[0074] Each of the sub-pixels SP has a light-emitting element ED disposed on an adhesive layer AD. Each of the light-emitting elements ED can emit light through current from a driving element DT. The light-emitting elements ED can include red light-emitting elements ED, green light-emitting elements ED, and blue light-emitting elements ED. The light-emitting elements ED can be LEDs or micro-LEDs.

[0075] Each of the light-emitting elements (EDs) includes: a first semiconductor pattern (SEM1); a light-emitting layer (EM); a second semiconductor pattern (SEM2); a first electrode (E1); and a second electrode (E2).

[0076] A first semiconductor pattern SEM1 is disposed on an adhesive layer AD, and a second semiconductor pattern SEM2 is disposed on the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 can be formed as semiconductor patterns obtained by doping semiconductor materials with n-type and p-type impurities. For example, each of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 can be a layer formed by doping materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), and the like with n-type or p-type impurities. Furthermore, the p-type impurity can be magnesium, zinc (Zn), beryllium (Be), or the like, while the n-type impurity can be silicon (Si), germanium, tin (Sn), or the like, but the invention is not limited thereto.

[0077] An emitting layer EM is disposed between a first semiconductor pattern SEM1 and a second semiconductor pattern SEM2. The emitting layer EM emits light by receiving holes and electrons from the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The emitting layer EM can be formed as a single layer or a multi-quantum well (MQW) structure, and can be formed from, for example, indium gallium nitride (InGaN), gallium nitride (GaN), or similar materials.

[0078] A first electrode E1 is disposed on a first semiconductor pattern SEM1. The first electrode E1 electrically connects the driving element DT to the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 may be formed from a semiconductor layer doped with n-type impurities. The first electrode E1 may be the anode of a light-emitting element ED, disposed on the first semiconductor pattern SEM1, and electrically connected to the driving element DT and capacitors C1 and C2 via a reflective layer RF. The first electrode E1 may be disposed on the upper surface of the first semiconductor layer SEM1. The first electrode E1 may be formed from a conductive material, such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0079] The second electrode E2 is disposed on the second semiconductor pattern SEM2. The second electrode E2 electrically connects the high-potential power line HL to the second semiconductor layer SEM2. The second semiconductor layer SEM2 can be formed as a semiconductor layer doped with p-type impurities. The second electrode E2 can be the cathode CAT of the light-emitting element ED. The second electrode E2 can be formed of a conductive material, such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0080] The light-emitting element (ED) may include a packaging layer (ENS). The ENS covers semiconductor patterns SEM1 and SEM2, as well as electrodes E1 and E2, to protect the ED. The ENS and the third planarization layer (PLN3) include contact holes exposing the first electrode E1 and the second electrode E2. The anode (AND) is connected to the reflective layer (RF) through the first contact hole passing through the ENS and PLN3. The cathode (CAT) is connected to the second electrode E2 through a second contact hole passing through the ENS and PLN3. Meanwhile, a portion of the side surface of the first semiconductor pattern SEM1 can be exposed because the ENS is not present on it.

[0081] The second planarization layer PLN2 and the third planarization layer PLN3 can cover the adhesive layer AD and the light-emitting element ED. The second planarization layer PLN2 contacts and fixes the light-emitting element ED to the lower end of its side surface. The third planarization layer PLN3 covers the light-emitting element ED on the second planarization layer PLN2. The third planarization layer PLN3 includes contact holes that expose the first electrode E1 and the second electrode E2 of the light-emitting element ED. The second planarization layer PLN2 and the third planarization layer PLN3 can be formed from a single layer or multiple layers of organic insulating material (e.g., photoresist or acrylic-based organic material).

[0082] The pattern of the sixth metal layer can be set on the third planarization layer PLN3. The sixth metal layer can include an anode AND and a cathode CAT. The anode AND electrically connects the first electrode E1 of the light-emitting element ED to the reflective layer RF. The anode AND can be connected to the first electrode E1 of the light-emitting element ED through contact holes passing through the insulating layers PLN3 and ENS, and can be connected to the reflective layer RF through contact holes passing through the insulating layers PAS2, AD, PLN2 and PLN3.

[0083] The cathode CAT is connected to the second electrode E2 of the light-emitting element ED through a contact hole passing through the insulating layers PLN3 and ENS. The cathode CAT can be connected to the low-potential power line CL.

[0084] According to an embodiment, the light-emitting element ED is shown as a horizontal structure having electrodes connected to the upper surfaces of a first semiconductor pattern SEM1 and a second semiconductor pattern SEM2, but the invention is not necessarily limited thereto. As an example, the light-emitting element ED may have a vertical structure in which the anode AND is disposed below the first semiconductor pattern SEM1.

[0085] The embankment pattern BB can be disposed on the second planarization layer PLN2. The embankment pattern BB can be spaced apart from the light-emitting element ED by a certain distance. The embankment pattern BB can cover the portion of the anode AND present in the contact holes passing through the insulating layers PLN2 and PLN3. The embankment pattern BB can prevent optical crosstalk between sub-pixels SP to reduce color mixing between sub-pixels SP. For this purpose, the embankment pattern BB can be formed of black resin, but the present invention is not limited thereto.

[0086] The first protective layer CPA can cover the sixth metal layer, the shoreline pattern BB, the second planarization layer PLN2, and the third planarization layer PLN3. The first protective layer CPA can be formed from a single layer of transparent epoxy resin, silicon oxide (SiOx) or silicon nitride (SiNx), multiple insulating layers, or the like.

[0087] Each of the first pad electrodes PAD1 disposed in the pad regions PA1 and PA2 of the first substrate SUBS1 may have a multilayer metal layer structure. For example, each of the first pad electrodes PAD1 may include a first pad metal layer PE1a, a second pad metal layer PE1b, and a third pad metal layer PE1c stacked on the outermost periphery of the front surface of the first substrate SUBS1.

[0088] The pattern of the third metal layer disposed on the second interlayer insulating layer ILD2 may further include a first pad metal layer PE1a. The first pad metal layer PE1a may be formed of the same metal as the source electrode SE and drain electrode DE of the drive element DT, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer.

[0089] The pattern of the fifth metal layer disposed on the first planarization layer PLN1 may further include a second pad metal layer PE1b. The second pad metal layer PE1b may be formed of the same metal as the reflective layer RF, such as silver (Ag), aluminum (Al), molybdenum (Mo), or a multilayer metal layer.

[0090] The pattern of the sixth metal layer disposed on the third planarization layer PLN3 may further include a third pad metal layer PE1c. The third pad metal layer PE1c may be formed of the same conductive material as the anode AND and cathode CAT, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multilayer metal layer.

[0091] A first metal layer ML1, a second metal layer ML2, and a plurality of insulating layers can be disposed beneath the first pad electrode PAD1. By disposing the first metal layer ML1, the second metal layer ML2, and the plurality of insulating layers beneath the first pad electrode PAD1, the step difference of the first pad electrode PAD1 can be adjusted. For example, a buffer layer BUF, a gate insulating layer GI, a first metal layer ML1, a first interlayer insulating layer ILD1, and a second metal layer ML2 can be sequentially disposed between the first pad electrode PAD1 and the first substrate SUBS1. The pattern of the second metal layer disposed on the gate insulating layer GI can include the first metal layer ML1. The pattern of the fourth metal layer disposed on the first interlayer insulating layer ILD1 can include the second metal layer ML2. The plurality of insulating layers beneath the first pad electrode PAD1 and the metal layers ML1 and ML2 are not limited to those layers shown in FIG. 5.

[0092] The second substrate SUBS2 can be disposed on the rear surface of the first substrate SUBS1. A bonding layer BDL is disposed between the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL is cured by various curing methods to bond the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL can be disposed only in a portion or the entire area between the first substrate SUBS1 and the second substrate SUBS2. The first substrate SUBS1 and the second substrate SUBS2 can be simultaneously diced and ground, so that the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 can be formed without steps.

[0093] A plurality of second pad electrodes PAD2 may be disposed on the outermost periphery of the rear surface of the second substrate SUBS2. The second pad electrodes PAD2 are electrically connected to the side line SRL and the first pad electrode PAD1 to transmit signals from circuit elements disposed on the rear surface of the second substrate SUBS2 to the sub-pixel SP disposed on the upper surface of the first substrate SUBS1.

[0094] Each of the second pad electrodes PAD2 can have a multilayer metal structure. For example, each of the second pad electrodes PAD2 can include a first pad metal layer PE2a, a second pad metal layer PE2b, and a third pad metal layer PE2c stacked on the outermost periphery of the back surface of the second substrate SUBS2. Each of the first pad metal layer PE2a and the second pad metal layer PE2b can be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal. The third pad metal layer PE2c can be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0095] The second protective layer (BCL) can be disposed on the rear surface of the second substrate SUBS2. The second protective layer (BCL) can cover various lines on the rear surface of the second substrate SUBS2, except for the second solder pad electrode PAD2. The second protective layer (BCL) can be made of an organic insulating material, such as phenylcyclobutene or an acrylic-based organic insulating material.

[0096] Multiple flexible films, PCBs, and similar circuit elements can be disposed on the rear surface of the second substrate SUBS2. The output terminals of the flexible films are electrically connected to the second pad electrodes PAD2, and the input terminals of the flexible films are electrically connected to the output terminals of the PCB. Therefore, signals or voltages output from the PCB can be transmitted via the flexible films, the second pad electrodes PAD2, the side lines SRL, multiple first pad electrodes PAD1, and lines connected to the first pad electrodes PAD1 to the sub-pixels SP disposed on the front surface of the first substrate SUBS1.

[0097] The side line SRL spans the side surfaces of the first substrate SUBS1 and the second substrate SUBS2, and electrically connects the first pad electrode PAD1 and the second pad electrode PAD2. The side line SRL can be formed on the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 by using a pad printing method using conductive inks containing silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr) or similar materials.

[0098] The side insulating layer (SDI) can cover the side lines (SRL), which are formed on the outermost peripheries of the upper, side, and rear surfaces of the first substrate SUBS1 and the second substrate SUBS2 bonded together. When the side lines (SRL) are made of metal, external light may be reflected from the side lines (SRL), or light emitted from the light-emitting element (ED) may be reflected from the side lines (SRL) and visually recognized by the user. To improve the image quality degradation caused by such reflected light, the side insulating layer (SDI) can contain a black material that absorbs external light. For example, the side insulating layer (SDI) can be formed on the outermost peripheries of the first substrate SUBS1 and the second substrate SUBS2 using black ink, which can be applied by printing.

[0099] The sealing layer SS can cover the side insulating layer SDI to protect the display panel PN from external vibration, moisture, oxygen, and the like. For example, the sealing layer SS can be made of black ink, polyimide (PI), polyurethane (PU), epoxy resin, acrylic insulating materials, and the like. The sealing layer SS can be a concept that includes the side insulating layer SDI. That is, the sealing layer SS and the side insulating layer SDI can be configured as a single layer.

[0100] The cover film MF can cover the front surface of the display panel PN. The cover film MF can contain one or more of various functional films, such as anti-scattering film, anti-glare film, anti-reflection film, low-reflection film, organic light-emitting diode (OLED) transmission controllable film, color difference compensation film, polarizer, and the like. When the display panel PN is damaged, the anti-scattering film prevents substrate segmentation or particle scattering. By extensively bonding the sealing layer SS to the front surface of the first substrate SUBS1, and then cutting along the cutting line overlapping the sealing layer SS, the cover film MF, together with the outer portion of the sealing layer SS, can be cut and removed. Therefore, the outermost exposed surfaces of the cover film MF and the sealing layer SS can be formed on the same plane without steps.

[0101] Figure 6 is a diagram illustrating pixels according to an embodiment of this specification. Figure 7 is a diagram illustrating a red sub-pixel according to an embodiment of this specification. Figure 8 is a diagram illustrating a green sub-pixel according to an embodiment of this specification. Figure 9 is a diagram illustrating a blue sub-pixel according to an embodiment of this specification. Figure 10 is a diagram illustrating the cathodes of the red, green, and blue sub-pixels.

[0102] Referring to Figure 6, a pixel can contain six sub-pixels. As an example, a pixel can contain two red sub-pixels R1 and R2, two green sub-pixels G1 and G2, and two blue sub-pixels B1 and B2. Each sub-pixel can contain a light-emitting element and a pixel circuit, which includes a compensation circuit. The compensation circuit is used to compensate for the threshold voltage of the driving element, and the pixel circuit can be a circuit containing a light-emitting element, a driving element, and a compensation circuit. When a sub-pixel contains two light-emitting elements and one compensation circuit, the sub-pixel can be defined as one sub-pixel.

[0103] According to an embodiment, each of the sub-pixels R1, R2, G1, G2, B1, and B2 can be driven independently or simultaneously. A plurality of sub-pixels R1, R2, G1, G2, B1, and B2 can be driven simultaneously via a shared gate line. However, the invention is not limited to this, and a plurality of gate lines can be configured such that a first pixel group of pixels R1, G1, and B1 connected to a first gate line SCAN1 and a second pixel group of pixels R2, G2, and B2 connected to a second gate line SCAN2 can be driven independently.

[0104] Two red sub-pixels, R1 and R2, can be connected to data lines VdataR1 and VdataR2, respectively. On the other hand, two green sub-pixels, G1 and G2, can share a single data line VdataG, and two blue sub-pixels, B1 and B2, can share a single data line VdataB. Therefore, the number of data lines can be reduced.

[0105] Red subpixels R1 and R2 have relatively low efficiency and can therefore be driven independently to adjust their brightness, while green subpixels G1 and G2 and blue subpixels B1 and B2 have relatively high efficiency and can therefore emit light simultaneously using a single data line.

[0106] In this case, since both light-emitting elements are simultaneously turned on through a single data voltage, it is advantageous to output the desired brightness even when the data voltage is reduced. However, the invention is not limited to this, and the green and blue sub-pixels can also be connected to the data line separately and driven independently.

[0107] Referring to Figure 7, the red sub-pixel may include: a first red sub-pixel (1-1 sub-pixel) R1; and a second red sub-pixel (1-2 sub-pixel) R2. The first red sub-pixel R1 may include: a first red light-emitting element ED11; and a first red compensation circuit PC11. The first red light-emitting element ED11 may be connected to the anode AND connected to the high-potential power line HL, and the cathode CAT connected to the low-potential power line CL1. The first red compensation circuit PC11 may be connected between the first data line VdataR1 and the low-potential power line CL1.

[0108] The second red sub-pixel R2 may include: a second red light-emitting element ED12; and a second red compensation circuit PC12. The second red light-emitting element ED12 may be connected to the anode connected to the high-potential power line HL and the cathode connected to the low-potential power line CL2. The second red compensation circuit PC12 may be connected between the second data line VdataR2 and the low-potential power line CL2.

[0109] According to an embodiment, the first red sub-pixel R1 and the second red sub-pixel R2 are respectively connected to the first data line VdataR1 and the second data line VdataR2, and can therefore be driven independently. Thus, when the voltage levels applied to the first data line VdataR1 and the second data line VdataR2 are adjusted differently, the first red light-emitting element ED11 and the second red light-emitting element ED12 can emit light at different brightness levels. That is, the brightness of the first red light-emitting element ED11 and the second red light-emitting element ED12 can be independently controlled according to the total brightness of the red light to be output from the pixel. Alternatively, the first red light-emitting element ED11 and the second red light-emitting element ED12 can be driven alternately. However, the invention is not limited to this, and the first red sub-pixel R1 and the second red sub-pixel R2 can be driven simultaneously through a single data line. Since each of the first red sub-pixel R1 and the second red sub-pixel R2 is configured as an independent pixel, even if one of the first red sub-pixel R1 and the second red sub-pixel R2 experiences a short-circuit fault, such a fault cannot affect the other.

[0110] Referring to Figure 8, the green sub-pixel may include: a first green sub-pixel (2-1 sub-pixel) G1; and a second green sub-pixel (2-2 sub-pixel) G2. The first green sub-pixel G1 may include: a first green light-emitting element ED21; and a first green compensation circuit PC21. The first green light-emitting element ED21 may be connected to the anode connected to the high-potential power line HL, and the cathode connected to the low-potential power line CL3. The first green compensation circuit PC21 may be connected between the third data line VdataG and the low-potential power line CL3.

[0111] The second green sub-pixel G2 may include: a second green light-emitting element ED22; and a second green compensation circuit PC22. The second green light-emitting element ED22 may be connected to the anode connected to the high-potential power line HL and the cathode connected to the low-potential power line CL4. The second green compensation circuit PC22 may be connected between the third data line VdataG and the low-potential power line CL4.

[0112] According to an embodiment, the first green sub-pixel G1 and the second green sub-pixel G2 are both connected to the third data line VdataG and can therefore be driven simultaneously. Therefore, the data voltage can be set to a relatively low value. For example, when the data voltage to be applied to output a predetermined brightness for the green sub-pixel in the corresponding frame is 1 V, since both green light-emitting elements emit light, even when the data voltage is reduced to 0.5 V and applied, the desired brightness of green light can still be output.

[0113] As an example, in the case of a second pixel in which one of the first green sub-pixel G1 and the second green sub-pixel G2 is faulty, only one sub-pixel is used to adjust the brightness, and therefore it is necessary to apply twice the data voltage to make the adjustment so that the same brightness can be achieved compared to the first pixel in which both sub-pixels are lit.

[0114] According to the embodiment, the anode of the first green light-emitting element ED21 and the anode of the second green light-emitting element ED22 can be electrically isolated from each other, and the cathode of the first green light-emitting element ED21 and the cathode of the second green light-emitting element ED22 can be electrically isolated from each other. Therefore, even if the high potential voltage VDD and the low potential voltage VSS are short-circuited due to a fault in the first green light-emitting element ED21 and the first green light-emitting element ED21 dims, the adjacent second green light-emitting element ED22 will not be affected.

[0115] Failures in the first green light-emitting element ED21 can be due to faults in the electrode pads or due to inherent defects in the semiconductor layer itself. Micro-sized light-emitting diodes are small in size and therefore susceptible to electrostatic discharge, and are fabricated on wafers at a microscale and then transferred to panels, thus suffering from high failure rates for various reasons.

[0116] Therefore, when the first green light-emitting element ED21 and the second green light-emitting element ED22 are connected in series or parallel, if one of the light-emitting elements experiences a short-circuit fault (a short circuit between the high potential voltage VDD and the low potential voltage VSS) and dims, the adjacent normal light-emitting element may also turn dark due to the flow of the short-circuit current. However, according to the embodiment, since the anode and cathode of the first green light-emitting element ED21 are separated from the anode and cathode of the second green light-emitting element ED22, even if one of these light-emitting elements experiences a short-circuit fault, the adjacent light-emitting element can be prevented from dimming. Therefore, the adjacent light-emitting elements can operate normally.

[0117] Referring to Figure 9, the blue sub-pixel may include: a first blue sub-pixel (3-1 sub-pixel) B1; and a second blue sub-pixel (3-2 sub-pixel) B2. The first blue sub-pixel B1 may include: a first blue light-emitting element ED31; and a first blue compensation circuit PC31. The first blue light-emitting element ED31 may be connected to the anode connected to the high-potential power line HL, and the cathode connected to the low-potential power line CL5. The first blue compensation circuit PC31 may be connected between the fourth data line VdataB and the low-potential power line CL5.

[0118] The second blue sub-pixel B2 may include: a second blue light-emitting element ED32; and a second blue compensation circuit PC32. The second blue light-emitting element ED32 may be connected to the anode connected to the high-potential power line HL and the cathode connected to the low-potential power line CL6. The second blue compensation circuit PC32 may be connected between the fourth data line VdataB and the low-potential power line CL6.

[0119] According to an embodiment, the first blue sub-pixel B1 and the second blue sub-pixel B2 are both connected to the fourth data line VdataB, and therefore can be driven simultaneously. Thus, the data voltage can be set to a level lower than the voltage level at which a single blue light-emitting element emits light at the desired brightness.

[0120] As an example, in the case of a fourth pixel in which one of the first blue sub-pixel B1 and the second blue sub-pixel B2 has failed, only one sub-pixel is used to adjust the brightness, and therefore, compared with a third pixel in which two sub-pixels are illuminated, it is necessary to apply twice the data voltage to make the adjustment so that the same brightness can be achieved.

[0121] Furthermore, the anode of the first blue light-emitting element ED31 and the anode of the second blue light-emitting element ED32 can be electrically isolated from each other, and the cathode of the first blue light-emitting element ED31 and the cathode of the second blue light-emitting element ED32 can be electrically isolated from each other. Therefore, even if one of these light-emitting elements experiences a short-circuit fault, it can prevent the adjacent light-emitting elements from dimming as well.

[0122] Referring to Figure 10, in a pixel, the anode And1 of the first red sub-pixel R1, the anode And2 of the second red sub-pixel R2, the anode And3 of the first green sub-pixel G1, the anode And4 of the second green sub-pixel G2, the anode And5 of the first blue sub-pixel B1, and the anode And6 of the second blue sub-pixel B2 can be electrically separated from each other.

[0123] In addition, the cathodes Cat1 of the first red sub-pixel R1, Cat2 of the second red sub-pixel R2, Cat3 of the first green sub-pixel G1, Cat4 of the second green sub-pixel G2, Cat5 of the first blue sub-pixel B1, and Cat6 of the second blue sub-pixel B2 can be electrically separated from each other.

[0124] Furthermore, the plurality of high-potential power lines HL connected to the anodes And1 to And6 can be isolated from each other, and the plurality of low-potential power lines CL connected to the cathodes Cat1 to Cat6 can also be isolated from each other. Therefore, it is possible to prevent the light-emitting elements of adjacent sub-pixels from dimming due to a short-circuit fault in the light-emitting element of any of the plurality of sub-elements.

[0125] Figure 11 is a circuit diagram illustrating a schematic pixel circuit according to one embodiment of this specification. Figure 12 is a circuit diagram illustrating a pixel circuit according to one embodiment of this specification.

[0126] Referring to Figure 11, sub-pixels SP1 and SP2 of the same color each include a light-emitting element ED, a driving element DT, a first switching element M1, and a compensation circuit PC. Sub-pixels SP1 and SP2 of the same color can be green or blue sub-pixels.

[0127] Since the two sub-pixels SP1 and SP2 have the same structure, with the data line PL2 to which the data voltage Vdata is applied interposed between the two sub-pixels, the pixel circuit of each sub-pixel is described by the same component symbols. The following description will be based on the second sub-pixel SP2 located on the right.

[0128] The second sub-pixel SP2 may include: a light-emitting element ED; a driving element DT; a first switching element M1; and a compensation circuit PC. The light-emitting element ED, the driving element DT, and the first switching element M1 may be connected in series between the high potential voltage VDD and the low potential voltage VSS.

[0129] The driving element DT adjusts the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT varies according to the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. Therefore, the current flowing through the driving element DT varies according to the data voltage Vdata. The light-emitting element ED can be driven to emit light by the current flowing from the driving element DT. A capacitor C can be connected between the gate electrode of the driving element DT and the first electrode. The capacitor C is charged using the gate-source voltage of the driving element DT.

[0130] The driving element DT can be connected between the light-emitting element ED and the first switching element M1. In this case, the driving element DT includes: a gate electrode to which the data voltage Vdata is applied; a first electrode connected to the cathode of the light-emitting element ED; and a second electrode connected to the first electrode of the first switching element M1.

[0131] The first switching element M1 switches the current path between a high potential voltage VDD and a low potential voltage VSS. The first switching element M1 can be turned on in response to the gate-on voltage of either gate signal GATE1 or GATE2, and can be turned off in response to the gate-off voltage of either gate signal GATE1 or GATE2. When the first switching element M1 is on, the driving element DT and the light-emitting element ED are electrically connected, allowing current to be supplied to the light-emitting element ED. When the first switching element M1 is off, the current path between the high potential voltage VDD and the low potential voltage VSS is blocked, and therefore current cannot be supplied to the light-emitting element ED.

[0132] The first switching element M1 can be connected between the driving element DT and the cathode voltage VSS. In this case, the first switching element M1 includes: a gate electrode connected to the first gate line; a first electrode connected to the second electrode of the driving element DT; and a second electrode connected to the node to which the cathode voltage VSS is applied.

[0133] The pixel circuit may further include a second switching element M2. The second switching element M2 is connected between the cathode and anode of the light-emitting element ED and can be turned on in response to a gate signal applied through the compensation circuit. When the second switching element M2 is turned on, the cathode and anode of the light-emitting element ED are short-circuited, and therefore the light-emitting element ED does not emit light. When the pixel circuit is initialized and the threshold voltage of the driving element DT is sampled, the second switching element M2 can prevent the light-emitting element ED from emitting light. The second switching element M2 includes: a gate electrode connected to a second gate line; a first electrode connected to the anode of the light-emitting element ED; and a second electrode connected to the cathode of the light-emitting element ED.

[0134] The first switching element M1 can be turned on in response to the gate turn-on voltage of the light emission signal and turned off in response to the gate turn-off voltage of the light emission signal, but the present invention is not limited thereto. The second switching element M2 can be turned on in response to the gate turn-on voltage of the first scan signal and turned off in response to the gate turn-off voltage of the first scan signal, but the present invention is not limited thereto.

[0135] The compensation circuit PC is connected to the data line to which the data voltage Vdata is applied, the gate line to which one or more scan signals SCAN1 and SCAN2 are applied, the gate electrode of the drive element DT, and the gate electrode of the first switching element M1. One or more scan signals SCAN1 and SCAN2 can be applied to the compensation circuit.

[0136] The compensation circuit transmits the data voltage Vdata to the gate electrode of the drive element DT using multiple transistors. The compensation circuit samples the threshold voltage of the drive element DT to the capacitor C and compensates for the gate voltage of the drive element DT using the threshold voltage. The compensation circuit can use a source follower or a diode connection circuit to compensate for the threshold voltage of the drive element DT.

[0137] Referring to Figure 12, the pixel circuit may include: a driving element DT connected to the light-emitting element ED; a plurality of switching elements M1 to M6; and a plurality of capacitors C1 to C3. The driving element DT and the plurality of switching elements M1 to M6 may be P-channel transistors, but the present invention is not limited thereto.

[0138] The driving element DT may have: a gate electrode G connected to the first node n1, a source electrode S connected to the second node n2, and a drain electrode D connected to the third node n3.

[0139] The light-emitting element ED can be positioned between the second node n2 and the high potential voltage VDD. The light-emitting element ED can be a micro-sized light-emitting diode, but the present invention is not limited to this. The source electrode S of the driving element DT can be connected to the cathode of the light-emitting element ED.

[0140] The first switching element M1 can be connected between the third node n3 of the driving element DT and the low potential voltage VSS. When the first switching element M1 is turned on in response to the gate turn-on voltage of the light emission signal EM, the first switching element M1 can connect the third node n3 to the low potential voltage VSS.

[0141] The second switching element M2 is connected between the cathode and anode of the light-emitting element ED, and can be turned on by the gate voltage of the first scan signal SCAN1. When the second switching element M2 is turned on, the light-emitting element does not emit light.

[0142] The third switching element M3 is connected between the reference voltage line PL1 and the fourth node n4, and when the third switching element M3 is turned on in response to the gate turn-on voltage of the light emission signal EM, the reference voltage Vref can be applied to the fourth node n4.

[0143] The fourth switching element M4 is disposed between the third node n3 and the first node n1, and when the fourth switching element M4 is turned on in response to the gate turn-on voltage of the first scan signal SCAN1, the third node n3 can be connected to the first node n1.

[0144] The fifth switching element M5 is located between the reference voltage line PL1 and the fifth node n5. When the fifth switching element M5 is turned on in response to the gate turn-on voltage of the second scan signal SCAN2, the reference voltage Vref can be applied to the fifth node n5.

[0145] The sixth switching element M6 is located between the data line PL2 and the fourth node n4. When the sixth switching element M6 is turned on in response to the gate turn-on voltage of the first scan signal SCAN1, the data voltage Vdata can be applied to the fourth node n4.

[0146] The first capacitor C1 can be disposed between the first node n1 and the fourth node n4, the second capacitor C2 can be disposed between the first node n1 and the second node n2, and the third capacitor C3 can be disposed between the second capacitor C2 and the anode of the light-emitting element ED. The critical voltage and data voltage of the driving element can be stored in the second capacitor C2 and the third capacitor C3, respectively.

[0147] Referring to Figure 13, during the first initialization period INI1, the first scan signal SCAN1 can be output as the gate turn-off voltage VGH, while the second scan signal SCAN2 can be output as the gate turn-on voltage VGL. The fifth switching element M5 applied by the second scan signal SCAN2 can be turned on, and the reference voltage can be applied to the third node n3. The reference voltage Vref applied during the illumination period of the previous frame can remain at the first node n1, and the reference voltage Vref can be applied to the third node n3.

[0148] During the second initialization period INI2, both the first scan signal SCAN1 and the second scan signal SCAN2 output as the gate turn-on voltage VGL, enabling the second switching element M2, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 to be turned on. Therefore, the data voltage Vdata can be charged to the first node n1, and the reference voltage Vref can be charged to the first node n1, allowing the first capacitor C1 to be initialized. Additionally, the gate electrode of the driving element DT can be initialized to the reference voltage Vref. In this situation, since the second switching element M2 is turned on, the cathode and anode of the light-emitting element ED can be short-circuited, and therefore the light-emitting element ED can not emit light.

[0149] During the sampling period SAM, the first scan signal SCAN1 has a gate-on voltage VGL, while the second scan signal SCAN2 has a gate-off voltage VGH, allowing the sixth switching element M6, the fourth switching element M4, and the second switching element M2 to be turned on. Therefore, the voltage VDD+Vth can be stored at the first node n1.

[0150] During the holding period HOL, the first scan signal SCAN1, the second scan signal SCAN2, and the light emission signal EM all have a gate turn-off voltage VGH, and therefore all switching elements can be turned off. Thus, the voltage VDD+Vth can be retained at the first node n1.

[0151] During the EMI emission period, the first scan signal SCAN1 and the second scan signal SCAN2 can have a gate turn-off voltage VGH, while the EMI emission signal can have a gate turn-on voltage VGL. The first switching element M1 and the third switching element M3 can be turned on. Therefore, the reference voltage Vref can be applied to the first node n1, and due to capacitor coupling, the voltage VDD+Vth-(Vdata-Vref) can be applied to the first node n1.

[0152] The current Ids flowing through the driving element DT can be defined as k(IVgsl-lVthl) 2. Therefore, assuming k(VDD-VDD-Vth+Vdata-Vref+Vth) 2, the expression can be simplified to k(Vdata-Vref) 2. Thus, the critical voltage of the driving element can be compensated.

[0153] Figure 14 is a diagram illustrating a pixel with parallel connected sub-pixels. Figure 15 is a diagram illustrating the sub-pixels of Figure 14.

[0154] Referring to Figures 14 and 15, a pixel can contain four sub-pixels: R1, R2, G, and B. That is, a pixel can contain a first red sub-pixel R1, a second red sub-pixel R2, a green sub-pixel G, and a blue sub-pixel B.

[0155] The first red sub-pixel R1 and the second red sub-pixel R2 can each include a light-emitting element ED and a compensation circuit PC, with the same structure as described in Figure 7. However, the green sub-pixel G can have two green light-emitting elements ED arranged in parallel, and the two green light-emitting elements ED can share one compensation circuit PC. Similarly, the red sub-pixel R can have two red light-emitting elements ED arranged in parallel, and the two red light-emitting elements ED can share one compensation circuit PC. In this structure, the number of compensation circuits can be reduced, thereby increasing the aperture ratio.

[0156] However, since the two green light-emitting elements ED1 and ED2 are connected in parallel, the following problem exists: when one of the light-emitting elements experiences a short circuit and dims, the adjacent light-emitting element will also short circuit and dim. Therefore, the following problem exists: all green light-emitting elements ED1 and ED2 in the corresponding pixel dim.

[0157] Figures 16 and 17 are diagrams illustrating the procedure for repairing subpixels.

[0158] Referring to Figure 16, the plurality of pixels may include: a first pixel (N), disposed on a first pixel line; and a second pixel (N+1), disposed on a second pixel line. The first pixel (N) may include a first sub-pixel SP1 and a second sub-pixel SP2 of the same color, while the second pixel (N+1) may include a third sub-pixel SP3 and a fourth sub-pixel SP4 of the same color. The first pixel line and the second pixel line may be adjacent to each other in the row direction (Y-axis direction), but the present invention is not limited thereto.

[0159] The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 each contain a light-emitting element ED, a compensation circuit PC, and a high-potential power line HL and a low-potential power line CL.

[0160] The first sub-pixel SP1 can be set to face the third sub-pixel SP3 in the row direction, while the second sub-pixel SP2 can be set to face the fourth sub-pixel SP4 in the row direction.

[0161] The low-potential power line CL11 in the first sub-pixel SP1 can extend toward the third sub-pixel SP3, while the low-potential power line CL13 in the third sub-pixel SP3 can extend toward the first sub-pixel SP1. Additionally, the low-potential power line CL12 in the second sub-pixel SP2 can extend toward the fourth sub-pixel SP4, while the low-potential power line CL14 in the fourth sub-pixel SP4 can extend toward the second sub-pixel SP2.

[0162] The solder joint WP can be formed at the end of each of the low-potential power lines CL11, CL12, CL13, and CL14 extending to the outside of each sub-pixel. The solder joint WP comprises overlapping metal layers, with an insulating layer interposed between the metal layers, and the metal layers can be selectively connected during the soldering process.

[0163] Referring to Figure 17, when the compensation circuit PC of the fourth sub-pixel SP4 fails, a repair portion WP2 can be formed by connecting the soldered portion WP of the low-potential power line CL14 of the fourth sub-pixel SP4 to the soldered portion WP of the low-potential power line CL12 of the second sub-pixel SP2. Therefore, in this case, the soldered portion WP can be connected in the fourth sub-pixel SP4 after the light-emitting element ED and the compensation circuit PC are disconnected. With this configuration, when the compensation circuit of each sub-pixel fails, the compensation circuit can be connected to the compensation circuit of the adjacent sub-pixel and operate normally.

[0164] A display panel and a display device including the display panel according to an embodiment of this specification can be described as follows.

[0165] A display panel according to an embodiment of this specification includes: a plurality of pixels; and gate lines and data lines connected to the plurality of pixels, wherein each of the plurality of pixels includes: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color; a 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line.

[0166] According to one or more embodiments of this specification, sub-pixel 1-1 may include a first compensation circuit connected to a first data line, while sub-pixel 1-2 may include a second compensation circuit connected to a second data line.

[0167] According to one or more embodiments of this specification, each of sub-pixels 3-1 and 3-2 may include compensation circuitry, and the compensation circuitry of sub-pixels 3-1 and 3-2 may be connected to a data line.

[0168] According to one or more embodiments of this specification, the first color may be red, the second color may be green, and the third color may be blue.

[0169] According to one or more embodiments of this specification, a plurality of pixels may include: a first pixel, wherein both sub-pixels 2-1 and 2-2 emit light when a data voltage is applied; and a second pixel, wherein only one of sub-pixels 2-1 and 2-2 emits light when a data voltage is applied.

[0170] According to one or more embodiments of this specification, the data voltage applied to the 2-1 sub-pixel and 2-2 sub-pixel of the second pixel may be greater than the data voltage applied to the 2-1 sub-pixel and 2-2 sub-pixel of the first pixel.

[0171] According to one or more embodiments of this specification, a plurality of pixels may include: a third pixel, wherein both sub-pixels 3-1 and 3-2 emit light when a data voltage is applied; and a fourth pixel, wherein only one of sub-pixels 3-1 and 3-2 emits light when a data voltage is applied.

[0172] According to one or more embodiments of this specification, the data voltage applied to the 3-1 and 3-2 sub-pixels of the fourth pixel can be greater than the data voltage applied to the 3-1 and 3-2 sub-pixels of the third pixel.

[0173] According to one or more embodiments of this specification, the display panel may include: a first gate line, wherein sub-pixels 1-1, 2-1, and 3-1 are connected to the first gate line; and a second gate line, wherein sub-pixels 1-2, 2-2, and 3-2 are connected to the second gate line.

[0174] According to one or more embodiments of this specification, each of sub-pixels 1-1 to 3-2 may include an anode and a cathode for applying voltage to a light-emitting element, the anodes of sub-pixels 1-1 to 3-2 may be separated from each other, and the cathodes of sub-pixels 1-1 to 3-2 may also be separated from each other.

[0175] According to one or more embodiments of this specification, the compensation circuit for sub-pixel 2-1 and the compensation circuit for sub-pixel 2-2 may have the same structure.

[0176] According to one or more embodiments of this specification, a plurality of pixels may include: a plurality of first pixels disposed in a first pixel line; and a plurality of second pixels disposed in a second pixel line adjacent to the first pixel line. A 2-1 sub-pixel of a first pixel may include a first low-potential power line connected to a first cathode of the 2-1 sub-pixel of the first pixel. A 2-1 sub-pixel of a second pixel may include a second low-potential power line connected to a second cathode of the 2-1 sub-pixel of the second pixel. The first low-potential power line may extend toward the second cathode, and the second low-potential power line may extend toward the first cathode. The first low-potential power line and the second low-potential power line may be electrically connected to each other.

[0177] According to one or more embodiments of this specification, the first low-potential power line of the 2-1 sub-pixel of the first pixel can be electrically connected to the compensation circuit of the 2-1 sub-pixel of the second pixel.

[0178] According to one or more embodiments of this specification, the first compensation circuit of sub-pixel 1-1 can be connected between the first data line and the first low potential line, while the second compensation circuit of sub-pixel 1-2 can be connected between the second data line and the second low potential line.

[0179] A display device according to one embodiment of this specification includes a display panel comprising: a plurality of pixels, a gate line and a data line connected to the plurality of pixels; a gate driver connected to the gate line; and a data driver connected to the data line, wherein each of the plurality of pixels includes: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color; a 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel may include a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line.

[0180] According to one or more embodiments of this specification, sub-pixel 1-1 may include a first compensation circuit connected to a first data line, while sub-pixel 1-2 may include a second compensation circuit connected to a second data line.

[0181] According to one or more embodiments of this specification, each of sub-pixels 3-1 and 3-2 may include compensation circuitry, and the compensation circuitry of sub-pixels 3-1 and 3-2 may be connected to a data line.

[0182] According to one or more embodiments of this specification, the first color may be red, the second color may be green, and the third color may be blue.

[0183] According to one or more embodiments of this specification, a plurality of pixels may include: a first pixel, wherein both sub-pixels 2-1 and 2-2 emit light when a data voltage is applied; and a second pixel, wherein only one of sub-pixels 2-1 and 2-2 emits light when a data voltage is applied.

[0184] According to one or more embodiments of this specification, the data voltage applied to the 2-1 sub-pixel and 2-2 sub-pixel of the second pixel may be greater than the data voltage applied to the 2-1 sub-pixel and 2-2 sub-pixel of the first pixel.

[0185] A display device according to an embodiment of this specification can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, navigation systems for vehicles, display devices for vehicles, devices for vehicles, theater equipment, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, consumer electronic devices, and the like.

[0186] According to this specification, even if one of the light-emitting elements of a plurality of sub-pixels dims, the remaining light-emitting elements can still emit light. Therefore, the number of dark spots in the light-emitting elements of the display device can be reduced. In addition, low-power operation becomes possible.

[0187] Furthermore, by using an improved pixel structure that promotes dark spots, it is possible to implement a display panel that is conducive to program optimization, high efficiency, high brightness, and long lifespan.

[0188] It should be noted that the advantages of this specification are not limited to those described above, and other advantages not described herein will be apparent to those skilled in the art from the following description.

[0189] Although embodiments and advantages thereof have been described in detail with reference to the accompanying drawings, it will be apparent to those skilled in the art to which this invention pertains that various changes, substitutions, and modifications may be made herein without departing from the scope of this specification. Therefore, the scope of this specification will be defined by the following claims rather than the embodiments described above, and all changes and modifications and their equivalents derived from the meaning and scope of the claims should be understood to be included within the scope of this specification.

[0190] This application claims priority and benefit to Korean Patent Application No. 10-2023-0192978, filed on December 27, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0191] 100: Display device AA: Display area ACT: Active Layer AD: Adhesive layer, insulation layer AK1: Aiming button, first aiming button AK2: Aim button, second aim button AND: Anode And1: The anode of the first red sub-pixel And2: The anode of the second red sub-pixel And3: The anode of the first green sub-pixel And4: The anode of the second green sub-pixel And5: The anode of the first blue sub-pixel And6: The anode of the second blue sub-pixel AVL1: High-potential power line AVL2: Low-potential power line B: Subpixel, Blue Subpixel B1: Blue subpixel, subpixel, pixel, first blue subpixel B2: Blue subpixel, subpixel, pixel, second blue subpixel BB: Embankment Pattern BCL: Second protective layer BDL: Bonding Layer BSM: Light Blocking Layer BUF: Buffer layer C: Capacitor C1: First capacitor, capacitor C1a: First capacitor electrode C1b: Second capacitor electrode C2: Second capacitor, capacitor C2a: Third capacitor electrode C3: Capacitor, third capacitor CAT: Cathode Cat1: Cathode of the first red sub-pixel Cat2: Cathode of the second red sub-pixel Cat3: Cathode of the first green sub-pixel Cat4: Cathode of the second green sub-pixel Cat5: Cathode of the first blue sub-pixel Cat6: Cathode of the second blue sub-pixel CH1: Contact Hole CL, CL1, CL2, CL3, CL4, CL5, CL6: Low-potential power lines CL11, CL12, CL13, CL14: Low-potential power lines CPA: First protective layer D: Drain electrode D1, D2: Separation distance DD: Data Drive DE: Drain electrode DL: Data Line DP: Data pad DT: Drive Component E1: First electrode, electrode E2: Second electrode, electrode ED: Light-emitting element, red light-emitting element, green light-emitting element, blue light-emitting element ED1, ED2: Green light-emitting elements ED11: First red light-emitting element ED12: Second red light-emitting element ED21: The first green light-emitting element ED22: Second Green Light-Emitting Element ED31: First blue light-emitting element ED32: Second blue light-emitting element EM: Emitting layer, emission signal EMI: Emission Period ENS: Encapsulation layer, insulating layer G: Gate electrode G1: Green subpixel, subpixel, pixel, first green subpixel G2: Green subpixel, subpixel, pixel, second green subpixel GA: Gate Drive Region GD: Gate Driver GE: Gate electrode GI: Gate Insulation Layer GP: Gate pad GVL: Gate Drive Line HL: High-potential power cord HOL: Duration of Maintenance ILD1: First interlayer insulation layer ILD2: Second interlayer insulation layer INI1: First Initialization Phase INI2: Second Initialization Phase M1: First switching element, switching element M2: Second switching element, switching element M3: Third switching element, switching element M4: Fourth switching element, switching element M5: Fifth switching element, switching element M6: Sixth switching element, switching element MF: Covering film ML1: First metal layer ML2: Second metal layer n1: First node n2: Second node n3: Third node n4: Fourth node n5: Fifth node NA: Non-display area PA1: Solder pad area, first solder pad area PA2: Solder pad area, second solder pad area PAD1: First solder pad electrode, short solder pad electrode PAD2: Second pad electrode, short pad electrode PAS1: First passivation layer PAS2: Second passivation layer, insulating layer PC: Compensation circuit PC11: First Red Compensation Circuit PC12: Second Red Compensation Circuit PC21: First Green Compensation Circuit PC22: Second Green Compensation Circuit PC31: First Blue Compensation Circuit PC32: Second Blue Compensation Circuit PE1a: First solder pad metal layer PE1b: Second solder pad metal layer PE1c: Third solder pad metal layer PE2a: First solder pad metal layer PE2b: Second solder pad metal layer PE2c: Third solder pad metal layer PIXEL (N): First pixel PIXEL (N+1): Second pixel PL1: Reference voltage line PL2: Data Line PLN1: First planarization layer PLN2: Second planarization layer, insulating layer PLN3: Third planarization layer, insulating layer PN: Display panel PX: Outermost pixel, adjacent pixel, pixel R1: Red subpixel, subpixel, pixel, first red subpixel R2: Red subpixel, subpixel, pixel, second red subpixel RF: Reflective layer S: Source electrode SAM: Sampling Period SCAN1: First gate line, scan signal, first scan signal SCAN2: Second gate line, scan signal, second scan signal SCL: Securing Line SDI: Side Insulation Layer SE: Source electrode SEM1: First semiconductor pattern, semiconductor pattern SEM2: Second semiconductor pattern, second semiconductor pattern layer, semiconductor pattern SL: Gate line SP: Subpixel SP1: Subpixel, First Subpixel SP2: Sub-pixel, Second Sub-pixel SP3: Third subpixel SP4: Fourth subpixel SRL: Sideline SS: Sealing layer SUBS: substrate SUBS1: First substrate SUBS2: Second substrate TC: Timing Controller TD: Large Screen Splicing Display Device UPA: Pixel Area Vdata: Data voltage VdataB: Data line, fourth data line VdataG: Data line, third data line VdataR1: Data line, first data line VdataR2: Data line, second data line VDD: High potential voltage VGH: Gate High Voltage, Gate Turn-Off Voltage VGL: Gate Low Voltage, Gate Turn-On Voltage VL1: High-potential power line VL2: Low-potential power line VP1: Power pad, high-potential power pad VP2: Low-potential power pad, power pad Vref: Reference voltage VSS: Low Potential Voltage, Cathode Voltage WP: Welding section WP2: Repair Section

Claims

1. A display panel, comprising: Multiple pixels; The plurality of pixels includes a gate line and a data line connected to the plurality of pixels, wherein each of the plurality of pixels comprises: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color; a 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel comprises a light-emitting element and a compensation circuit, the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line, the 1-1 sub-pixel comprises a first compensation circuit connected to a first data line, and the 1-2 sub-pixel comprises a second compensation circuit connected to a second data line.

2. The display panel as described in claim 1, wherein, Each of the 3-1 sub-pixel and the 3-2 sub-pixel includes a compensation circuit, and the compensation circuits of the 3-1 sub-pixel and the 3-2 sub-pixel are connected to a data line.

3. The display panel as described in claim 1, wherein, The first color is red, the second color is green, and the third color is blue.

4. The display panel as described in claim 1, wherein, The plurality of pixels includes: a first pixel, wherein both the 2-1 sub-pixel and the 2-2 sub-pixel emit light when a data voltage is applied; and a second pixel, wherein only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light when the data voltage is applied.

5. The display panel as described in claim 4, wherein, The data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel is greater than the data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

6. The display panel as described in claim 4, wherein, The plurality of pixels includes: a third pixel, wherein both the 3-1 sub-pixel and the 3-2 sub-pixel emit light when a data voltage is applied; and a fourth pixel, wherein only one of the 3-1 sub-pixel and the 3-2 sub-pixel emits light when the data voltage is applied.

7. The display panel as described in claim 6, wherein, The data voltage applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the fourth pixel is greater than the data voltage applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the third pixel.

8. The display panel as described in claim 1, comprising: A first gate line, wherein the 1-1 sub-pixel, the 2-1 sub-pixel, and the 3-1 sub-pixel are connected to the first gate line; And a second gate line, wherein the 1-2 sub-pixel, the 2-2 sub-pixel and the 3-2 sub-pixel are connected to the second gate line.

9. The display panel as described in claim 1, wherein, Each of the 1-1 sub-pixels to the 3-2 sub-pixels includes an anode and a cathode to which a voltage is applied to the light-emitting element, wherein the anodes of the 1-1 sub-pixels to the 3-2 sub-pixels are separated from each other, and the cathodes of the 1-1 sub-pixels to the 3-2 sub-pixels are separated from each other.

10. The display panel as described in claim 1, wherein, The compensation circuit for the 2-1 sub-pixel and the compensation circuit for the 2-2 sub-pixel have the same structure.

11. The display panel as described in claim 1, wherein, The plurality of pixels includes: a plurality of first pixels disposed in a first pixel line; and a plurality of second pixels disposed in a second pixel line adjacent to the first pixel line. The 2-1 sub-pixel of the first pixel includes: a first low-potential power line connected to a first cathode of the 2-1 sub-pixel of the first pixel. The 2-1 sub-pixel of the second pixel includes: a second low-potential power line connected to a second cathode of the 2-1 sub-pixel of the second pixel. The first low-potential power line extends toward the second cathode. The second low-potential power line extends toward the first cathode. The first low-potential power line and the second low-potential power line are electrically connected to each other.

12. The display panel as described in claim 11, wherein, The first low-potential power line of the 2-1 sub-pixel of the second pixel is electrically connected to the compensation circuit of the 2-1 sub-pixel of the first pixel.

13. The display panel as described in claim 1, wherein, The first compensation circuit of the 1-1 sub-pixel is connected between the first data line and a first low potential line, and the second compensation circuit of the 1-2 sub-pixel is connected between the second data line and a second low potential line.

14. A display device, comprising: A display panel includes a plurality of pixels, a gate line, and a data line, all connected to the plurality of pixels; a gate driver connected to the gate line; and a data driver connected to the data line, wherein each of the plurality of pixels includes: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color; a 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel includes a light-emitting element and a compensation circuit, the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line, the 1-1 sub-pixel includes a first compensation circuit connected to a first data line, and the 1-2 sub-pixel includes a second compensation circuit connected to a second data line.

15. The display device as claimed in claim 14, wherein, Each of the 3-1 sub-pixel and the 3-2 sub-pixel includes a compensation circuit, and the compensation circuits of the 3-1 sub-pixel and the 3-2 sub-pixel are connected to a data line.

16. The display device as claimed in claim 14, wherein, The first color is red, the second color is green, and the third color is blue.

17. The display device as claimed in claim 14, wherein, The plurality of pixels includes: a first pixel, wherein both the 2-1 sub-pixel and the 2-2 sub-pixel emit light when a data voltage is applied; and a second pixel, wherein only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light when the data voltage is applied.

18. The display device as claimed in claim 17, wherein, The data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel is greater than the data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

Images